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Could you upload your vhdl file to somewhere? /MikhailArticle: 104626
Vivek Menon <vivek.menon79@gmail.com> wrote: >Hi all, >I am using a Xilinx V2Pro7 FF672 board. I want to send some data values >using an ethernet card.(no Power PC, only logic fabric) >Can someone suggest where to start from?? http://www.fpga4fun.com/10BASE-T.html Asfair, 10Base-T use 3.3V..Article: 104627
It is solved. Thanks all again.Article: 104628
I want to test uart function only. Data is transmitted from matlab to FPGA board(uart), and is sent back to matlab. I have a question here. How can I trigger the write signal and read signal of UART? Thanks in advance. \zhiArticle: 104629
>Could you upload your vhdl file to somewhere?
>
>/Mikhail
>
u want to see the instantiated file it is just a inverter ...
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity inverter is
Port ( s : in std_logic_vector(0 to 31);
t : out std_logic_vector(0 to 31));
end inverter;
architecture Behavioral of inverter is
begin
t<=not s;
end Behavioral;
this inverter is called in my userip.vhd file .......
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg_write_select : std_logic_vector(0 to 2);
signal slv_reg_read_select : std_logic_vector(0 to 2);
signal slv_ip2bus_data : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal h : std_logic_vector(0 to 31);
signal k : std_logic_vector(0 to 31);
component inverter
port( s : in std_logic_vector(0 to 31);
t : out std_logic_vector(0 to 31));
end component;
attribute box_type : string;
attribute box_type of inverter : component is "black_box";
begin
we: inverter
port map(h,k);
/gary
Article: 104630Hi,I need 18v04 to config fpga(for example virtex),when the 18v04 is on PCB board,it can work correctly.When I use jumpline for the conection,it does't work(i.e can't config the fpga) but can be programmed through JTAG.I need ur suggestion.Thank u.Article: 104631
ColmF wrote: > Hi, > > I've trawled around this group and on the web a little, but haven't > found anything to suit my purposes, so I thought I'd post here... > > I'm designing a board with two FPGAs, both Cylone-II devices. One will > contain a PCI core and will always be programmed by a serial > configuration device that never changes. The other will also be loaded > by a (separate) serial configuration device, but I would like to be > able to change this configuration depending on the function required > for the board. > > Ideally, I would implement a small core in the PCI FPGA. I would then > fetch the required configuration file from somewhere via the PCI > interface and store it in a local on-board memory. The PCI FPGA would > then stream the configuration file to the serial configuration device > for the other FPGA. > > So, questions: > - Is it possible to do this in such a straighforward manner? > - Is there a core available to interface to the Active Serial interface > of the configuration device? > - What format does the configuration file need to be in? > > It strikes me that this should be a simple task to achieve - or am I > totally wrong? > > Thanks, > > Colm. > Hi Colm, You can do this by using the Altera parallel configuration device for sure, simply connect the standard flash interface to your first Fpga and write the new image. If that's an option. FYI, you might find more Cyclone traffic at www.niosforum.com AlanArticle: 104632
Alan Myler schrieb: > ColmF wrote: > > > Hi, > > > > I've trawled around this group and on the web a little, but haven't > > found anything to suit my purposes, so I thought I'd post here... > > > > I'm designing a board with two FPGAs, both Cylone-II devices. One will > > contain a PCI core and will always be programmed by a serial > > configuration device that never changes. The other will also be loaded > > by a (separate) serial configuration device, but I would like to be > > able to change this configuration depending on the function required > > for the board. > > > > Ideally, I would implement a small core in the PCI FPGA. I would then > > fetch the required configuration file from somewhere via the PCI > > interface and store it in a local on-board memory. The PCI FPGA would > > then stream the configuration file to the serial configuration device > > for the other FPGA. > > > > So, questions: > > - Is it possible to do this in such a straighforward manner? > > - Is there a core available to interface to the Active Serial interface > > of the configuration device? > > - What format does the configuration file need to be in? > > > > It strikes me that this should be a simple task to achieve - or am I > > totally wrong? > > > > Thanks, > > > > Colm. > > > > Hi Colm, > > You can do this by using the Altera parallel configuration device > for sure, simply connect the standard flash interface to your > first Fpga and write the new image. If that's an option. > > FYI, you might find more Cyclone traffic at www.niosforum.com > > Alan Alan, the OP wanted 1) solution over PCI bus 2) most likely needs the PCI-FPGA ASMI interface to be used to programm the spi flash on that FPGA, so its already used and can not be connected to the SPI flash of the other FPGA so your suggestion doesnt sound like an option for the OP AnttiArticle: 104633
wuyi316904@gmail.com schrieb: > Hi,I need 18v04 to config fpga(for example virtex),when the 18v04 is on > PCB board,it can work correctly.When I use jumpline for the > conection,it does't work(i.e can't config the fpga) but can be > programmed through JTAG.I need ur suggestion.Thank u. 1) Check your wire connections 2) get a good DSO and check signal quality Antti http://antti-brain.comArticle: 104634
Solved the problem of writing a single file reformatting the compact flash with the utility accompaining the cf reader I bought... Yet, I noticed that to open multiple in writing at the same time, I must open the file and then do some work on it before opening the next. If I open all the files I need (without doing any operation on them between the fopens) and then write on them, only the first one gets opened correctly... I don't know if this is still related to the File System format or if it's just a XilFATFS problem...Article: 104635
Hi, I've just had the exact same problem as this. You've probably solved it by now but I thought I'd post my solution in case anyone else is having the same problem. The error stems from some sort of conflict between EDK's version of cygwin and another version that you have installed already. You're supposed to be able to use the command xbash -override to switch to EDK's version but in my experience this didn't work. My solution was to delete my original cygwin installation and remove the registry entry for Cygnus Solutions. EDK should then default to using its own version of cygwin; clean the libraries in your project and it should work. However, if you want to keep your cygwin installation for something else I guess you've still got a problem. Hope this helps... DavidArticle: 104636
I just upgraded ISE 6.3.03 to 8.1 and already I am experiencing varying synthesis results. For one thing I do not infer FSM any more and the next states are bunch of latches. There is unexpected ROM inference though. This design is synchronous and works fine in ver 6 both at behavioral and gate level. For Post Route simulation, under the testbench target is UUT as expected, but with a "?". When I add the *_timesim.vhd I get duplicate design unit error. I don't know whether Xilinx went thru a major overhaul for XST engine after ver 6. Please advise about getting consistent results across the board. Thanks. YZArticle: 104637
Using the ISERDES primitive in Virtex 4 in DDR mode (for data input from an ADC), what timing constraints should be applied? In particular, I want to know the maximum data update rate (or alternatively, maximum source-synchronous clock frequency) that can be used to get the data into the FPGA. I assume this is limited by pin capacitance or other physical constraints, but don't know what it is in my design. For example, say I have a single data input DATA and a single source-synchronous clock CLK (both of which come from the ADC). They are both LVDS, so I used IBUFDS. Both enter separate ISERDES. I use the "direct" combinatorial output of the CLK ISERDES (O) to feed a BUFIO, the output of which becomes the CLK for both ISERDES. This also feeds a BUFR with /2 divider, which feeds CLKDIV on both. I then get 4 demultiplexed outputs of DATA Q0-3, which can then feed a FIFO or DSP core. So far I have applied a clock frequency constraint to the O output of the CLK ISERDES, and that is all. But the timing analyser only seems to check the CLKDIV constraints for the data outputs in the cores that follow, not the ISERDES itself... Any enlightenment would be much appreciated. TomArticle: 104638
Yaseen Zaidi schrieb: > I just upgraded ISE 6.3.03 to 8.1 and already I am experiencing varying > synthesis results. For one thing I do not infer FSM any more and the > next states are bunch of latches. There is unexpected ROM inference > though. This design is synchronous and works fine in ver 6 both at > behavioral and gate level. > > For Post Route simulation, under the testbench target is UUT as > expected, but with a "?". When I add the *_timesim.vhd I get duplicate > design unit error. > > I don't know whether Xilinx went thru a major overhaul for XST engine > after ver 6. Please advise about getting consistent results across the > board. > > > > Thanks. > YZ unfortunatly Xilinx software just gets more and more buggy every major release. therefore if you have some project working on some specific ISE major release you must keep a working copy of that ISE release as using newer major release may couse any amount of unexpected results. Sorry Xilinx. This is the way it is. I have been suggesting to upgrade to 8.1 (both ISE and EDK) but recently I have had REALLY REALLY bad trouble only because I dont have ISE 7.1 installation anymore and one important PCI-X design just refuses to work at all on 8.1 So I need to re-install 7.1 again just for that one project. I am still saying that upgrade to 8.1 is a must, but it is equally important to keep working parallel installations of 6.x and 7.x tools (both ISE and EDK). antti http://antti-brain.comArticle: 104639
Hi I think Xilinx has said the service packs should come once a months? So is the EDK service pack delaying or may there will be no SP and comes out EDK 8.2? the reason why I am asking is the issue that - EDK 8.1 SP2 can not use FSL links with MicroBlaze 3.0 (bug!!!) and MicroBlaze 4.0 has still to my knowledge issues with uClinux, so its very complicated to make Impulse-C codeveloper FSL accelerator demos for systems that can run uclinux. AnttiArticle: 104640
Antti wrote: > radarman schrieb: > > > Antti wrote: > > > radarman schrieb: > > > > > > > Rene Tschaggelar wrote: > > > > > burn.sir@gmail.com wrote: > > > > > > > > > > > Hi all, > > > Antti, > > Could you point me to some more info on the ACE format and players? The > > only info I seem to be able to dig up is on SystemACE - the Xilinx CF > > reader. This sounds like a good use for a smallish CPLD, and something > > I can try out on my Digilent XC2XL board. > > > > Thanks! > > -Seth > > Hi Seth, > > There is no public info on the ACE format. So you have 2 options: > > Choice #1: You (or anyone else) can obtain it in some time. The actual > amount you would spend depends on your brain and mileage. For me the > target time was about one hour. You can try obtaining this info for fun > if you like using your brain. Dont feel bad if your target time is more > than one hour. > > or > > Choice #2: Get my brain. The explanation how I used my brain may come > handy now and later. > > http://antti-brain.com > > As of players - I have not implemented the player but inside the brain > snapshot are ACE dump and compress utilities with full source codes, > writing an player is trivial as well. Both the dump and compress > utilities did take about one hour each of time to write from scratch. > Note the ACE compress utility is only able to compress ACE files > generated by ISE/Impact version 8.1 or earlier, if Xilinx enhances its > ACE output generation in new releases of the ISE then the utility will > no longer be able to compress the ACE files. > > Antti No need. XAPP139 appears to take all the mystery out of it. It appears that with careful timing, you could even use a serial platform flash with your CPLD, allowing for JTAG programmability using standard tools. You appear to still need a bit counter, though. I'm assuming that you were planning on pre-programming the size of N into the design - since each device has a different number of bits in the configuration stream. http://www.xilinx.com/bvdocs/appnotes/xapp139.pdf I haven't had time to sit down and write the code yet, but an hour seems reasonable. -SethArticle: 104641
radarman schrieb: > Antti wrote: > > radarman schrieb: > > > > > Antti wrote: > > > > radarman schrieb: > > > > > > > > > Rene Tschaggelar wrote: > > > > > > burn.sir@gmail.com wrote: > > > > > > > > > > > > > Hi all, > > > > > Antti, > > > Could you point me to some more info on the ACE format and players? The > > > only info I seem to be able to dig up is on SystemACE - the Xilinx CF > > > reader. This sounds like a good use for a smallish CPLD, and something > > > I can try out on my Digilent XC2XL board. > > > > > > Thanks! > > > -Seth > > > > Hi Seth, > > > > There is no public info on the ACE format. So you have 2 options: > > > > Choice #1: You (or anyone else) can obtain it in some time. The actual > > amount you would spend depends on your brain and mileage. For me the > > target time was about one hour. You can try obtaining this info for fun > > if you like using your brain. Dont feel bad if your target time is more > > than one hour. > > > > or > > > > Choice #2: Get my brain. The explanation how I used my brain may come > > handy now and later. > > > > http://antti-brain.com > > > > As of players - I have not implemented the player but inside the brain > > snapshot are ACE dump and compress utilities with full source codes, > > writing an player is trivial as well. Both the dump and compress > > utilities did take about one hour each of time to write from scratch. > > Note the ACE compress utility is only able to compress ACE files > > generated by ISE/Impact version 8.1 or earlier, if Xilinx enhances its > > ACE output generation in new releases of the ISE then the utility will > > no longer be able to compress the ACE files. > > > > Antti > > No need. XAPP139 appears to take all the mystery out of it. It appears > that with careful timing, you could even use a serial platform flash > with your CPLD, allowing for JTAG programmability using standard tools. > You appear to still need a bit counter, though. I'm assuming that you > were planning on pre-programming the size of N into the design - since > each device has a different number of bits in the configuration stream. > > http://www.xilinx.com/bvdocs/appnotes/xapp139.pdf > > I haven't had time to sit down and write the code yet, but an hour > seems reasonable. > > -Seth o sure an custom jtag bytecode player can sure be implemented within one hour :) but the docu you referred only talks about jtag config, there is defenetly no mystery about that and a PLD that can configure an FPGA using JTAG from spi flash should fit into 36 macrocells. AnttiArticle: 104642
Hey! Has anyone managed to get LwIP running on a Xilinx Virtex 2 Pro with only on-chip memory? Best regards, HampusArticle: 104643
I have a design for vsprom.My idea is that config FPGA with Xilinx CPLD and parallel flash memory.The design is correct in spartan platform but failure in spartan-2.Can u give me some suggestions? I know that the algorithm of config spartan and sparan-2 is different.There is a internal counter for spartan bitstream,but the spartan-2 use command reg for the bitstream control.Is this the reason why the design does't work for spartan-2?Article: 104644
Thanks for all that information! It seems to me to be a good solution to change to GSRD2. Has anybody experiences if the current downloadable version will work with the Montavista Linux Preview Kit 3.1. I managed it to run it on GSRD1 design. I can reach about 120 Mbits/s now. If i change to the new one i have to get it run there with the same performance. My second approach is to use the DCR-Bus in the GSRD1. There is a Interrupt contoller connected to the DCR and i would like to do it like the source from there. Is there a chance that this works in the end? What do you think? Eric Guru schrieb: >> Out of curiousity: did you EVER have a GSRD implementation working on >> the MiniModule? I actually emailed Xilinx a while ago asking if this >> reference design would work on the MiniModule, and I was told that it >> would not due to several technical reasons (that were all enumerated at >> the time, and made sense to me, though I don't have them in front of me >> right now). So, I'd be curious to hear if you had the original GSRD >> working, and if you do in fact get the GSRD2 working. >> >> Regards, >> John O. >> www.jrobot.net > > Hi John, > > You shocked me with your response. I have NEVER implemented an original > GSRD to work on MiniModule. I actually did not find it necessary since > I was waiting for GSRD2 (I tried to save some time). If there are some > technical limits that prevent that I would like to see them written, > because nobody told me yet, that this is not possible. I only had the > original TEMAC reference design working (using LL_TEMAC in a > CoreConnect style and lwip stack). > > With regrets, > > Guru >Article: 104645
I've been reading about chaos theory and it occurred to me that metastability might be a chaotic process. It seems something as simple as a damped, driven pendulum (a grandfather clock) can exhibit chaos. The pendulum can swing stabily if given enough energy initially so that it is driven and remains above a threshold point. But if released well below the threshold it will decay to a static point. It will exhibit chaotic behaviour when released near the threshold point, rising and falling in ampitude and never achieving a stable period, but never decaying to a static point either. Does anyone know if a FF driven into metastability meets the criteria for chaos? Are there factors that prevent a FF output from being chaotic even in metastability?Article: 104646
Hello All, Could anyone please tell me: * Whether I can use "VREF" pins for LVDS output? * What is HSWAPEN exactly for Thank you. Vassili SavinovArticle: 104647
Antti wrote: > Yaseen Zaidi schrieb: > > > I just upgraded ISE 6.3.03 to 8.1 and already I am experiencing varying > > synthesis results. For one thing I do not infer FSM any more and the > > next states are bunch of latches. There is unexpected ROM inference > > though. This design is synchronous and works fine in ver 6 both at > > behavioral and gate level. > > > > For Post Route simulation, under the testbench target is UUT as > > expected, but with a "?". When I add the *_timesim.vhd I get duplicate > > design unit error. > > > > I don't know whether Xilinx went thru a major overhaul for XST engine > > after ver 6. Please advise about getting consistent results across the > > board. > > > > > > > > Thanks. > > YZ > > unfortunatly Xilinx software just gets more and more buggy every major > release. > > therefore if you have some project working on some specific ISE major > release you must keep a working copy of that ISE release as using newer > major release may couse any amount of unexpected results. > > Sorry Xilinx. This is the way it is. I have been suggesting to upgrade > to 8.1 (both ISE and EDK) but recently I have had REALLY REALLY bad > trouble only because I dont have ISE 7.1 installation anymore and one > important PCI-X design just refuses to work at all on 8.1 > So I need to re-install 7.1 again just for that one project. > > I am still saying that upgrade to 8.1 is a must, but it is equally > important to keep working parallel installations of 6.x and 7.x tools > (both ISE and EDK). > > antti > http://antti-brain.com I have got the same problem,too. After installing ISE 8.1i, I found some of my projects created in 7.1i can not be opened again.Article: 104648
did you connect Vccaux? (2.5V)
Aurash
blisca wrote:
>for reading the device ID how should the PROGRAM pin be ?
>
>thank you all
>(i'm still spending hours and days trying to do it,no way....no activity on
>TDI or TDO)
>
>
>here ,once ,more the things that i did:
>
>i connected just one 1.8V supply to the VCCINT of the fpga(pin A9),it is not
>easy to test it (soldering wires on a bga as i do is even worse ...)but it
>looks
>that it should be enough for the core,correct???or i need to
>
>i connected in 7 points the 3.3VCCO(A2,B2,B12 , A13,G12,N1,M2) and the
>ground in 3
>points(A1,J1,N12)
>
>i connected the jtag signals,TCK,TDI,TMS,TDO(this one to the level
>amplifier)
>
>I connected PROGRAM fixed to 3.3V,then i tried to connect it with TMS,same
>result.....
>
>I left M0 and M2 open,and them are high,M1 tied to ground,this for choosing
>boundary scan mode
>
>using the debug chain utility i verified that the signals are working but i
>noticed that there is no movement on TMS,and of course on TDO
>
>there is something else missing?
>
>Thank you to everyone in the group that will help me or just will read this
>
>Diego
>
>
>
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 104649blisca schrieb: > for reading the device ID how should the PROGRAM pin be ? > > thank you all > (i'm still spending hours and days trying to do it,no way....no activity on > TDI or TDO) Hi I have succesfully soldered wires to Virtex 2000 BGA and the proto did work prog_b needs to have an pullup to logic high level xilinx datasheet says it has internal pullup but on Virtex family JTAG config does not work without external pullup, that is the JTAG chain is accessible but configuratio fails. minimal connections are GND VCCINT VCCIO in the bank that supply JTAG PROG_B pullup JTAG pins thats all! if those connections are ok the FPGA should get configured over JTAG Antti http://antti-brain.com
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z