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Threads Starting Feb 2001

28976: 01/02/01: Krishnan: 64-bit counter @ 200 MHz on FPGA?
    28980: 01/02/01: Ray Andraka: Re: 64-bit counter @ 200 MHz on FPGA?
        28983: 01/02/01: Krishnan: Re: 64-bit counter @ 200 MHz on FPGA?
            29004: 01/02/01: Peter Alfke: Re: 64-bit counter @ 200 MHz on FPGA?
                29010: 01/02/02: Jim Granville: Re: 64-bit counter @ 200 MHz on FPGA?
    28984: 01/01/31: Terry Hicks: Re: 64-bit counter @ 200 MHz on FPGA?
    28986: 01/02/01: Peter Alfke: Re: 64-bit counter @ 200 MHz on FPGA?
    28995: 01/02/01: Wolfgang Loewer: Re: 64-bit counter @ 200 MHz on FPGA?
28987: 01/02/01: rk: Test
28988: 01/02/01: Vladislav Vasilenko: PCI testbench
28989: 01/02/01: Karim LIMAM: JTAG Programming with SpartanII demo card
    29001: 01/02/01: Falk Brunner: Re: JTAG Programming with SpartanII demo card
        29022: 01/02/02: Karim LIMAM: Re: JTAG Programming with SpartanII demo card
            29090: 01/02/05: Marc Baker: Re: JTAG Programming with SpartanII demo card
    29029: 01/02/02: Marc Baker: Re: JTAG Programming with SpartanII demo card
28990: 01/02/01: Gerhard Griessnig: More then 4 Clocks
    29002: 01/02/01: Falk Brunner: Re: More then 4 Clocks
        29009: 01/02/01: Simon Bacon: Re: More then 4 Clocks
        29020: 01/02/02: Gerhard Griessnig: Re: More then 4 Clocks
            29063: 01/02/04: Falk Brunner: Re: More then 4 Clocks
    29003: 01/02/01: <jdaughenb@my-deja.com>: Re: More then 4 Clocks
28991: 01/02/01: Lenny: Virtex : Timing Problem
    29031: 01/02/02: Brian Philofsky: Re: Virtex : Timing Problem
28992: 01/02/01: Sally Verkaik: Short Course Announcement
28994: 01/02/01: Daniel Nilsson: lcd driver for EG2401S
28997: 01/02/01: Guibert, Martin: Virtex PCI Core problem
28999: 01/02/01: <frouatbi@my-deja.com>: It's time to make a little dance
    29000: 01/02/01: Muzaffer Kal: Re: It's time to make a little dance
29005: 01/02/01: jean-francois hasson: A54SX type FPGA from ACTEL questions
    29017: 01/02/01: rk: Re: A54SX type FPGA from ACTEL questions
29012: 01/02/01: Todd McKenzie: Opportunity Knocks
29013: 01/02/01: Dave Nadler: Spartan-II TBUF questions
    29024: 01/02/02: Simon Bacon: Re: Spartan-II TBUF questions
29014: 01/02/02: Kang Liat Chuan: How different is FPGA design from IC design
    29026: 01/02/02: Joe Hass: Re: How different is FPGA design from IC design
        29070: 01/02/05: Jon Schneider: Re: How different is FPGA design from IC design
29019: 01/02/02: Zhen Luo: FPGA board with lots of SRAM?
    29025: 01/02/02: Jean-Michel GUEUGNOT: Re: FPGA board with lots of SRAM?
    29073: 01/02/05: Vincent Clerc: Re: FPGA board with lots of SRAM?
        29081: 01/02/05: ajd: Re: FPGA board with lots of SRAM?
29027: 01/02/02: Alan Horton: Xilinx question
    29030: 01/02/02: Jan Kindt: Re: Xilinx question
    29034: 01/02/02: Tom Burgess: Re: Xilinx question
    29665: 01/03/04: Richard Erlacher: Re: Xilinx question
29028: 01/02/02: Dan Alley: virtex mapping failing after small change to source files
29032: 01/02/02: <dominetmike@my-deja.com>: We are looking for Hardware Engineers in San Jose
29033: 01/02/02: Michael Barr: ANNOUNCE: New Article on Run-Time Calibration
29035: 01/02/02: Christof Paar: CHES 2001 --- Final CFP
29037: 01/02/03: robert: Job in Southern California - mention this newsgroup
29040: 01/02/03: Desilva: faq or just basic info
    29118: 01/02/07: Tony Burch: Re: faq or just basic info
29041: 01/02/03: Kevin J. McCann: Help for a novice. Where to begin?
    29042: 01/02/03: Dave Vanden Bout: Re: Help for a novice. Where to begin?
        29044: 01/02/03: Terry Hicks: Re: Help for a novice. Where to begin?
    29053: 01/02/04: Ed Ngai: Re: Help for a novice. Where to begin?
        29077: 01/02/05: Andy Peters: Re: Help for a novice. Where to begin?
            29080: 01/02/05: Brian Philofsky: Re: Help for a novice. Where to begin?
                29106: 01/02/06: Andy Peters: Re: Help for a novice. Where to begin?
                    29221: 01/02/10: Rick Filipkiewicz: Re: Help for a novice. Where to begin?
                        29225: 01/02/10: Peter Alfke: Re: Help for a novice. Where to begin?
                            29230: 01/02/10: Rick Filipkiewicz: Re: Help for a novice. Where to begin?
                        29311: 01/02/13: Andy Peters: Re: Help for a novice. Where to begin?
    29116: 01/02/07: Tony Burch: Re: Help for a novice. Where to begin?
29049: 01/02/03: mok: HELP!!!!
29051: 01/02/04: Rob Finch: interior timing constraints - Xilinx F1.5
    29068: 01/02/05: Utku Ozcan: Re: interior timing constraints - Xilinx F1.5
        29123: 01/02/07: Rob Finch: Re: interior timing constraints - Xilinx F1.5
            29129: 01/02/07: Utku Ozcan: Re: interior timing constraints - Xilinx F1.5
            29133: 01/02/07: <eml@riverside-machines.com.NOSPAM>: Re: interior timing constraints - Xilinx F1.5
29052: 01/02/04: EKC: FPGA Conferences
    29060: 01/02/04: Jan Gray: Re: FPGA Conferences
29058: 01/02/04: goran: help need to make a clock multiplier
    29061: 01/02/04: Peter Alfke: Re: help need to make a clock multiplier
    29155: 01/02/08: Goran: Re: help need to make a clock multiplier
29059: 01/02/04: Dr Daz: Xilinx post-synthesis (leonardo) simulation (modelsim)
    29079: 01/02/05: Brian Philofsky: Re: Xilinx post-synthesis (leonardo) simulation (modelsim)
        29087: 01/02/05: Philip Freidin: Installed Documentation
29062: 01/02/04: james.rowland1: initialise state machine on Altera
    29168: 01/02/08: Simon Bacon: Re: initialise state machine on Altera
29069: 01/02/05: <kkdeep@my-deja.com>: in-out pad uasage in fpga compiler II
    29078: 01/02/05: Brian Philofsky: Re: in-out pad uasage in fpga compiler II
29071: 01/02/05: <tchoh@my-deja.com>: Rijndael
    29082: 01/02/05: ajd: Re: Rijndael
        29095: 01/02/06: <tchoh@my-deja.com>: Re: Rijndael
    29088: 01/02/05: <jzakiya@my-deja.com>: Re: Rijndael
        29091: 01/02/05: Eric Smith: Re: Rijndael
            29093: 01/02/06: <jzakiya@mail.com>: Re: Rijndael
                29338: 01/02/15: Catalin Baetoniu: Re: Rijndael
                    29363: 01/02/16: Brendan Lynskey: Re: Rijndael
                        29366: 01/02/16: Keith R. Williams: Re: Rijndael
                            29367: 01/02/16: Panu =?iso-8859-1?Q?H=E4m=E4l=E4inen?=: Re: Rijndael
    29352: 01/02/15: Andy Peters: Re: Rijndael
        29354: 01/02/15: Eric Braeden: Re: Rijndael
29072: 01/02/05: Josselin Lebahar: !!!!!!!!!!!!!! Offre d'emploi !!!!!!!!!!!!!!!!!!! URGENT
29074: 01/02/05: "Eric Jeandeau": Handel-C language.
    29113: 01/02/06: JianYong Niu: Re: Handel-C language.
        29130: 01/02/07: "Eric Jeandeau": Re: Re: Handel-C language.
            29304: 01/02/13: Jamie Lokier: Re: Handel-C language.
                29321: 01/02/14: Jamie Lokier: Re: Handel-C language.
29075: 01/02/05: <frouatbi@my-deja.com>: who wants to work in France ????
    29083: 01/02/05: Jerry English: Re: who wants to work in France ????
        29085: 01/02/05: Dan: Hey Jerry, he lives in Montreal. Still Canadian last time I checked.
    29086: 01/02/05: Jimmy Roberts: Re: who wants to work in France ????
    29094: 01/02/06: Vincent Clerc: Re: who wants to work in France ????
    29114: 01/02/06: Stuart Clubb: Re: who wants to work in France ????
29084: 01/02/05: An: Xilinx Project Manager 3.1i: viewing signals
29089: 01/02/06: Jeff and Bev Neil: .ucf commands
    29092: 01/02/06: S. Ramirez: Re: .ucf commands
29096: 01/02/06: Marc: switching Matrix, FPGA or CPLD? - smatrix.JPG (0/1)
    29103: 01/02/06: Jan Gray: Re: switching Matrix, FPGA or CPLD? - smatrix.JPG (0/1)
        29121: 01/02/06: Marc: Re: switching Matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29097: 01/02/06: Marc: switching Matrix, FPGA or CPLD? - smatrix.JPG (1/1)
29098: 01/02/06: V R: Xilinx XC4010
    29104: 01/02/06: Simon Bacon: Re: Xilinx XC4010
    29108: 01/02/06: Scott Hauck: Re: Xilinx XC4010
        29111: 01/02/06: Peter Alfke: Re: Xilinx XC4010
    29110: 01/02/06: Brian Philofsky: Re: Xilinx XC4010
        29128: 01/02/07: V R: Re: Xilinx XC4010
            29139: 01/02/07: Brian Philofsky: Re: Xilinx XC4010
29099: 01/02/06: JianYong Niu: Xilinx Implementation Error! need help urgently
    29112: 01/02/06: Falk Brunner: Re: Xilinx Implementation Error! need help urgently
    29206: 01/02/09: Tom Dillon: Re: Xilinx Implementation Error! need help urgently
29100: 01/02/06: ask: where FlexGen is?
29101: 01/02/06: <erika_uk@my-deja.com>: can -(A+B) computed in one level of logic ?
    29107: 01/02/06: <kolja@prowokulta.org>: Re: can -(A+B) computed in one level of logic ?
        29176: 01/02/08: Daniel Lang: Re: can -(A+B) computed in one level of logic ?
29102: 01/02/06: Chris Anderson: PAL/GAL 22V10 (CE) programmers?
    29152: 01/02/08: Bertram Geiger: Re: PAL/GAL 22V10 (CE) programmers?
29105: 01/02/06: Andy Peters: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
    29119: 01/02/06: Marc: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
        29122: 01/02/06: Peter Alfke: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
            29124: 01/02/07: Marc: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
            29127: 01/02/07: Jim Granville: Re: Switching matrix, FPGA or CPLD? -
    29126: 01/02/06: Theron Hicks (Terry): Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
        29132: 01/02/07: <eml@riverside-machines.com.NOSPAM>: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29109: 01/02/06: Mike DeCellis: Digital/Hardware Designer with Ericsson
    29120: 01/02/06: SiliconLinx: Re: Digital/Hardware Designer with Ericsson
29115: 01/02/06: Robert Sefton: MPEG1 video encoder availability?
    29117: 01/02/06: Matthew Donadio: Re: MPEG1 video encoder availability?
29125: 01/02/06: Philip Freidin: FAQ
29131: 01/02/07: Gil Golov: Spartan II/Virtex DLL with Exemplar - help
    29568: 01/02/27: Andreas Wolf: Re: Spartan II/Virtex DLL with Exemplar - help
29134: 01/02/07: S. Ramirez: 8B/10B Encoding
    29135: 01/02/07: Michael Boehnel: Re: 8B/10B Encoding
    29136: 01/02/07: Jason Daughenbaugh: Re: 8B/10B Encoding
        29167: 01/02/08: Brian Drummond: Re: 8B/10B Encoding
    29137: 01/02/07: Michael Strothjohann: Re: 8B/10B Encoding
    29142: 01/02/07: Philip Freidin: Re: 8B/10B Encoding
    29277: 01/02/12: Dan K: Re: 8B/10B Encoding
29138: 01/02/07: Jean-Paul Smeets: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29140: 01/02/07: <p25486@my-deja.com>: Mentor Advice
    29143: 01/02/07: Chris G. Schneider: Re: Mentor Advice
    29165: 01/02/08: Newsbrowser: Re: Mentor Advice
        29327: 01/02/14: Nial Stewart: Re: Mentor Advice
            29375: 01/02/16: Erik Widding: Re: Mentor Advice
    29216: 01/02/09: Stuart Clubb: Re: Mentor Advice
        29254: 01/02/11: <eml@riverside-machines.com.NOSPAM>: Re: Mentor Advice
29141: 01/02/07: <eml@riverside-machines.com.NOSPAM>: JTAG debugging?
    29149: 01/02/08: Jaan Sirp: Re: JTAG debugging?
    29285: 01/02/12: Dmitry Kuznetsov: Re: JTAG debugging?
        29344: 01/02/15: <eml@riverside-machines.com.NOSPAM>: FAQ submission (was: Re: JTAG debugging?)
29144: 01/02/07: Raymond Chow: Xilinx vs Altera
    29146: 01/02/08: S. Ramirez: Re: Xilinx vs Altera
        29153: 01/02/08: Brian Gogan: Re: Xilinx vs Altera
        29157: 01/02/08: <serebr@my-deja.com>: Re: Xilinx vs Altera
            29161: 01/02/08: Peter Alfke: Re: Xilinx vs Altera
                29163: 01/02/08: Jakab Tanko: Re: Xilinx vs Altera
                    29166: 01/02/08: Kamal Patel: Re: Xilinx vs Altera
                        29193: 01/02/09: Jakab Tanko: Re: Xilinx vs Altera
                            29202: 01/02/09: Andy Peters: Re: Xilinx vs Altera
                                29275: 01/02/12: Jakab Tanko: Re: Xilinx vs Altera
                29178: 01/02/09: Rick Filipkiewicz: Re: Xilinx vs Altera
                    29183: 01/02/09: Eric Montreal: Re: Xilinx vs Altera
                    29184: 01/02/09: Eric Montreal: Re: Xilinx vs Altera
                29181: 01/02/08: Eric Smith: Re: Xilinx vs Altera
                    29204: 01/02/09: Peter Alfke: Re: Xilinx vs Altera
                        29213: 01/02/09: Hal Murray: Re: Xilinx vs Altera
                        29215: 01/02/09: Eric Smith: Re: Xilinx vs Altera
29145: 01/02/07: Rick Filipkiewicz: Verilog model of I2C/SMB
    29150: 01/02/08: Tomek: Re: Verilog model of I2C/SMB
29147: 01/02/08: Klaus Falser: VHDL-Mode
    29162: 01/02/08: Reto Zimmermann: Re: VHDL-Mode
29148: 01/02/08: Panu =?iso-8859-1?Q?H=E4m=E4l=E4inen?=: AES (Rijndael) in FPGAs
29151: 01/02/08: Le Mer Michel: Re: Altera, NON JTAG devices.
    29177: 01/02/08: Daniel Lang: Re: Altera, NON JTAG devices.
29154: 01/02/08: Christian Plessl: Wired-or on Virtex FPGAs
    29164: 01/02/08: Brian Philofsky: Re: Wired-or on Virtex FPGAs
        29192: 01/02/09: Christian Plessl: Re: Wired-or on Virtex FPGAs
            29217: 01/02/09: Brian Philofsky: Re: Wired-or on Virtex FPGAs
                29274: 01/02/12: Christian Plessl: Re: Wired-or on Virtex FPGAs
            29223: 01/02/10: Phil Hays: Re: Wired-or on Virtex FPGAs
                29231: 01/02/10: Chris G. Schneider: Re: Wired-or on Virtex FPGAs
                    29242: 01/02/10: Phil Hays: Re: Wired-or on Virtex FPGAs
                29265: 01/02/11: Keith R. Williams: Re: Wired-or on Virtex FPGAs
                    29266: 01/02/11: Jan Gray: Re: Wired-or on Virtex FPGAs
                        29345: 01/02/15: <eml@riverside-machines.com.NOSPAM>: Re: Wired-or on Virtex FPGAs
                        29353: 01/02/15: Keith R. Williams: Re: Wired-or on Virtex FPGAs
            29271: 01/02/12: Kent Orthner: Re: Wired-or on Virtex FPGAs
    29170: 01/02/08: <eml@riverside-machines.com.NOSPAM>: Re: Wired-or on Virtex FPGAs
    29273: 01/02/12: <kolja@prowokulta.org>: Re: Wired-or on Virtex FPGAs
29156: 01/02/08: L.C.: Altera, NON JTAG devices.
29158: 01/02/08: Harjo Otten: First XILINX PCI core project
    29171: 01/02/08: John Ayer: Re: First XILINX PCI core project
        29173: 01/02/08: Simon Bacon: Re: First XILINX PCI core project
    29188: 01/02/09: Hkan Pettersson: Re: First XILINX PCI core project
29160: 01/02/08: Jorge Neves: Xilinx 4010E development kit
    29175: 01/02/08: Anna Acevedo: Re: Xilinx 4010E development kit
    29219: 01/02/10: Tony Burch: Re: Xilinx 4010E development kit
29169: 01/02/08: L.C.: Altera non JTAG devices. Prog specs?
29172: 01/02/08: Muzaffer Kal: parallel PRBS ?
29174: 01/02/08: Jan Gray: on making it too convenient to download PDFs
    29179: 01/02/08: Eric Smith: Re: on making it too convenient to download PDFs
    29180: 01/02/09: Phil Hays: Re: on making it too convenient to download PDFs
29182: 01/02/08: Eddy Sambuaga: Need help using bitgen
    29211: 01/02/09: Jamie Sanderson: Re: Need help using bitgen
    29287: 01/02/12: Mike: Re: Need help using bitgen
    29312: 01/02/13: David Hawke: Re: Need help using bitgen
29185: 01/02/09: ġ: FPGA for ADS7843
29186: 01/02/09: Kons Henrik Bohre: Can a Virtex control its own reconfiguration?
    29214: 01/02/09: Peter Alfke: Re: Can a Virtex control its own reconfiguration?
        29317: 01/02/13: Steve Casselman: Re: Can a Virtex control its own reconfiguration?
29187: 01/02/09: Gil Golov: Virtex XCV2000E-6 BG560C - Orcad capture symbol
    29246: 01/02/11: Austin Franklin: Re: Virtex XCV2000E-6 BG560C - Orcad capture symbol
        29309: 01/02/13: Andy Peters: Re: Virtex XCV2000E-6 BG560C - Orcad capture symbol
            29332: 01/02/14: Austin Franklin: Re: Virtex XCV2000E-6 BG560C - Orcad capture symbol
                29335: 01/02/15: Muzaffer Kal: Re: Virtex XCV2000E-6 BG560C - Orcad capture symbol
    29270: 01/02/12: Laurent Gauch: Re: Virtex XCV2000E-6 BG560C - Orcad capture symbol
    29279: 01/02/12: Ingo Cyliax: Re: Virtex XCV2000E-6 BG560C - Orcad capture symbol
29189: 01/02/09: Arthur Agababyan: verilog book
    29210: 01/02/09: <kamiak@my-deja.com>: Re: verilog book
    29220: 01/02/10: <voodoo98_ca@my-deja.com>: Re: verilog book
29190: 01/02/09: Richard Wilkinson: Synplify on Windows2000?
    29194: 01/02/09: Chris Briggs: Re: Synplify on Windows2000?
    29197: 01/02/09: Keith R. Williams: Re: Synplify on Windows2000?
    29205: 01/02/09: Tom Dillon: Re: Synplify on Windows2000?
29191: 01/02/09: PhilipKD: what exactly is the dff between fpga and cpld?
    29199: 01/02/09: Gil Golov: Re: what exactly is the dff between fpga and cpld?
        29208: 01/02/09: PhilipKD: Re: what exactly is the dff between fpga and cpld?
    29218: 01/02/09: Kraig Lund: Re: what exactly is the dff between fpga and cpld?
        29224: 01/02/10: Peter Alfke: Re: what exactly is the dff between fpga and cpld?
            29256: 01/02/11: rk: Re: what exactly is the dff between fpga and cpld?
29195: 01/02/09: <erika_uk@my-deja.com>: counter
    29198: 01/02/09: Daniel Nilsson: SV: counter
29196: 01/02/09: Guibert, Martin: Low skew lines in Virtex-E
    29200: 01/02/09: Simon Bacon: Re: Low skew lines in Virtex-E
    29201: 01/02/09: Falk Brunner: Re: Low skew lines in Virtex-E
    29203: 01/02/09: Tom Dillon: Re: Low skew lines in Virtex-E
    29212: 01/02/09: Jamie Sanderson: Re: Low skew lines in Virtex-E
29222: 01/02/10: EKC: VHDL PID
    29361: 01/02/16: Blake Henry: Re: VHDL PID
29226: 01/02/10: Peter Alfke: Re: double precision floating point arithmetic
29228: 01/02/10: Muzaffer Kal: Re: double precision floating point arithmetic
    29229: 01/02/10: Terje Mathisen: Re: double precision floating point arithmetic
29232: 01/02/10: <erika_uk@my-deja.com>: does a disabled FDC consume power ?
    29239: 01/02/10: Peter Alfke: Re: does a disabled FDC consume power ?
29233: 01/02/10: <karenwlead@my-deja.com>: any idea ?
    29234: 01/02/10: Falk Brunner: Re: any idea ?
        29236: 01/02/10: <karenwlead@my-deja.com>: Re: any idea ?
            29237: 01/02/10: Falk Brunner: Re: any idea ?
                29238: 01/02/10: <karenwlead@my-deja.com>: Re: any idea ?
                29245: 01/02/10: rk: Re: any idea ?
                    29251: 01/02/11: Peter Alfke: Re: any idea ?
                    29253: 01/02/11: Peter Alfke: Re: any idea ?
                        29255: 01/02/11: rk: Re: any idea ?
                            29257: 01/02/11: <karenwlead@my-deja.com>: Re: any idea ?
                                29258: 01/02/11: Falk Brunner: Re: any idea ?
                                29260: 01/02/11: rk: Re: any idea ?
                                    29280: 01/02/12: <karenwlead@my-deja.com>: Re: any idea ?
                                29263: 01/02/12: Jim Granville: Re: any idea ?
                                29281: 01/02/12: Eric Montreal: Re: any idea ?
                    29307: 01/02/13: Andy Peters: Re: any idea ?
                        29316: 01/02/13: rk: Re: any idea ?
            29244: 01/02/11: Eric Montreal: Re: any idea ?
    29240: 01/02/10: Peter Alfke: Re: any idea ?
29235: 01/02/10: Bob Perlman: Re: double precision floating point arithmetic
    29249: 01/02/11: V R: OT: IEEE & Floating point
        29250: 01/02/11: Terje Mathisen: Re: OT: IEEE & Floating point
        29252: 01/02/11: Peter Alfke: Re: OT: IEEE & Floating point
            29259: 01/02/11: Jan Gray: Re: OT: IEEE & Floating point
        29269: 01/02/11: John Larkin: Re: OT: IEEE & Floating point
        29298: 01/02/13: Leon Heller: Re: IEEE & Floating point
            29330: 01/02/14: glen herrmannsfeldt: Re: IEEE & Floating point
29241: 01/02/10: glen herrmannsfeldt: Re: double precision floating point arithmetic
    29283: 01/02/12: Al Grant: Re: double precision floating point arithmetic
        29284: 01/02/12: Nick Maclaren: Re: double precision floating point arithmetic
            29347: 01/02/15: Herman Rubin: Re: double precision floating point arithmetic
        29288: 01/02/12: glen herrmannsfeldt: Re: double precision floating point arithmetic
            29289: 01/02/12: Terje Mathisen: Re: double precision floating point arithmetic
                29297: 01/02/13: Al Grant: Re: double precision floating point arithmetic
                29315: 01/02/14: glen herrmannsfeldt: Re: double precision floating point arithmetic
29243: 01/02/10: Reto Zimmermann: Emacs VHDL Mode 3.31 released
    29390: 01/02/18: Jon Keeble: Re: Emacs VHDL Mode 3.31 released
        29396: 01/02/19: Michael Strothjohann: Re: Emacs VHDL Mode 3.31 released
29247: 01/02/11: Daniel Nilsson: OT: SEIKO-EPSON LCD behaving strange.
    29267: 01/02/11: Philip Freidin: Re: OT: SEIKO-EPSON LCD behaving strange.
29248: 01/02/10: Kevin: Re: double precision floating point arithmetic
29261: 01/02/11: Dan: FPGAs take wron road. SoC NO - on-the-fly reprogrammability YES
    29292: 01/02/13: Stuart Clubb: Re: FPGAs take wron road. SoC NO - on-the-fly reprogrammability YES
29262: 01/02/11: Matt Billenstein: Re: double precision floating point arithmetic
    29264: 01/02/11: Terje Mathisen: Re: double precision floating point arithmetic
    29272: 01/02/12: <kolja@prowokulta.org>: Re: double precision floating point arithmetic
        29286: 01/02/12: Matt Billenstein: Re: double precision floating point arithmetic
    29276: 01/02/12: david garnett: Re: double precision floating point arithmetic
    29342: 01/02/15: Renaud Pacalet: Re: double precision floating point arithmetic
29268: 01/02/12: Jan Gray: Re: New DES/AES (RIJNDAEL) Cores
29278: 01/02/12: Patrik Eriksson: Xilinx PAR core dump
29282: 01/02/12: I. Purnhagen: Virtex Symbol for eDesigner/Viewlogic
29290: 01/02/12: noelia: dedicated carry logic
29291: 01/02/13: Jean-Paul Smeets: QuickLogic PCI arbiter in QAN24 completely wrong
29293: 01/02/13: Clyde R. Shappee: Re: double precision floating point arithmetic
29294: 01/02/13: Pratip Mukherjee: Programming a CPLD
    29295: 01/02/13: Klaus Falser: Re: Programming a CPLD
        29302: 01/02/13: Pratip Mukherjee: Re: Programming a CPLD
            29322: 01/02/14: Daniel Nilsson: SV: Programming a CPLD
            29340: 01/02/15: Klaus Falser: Re: Programming a CPLD
            29348: 01/02/15: Bertram Geiger: Re: Programming a CPLD
    29748: 01/03/07: A. dhermies: Re: Programming a CPLD
        29752: 01/03/07: Bertram Geiger: Re: Programming a CPLD
29296: 01/02/13: Brian Philofsky: Re: The usage of 'Guide files' in Xilinx foundation 2.1i
29299: 01/02/13: Sang-hee Lee: The usage of 'Guide files' in Xilinx foundation 2.1i
29300: 01/02/13: Mathias Schmalisch: ROM initialization in VHDL for Virtex
    29306: 01/02/13: Chris Dunlap: Re: ROM initialization in VHDL for Virtex
29301: 01/02/13: EuroEDA Information: Expressive V3 Released in Europe
29303: 01/02/13: Jon Schneider: What does specman do ?
29305: 01/02/13: radhika: Configuration of FPGA using SPROM
29308: 01/02/13: radhika: Configuration of FPGA using SPROM
    29314: 01/02/13: Chris Dunlap: Re: Configuration of FPGA using SPROM
        29339: 01/02/14: radhika: Re: Configuration of FPGA using SPROM
            29350: 01/02/15: Mark Momcilovich: Re: Configuration of FPGA using SPROM
            29370: 01/02/16: Chris Dunlap: Re: Configuration of FPGA using SPROM
                29387: 01/02/17: radhika: Re: Configuration of FPGA using SPROM
                    29400: 01/02/19: Chris Dunlap: Re: Configuration of FPGA using SPROM
                        29427: 01/02/20: radhika: Re: Configuration of FPGA using SPROM
    29381: 01/02/17: Kent Orthner: Re: Configuration of FPGA using SPROM
        29384: 01/02/17: Theron Hicks (Terry): Re: Configuration of FPGA using SPROM
            29386: 01/02/17: radhika: Re: Configuration of FPGA using SPROM
29310: 01/02/13: abdsamad benkrid: test
29313: 01/02/13: "erika churchil": ignore it
29318: 01/02/13: Richard B. Katz: 2001 MAPLD Conference - 1st Call for Papers
29319: 01/02/14: C.Schlehaus: Integrated Conf.EPROM / smaller Footprints?
    29320: 01/02/14: Ulf Samuelsson: Re: Integrated Conf.EPROM / smaller Footprints?
        29337: 01/02/15: Kent Orthner: Re: Integrated Conf.EPROM / smaller Footprints?
    29432: 01/02/21: Thorsten Bunte: Re: Integrated Conf.EPROM / smaller Footprints?
        29448: 01/02/21: C.Schlehaus: Re: Integrated Conf.EPROM / smaller Footprints?
            29452: 01/02/22: Kent Orthner: Re: Integrated Conf.EPROM / smaller Footprints?
29323: 01/02/14: Pascal Delouche: Problem with pipelined divider in Virtex
    29325: 01/02/14: Muzaffer Kal: Re: Problem with pipelined divider in Virtex
29324: 01/02/14: Matthias Fuchs: Duplicate definitions for timing specs (xilinx fnd)
    29326: 01/02/14: Jamie Sanderson: Re: Duplicate definitions for timing specs (xilinx fnd)
    29329: 01/02/14: Daniel O'Connell: Re: Duplicate definitions for timing specs (xilinx fnd)
29328: 01/02/14: Paul Smith: Spartan II power
    29331: 01/02/14: Falk Brunner: Re: Spartan II power
    29431: 01/02/21: Rick Collins: Re: Spartan II power
        29449: 01/02/21: Paul Smith: Re: Spartan II power
        29521: 01/02/24: Austin Lesea: Re: Spartan II power
            29527: 01/02/25: Rick Collins: Re: Spartan II power
                29535: 01/02/25: Falk Brunner: Re: Spartan II power
                    29536: 01/02/26: Peter Alfke: Re: Spartan II power
                        29542: 01/02/26: Jerry English: Re: Spartan II power
                            29549: 01/02/26: Austin Lesea: Re: Spartan II power
                                29592: 01/02/27: rk: Re: Spartan II power
                    29548: 01/02/26: Austin Lesea: Re: Spartan II power
                29547: 01/02/26: Austin Lesea: Re: Spartan II power
                    29553: 01/02/26: Simon Bacon: Re: Spartan II power
                    29567: 01/02/27: Rick Collins: Re: Spartan II power
                        29579: 01/02/27: Magnus Homann: Re: Spartan II power
                        29595: 01/02/27: Austin Lesea: Re: Spartan II power
                            29689: 01/03/05: Rick Collins: Re: Spartan II power
                    29574: 01/02/27: Ray Andraka: Re: Spartan II power
                        29576: 01/02/27: Simon Bacon: Re: Spartan II power
                        29597: 01/02/27: Rick Collins: Re: Spartan II power
                            29604: 01/02/28: Austin Lesea: Re: Spartan II power
                                29690: 01/03/05: Rick Collins: Re: Spartan II power
                                    29934: 01/03/19: Hal Murray: Re: Spartan II power
29341: 01/02/15: Dmitry Vodes: K-bus interface (ISO-9141)
29343: 01/02/15: Geert Van Doorselaer: Configuration file of SpartanXL
    29355: 01/02/15: Falk Brunner: Re: Configuration file of SpartanXL
    29356: 01/02/15: Philip Freidin: Re: Configuration file of SpartanXL
29346: 01/02/15: Ulises Hernandez: Bubble tristate
    29351: 01/02/15: Laurent Gauch: Re: Bubble tristate
29349: 01/02/15: Brian Borts: Alpha Job Consulting News
    29382: 01/02/17: Kent Orthner: Re: Alpha Job Consulting News
29357: 01/02/15: mark: Design of a divide by 6.5 counter ?
    29372: 01/02/16: Lukose Ninan: Re: Design of a divide by 6.5 counter ?
    29380: 01/02/17: Peter Alfke: Re: Design of a divide by 6.5 counter ?
29358: 01/02/15: Craig McAdam: Xilinx GSR in Verilog simulations
    29362: 01/02/16: <eml@riverside-machines.com.NOSPAM>: Re: Xilinx GSR in Verilog simulations
    29376: 01/02/16: Simon Bacon: Re: Xilinx GSR in Verilog simulations
        30276: 01/03/30: luu thanh trung: Re: Xilinx GSR in Verilog simulations
            30277: 01/03/30: Tom: Re: Xilinx GSR in Verilog simulations
29359: 01/02/16: Stan Ramsden: Xilinx XC18v04 programming via FPGA
    30079: 01/03/22: Tom Biggs: Re: Xilinx XC18v04 programming via FPGA
29360: 01/02/16: Kostas Marinis: Implementing a 64-bit/66MHz PCI controller
    29377: 01/02/16: Rick Filipkiewicz: Re: Implementing a 64-bit/66MHz PCI controller
29364: 01/02/16: Richard Meester: Optimization problem with SPARTANII
29365: 01/02/16: Ed Ngai: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29368: 01/02/16: hsdary: help
    29369: 01/02/16: Chris Dunlap: Re: help
29371: 01/02/16: Muzaffer Kal: DSPIA Inc. becomes Xilinx XPERTS Partner
29373: 01/02/16: Erik Wahlstrom: Vertex Place & Route Time
    29374: 01/02/16: Simon Bacon: Re: Vertex Place & Route Time
    29379: 01/02/16: Rick Filipkiewicz: Re: Vertex Place & Route Time
        29383: 01/02/17: Simon Bacon: Re: Vertex Place & Route Time
            29385: 01/02/17: Rick Filipkiewicz: Re: Vertex Place & Route Time
29378: 01/02/16: Joe C.: Altera process change....
    29393: 01/02/19: Rick Filipkiewicz: Re: Altera process change....
        29419: 01/02/20: Jean-Paul Smeets: Re: Altera process change....
    29433: 01/02/21: Nial Stewart: Re: Altera process change....
29388: 01/02/18: Mrcio Longaray: Samll quantities ordering
    29506: 01/02/23: Philip Freidin: Re: Samll quantities ordering
        29507: 01/02/23: Eric Smith: Re: Samll quantities ordering
            29584: 01/02/27: Eric Smith: Re: Samll quantities ordering
                29586: 01/02/27: Reinoud: Re: Samll quantities ordering
    29510: 01/02/24: Brian Goudy: Re: Samll quantities ordering
29389: 01/02/18: W.Turk: what
    29401: 01/02/19: Chris Dunlap: Re: what
29391: 01/02/18: Reto Zimmermann: Emacs VHDL Mode 3.32 beta
29392: 01/02/18: Gustav Jindra: XILINX WebPACK
29394: 01/02/19: Rajesh Bawankule: Verilog FAQ : February 2001
29395: 01/02/19: Heinrich Fonfara: Fine Phase Shift in VirtexII
    29404: 01/02/19: Peter Alfke: Re: Fine Phase Shift in VirtexII
    29418: 01/02/20: Erik Widding: Re: Fine Phase Shift in VirtexII
        29420: 01/02/20: Falk Brunner: Re: Fine Phase Shift in VirtexII
            29422: 01/02/20: Erik Widding: Re: Fine Phase Shift in VirtexII
    29446: 01/02/21: Heinrich Fonfara: Re: Fine Phase Shift in VirtexII
29397: 01/02/19: Zakharko Y.: problem with pogrammer for serial EPROM
29398: 01/02/19: ccu: ALtera CPLD
    29402: 01/02/19: Andy Peters: Re: ALtera CPLD
        29406: 01/02/20: Rick Filipkiewicz: Re: ALtera CPLD
    29405: 01/02/19: Muzaffer Kal: Re: ALtera CPLD
    29424: 01/02/21: luigi funes: Re: ALtera CPLD
29399: 01/02/19: kops: 1/32
29403: 01/02/19: Max L.: Infering DPRAM with both outputs
    29441: 01/02/21: Jaan Sirp: Re: Infering DPRAM with both outputs
    29451: 01/02/22: Me: Re: Infering DPRAM with both outputs
29407: 01/02/19: Arrigo Benedetti: meeting high hold time input requirement with Virtex
    29409: 01/02/20: Phil Hays: Re: meeting high hold time input requirement with Virtex
        29410: 01/02/20: Kent Orthner: Re: meeting high hold time input requirement with Virtex
29408: 01/02/20: Kent Orthner: 5 Clocks in a spartan-II
    29416: 01/02/20: Chris G. Schneider: Re: 5 Clocks in a spartan-II
        29425: 01/02/21: Kent Orthner: Re: 5 Clocks in a spartan-II
29411: 01/02/20: Helen Long: UCF problem "- Could not find NET "
    29412: 01/02/20: Richard Meester: Re: UCF problem "- Could not find NET "
    29414: 01/02/20: Laurent Gauch: Re: UCF problem "- Could not find NET "
    29415: 01/02/20: Dave Vanden Bout: Re: UCF problem "- Could not find NET "
    29417: 01/02/20: Chris G. Schneider: Re: UCF problem "- Could not find NET "
    29467: 01/02/22: Andy Peters: Re: UCF problem "- Could not find NET "
    29473: 01/02/22: Thomas: SV: UCF problem "- Could not find NET "
29413: 01/02/20: ajd: RSA on FPGA
    29436: 01/02/21: Bjrn B Larsen: Re: RSA on FPGA
29421: 01/02/20: "erika churchil": to you sir Peter Alfke...
    29423: 01/02/20: Chris Dunlap: Re: to you sir Peter Alfke...
    29443: 01/02/21: Falk Brunner: Re: to you sir Peter Alfke...
29426: 01/02/20: Neo WT: Virtex E:Sample price
    29428: 01/02/20: Dave Vanden Bout: Re: Virtex E:Sample price
    29429: 01/02/21: Pratip Mukherjee: Re: Virtex E:Sample price
    29468: 01/02/22: Peter Alfke: Re: Virtex E:Sample price
        29472: 01/02/22: Eric Smith: Re: Virtex E:Sample price
            29475: 01/02/22: Peter Alfke: Re: Virtex E:Sample price
        29480: 01/02/23: Simon Bacon: Re: Virtex E:Sample price
29430: 01/02/21: Sang-hee Lee: Xilinx CoreGen problem.
29434: 01/02/21: Sally Verkaik: Short Course Announcement
29435: 01/02/21: Goran: clock divider by 1.5
    29442: 01/02/21: Peter Alfke: Re: clock divider by 1.5
    29456: 01/02/22: Alex Gaivoronsky: Re: clock divider by 1.5
    29457: 01/02/22: Wolfgang Loewer: Re: clock divider by 1.5
    29458: 01/02/22: Utku Ozcan: Re: clock divider by 1.5
    29816: 01/03/12: goran: Re: clock divider by 1.5
        29820: 01/03/12: Ray Andraka: Re: clock divider by 1.5
        29822: 01/03/12: Bertram Geiger: Re: clock divider by 1.5
    29834: 01/03/13: goran: Re: clock divider by 1.5
29437: 01/02/21: Tom: Second Source For ALTERA EPC1 ?
    29460: 01/02/22: Giorgio Poli: Re: Second Source For ALTERA EPC1 ?
    29528: 01/02/25: Mark Korsloot: Re: Second Source For ALTERA EPC1 ?
29438: 01/02/21: Jon S.: Programming Altera CPLD?
    29455: 01/02/22: Brian Goudy: Re: Programming Altera CPLD?
        29464: 01/02/22: Jon S.: Re: Programming Altera CPLD?
            29476: 01/02/22: Brian Goudy: Re: Programming Altera CPLD?
    29470: 01/02/22: Steve Rencontre: Re: Programming Altera CPLD?
29439: 01/02/21: Reinoud: Xilinx tools: RLOC hierarchy with HDL design?
    29563: 01/02/27: Ray Andraka: Re: Xilinx tools: RLOC hierarchy with HDL design?
        29564: 01/02/27: Jan Gray: Re: Xilinx tools: RLOC hierarchy with HDL design?
            29569: 01/02/27: Simon Bacon: Re: Xilinx tools: RLOC hierarchy with HDL design?
            29570: 01/02/27: Reinoud: Re: Xilinx tools: RLOC hierarchy with HDL design?
                29571: 01/02/27: Reinoud: Re: Xilinx tools: RLOC hierarchy with HDL design?
                29572: 01/02/27: Ray Andraka: Re: Xilinx tools: RLOC hierarchy with HDL design?
                    29615: 01/03/01: BriMDavis: Re: Xilinx tools: RLOC hierarchy with HDL design?
                        29644: 01/03/03: Simon Bacon: Re: Xilinx tools: RLOC hierarchy with HDL design?
                29580: 01/02/27: Jan Gray: Re: Xilinx tools: RLOC hierarchy with HDL design?
                    29583: 01/02/27: Chris G. Schneider: Re: Xilinx tools: RLOC hierarchy with HDL design?
29440: 01/02/21: Frode Vatvedt Fjeld: Clocks
    29444: 01/02/21: Falk Brunner: Re: Clocks
        29445: 01/02/21: Frode Vatvedt Fjeld: Re: Clocks
            29447: 01/02/21: eteam: Re: Clocks
29450: 01/02/21: Jorge Neves: How to get Xilinx FPGA demo board?
    29459: 01/02/22: Laurent Gauch: Re: How to get Xilinx FPGA demo board?
        29756: 01/03/07: Austin Franklin: Re: How to get Xilinx FPGA demo board?
    29461: 01/02/23: Tony Burch: Re: How to get Xilinx FPGA demo board?
    29465: 01/02/22: Zimba: Re: How to get Xilinx FPGA demo board?
29453: 01/02/22: George P. Burdell: Virtex USB solution
    29454: 01/02/22: Muzaffer Kal: Re: Virtex USB solution
    29466: 01/02/22: Andy Peters: Re: Virtex USB solution
        29479: 01/02/23: Simon Bacon: Re: Virtex USB solution
        29565: 01/02/26: Austin Lesea: Re: Virtex USB solution
            29573: 01/02/27: Ray Andraka: Re: Virtex USB solution
            29609: 01/02/28: Andy Peters: Re: Virtex USB solution
                29726: 01/03/06: Felix Bertram: Re: Virtex USB solution
                    29738: 01/03/06: Andy Peters: Re: Virtex USB solution
                        29946: 01/03/19: Kolja Sulimma: Re: Virtex USB solution
    29485: 01/02/23: Felix Bertram: Re: Virtex USB solution
29462: 01/02/22: James Wallis: PCI : Not booting on ASUS
    29484: 01/02/23: Sosgez: Re: PCI : Not booting on ASUS
    29706: 01/03/05: James Wallis: Re: PCI : Not booting on ASUS
29463: 01/02/22: Mark: Virtex II availability
    29471: 01/02/22: Eric Smith: Re: Virtex II availability
    29478: 01/02/22: Rick Filipkiewicz: Re: Virtex II availability
        29550: 01/02/26: Peter Alfke: Re: Virtex II availability
    29657: 01/03/03: Eric Smith: Re: Virtex II availability
29469: 01/02/22: friedt jean-michel: fpga from linux/hc11
    29474: 01/02/22: Reinoud: Re: fpga from linux/hc11
        30289: 01/03/31: Gonzalo Arana: Re: fpga from linux/hc11
            30526: 01/04/12: Pericles: Re: fpga from linux/hc11
29477: 01/02/22: Yunjian William Jiang: Announcement of MVSIS release
29481: 01/02/23: "Jaimeet Aneja": Partial reconfig
    29482: 01/02/23: Kent Orthner: Re: Partial reconfig
    29487: 01/02/23: Phil James-Roxby: Re: Partial reconfig
        29562: 01/02/27: "Jaimeet Aneja": Re: Re: Partial reconfig
29483: 01/02/22: wayne: programmable coefficient fir filter?
    29486: 01/02/23: Phil James-Roxby: Re: programmable coefficient fir filter?
    29494: 01/02/23: Wolfgang Loewer: Re: programmable coefficient fir filter?
    29502: 01/02/23: wayne: Re: programmable coefficient fir filter?
        29590: 01/02/27: Ray Andraka: Re: programmable coefficient fir filter?
29488: 01/02/23: Nicolas Matringe: UCF mode for Emacs?
    29492: 01/02/23: Utku Ozcan: Re: UCF mode for Emacs?
        29495: 01/02/23: Gyles Harvey: UCF mode for vim (Re: UCF mode for Emacs?)
            29503: 01/02/23: Chris G. Schneider: Re: UCF mode for vim (Re: UCF mode for Emacs?)
    29504: 01/02/23: Chris G. Schneider: Re: UCF mode for Emacs?
29489: 01/02/23: mygenie: Help : Question about Synopsis
    29490: 01/02/23: Simon Bacon: Re: Help : Question about Synopsis
29491: 01/02/23: Alan Hall: Is anybody using Quicklogic PCI/FPGA devices?
    29501: 01/02/23: Steve Rencontre: Re: Is anybody using Quicklogic PCI/FPGA devices?
        29517: 01/02/24: John Larkin: Re: Is anybody using Quicklogic PCI/FPGA devices?
    29509: 01/02/24: Alan Hall: Re: Is anybody using Quicklogic PCI/FPGA devices?
        29526: 01/02/25: Steve Rencontre: Re: Is anybody using Quicklogic PCI/FPGA devices?
            29529: 01/02/25: Peter Alfke: Re: Is anybody using Quicklogic PCI/FPGA devices?
                29532: 01/02/25: Muzaffer Kal: Re: Is anybody using Quicklogic PCI/FPGA devices?
                    29534: 01/02/25: Peter Alfke: Re: Is anybody using Quicklogic PCI/FPGA devices?
                29552: 01/02/26: Steve Rencontre: Re: Is anybody using Quicklogic PCI/FPGA devices?
    29520: 01/02/24: S. Ramirez: Re: Is anybody using Quicklogic PCI/FPGA devices?
29493: 01/02/23: W.Turk: how do i?
29496: 01/02/23: Dmitri Katchalov: Getting started
29497: 01/02/23: AvdL: Searching for FPGA designer (PCI interface,DES, IDE)
    29499: 01/02/23: Laurent Gauch: Re: Searching for FPGA designer (PCI interface,DES, IDE)
    29559: 01/02/26: Tom Dillon: Re: Searching for FPGA designer (PCI interface,DES, IDE)
29498: 01/02/23: Seb C: ERROR on Xilinx fundation
    29500: 01/02/23: Falk Brunner: Re: ERROR on Xilinx fundation
        29515: 01/02/24: Rick Collins: Re: ERROR on Xilinx fundation
    29608: 01/02/28: Andy Peters: Re: ERROR on Xilinx fundation
29505: 01/02/23: Qian: UNISIM
    29602: 01/02/28: Ulises Hernandez: Re: UNISIM
    29607: 01/02/28: Andy Peters: Re: UNISIM
    29616: 01/03/01: Rmi SEGLIE: Re: UNISIM
    29617: 01/03/01: Rmi SEGLIE: Re: UNISIM
29508: 01/02/24: Prasanth Kumar: Viewing the netlist after synthesis of Verilog
29511: 01/02/24: Will: cpul vs vhdl
    29514: 01/02/24: Rick Collins: Re: cpul vs vhdl
        29516: 01/02/24: Will: Re: cpul vs vhdl
            29566: 01/02/27: Joel Kolstad: Re: cpul vs vhdl
                29581: 01/02/27: Bertram Geiger: Re: cpul vs vhdl
            29591: 01/02/28: Jim Granville: Re: cpul vs vhdl
            29606: 01/02/28: Andy Peters: Re: cpul vs vhdl
                29815: 01/03/12: Compilit: Re: cpul vs vhdl
    29522: 01/02/24: Brian Goudy: Re: cpul vs vhdl
    29531: 01/02/26: Jim Granville: Re: cpul vs vhdl
        29541: 01/02/26: Jamie Lokier: Re: cpul vs vhdl
        30149: 01/03/26: Richard Erlacher: Re: cpul vs vhdl
    29545: 01/02/26: Gil Golov: Re: cpul vs vhdl
    29589: 01/02/27: <NOSPAM@NOSPAM.NOSPAM>: Re: cpul vs vhdl
29512: 01/02/24: david garnett: Soldering and Unsoldering PQFP by hand ...
    29513: 01/02/24: Rick Filipkiewicz: Re: Soldering and Unsoldering PQFP by hand ...
    29518: 01/02/24: John Larkin: Re: Soldering and Unsoldering PQFP by hand ...
        29537: 01/02/25: Neo Wei Thiam: Re: Soldering and Unsoldering PQFP by hand ...
    29523: 01/02/25: Ed Ngai: Re: Soldering and Unsoldering PQFP by hand ...
29524: 01/02/25: Catalin Baetoniu: Metastability data for Spartan2, Virtex and VirtexE?
    29546: 01/02/26: Peter Alfke: Re: Metastability data for Spartan2, Virtex and VirtexE?
29525: 01/02/25: Pai H Chou: Call for Participation: PhD Forum at DAC (deadline March 16)
29530: 01/02/25: Chengping Zhang: I want to learn sth about FPGA
    29575: 01/02/27: Ray Andraka: Re: I want to learn sth about FPGA
29533: 01/02/25: Dan: VDHL Book recomendation please. Xilinx designer.
    29539: 01/02/26: Tony Burch: Re: VDHL Book recomendation please. Xilinx designer.
    29543: 01/02/26: Gil Golov: Re: VDHL Book recomendation please. Xilinx designer.
29538: 01/02/25: jim: answer
29540: 01/02/26: ajd: RE: Rijndael
    29551: 01/02/26: jmn: Re: Rijndael
29544: 01/02/26: Michael Boehnel: Virtex bidirectional pins
29554: 01/02/26: weMPEC: VHDL:case
    29555: 01/02/26: C.Schlehaus: Re: VHDL:case
    29557: 01/02/26: Chris Dunlap: Re: VHDL:case
    29558: 01/02/26: VhdlCohen: Re: VHDL:case
29556: 01/02/26: Reinoud: Linux Xilinx Programmer
29560: 01/02/27: James Lawrence: Computer Guide
29561: 01/02/27: "Jaimeet Aneja": Partial Reconfig using JBits
    29582: 01/02/27: Antti Lukats: Re: Partial Reconfig using JBits
        29593: 01/02/27: Neil Franklin: Re: Partial Reconfig using JBits
        29594: 01/02/28: "Jaimeet Aneja": Re: Re: Partial Reconfig using JBits
29578: 01/02/27: Vincent Monroe: Programming Vertex-II FPGAs.
29585: 01/02/27: Chris G. Schneider: Xilinx P&R problem?
29587: 01/02/27: InGenius Engineering: ASIC ASIC ASIC - CANADA - ASIC ASIC ASIC ASIC ASIC
29588: 01/02/27: Bard_64: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
    29596: 01/02/28: Rick Filipkiewicz: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
        29605: 01/02/28: Bard_64: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
        29613: 01/03/01: <yuryws@banet.net>: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
            29625: 01/03/02: Rick Filipkiewicz: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
                29627: 01/03/02: Muzaffer Kal: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
                    29636: 01/03/02: Rick Filipkiewicz: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
                        29639: 01/03/03: <muzaffer@dspia.com>: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
                        29666: 01/03/04: Eric Montreal: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
                            29675: 01/03/05: Rick Filipkiewicz: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
                29640: 01/03/03: <yuryws@banet.net>: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
    29614: 01/03/01: <yuryws@banet.net>: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
    29660: 01/03/04: Heinz Wolter: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
29598: 01/02/28: <Kelvin>: Virtex ambit support
    29599: 01/02/28: Muzaffer Kal: Re: Virtex ambit support
        29600: 01/02/28: <Kelvin>: Re: Virtex ambit support
            29601: 01/02/28: Muzaffer Kal: Re: Virtex ambit support
                29603: 01/02/28: Jerry English: Re: Virtex ambit support
            29668: 01/03/04: Vikram Pasham: Re: Virtex ambit support
29611: 01/02/28: Jonas Thor: SRAM vs. FLASH?
    29612: 01/03/01: Peter Alfke: Re: SRAM vs. FLASH?


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