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Make sure to keep your program pulse short. It should not be greater than .5ms. You should need to pulse program at all though, the FPGA will autoconfigure on powerup. I have never heard of DONE going high right at the start of configuration. I would very your board connections and make sure the pullup resistor is not too small. Use an o-scope and charachterize DIN, INIT, and DONE. It is rare for one of those FPGAs to be bad but if you have verified no board level problems, it could be possible that you have a bad device. You may want to try another one just to be sure. Of course, you may want to write out a raw bits file from the prom file formater to verify the data on din when o-scoping it. The .rbt file is easy to read in terms of figuring out the data being shifted into the device. Good luck, Chris radhika wrote: > hi chris, > I tried calling the support hotline and they would not answer my questions probably cos i am a student and they just asked me to send an email to xup@xilinx.com which I did thats about it . > I have connected my init signal to Vcc through a 4.7K and now the scenario has changed my init is low and when i apply a 0V pulse at my prog pin and remove the pulse init is going high along with prog pin but ldc adn done are going high at the same moment but i think atleast 3 to 4 clk pulses are required to start confn and how should the cclk be after the end of confn and my hdc is high both during and after configuration. > regards > radhikaArticle: 29401
Those are constraint attributes you can place on your RAM block if you wanted to initialize the RAM on powerup. It looks like you have elected not to initialize it so it will default to all zeros. Chris "W.Turk" wrote: > Hi : > The message occured when i use Foundation3.1 : > WARNING:NgdBuild:526 - On the RAMB4_S8_S8 symbol "p2/u1/bram4", the following > properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, > INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, > INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be used. > what's meaning? > How do i? > Thanks a lotArticle: 29402
ccu wrote: > > I found CPLD no internal tri-state buffer to share the same bus. > If there are more than 100 registers need to access via external cpu > bidirection data port(8051) . > How can i avoid the huge100:1 mux output? Choose an FPGA with internal tristates. --aArticle: 29403
Hello, The question refers to dual ported memory inferring using Leonardo Spectrum for synthesis and targeting Xilinx' Spartan XL device: How to infer both outputs of a dual ported memory's element (namely SPO and DPO of RAM16X1D) from plain Verilog. An attempt to write: //+++ module memdp64x1( raddr, waddr, do, do_at_wa, di, we, clk ); .... always @(posedge clk) if (we) mem[waddr] = di; assign do = mem[raddr]; assign do_at_wa = mem[waddr]; //--- results in 'plain' logic (sea of DFFs and LUTs). Any clues are welcome.Article: 29404
Heinrich, what you describe cannot be done with one DCM. It requires a fixed input frequency and can generate a fixed phase difference set by configuration, or it can step the phase in increments of ~50 ps forwards or backwards. Tell us what you want to achieve, and there might be a different way to do that with two DCMs if your pattern is fixed. Gruß Peter Alfke, Xilinx Applications P.S. Today is a holiday in the US: Presidents' Day ( Washington's and Lincoln's birthdays combined). Heinrich Fonfara wrote: > We intend to use the VirtexII device for inserting periods each x > nanoseconds in a clock with a period of y nanoseconds (for example 3 > periods with 8ns each, then 1 or 2 periods of 10ns, then some of 8ns and > so on......) so that the phase is shifted dynamically by 2 ns in a > certain direction. The shifting should be controlled by an appropriate > pulse. > In the data sheets I did not find enough information to know if that is > possible to realize it with DCM of VirtexII. > It would be great if someone could tell me where to get more information > about phase shifting applications. > > Thanks in advance > > Heinrich FonfaraArticle: 29405
"ccu" <d837928@oz.nthu.edu.tw> wrote: >I found CPLD no internal tri-state buffer to share the same bus. >If there are more than 100 registers need to access via external cpu >bidirection data port(8051) . >How can i avoid the huge100:1 mux output? > If you can't change your device to one which has internal tri-states, you can design a tree of muxes. You can do a three-level 4:1 mux tree with a 2:1 mux at the end to generate a 128:1 mux. This needs 42 4:1 muxes and a 2:1 mux. Muzaffer FPGA DSP Consulting http://www.dspia.comArticle: 29406
Andy Peters wrote: > ccu wrote: > > > > I found CPLD no internal tri-state buffer to share the same bus. > > If there are more than 100 registers need to access via external cpu > > bidirection data port(8051) . > > How can i avoid the huge100:1 mux output? > > Choose an FPGA with internal tristates. > > --a With up to 800 register bits he's going to need an FPGA anyway.Article: 29407
Dear all, I am interfacing a RAMDAC (IBM RGB526) to a Virtex device and I have found problems in meeting the DAC input hold time requirement with respect to its load clock, that can be as high as 4 ns. Since the Virtex min clock to out is 1.5ns this is clearly a problem if the DAC load clock is the same clock driving the output registers inside the FPGA. The solution that I have implemented is to have the Virtex generate the DAC clock by delaying the main pixel clock with a linear array of LUT1's configured as buffers. Is there any better way to solve this without resorting to an external clock management device like the Roboclock? Thanks, -ArrigoArticle: 29408
Okay, so I know that this topic has been covered before, and I've read through the Deja News (It's now google, with a much better interface), so I'm really only looking for some reassurance. I have 4x 77.76 clocks, not necessarily in phase or with exactly the same frequency, driving the four major blocks on the chip. I then have an processor interface block running at 52MHz. This bock doesn't really do much more than push stuff in a FIFO, and pop stuff off of it. I plan to have each 77.76MHz clock on a primary clock line, from a PLL. This leaves the 52MHz clock on a secondary clock line. I plan to keep all of the logic driven by the secondary clock line on the right side of the chip, with the exception of the BlockRAMs for the FIFO; they'll be on both sides. This leaves me with two questions: 1. Using the primary clock lines, I'm guaranteed not to have race conditions between FF inputs and CLK inputs. If I use the secondary clock lines, will I run into problems with this? Does trace handle this fairly well? 2. Where should I connect the pin for the secondary clock line? I figure it should be on the top, in the middle of the right half. Unfortunately, I have to choose the pin-out and get the PCB into fabrication, and *then* do the FPGA design, so I can't simply decide later when it's all said and done. Any comments, suggestions, and sweet nothings will be greatly appreciated. -KentArticle: 29409
Arrigo Benedetti wrote: > Is there any better way to solve this without resorting to an external > clock management device like the Roboclock? An idea is to put out the data on the other edge of clock. If the external device latches on the rising edge of clock, put out data after the falling edge of clock. Hold time is then a half a clock period. Setup time might be an issue, as it is less than a half a clock period. However, many devices with large hold times have small setup times. ____ ____ ____ ____ ____ / \____/ \____/ \____/ \____/ \____ ______ _________ _________ _________ _________ ______X_________X_________X_________X_________X -- Phil HaysArticle: 29410
> Arrigo Benedetti wrote: > > Is there any better way to solve this without resorting to an external > > clock management device like the Roboclock? Phil Hays <spampostmaster@home.com> writes: > An idea is to put out the data on the other edge of clock. If the external > device latches on the rising edge of clock, put out data after the falling edge > of clock. Hold time is then a half a clock period. Setup time might be an > issue, as it is less than a half a clock period. However, many devices with > large hold times have small setup times. Another variation on Phil's solution is to use the output of the Virtex DLL to drive your logic inside the FPGA. By using the +90, +180, or +270 delay output options from the DLL, you can skew your output data in 1/4 clock cycle increments. There's also fast vs. slow (Slew rate limited) output driver options that you can fiddle with. HTH, -KentArticle: 29411
Hi I am trying to generate bit file and download to XS40 board
I use XC40005XLPC84, but I can successfully implement it without
my own ucf file, it I connet my ucf file it fails
What is wrong? My code and my ucf file and error message are listed
below thanks a lot!
Qian
Here is my code
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity noGSR is
port(
CLOCK: in STD_LOGIC;
--RESET: in STD_LOGIC;
--HEX: in STD_LOGIC_VECTOR(3 downto 0);
LED: out STD_LOGIC_VECTOR(6 downto 0));
end noGSR;
architecture SIMPLE of noGSR is
signal HEX: STD_LOGIC_VECTOR(3 downto 0);
begin
HEX<="0000";
UP_COUNTER:process(CLOCK)
begin
-- if(RESET='1') then
if(CLOCK'event and CLOCK='1') then
HEX <= HEX + 1;
end if;
end process;
SHOW:process(HEX)
begin
....
end process;
end SIMPLE;
Here is my ucf file
NET CLOCK LOC=P13;
NET LED LOC=25,26,24,20,23,18,19;
And I use Xilinx Foundation 2.1l to implement it
it shows error
Annotating constraints to design from file "led.ucf" ...
ERROR:NgdHelpers:18 - Could not find NET "CLOCK" in design "led". NET entry
is
"NET CLOCK LOC=P13;
"
ERROR:NgdHelpers:18 - Could not find NET "LED" in design "led". NET entry
is
"NET LED LOC=25,26,24,20,23,18,19;
"
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "led.ucf".
One or more errors were found during NGDBUILD. No NGD file will be written.
Writing NGDBUILD log file "led.bld"...
==================================================
Article: 29412Helen, Best thing to do is to open the constraint editor, or the edif file with an editor, and look how the net is called. Probably the net is renamed by the ngdbuild or the mapper. Once you find the net you need, change the name in the UCF file. Richard Helen Long wrote: > Hi I am trying to generate bit file and download to XS40 board > I use XC40005XLPC84, but I can successfully implement it without > my own ucf file, it I connet my ucf file it fails > What is wrong? My code and my ucf file and error message are listed > below thanks a lot! > > Qian > > Here is my code > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_unsigned.all; > > entity noGSR is > port( > CLOCK: in STD_LOGIC; > --RESET: in STD_LOGIC; > --HEX: in STD_LOGIC_VECTOR(3 downto 0); > LED: out STD_LOGIC_VECTOR(6 downto 0)); > end noGSR; > > architecture SIMPLE of noGSR is > signal HEX: STD_LOGIC_VECTOR(3 downto 0); > > begin > HEX<="0000"; > UP_COUNTER:process(CLOCK) > begin > -- if(RESET='1') then > > if(CLOCK'event and CLOCK='1') then > HEX <= HEX + 1; > end if; > end process; > SHOW:process(HEX) > begin > .... > end process; > > end SIMPLE; > > Here is my ucf file > NET CLOCK LOC=P13; > NET LED LOC=25,26,24,20,23,18,19; > > And I use Xilinx Foundation 2.1l to implement it > it shows error > > Annotating constraints to design from file "led.ucf" ... > ERROR:NgdHelpers:18 - Could not find NET "CLOCK" in design "led". NET entry > is > "NET CLOCK LOC=P13; > " > ERROR:NgdHelpers:18 - Could not find NET "LED" in design "led". NET entry > is > "NET LED LOC=25,26,24,20,23,18,19; > > " > ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. > ERROR:NgdBuild:19 - Errors found while parsing constraint file "led.ucf". > > One or more errors were found during NGDBUILD. No NGD file will be written. > > Writing NGDBUILD log file "led.bld"... > > ================================================== -- Quest Innovations tel: +31 (0) 227 604046 http://www.quest-innovations.comArticle: 29413
Anyone ever done it? Which bits of the algorithm were implemented? AndrewArticle: 29414
Helen, The best way is to generate the .ucf automatically using Xilinx Design Manager tool (menu Design -> Lock Pins...). You will see directly what are your real pad names. Laurent for Amontec www.amontec.com ------------------------------------------------------ Amontec introduces a new PCI core development system Helen Long wrote: > Hi I am trying to generate bit file and download to XS40 board > I use XC40005XLPC84, but I can successfully implement it without > my own ucf file, it I connet my ucf file it fails > What is wrong? My code and my ucf file and error message are listed > below thanks a lot! > > Qian > > Here is my code > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_unsigned.all; > > entity noGSR is > port( > CLOCK: in STD_LOGIC; > --RESET: in STD_LOGIC; > --HEX: in STD_LOGIC_VECTOR(3 downto 0); > LED: out STD_LOGIC_VECTOR(6 downto 0)); > end noGSR; > > architecture SIMPLE of noGSR is > signal HEX: STD_LOGIC_VECTOR(3 downto 0); > > begin > HEX<="0000"; > UP_COUNTER:process(CLOCK) > begin > -- if(RESET='1') then > > if(CLOCK'event and CLOCK='1') then > HEX <= HEX + 1; > end if; > end process; > SHOW:process(HEX) > begin > ..... > end process; > > end SIMPLE; > > > Here is my ucf file > NET CLOCK LOC=P13; > NET LED LOC=25,26,24,20,23,18,19; > > And I use Xilinx Foundation 2.1l to implement it > it shows error > > Annotating constraints to design from file "led.ucf" ... > ERROR:NgdHelpers:18 - Could not find NET "CLOCK" in design "led". NET entry > is > "NET CLOCK LOC=P13; > " > ERROR:NgdHelpers:18 - Could not find NET "LED" in design "led". NET entry > is > "NET LED LOC=25,26,24,20,23,18,19; > > > " > ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. > ERROR:NgdBuild:19 - Errors found while parsing constraint file "led.ucf". > > One or more errors were found during NGDBUILD. No NGD file will be written. > > Writing NGDBUILD log file "led.bld"... > > ==================================================Article: 29415
Helen Long wrote: > Hi I am trying to generate bit file and download to XS40 board > I use XC40005XLPC84, but I can successfully implement it without > my own ucf file, it I connet my ucf file it fails > What is wrong? My code and my ucf file and error message are listed > below thanks a lot! You might try expanding your constraint into individual constraints as follows: NET LED<0> LOC=P25; NET LED<1> LOC=P26; ... > > > Qian > > Here is my code > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_unsigned.all; > > entity noGSR is > port( > CLOCK: in STD_LOGIC; > --RESET: in STD_LOGIC; > --HEX: in STD_LOGIC_VECTOR(3 downto 0); > LED: out STD_LOGIC_VECTOR(6 downto 0)); > end noGSR; > > architecture SIMPLE of noGSR is > signal HEX: STD_LOGIC_VECTOR(3 downto 0); > > begin > HEX<="0000"; > UP_COUNTER:process(CLOCK) > begin > -- if(RESET='1') then > > if(CLOCK'event and CLOCK='1') then > HEX <= HEX + 1; > end if; > end process; > SHOW:process(HEX) > begin > .... > end process; > > end SIMPLE; > > Here is my ucf file > NET CLOCK LOC=P13; > NET LED LOC=25,26,24,20,23,18,19; > > And I use Xilinx Foundation 2.1l to implement it > it shows error > > Annotating constraints to design from file "led.ucf" ... > ERROR:NgdHelpers:18 - Could not find NET "CLOCK" in design "led". NET entry > is > "NET CLOCK LOC=P13; > " > ERROR:NgdHelpers:18 - Could not find NET "LED" in design "led". NET entry > is > "NET LED LOC=25,26,24,20,23,18,19; > > " > ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. > ERROR:NgdBuild:19 - Errors found while parsing constraint file "led.ucf". > > One or more errors were found during NGDBUILD. No NGD file will be written. > > Writing NGDBUILD log file "led.bld"... > > ================================================== -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||Article: 29416
Kent Orthner <korthner@hotmail.nospam.com> writes: > I have 4x 77.76 clocks, not necessarily in phase or with > exactly the same frequency, driving the four major blocks > on the chip. I then have an processor interface block > running at 52MHz. This bock doesn't really do much > more than push stuff in a FIFO, and pop stuff off of it. > > I plan to have each 77.76MHz clock on a primary clock line, > from a PLL. > > This leaves the 52MHz clock on a secondary clock line. I > plan to keep all of the logic driven by the secondary clock > line on the right side of the chip, with the exception of the > BlockRAMs for the FIFO; they'll be on both sides. > > This leaves me with two questions: > > 1. Using the primary clock lines, I'm guaranteed not to have > race conditions between FF inputs and CLK inputs. If I use > the secondary clock lines, will I run into problems with this? > Does trace handle this fairly well? Clock skew may be a problem. One time I used a secondary clock for a clock with 39 MHz (without intension) and it worked with no problems. There were a lot of really large counters driven by this "clock" net. As far as I remember, trace calculates the clock skew as well. > 2. Where should I connect the pin for the secondary clock line? > I figure it should be on the top, in the middle of the right half. It would be best to but in the center of yout logic. Unfortunately the pads are at the edge of the die :-). But try to avoid long routing delays. > Unfortunately, I have to choose the pin-out and get the PCB > into fabrication, and *then* do the FPGA design, so I can't > simply decide later when it's all said and done. We do it that way, too. This saves a lot of time. It just reqiures good communication between FPGA and PCB designers. > Any comments, suggestions, and sweet nothings will be > greatly appreciated. You did not mention your application, but the four nearly identical clock just raise the question whether you can combine them. External phase differnce may be comensated by using the DLLs, but ask the experts on this subject. One other thig is that 52Mhz * 1.5 = 78 MHz approx 77.76 MHz. Can you derive the 52 MHz from 77.76 MHz? Or why don't you use 77.76 MHz for your processor interface? -- ChrisArticle: 29417
"Helen Long" <madisonfff@usa.net> writes: > Hi I am trying to generate bit file and download to XS40 board > I use XC40005XLPC84, but I can successfully implement it without > my own ucf file, it I connet my ucf file it fails > What is wrong? My code and my ucf file and error message are listed > below thanks a lot! > > Qian > > Here is my code > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_unsigned.all; > > entity noGSR is > port( > CLOCK: in STD_LOGIC; > --RESET: in STD_LOGIC; > --HEX: in STD_LOGIC_VECTOR(3 downto 0); > LED: out STD_LOGIC_VECTOR(6 downto 0)); > end noGSR; > > architecture SIMPLE of noGSR is > signal HEX: STD_LOGIC_VECTOR(3 downto 0); > > begin > HEX<="0000"; > UP_COUNTER:process(CLOCK) > begin > -- if(RESET='1') then > > if(CLOCK'event and CLOCK='1') then > HEX <= HEX + 1; > end if; > end process; > SHOW:process(HEX) > begin > .... > end process; > > end SIMPLE; > > > Here is my ucf file > NET CLOCK LOC=P13; > NET LED LOC=25,26,24,20,23,18,19; > > And I use Xilinx Foundation 2.1l to implement it > it shows error > > Annotating constraints to design from file "led.ucf" ... > ERROR:NgdHelpers:18 - Could not find NET "CLOCK" in design "led". NET entry > is > "NET CLOCK LOC=P13; > " > ERROR:NgdHelpers:18 - Could not find NET "LED" in design "led". NET entry > is > "NET LED LOC=25,26,24,20,23,18,19; > > > " > ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. > ERROR:NgdBuild:19 - Errors found while parsing constraint file "led.ucf". > > One or more errors were found during NGDBUILD. No NGD file will be written. > > Writing NGDBUILD log file "led.bld"... > > ================================================== > > > > > Did you connect LED <= HEX ? -- ChrisArticle: 29418
"Heinrich Fonfara" <fonfarah@ibmt.fhg.de> wrote in message
news:3A9102B2.D72DC65F@ibmt.fhg.de...
> We intend to use the VirtexII device for inserting periods each x
> nanoseconds in a clock with a period of y nanoseconds (for example 3
> periods with 8ns each, then 1 or 2 periods of 10ns, then some of 8ns and
> so on......) so that the phase is shifted dynamically by 2 ns in a
> certain direction. The shifting should be controlled by an appropriate
> pulse.
> In the data sheets I did not find enough information to know if that is
> possible to realize it with DCM of VirtexII.
You couldn't do this in one DCM. But you could do this with three DCMs, two
LUTs and a BUFGMUX.
Use one DCM to create a clock with period Y, and 50% duty cycle, call this
signal Y1.
Use a second DCM to phase shift Y1 by -Y/2 + 8nS, call this signal X1.
Use a second DCM to phase shift Y1 by -Y/2 + 10nS, call this signal X2.
Use two LUTs to produce the following signals:
XP1 = Y1 and X1
XP2 = Y1 and X2
Use a BUFGMUX to switch between XP1 and XP2.
I make no claims that this is a reasonable solution to the problem. I only
claim that it probably won't glitch if:
X is less than 1/2Y - a couple of nS.
You floorplan the circuit, or atleast define max delays to ensure
somewhat matched skew.
The reason for this is that any two input circuit represented in a LUT will
not glitch as long as only one input changes at a time. Hence the reason
for subtracting a couple extra nS.
DCM and BUFGMUX are definitely pretty cool elements in the Virtex-II
architecture. Thuimbs up to Xilinx on this one...
Regards,
Erik Widding.
--
Birger Engineering, Inc. -------------------------------- 781.481.9233
38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.com
Article: 29419On Mon, 19 Feb 2001 08:35:17 +0000, Rick Filipkiewicz <rick@algor.co.uk> wrote: >> Arcane question, but... >> Has anyone had trouble with Altera's 10K50V devices following the >> process change from E50 to F51 over the course of last year? >> We have 10-for-10 bad pcbs that have F51s, that work with E50s. >> They went from 3 to 4-layer metal, same fabs/geometry. >> Thanks! >> Joe Curren >> Printrex, Inc. > >Don't know Altera specifically but I've come across similar situations >before. Causes were either: > >o The new process is faster & so is leading to hold time problems >somehwhere. > >o The metatstability characteristics have changed - got worse. Unlikely >if the first possibility is true. I have seen something similar when we used a faster version of an FPGA. These were also hold time problems. However there is a trick you can use to verify this. We normally use a cooling spray to cool the FPGA from 25 C (room temperature) to well below 0C. Simply cool the FPGA till the outside turns completely white (water in the air forms a thin layer of snow). This can be used to simulate faster versions of the device. If you just meet your hold time, cooling the device will cause it to fail. J.P. Smeets J.P. Smeets business: Ellips Woenselsestr 352A 5623 EG Eindhoven tel: +31-40-2456540 fax: +31-40-2467183 email: jeanpaul@ellips.nl home: Loondermolen 23 5612 MH Eindhoven tel: +31-40-2465105 email: jpsmeets@xs4all.nlArticle: 29420
Erik Widding schrieb: > > You couldn't do this in one DCM. But you could do this with three DCMs, two > LUTs and a BUFGMUX. > > Use one DCM to create a clock with period Y, and 50% duty cycle, call this > signal Y1. > Use a second DCM to phase shift Y1 by -Y/2 + 8nS, call this signal X1. > Use a second DCM to phase shift Y1 by -Y/2 + 10nS, call this signal X2. > Use two LUTs to produce the following signals: > XP1 = Y1 and X1 > XP2 = Y1 and X2 > Use a BUFGMUX to switch between XP1 and XP2. > > I make no claims that this is a reasonable solution to the problem. I only > claim that it probably won't glitch if: > X is less than 1/2Y - a couple of nS. > You floorplan the circuit, or atleast define max delays to ensure > somewhat matched skew. Hmmm, I dont think thats a really FINE resolution, this can be also done with a high speed clock (say 200MHz). This gives you a resolution of 5ns (2.5ns if you can manage to use both edges.) I did this for a digital PLL in a Spartan II -5 device @150 MHz (Yeahh, I know, sounds like DC for the high speed guys ;-)) A question to the Xilinx guys. Why dont you let the user (me ;-)) access the delay line directly, so that the user defined logic can control on which tap the delay line is taped?? This would be VERY nice for frequency synthesizer/PLLs based on DDS (I saw a chip on PLAIN OLD 0.8u technology which had a 32 tap delay line running at 100MHz with a delay of 150ps per tap, which gives you a so called virtual frequency resolution of 3.2 GHz) With the 45ps of Virtex II this would be MUCH better. -- MFG FalkArticle: 29421
Hello, Last week, i asked if a disabled FDC still consumes power or now. The answer of PETER said that a disabled FDC consumes as much power as a clocked FDC but with a constant input. could you tell me how,generally ,we compute a power ?, and what's the ratio between the power consumed by a disabled FDC and the power consumed by an FDC fed by an input that toggles continuosely between 1 and 0 ? Anticipated thanks --Erika _________________________________________________________________________ Get Your Private, Free E-mail from MSN Hotmail at http://www.hotmail.com. -- Posted from [143.117.60.33] by way of f223.law4.hotmail.com [216.33.149.223] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 29422
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:3A92E72A.AE9D5F54@gmx.de... > Erik Widding schrieb: > > > > I make no claims that this is a reasonable solution to the problem. I only > > claim that it probably won't glitch if: > > X is less than 1/2Y minus a couple of nS. > > You floorplan the circuit, or atleast define max delays to ensure > > somewhat matched skew. > > Hmmm, I dont think thats a really FINE resolution, this can be also done > with a high speed clock (say 200MHz). > This gives you a resolution of 5ns (2.5ns if you can manage to use both > edges.) I must admit writing the post a little too quickly, and possibly leaving too much for the reader to conclude. I made no statements about resolution, which happens to be as good as that of the DCM, i.e. 100pS range, BUT you can only switch between two pulse widths. So if you need a third pulse width you would need to spend enough time outputting the pulses X1 while you change the pulse width X2, using a state machine to control phase shift on the DCM. > I did this for a digital PLL in a Spartan II -5 device @150 MHz (Yeahh, > I know, sounds like DC for the high speed guys ;-)) Technically, this would be a DLL. And it is an option. If one used the 0 and 180 outputs of a DCM to drive two state machines one should easily be able to create output pulses with a resolution of ~1400pS ( 1/(360MHz*2) the max speed of DCM in -4) and an accuracy of better than 500pS (error dominated by max delay through LUT for 4 input function in -4). Using the three DCMs merely gets you about 10X the resolution, and about the same accuracy, with some serious limitations of course. Regards, Erik Widding. -- Birger Engineering, Inc. -------------------------------- 781.481.9233 38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.comArticle: 29423
The power calculators should take that into account for you. You will say in the power calculator how many flops you have, then seperately what the toggle rate is on those flops. That seems to be the obvious answer although I missed the first question and the answer so you could be going down a completely different route than what I answered :) Chris erika churchil wrote: > Hello, > > Last week, i asked if a disabled FDC still consumes power or now. > The answer of PETER said that a disabled FDC consumes as much power as a > clocked FDC but with a constant input. > > could you tell me how,generally ,we compute a power ?, and what's the ratio > between the power consumed by a disabled FDC and the power consumed by an > FDC fed by an input that toggles continuosely between 1 and 0 ? > > Anticipated thanks > > --Erika > _________________________________________________________________________ > Get Your Private, Free E-mail from MSN Hotmail at http://www.hotmail.com. > > -- > Posted from [143.117.60.33] by way of f223.law4.hotmail.com [216.33.149.223] > via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 29424
ccu ha scritto nel messaggio <96rb23$oo7$1@thccy25.nthu.edu.tw>... >I found CPLD no internal tri-state buffer to share the same bus. >If there are more than 100 registers need to access via external cpu >bidirection data port(8051) . >How can i avoid the huge100:1 mux output? If you don't need speed, you could access it serially, as a shift register. Luigi
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