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Threads Starting Mar 2008

129639: 08/03/01: sami: HELP > Face/Edge detection on FPGA
    129652: 08/03/02: MM: Re: HELP > Face/Edge detection on FPGA
    129656: 08/03/02: Alex Colvin: Re: HELP > Face/Edge detection on FPGA
    129674: 08/03/02: mh: Re: HELP > Face/Edge detection on FPGA
129640: 08/03/01: sdf: Quartus 7.2sp2 memory exhaustion
129642: 08/03/01: Antti: FPGA's be afraid, very afraid, of my wife!
    129643: 08/03/01: Arlet Ottens: Re: FPGA's be afraid, very afraid, of my wife!
    129644: 08/03/01: Falk Brunner: Re: FPGA's be afraid, very afraid, of my wife!
    129645: 08/03/01: Antti: Re: FPGA's be afraid, very afraid, of my wife!
    129650: 08/03/01: Gabor: Re: FPGA's be afraid, very afraid, of my wife!
    129651: 08/03/02: MM: Re: FPGA's be afraid, very afraid, of my wife!
129649: 08/03/01: cwoodring: Avnet/Memec V4FX12LC proto card and SysGen
    129755: 08/03/04: Bryan: Re: Avnet/Memec V4FX12LC proto card and SysGen
        129881: 08/03/07: cwoodring: Re: Avnet/Memec V4FX12LC proto card and SysGen
129658: 08/03/02: sriman: clock generation
    129693: 08/03/03: Dave Pollum: Re: clock generation
129661: 08/03/02: rickman: Synplify crashing
    129662: 08/03/02: rickman: Re: Synplify crashing
129667: 08/03/02: <wmwmurray@gmail.com>: FPGA/CPLD group on LinkedIn
    129668: 08/03/02: <sky465nm@trline5.org>: Re: FPGA/CPLD group on LinkedIn
        129675: 08/03/02: John_H: Re: FPGA/CPLD group on LinkedIn
        129691: 08/03/03: Symon: Re: FPGA/CPLD group on LinkedIn
        129709: 08/03/03: <sky465nm@trline5.org>: Re: FPGA/CPLD group on LinkedIn
    129670: 08/03/02: <wmwmurray@gmail.com>: Re: FPGA/CPLD group on LinkedIn
    129689: 08/03/03: rickman: Re: FPGA/CPLD group on LinkedIn
    129690: 08/03/03: rickman: Re: FPGA/CPLD group on LinkedIn
    129763: 08/03/04: <wmwmurray@gmail.com>: Re: FPGA/CPLD group on LinkedIn
129679: 08/03/02: Antti: Virtex-5 FXT coming soon?
    129680: 08/03/03: Kolja Sulimma: Re: Virtex-5 FXT coming soon?
        129702: 08/03/03: BobW: Re: Virtex-5 FXT coming soon?
            130989: 08/04/07: Ed McGettigan: Re: Virtex-5 FXT coming soon?
    129683: 08/03/03: Antti: Re: Virtex-5 FXT coming soon?
    129695: 08/03/03: Kolja Sulimma: Re: Virtex-5 FXT coming soon?
    129696: 08/03/03: Antti: Re: Virtex-5 FXT coming soon?
    130424: 08/03/23: <pmulliki@yahoo.com>: Re: Virtex-5 FXT coming soon?
    130931: 08/04/05: Simon: Re: Virtex-5 FXT coming soon?
    130935: 08/04/05: Peter Alfke: Re: Virtex-5 FXT coming soon?
    130985: 08/04/07: Simon: Re: Virtex-5 FXT coming soon?
129697: 08/03/03: Kolja Sulimma: clock distribution accross boards
    129701: 08/03/03: Peter Alfke: Re: clock distribution accross boards
    129703: 08/03/03: John_H: Re: clock distribution accross boards
    129705: 08/03/03: Symon: Re: clock distribution accross boards
    129706: 08/03/03: austin: Re: clock distribution accross boards
    129717: 08/03/03: MM: Re: clock distribution accross boards
        129749: 08/03/04: MM: Re: clock distribution accross boards
    129728: 08/03/04: Kolja Sulimma: Re: clock distribution accross boards
    129729: 08/03/04: Kolja Sulimma: Re: clock distribution accross boards
    129730: 08/03/04: Kolja Sulimma: Re: clock distribution accross boards
    129732: 08/03/04: Kolja Sulimma: Re: clock distribution accross boards
    129751: 08/03/04: John_H: Re: clock distribution accross boards
    129771: 08/03/05: Kolja Sulimma: Re: clock distribution accross boards
    129775: 08/03/05: KJ: Re: clock distribution accross boards
129699: 08/03/03: Xesium: ICAP for readback on Microblaze...
129700: 08/03/03: Xesium: ICAP for readback on Microblaze...
129707: 08/03/03: Antti: my Spartan-4 wishlist
    129713: 08/03/03: DJ Delorie: Re: my Spartan-4 wishlist
        129719: 08/03/03: <sky465nm@trline5.org>: Re: my Spartan-4 wishlist
        129723: 08/03/04: Kim Enkovaara: Re: my Spartan-4 wishlist
        129731: 08/03/04: Rainer Buchty: Re: my Spartan-4 wishlist
        129762: 08/03/05: DJ Delorie: Re: my Spartan-4 wishlist
    129715: 08/03/03: M.Randelzhofer: Re: my Spartan-4 wishlist
        129718: 08/03/03: Nico Coesel: Re: my Spartan-4 wishlist
            129784: 08/03/05: Nico Coesel: Re: my Spartan-4 wishlist
    129716: 08/03/03: Antti: Re: my Spartan-4 wishlist
    129720: 08/03/03: Sean Durkin: Re: my Spartan-4 wishlist
    129745: 08/03/04: Antti: Re: my Spartan-4 wishlist
    129759: 08/03/04: rickman: Re: my Spartan-4 wishlist
    129760: 08/03/04: rickman: Re: my Spartan-4 wishlist
    129761: 08/03/04: rickman: Re: my Spartan-4 wishlist
    129764: 08/03/04: rickman: Re: my Spartan-4 wishlist
    129765: 08/03/04: Antti: Re: my Spartan-4 wishlist
    129774: 08/03/05: rickman: Re: my Spartan-4 wishlist
    129776: 08/03/05: Antti: Re: my Spartan-4 wishlist
    132272: 08/05/20: PFC: Re: my Spartan-4 wishlist
        132283: 08/05/20: Uwe Bonnes: Re: my Spartan-4 wishlist
            132287: 08/05/20: PFC: Re: my Spartan-4 wishlist
129708: 08/03/03: Dwayne Dilbeck: "Use Multi-level Logic Optimization" -- Advanced Fitting option
    129711: 08/03/03: DJ Delorie: Re: "Use Multi-level Logic Optimization" -- Advanced Fitting option
        129714: 08/03/03: Dwayne Dilbeck: Re: "Use Multi-level Logic Optimization" -- Advanced Fitting option
129712: 08/03/03: FPGA: verifying UNIFORM using matlab
    129726: 08/03/04: Tricky: Re: verifying UNIFORM using matlab
    129739: 08/03/04: FPGA: Re: verifying UNIFORM using matlab
    129740: 08/03/04: Tricky: Re: verifying UNIFORM using matlab
    129741: 08/03/04: FPGA: Re: verifying UNIFORM using matlab
    129742: 08/03/04: Tricky: Re: verifying UNIFORM using matlab
    129753: 08/03/04: FPGA: Re: verifying UNIFORM using matlab
    129816: 08/03/05: ajjc: Re: verifying UNIFORM using matlab
129724: 08/03/03: mani: reconfiguration of virtex 2 pro
129734: 08/03/04: Olaf: PARAMETER C_SPLIT error
    129735: 08/03/04: Olaf: Re: PARAMETER C_SPLIT error
    129736: 08/03/04: Andreas Hofmann: Re: PARAMETER C_SPLIT error
        129737: 08/03/04: Olaf: Re: PARAMETER C_SPLIT error
129743: 08/03/04: <manuel-lozano@mixmail.com>: FPGA for a DVB common interface implementation
129744: 08/03/04: <manuel-lozano@mixmail.com>: FPGA for a DVB common interface implementation
    129748: 08/03/04: <sky465nm@trline5.org>: Re: FPGA for a DVB common interface implementation
129746: 08/03/04: sdf: [Altera] How to infer some code into ROM-blocks (in automatic way),
    129747: 08/03/04: sdf: Re: How to infer some code into ROM-blocks (in automatic way), but
    129756: 08/03/05: Mark McDougall: Re: [Altera] How to infer some code into ROM-blocks (in automatic
129750: 08/03/04: Frai: AES Bitstream Encryption in Virtex-4. How safe it is?
    129752: 08/03/04: austin: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
        129778: 08/03/06: Allan Herriman: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
            129780: 08/03/05: austin: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
                129783: 08/03/06: Allan Herriman: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
                    129785: 08/03/05: austin: Removal of a feature, moving SCD to production
                        129792: 08/03/06: Allan Herriman: Re: Removal of a feature, moving SCD to production
                            129796: 08/03/05: austin: Re: Removal of a feature, moving SCD to production
    129754: 08/03/04: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
        129788: 08/03/05: austin: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
            129797: 08/03/05: <sky465nm@trline5.org>: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
                129799: 08/03/05: austin: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
                    129827: 08/03/06: Eric Smith: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
            129798: 08/03/05: austin: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
                129801: 08/03/05: Sean Durkin: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
            129806: 08/03/05: Nico Coesel: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
                129808: 08/03/05: austin: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
            129812: 08/03/06: Andreas Ehliar: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
            129826: 08/03/06: Eric Smith: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
                129836: 08/03/06: austin: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
                    129840: 08/03/07: Allan Herriman: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
                        129844: 08/03/06: austin: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
                            129846: 08/03/07: Allan Herriman: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
                        129845: 08/03/06: austin: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
            148955: 10/09/15: kenS: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
    129769: 08/03/05: Frai: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
    129773: 08/03/05: <jetmarc@hotmail.com>: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
    129790: 08/03/05: Antti: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
    129828: 08/03/06: diogratia: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
    129829: 08/03/06: diogratia: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
    148960: 10/09/15: Ed McGettigan: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129758: 08/03/05: jtw: Re: Blast from the past
    129805: 08/03/06: Dejan: Re: Blast from the past
        129843: 08/03/07: Jim Granville: Re: Blast from the past
129768: 08/03/05: nezhate: Bit Error Rate Test
    129779: 08/03/05: rickman: Re: Bit Error Rate Test
    129782: 08/03/06: Allan Herriman: Re: Bit Error Rate Test
        129789: 08/03/05: Symon: Re: Bit Error Rate Test
            129791: 08/03/06: Allan Herriman: Re: Bit Error Rate Test
    129813: 08/03/05: nezhate: Re: Bit Error Rate Test
129770: 08/03/05: Olaf: EDK 9.2 MicroBlaze Tutorial and SDRAM TestApp_memory
    129825: 08/03/06: Guru: Re: EDK 9.2 MicroBlaze Tutorial and SDRAM TestApp_memory
129772: 08/03/05: maverick: PCI Timing Contraints ignored
    129815: 08/03/05: maverick: Re: PCI Timing Contraints ignored
        129834: 08/03/06: John_H: Re: PCI Timing Contraints ignored
129781: 08/03/05: <sky465nm@trline5.org>: Spartan-3E + SPI EEPROM
    129795: 08/03/05: Antti: Re: Spartan-3E + SPI EEPROM
        129849: 08/03/07: <sky465nm@trline5.org>: Re: Spartan-3E + SPI EEPROM
            129878: 08/03/08: <sky465nm@trline5.org>: Re: Spartan-3E + SPI EEPROM
        129858: 08/03/07: Gabor: Re: Spartan-3E + SPI EEPROM
        129859: 08/03/07: Antti: Re: Spartan-3E + SPI EEPROM
        129874: 08/03/07: Gabor: Re: Spartan-3E + SPI EEPROM
129786: 08/03/05: jon: Virtex 5
129787: 08/03/05: Antti: Anyone to open "FPGA museum" ? Here is first item :)
    129793: 08/03/05: <sky465nm@trline5.org>: Re: Anyone to open "FPGA museum" ? Here is first item :)
        129807: 08/03/06: <sky465nm@trline5.org>: Re: Anyone to open "FPGA museum" ? Here is first item :)
        129817: 08/03/06: MM: Re: Anyone to open "FPGA museum" ? Here is first item :)
        129872: 08/03/07: Derek Palmer: Re: Anyone to open "FPGA museum" ? Here is first item :)
    129794: 08/03/05: Antti: Re: Anyone to open "FPGA museum" ? Here is first item :)
    129803: 08/03/05: Dwayne Dilbeck: Re: Anyone to open "FPGA museum" ? Here is first item :)
        129818: 08/03/06: MM: Re: Anyone to open "FPGA museum" ? Here is first item :)
    129820: 08/03/05: Antti: Re: Anyone to open "FPGA museum" ? Here is first item :)
    129821: 08/03/05: Antti: Re: Anyone to open "FPGA museum" ? Here is first item :)
    129823: 08/03/05: Antti: Re: Anyone to open "FPGA museum" ? Here is first item :)
    129824: 08/03/06: -jg: Re: Anyone to open "FPGA museum" ? Here is first item :)
    129856: 08/03/07: Totally_Lost: Re: Anyone to open "FPGA museum" ? Here is first item :)
129800: 08/03/05: Dan K: could use some help with verilog/vhdl
    129802: 08/03/05: Dwayne Dilbeck: Re: could use some help with verilog/vhdl
        129819: 08/03/05: PatC: Re: could use some help with verilog/vhdl
129804: 08/03/05: Fei Liu: question about verilog language constructs
    129809: 08/03/05: Dwayne Dilbeck: Re: question about verilog language constructs
    129810: 08/03/05: Fei Liu: Re: question about verilog language constructs
    129811: 08/03/05: lm317t: Re: question about verilog language constructs
129814: 08/03/05: <kiransr.ckm@gmail.com>: how to optimize a design for speed
    129822: 08/03/06: backhus: Re: how to optimize a design for speed
    129839: 08/03/06: Mike Treseler: Re: how to optimize a design for speed
129830: 08/03/06: Pablo: I could run my program at DDR Sdram.
    129831: 08/03/06: morphiend: Re: I could run my program at DDR Sdram.
    129832: 08/03/06: Gabor: Re: I could run my program at DDR Sdram.
    129837: 08/03/06: Pablo: Re: I could run my program at DDR Sdram.
129833: 08/03/06: <paragon.john@gmail.com>: 802.16d with Xilinx Viterbi Decoder
129835: 08/03/06: CTSportPilot: Re: Blast from the past
129838: 08/03/06: John_H: Re: Blast from the past
129841: 08/03/06: KJ: Re: Blast from the past
129842: 08/03/06: CTSportPilot: Re: Blast from the past
129848: 08/03/07: John Williams: MicroBlaze MMU support test release now available
129850: 08/03/06: Fei Liu: XC3S50-4VQ100C fpga chip
    129864: 08/03/07: Dave Pollum: Re: XC3S50-4VQ100C fpga chip
    129890: 08/03/08: lm317t: Re: XC3S50-4VQ100C fpga chip
        129964: 08/03/11: glen herrmannsfeldt: Re: XC3S50-4VQ100C fpga chip
    129894: 08/03/08: Fei Liu: Re: XC3S50-4VQ100C fpga chip
    129905: 08/03/09: Leon: Re: XC3S50-4VQ100C fpga chip
    129911: 08/03/10: Jim Granville: Re: XC3S50-4VQ100C fpga chip
129851: 08/03/06: Yao Sics: how to Load file data into memory by NIOS II IDE?
    129855: 08/03/07: <=?ISO-8859-1?Q?G=F3rski_Adam?=>: Re: how to Load file data into memory by NIOS II IDE?
129852: 08/03/06: chestnut: Xilinx MIG2.0 DDR2 memory controller
    129854: 08/03/07: techG: Re: Xilinx MIG2.0 DDR2 memory controller
129853: 08/03/07: Uwe Bonnes: Spartan-3A DSP Starter: JX Connector Part number
    129860: 08/03/07: John_H: Re: Spartan-3A DSP Starter: JX Connector Part number
        129861: 08/03/07: Uwe Bonnes: Re: Spartan-3A DSP Starter: JX Connector Part number
        129927: 08/03/10: Bryan: Re: Spartan-3A DSP Starter: JX Connector Part number
129857: 08/03/07: =?ISO-8859-1?Q?J=FCrgen_B=F6hm?=: Fixing design, leaving BRAMS variable
    129862: 08/03/07: Symon: Re: Fixing design, leaving BRAMS variable
        129908: 08/03/09: =?ISO-8859-1?Q?J=FCrgen_B=F6hm?=: Re: Fixing design, leaving BRAMS variable
129865: 08/03/07: Markus Kuhn: Altera Quartus II v7.2 SP2 under openSUSE 10.3 (i686)
    129901: 08/03/08: Tommy Thorn: Re: Altera Quartus II v7.2 SP2 under openSUSE 10.3 (i686)
129866: 08/03/07: Roger: ML523 power module schematics
    129868: 08/03/07: austin: Re: ML523 power module schematics
        129886: 08/03/08: Roger: Re: ML523 power module schematics
            129919: 08/03/10: austin: Re: ML523 power module schematics
129867: 08/03/08: Jim Granville: SiliconBlue enters the FPGA fray
    129869: 08/03/07: austin: Re: SiliconBlue enters the FPGA fray
        129870: 08/03/07: austin: Re: SiliconBlue enters the FPGA fray
            129871: 08/03/08: Jim Granville: Re: SiliconBlue enters the FPGA fray
                129873: 08/03/07: austin: Re: SiliconBlue enters the FPGA fray
                    129885: 08/03/08: <sky465nm@trline5.org>: Re: SiliconBlue enters the FPGA fray
                    129921: 08/03/10: austin: Re: SiliconBlue enters the FPGA fray
                        129925: 08/03/10: austin: Re: SiliconBlue enters the FPGA fray
                            130008: 08/03/13: Jim Granville: Re: SiliconBlue enters the FPGA fray
                                130106: 08/03/14: Eric Smith: Re: SiliconBlue enters the FPGA fray
                                130121: 08/03/15: Mike Treseler: Re: SiliconBlue enters the FPGA fray
                            130009: 08/03/13: Jim Granville: Re: SiliconBlue enters the FPGA fray
        129875: 08/03/07: Gabor: Re: SiliconBlue enters the FPGA fray
        129884: 08/03/07: Antti: Re: SiliconBlue enters the FPGA fray
        129924: 08/03/10: John_H: Re: SiliconBlue enters the FPGA fray
        129926: 08/03/10: Peter Alfke: Re: SiliconBlue enters the FPGA fray
        129953: 08/03/11: <info2@rayed.de>: Re: SiliconBlue enters the FPGA fray
        130002: 08/03/12: Antti: Re: SiliconBlue enters the FPGA fray
        130004: 08/03/12: Peter Alfke: Re: SiliconBlue enters the FPGA fray
        130006: 08/03/12: Antti: Re: SiliconBlue enters the FPGA fray
        130089: 08/03/14: Antti: Re: SiliconBlue enters the FPGA fray
        130124: 08/03/15: Antti: Re: SiliconBlue enters the FPGA fray
        130127: 08/03/15: Peter Alfke: Re: SiliconBlue enters the FPGA fray
        130128: 08/03/15: Antti: Re: SiliconBlue enters the FPGA fray
129876: 08/03/07: MM: Danger of having JTAG TAP controller always enabled in Xilinx parts
    129877: 08/03/07: austin: Re: Danger of having JTAG TAP controller always enabled in Xilinx
        129879: 08/03/07: MM: Re: Danger of having JTAG TAP controller always enabled in Xilinx parts
            129883: 08/03/07: austin: Re: Danger of having JTAG TAP controller always enabled in Xilinx
                130040: 08/03/13: Jon Elson: Re: Danger of having JTAG TAP controller always enabled in Xilinx
    129880: 08/03/07: John_H: Re: Danger of having JTAG TAP controller always enabled in Xilinx
        129882: 08/03/07: MM: Re: Danger of having JTAG TAP controller always enabled in Xilinx parts
129887: 08/03/08: Enzo B.: Datasheet on Micron's secure products
    129889: 08/03/08: donald: Re: Datasheet on Micron's secure products
        129897: 08/03/08: Enzo B.: Re: Datasheet on Micron's secure products
            129898: 08/03/08: Sean Durkin: Re: Datasheet on Micron's secure products
            129899: 08/03/08: Symon: Re: Datasheet on Micron's secure products
129888: 08/03/08: sdf: Cyclone III and Quartus 7.2sp2
    129891: 08/03/08: Rob: Re: Cyclone III and Quartus 7.2sp2
    129892: 08/03/08: sdf: Re: Cyclone III and Quartus 7.2sp2
    129895: 08/03/08: Mike Treseler: Re: Cyclone III and Quartus 7.2sp2
    129896: 08/03/08: Frank Buss: Re: Cyclone III and Quartus 7.2sp2
    129900: 08/03/08: Tommy Thorn: Re: Cyclone III and Quartus 7.2sp2
        129910: 08/03/09: Mike Treseler: Re: Cyclone III and Quartus 7.2sp2
    129903: 08/03/08: sdf: Re: Cyclone III and Quartus 7.2sp2
    129906: 08/03/09: Tommy Thorn: Re: Cyclone III and Quartus 7.2sp2
    129907: 08/03/09: sdf: Re: Cyclone III and Quartus 7.2sp2
129893: 08/03/08: <hilo_pupu@hotmail.com>: Hardware Cosim one wrong output and one correct output
129902: 08/03/08: rponsard@gmail.com: opencores down ?
    129912: 08/03/10: <sky465nm@trline5.org>: Re: opencores down ?
        129918: 08/03/10: Uwe Bonnes: Re: opencores down ?
129909: 08/03/09: <JonathanScottRose@gmail.com>: New Release of VPR, Version 5.0 Beta
129913: 08/03/09: <rg.jones@rogers.com>: Trying to contact Jeung Joon Lee
129914: 08/03/10: Grubi: Virtex-4 VLX25 DCM problem
    129920: 08/03/10: austin: Re: Virtex-4 VLX25 DCM problem
        129928: 08/03/10: Grubi: Re: Virtex-4 VLX25 DCM problem
            129930: 08/03/10: Grubi: Re: Virtex-4 VLX25 DCM problem
                129931: 08/03/10: austin: Re: Virtex-4 VLX25 DCM problem
        129929: 08/03/10: Grubi: Re: Virtex-4 VLX25 DCM problem
            129948: 08/03/11: austin: Re: Virtex-4 VLX25 DCM problem
    129932: 08/03/10: Peter Alfke: Re: Virtex-4 VLX25 DCM problem
        130083: 08/03/14: Grubi: Re: Virtex-4 VLX25 DCM problem
        130086: 08/03/14: Grubi: Re: Virtex-4 VLX25 DCM problem
    129933: 08/03/10: Peter Alfke: Re: Virtex-4 VLX25 DCM problem
    129934: 08/03/10: mh: Re: Virtex-4 VLX25 DCM problem
    129937: 08/03/11: John McCaskill: Re: Virtex-4 VLX25 DCM problem
        129980: 08/03/12: Grubi: Re: Virtex-4 VLX25 DCM problem
129915: 08/03/10: <jshrini.vasu@gmail.com>: its regarding to the Max Frequency in xilinx FPGA
    129916: 08/03/10: Gabor: Re: its regarding to the Max Frequency in xilinx FPGA
        129917: 08/03/10: David Spencer: Re: its regarding to the Max Frequency in xilinx FPGA
    129923: 08/03/10: Kolja Sulimma: Re: its regarding to the Max Frequency in xilinx FPGA
    129990: 08/03/12: Marc Randolph: Re: its regarding to the Max Frequency in xilinx FPGA
129935: 08/03/11: <jshrini.vasu@gmail.com>: vhdl code realization
    129944: 08/03/11: Mike Treseler: Re: vhdl code realization
129936: 08/03/11: Udo: Virtex-5 FX when ? (III)
    130013: 08/03/12: Xilinx User: Re: Virtex-5 FX when ? (III)
        130107: 08/03/14: Eric Smith: Re: Virtex-5 FX when ? (III)
        130123: 08/03/15: Mike Treseler: Re: Virtex-5 FX when ? (III)
            130140: 08/03/16: arko: Re: Virtex-5 FX when ? (III)
    130197: 08/03/17: gtwrek@pacbell.net: Re: Virtex-5 FX when ? (III)
129938: 08/03/11: Andreas Ehliar: Contradicting messages from Xilinx' place and route/timing analyzer
129939: 08/03/11: satyam: Matlab, RS-232, Ethernet
    129945: 08/03/11: Dave: Re: Matlab, RS-232, Ethernet
    129966: 08/03/11: <sky465nm@trline4.org>: Re: Matlab, RS-232, Ethernet
        130032: 08/03/13: <sky465nm@trline4.org>: Re: Matlab, RS-232, Ethernet
    129978: 08/03/12: StYm: Re: Matlab, RS-232, Ethernet
    130003: 08/03/12: lm317t: Re: Matlab, RS-232, Ethernet
    130018: 08/03/13: StYm: Re: Matlab, RS-232, Ethernet
    130024: 08/03/13: lm317t: Re: Matlab, RS-232, Ethernet
    130028: 08/03/13: jkljljklk: Re: Matlab, RS-232, Ethernet
129940: 08/03/11: Paul Boven: BRAM synthesis question
    129941: 08/03/11: Mike Treseler: Re: BRAM synthesis question
    129942: 08/03/11: Dave: Re: BRAM synthesis question
    129946: 08/03/11: Symon: Re: BRAM synthesis question
        129954: 08/03/11: Mike Treseler: Re: BRAM synthesis question
            130125: 08/03/15: Walter Dvorak: Re: BRAM synthesis question
        129956: 08/03/11: donald: Re: BRAM synthesis question
            129962: 08/03/11: glen herrmannsfeldt: Re: BRAM synthesis question
        129957: 08/03/11: Nico Coesel: Re: BRAM synthesis question
        129959: 08/03/11: Paul Boven: Re: BRAM synthesis question
        129963: 08/03/11: glen herrmannsfeldt: Re: BRAM synthesis question
        129989: 08/03/12: Symon: Re: BRAM synthesis question
    129951: 08/03/11: Peter Alfke: Re: BRAM synthesis question
    129952: 08/03/11: <job@amontec.com>: Re: BRAM synthesis question
    129955: 08/03/11: <job@amontec.com>: Re: BRAM synthesis question
129943: 08/03/12: Tony Burch: Ann: New FPGA beginner's Video guide
    129960: 08/03/11: Dwayne Dilbeck: Re: New FPGA beginner's Video guide
        129961: 08/03/11: Dwayne Dilbeck: Re: New FPGA beginner's Video guide
            129975: 08/03/12: Tony Burch: Re: New FPGA beginner's Video guide
                129977: 08/03/12: <sky465nm@trline4.org>: Re: New FPGA beginner's Video guide
        129972: 08/03/12: Tony Burch: Re: New FPGA beginner's Video guide
129947: 08/03/11: wicky: Could I develop a new gui using java based on the script language of
    129949: 08/03/11: Jeff Cunningham: Re: Could I develop a new gui using java based on the script language
    129950: 08/03/11: wicky: Re: Could I develop a new gui using java based on the script language
    129958: 08/03/11: Dwayne Dilbeck: Re: Could I develop a new gui using java based on the script language of ChipScope?
        130001: 08/03/12: Dwayne Dilbeck: Re: Could I develop a new gui using java based on the script language of ChipScope?
        130016: 08/03/13: Andreas Ehliar: Re: Could I develop a new gui using java based on the script language of ChipScope?
    129971: 08/03/11: wicky: Re: Could I develop a new gui using java based on the script language
    130005: 08/03/12: <SKatsyuba@gmail.com>: Re: Could I develop a new gui using java based on the script language
    130012: 08/03/12: wicky: Re: Could I develop a new gui using java based on the script language
129967: 08/03/11: <mikechin2000@gmail.com>: avnet virtex-5 lx eval kit ddr problem
    129992: 08/03/12: Bryan: Re: avnet virtex-5 lx eval kit ddr problem
    129996: 08/03/12: <mikechin2000@gmail.com>: Re: avnet virtex-5 lx eval kit ddr problem
129976: 08/03/11: <muthusnv@gmail.com>: Design complexity in Logic cells - Virtex-5 FPGA
    129982: 08/03/12: Kolja Sulimma: Re: Design complexity in Logic cells - Virtex-5 FPGA
        130114: 08/03/14: jtw: Re: Design complexity in Logic cells - Virtex-5 FPGA
    130017: 08/03/12: <bkurtz@engineer.com>: Re: Design complexity in Logic cells - Virtex-5 FPGA
    130021: 08/03/13: Kolja Sulimma: Re: Design complexity in Logic cells - Virtex-5 FPGA
    130030: 08/03/13: Mike Treseler: Re: Design complexity in Logic cells - Virtex-5 FPGA
129979: 08/03/12: LilacSkin: VME 2 Ghz clock generator
    129981: 08/03/12: Kolja Sulimma: Re: VME 2 Ghz clock generator
    129984: 08/03/12: LilacSkin: Re: VME 2 Ghz clock generator
    129991: 08/03/12: Kolja Sulimma: Re: VME 2 Ghz clock generator
129985: 08/03/12: sdf: Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal
    129997: 08/03/12: <ghelbig@lycos.com>: Re: Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal
        130014: 08/03/12: Xilinx User: Re: Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal without Nios2?
            130055: 08/03/14: Alex Freed: Re: Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal
            130056: 08/03/14: David Brown: Re: Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal
    130007: 08/03/12: sdf: Re: Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal
    130033: 08/03/13: <ghelbig@lycos.com>: Re: Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal
129987: 08/03/12: CTSportPilot: Re: Blast from the past
129988: 08/03/12: CTSportPilot: Re: Blast from the past
129993: 08/03/12: vt2001cpe: Xilinx Pipelined Divider for V5?
129994: 08/03/12: u_stadler@yahoo.de: infer block ram with mismatched port width
    129995: 08/03/12: John_H: Re: infer block ram with mismatched port width
    130000: 08/03/12: KJ: Re: infer block ram with mismatched port width
129998: 08/03/12: Dale: Is 32 bit Xilinx ISE Webpack compatible with 64 bit ChipScope Pro?
129999: 08/03/12: Weltraumbaer: Temporarely no answer on MEM32 Read request
130010: 08/03/12: kislo: microblaze to blockram - Byte-Writes
    130026: 08/03/13: Andreas Hofmann: Re: microblaze to blockram - Byte-Writes
    130027: 08/03/13: Peter Alfke: Re: microblaze to blockram - Byte-Writes
    130039: 08/03/13: kislo: Re: microblaze to blockram - Byte-Writes
130011: 08/03/12: mynewlifever@yahoo.com.cn: Using xilinx XAUI core in Ethernet design. What is the exact frame
130015: 08/03/12: Xilinx User: Xilinx ISE Evaluation DVD 10.1 request...
    130108: 08/03/14: Eric Smith: Re: Xilinx ISE Evaluation DVD 10.1 request...
130019: 08/03/13: sdf: Almost offtopic about HDL optimizing.
    130020: 08/03/13: Kolja Sulimma: Re: Almost offtopic about HDL optimizing.
    130022: 08/03/13: sdf: Re: Almost offtopic about HDL optimizing.
    130029: 08/03/13: MM: Re: Almost offtopic about HDL optimizing.
    130101: 08/03/14: Kolja Sulimma: Re: Almost offtopic about HDL optimizing.
130023: 08/03/13: water9580@yahoo.com: MAXDELAY="1.0"
130025: 08/03/13: Charles Wagner: ALTERA SOPC : ptf-sopc files
    130031: 08/03/13: KJ: Re: ALTERA SOPC : ptf-sopc files
130034: 08/03/13: <ghelbig@lycos.com>: Re: Problem with Spartan 3 StarterKit
130035: 08/03/13: Paul Urbanus: Re: Problem with Spartan 3 StarterKit
    130037: 08/03/13: Christian Schrader: Re: Problem with Spartan 3 StarterKit
130036: 08/03/13: <robquigley@gmail.com>: SDC of NCF?
    130042: 08/03/13: Mike Treseler: Re: SDC of NCF?
    130045: 08/03/13: HT-Lab: Re: SDC of NCF?
130038: 08/03/13: FPGA: simulating Xilinx cores
    130041: 08/03/13: <ghelbig@lycos.com>: Re: simulating Xilinx cores
130043: 08/03/13: Paul Urbanus: Re: Problem with Spartan 3 StarterKit
    130044: 08/03/13: Paul Urbanus: Re: Problem with Spartan 3 StarterKit
        130129: 08/03/16: Tony Burch: Re: Problem with Spartan 3 StarterKit
130046: 08/03/13: Sue: Design entries for FSM
    130047: 08/03/13: John_H: Re: Design entries for FSM
    130068: 08/03/14: Sue: Re: Design entries for FSM
    130069: 08/03/14: John_H: Re: Design entries for FSM
    130071: 08/03/14: Sue: Re: Design entries for FSM
    130073: 08/03/14: KJ: Re: Design entries for FSM
    130074: 08/03/14: Sue: Re: Design entries for FSM
    130075: 08/03/14: John_H: Re: Design entries for FSM
    130077: 08/03/14: Gabor: Re: Design entries for FSM
130048: 08/03/13: Antti: Actel PA3 with DirectC or SVF, anybody had any success?
    130050: 08/03/14: <job@amontec.com>: Re: Actel PA3 with DirectC or SVF, anybody had any success?
    130051: 08/03/14: Antti: Re: Actel PA3 with DirectC or SVF, anybody had any success?
    130058: 08/03/14: <job@amontec.com>: Re: Actel PA3 with DirectC or SVF, anybody had any success?
    130059: 08/03/14: Antti: Re: Actel PA3 with DirectC or SVF, anybody had any success?
    130060: 08/03/14: <job@amontec.com>: Re: Actel PA3 with DirectC or SVF, anybody had any success?
    130062: 08/03/14: Antti: Re: Actel PA3 with DirectC or SVF, anybody had any success?
    130064: 08/03/14: <job@amontec.com>: Re: Actel PA3 with DirectC or SVF, anybody had any success?
    130085: 08/03/14: Antti: Re: Actel PA3 with DirectC or SVF, anybody had any success?
    130407: 08/03/22: Antti: Re: Actel PA3 with DirectC or SVF, anybody had any success?
130049: 08/03/14: life.is.best: ICMP checksum
130052: 08/03/14: Morten Leikvoll: DDR3 speed, Altera vs Xilinx
    130053: 08/03/14: Antti: Re: DDR3 speed, Altera vs Xilinx
    130054: 08/03/14: Kim Enkovaara: Re: DDR3 speed, Altera vs Xilinx
        130067: 08/03/14: austin: Re: DDR3 speed, Altera vs Xilinx
            130078: 08/03/14: Nico Coesel: Re: DDR3 speed, Altera vs Xilinx
                130088: 08/03/14: austin: Re: DDR3 speed, Altera vs Xilinx
                    130093: 08/03/14: austin: Re: DDR3 speed, Altera vs Xilinx
                        130099: 08/03/14: Gavin Scott: Re: DDR3 speed, Altera vs Xilinx
                        130104: 08/03/14: Alex Freed: Re: DDR3 speed, Altera vs Xilinx
                        130116: 08/03/15: Nico Coesel: Re: DDR3 speed, Altera vs Xilinx
                            130118: 08/03/15: Uwe Bonnes: Re: DDR3 speed, Altera vs Xilinx
                            130202: 08/03/17: Eric Smith: Re: DDR3 speed, Altera vs Xilinx
                130115: 08/03/15: Nico Coesel: Re: DDR3 speed, Altera vs Xilinx
            130147: 08/03/17: Morten Leikvoll: Re: DDR3 speed, Altera vs Xilinx
                130172: 08/03/17: austin: Altera vs Xilinx
                    130225: 08/03/18: Morten Leikvoll: Re: Altera vs Xilinx
        130070: 08/03/14: Antti: Re: DDR3 speed, Altera vs Xilinx
        130079: 08/03/14: John_H: Re: DDR3 speed, Altera vs Xilinx
        130084: 08/03/14: Antti: Re: DDR3 speed, Altera vs Xilinx
        130090: 08/03/14: Antti: Re: DDR3 speed, Altera vs Xilinx
        130095: 08/03/14: Antti: Re: DDR3 speed, Altera vs Xilinx
        130096: 08/03/14: Antti: Re: DDR3 speed, Altera vs Xilinx
        130117: 08/03/15: Antti: Re: DDR3 speed, Altera vs Xilinx
        130119: 08/03/15: Andrew Burnside: Re: DDR3 speed, Altera vs Xilinx
        130141: 08/03/16: Dave Greenfield: Re: DDR3 speed, Altera vs Xilinx
        130143: 08/03/16: Antti: Re: DDR3 speed, Altera vs Xilinx
        130155: 08/03/17: Kolja Sulimma: Re: DDR3 speed, Altera vs Xilinx
        130210: 08/03/17: Antti: Re: DDR3 speed, Altera vs Xilinx
        130425: 08/03/23: <pmulliki@yahoo.com>: Re: Altera vs Xilinx
130057: 08/03/14: <joel.pigdon@gmail.com>: Xilinx S3DSP + EDK Board, too good to be true?
    130063: 08/03/14: Uwe Bonnes: Re: Xilinx S3DSP + EDK Board, too good to be true?
        130082: 08/03/14: Uwe Bonnes: Re: Xilinx S3DSP + EDK Board, too good to be true?
    130065: 08/03/14: Antti: Re: Xilinx S3DSP + EDK Board, too good to be true?
    130072: 08/03/14: John_H: Re: Xilinx S3DSP + EDK Board, too good to be true?
        130076: 08/03/14: Uwe Bonnes: Re: Xilinx S3DSP + EDK Board, too good to be true?
            130081: 08/03/14: Uwe Bonnes: Re: Xilinx S3DSP + EDK Board, too good to be true?
    130080: 08/03/14: John_H: Re: Xilinx S3DSP + EDK Board, too good to be true?
    130087: 08/03/14: Antti: Re: Xilinx S3DSP + EDK Board, too good to be true?
    130091: 08/03/14: Bryan: Re: Xilinx S3DSP + EDK Board, too good to be true?
    130092: 08/03/14: Antti: Re: Xilinx S3DSP + EDK Board, too good to be true?
130061: 08/03/14: Livia: I need help! Connecting my dual port RAM to a microblaze
130094: 08/03/14: Daniel: Help on Virtex-II Pro global clocks.
    130113: 08/03/14: jtw: Re: Help on Virtex-II Pro global clocks.
        130186: 08/03/17: Duane Clark: Re: Help on Virtex-II Pro global clocks.
            130198: 08/03/17: Duane Clark: Re: Help on Virtex-II Pro global clocks.
                130240: 08/03/18: Joseph Samson: Re: Help on Virtex-II Pro global clocks.
                130251: 08/03/19: Duane Clark: Re: Help on Virtex-II Pro global clocks.
    130159: 08/03/17: Daniel: Re: Help on Virtex-II Pro global clocks.
    130191: 08/03/17: Daniel: Re: Help on Virtex-II Pro global clocks.
    130238: 08/03/18: Daniel: Re: Help on Virtex-II Pro global clocks.
130097: 08/03/14: Alex Colvin: Re: Problem with Spartan 3 StarterKit
130098: 08/03/14: M. Hamed: Detecting a pulse with minimum width
    130102: 08/03/14: Brad Smallridge: Re: Detecting a pulse with minimum width
        130109: 08/03/14: KJ: Re: Detecting a pulse with minimum width
    130105: 08/03/14: M. Hamed: Re: Detecting a pulse with minimum width
130100: 08/03/14: Brad Smallridge: Xilinx Tristate Registration
    130103: 08/03/14: John_H: Re: Xilinx Tristate Registration
    130110: 08/03/15: Symon: Re: Xilinx Tristate Registration
        130111: 08/03/15: Symon: Re: Xilinx Tristate Registration
    130112: 08/03/14: <pete@coho.org>: Re: Xilinx Tristate Registration
        130160: 08/03/17: Gabor: Re: Xilinx Tristate Registration
    130120: 08/03/15: John Adair: Re: Xilinx Tristate Registration
        130137: 08/03/16: Brad Smallridge: Re: Xilinx Tristate Registration
            130200: 08/03/17: Brad Smallridge: Re: Xilinx Tristate Registration
        130139: 08/03/16: Brian Davis: Re: Xilinx Tristate Registration
        130223: 08/03/18: Gabor: Re: Xilinx Tristate Registration
130122: 08/03/15: ertw: ISSI SRAM.
    130126: 08/03/15: radarman: Re: ISSI SRAM.
130130: 08/03/16: Antti: Re: Problem with Spartan 3 StarterKit
130131: 08/03/16: Antti: ISE 9.2SP4 error
    130132: 08/03/16: Antti: Re: ISE 9.2SP4 error
        130151: 08/03/17: <sky465nm@trline4.org>: Re: ISE 9.2SP4 error
            130161: 08/03/17: David Brown: Re: ISE 9.2SP4 error
                130163: 08/03/17: Mike Treseler: Re: ISE 9.2SP4 error
                    130203: 08/03/17: Eric Smith: Re: ISE 9.2SP4 error
                130177: 08/03/17: David Brown: Re: ISE 9.2SP4 error
        130260: 08/03/19: Zara: Re: ISE 9.2SP4 error
    130152: 08/03/17: Antti: Re: ISE 9.2SP4 error
    130157: 08/03/17: Antti: Re: ISE 9.2SP4 error
    130165: 08/03/17: Antti: Re: ISE 9.2SP4 error
130133: 08/03/16: Eng.Emad Samuel: Need help in SDR
    130134: 08/03/16: Antti: Re: Need help in SDR
    130136: 08/03/16: John_H: Re: Need help in SDR
130135: 08/03/16: Antti: Xilinx impact, boldly going into nightmareland
    130169: 08/03/17: AugustoEinsfeldt: Re: Xilinx impact, boldly going into nightmareland
130138: 08/03/17: Uwe Bonnes: Wondering about "LatticeMico32 Open Source Licensing"
    130142: 08/03/16: Antti: Re: Wondering about "LatticeMico32 Open Source Licensing"
        130164: 08/03/17: Uwe Bonnes: Re: Wondering about "LatticeMico32 Open Source Licensing"
            130185: 08/03/17: Uwe Bonnes: Re: Wondering about "LatticeMico32 Open Source Licensing"
        130166: 08/03/17: Antti: Re: Wondering about "LatticeMico32 Open Source Licensing"
        130178: 08/03/17: Jon Beniston: Re: Wondering about "LatticeMico32 Open Source Licensing"
        130179: 08/03/17: Jon Beniston: Re: Wondering about "LatticeMico32 Open Source Licensing"
130144: 08/03/17: Dilan: implementing ethernet FCS code in verilog
    130146: 08/03/17: <sky465nm@trline4.org>: Re: implementing ethernet FCS code in verilog
        130187: 08/03/17: glen herrmannsfeldt: Re: implementing ethernet FCS code in verilog
        130215: 08/03/18: <sky465nm@trline4.org>: Re: implementing ethernet FCS code in verilog
    130205: 08/03/17: Dilan: Re: implementing ethernet FCS code in verilog
130145: 08/03/17: <climber.tim@gmail.com>: Designing CPU
    130148: 08/03/17: <sky465nm@trline4.org>: Re: Designing CPU
    130149: 08/03/17: Jonathan Bromley: Re: Designing CPU
        130167: 08/03/17: David Spencer: Re: Designing CPU
    130150: 08/03/17: Alex Freed: Re: Designing CPU
    130153: 08/03/17: Kolja Sulimma: Re: Designing CPU
    130154: 08/03/17: Jim Granville: Re: Designing CPU
    130156: 08/03/17: HT-Lab: Re: Designing CPU
        130170: 08/03/17: Symon: Re: Designing CPU
        130193: 08/03/18: Jim Granville: Re: Designing CPU
        130199: 08/03/18: Jim Granville: Re: Designing CPU
    130162: 08/03/17: Antti: Re: Designing CPU
    130184: 08/03/17: Jecel: Re: Designing CPU
    130190: 08/03/17: John_H: Re: Designing CPU
    130206: 08/03/17: Jecel: Re: Designing CPU
    130217: 08/03/18: Antti: Re: Designing CPU
    130371: 08/03/21: <referringto@googlemail.com>: Re: Designing CPU
        130372: 08/03/21: Frank Buss: Re: Designing CPU
            130469: 08/03/25: Herbert Kleebauer: Re: Designing CPU
    130383: 08/03/21: <referringto@googlemail.com>: Re: Designing CPU
    130393: 08/03/21: donald: Re: Designing CPU
130158: 08/03/17: bish: total cost for virtex II pro FPGA
    130168: 08/03/17: Uwe Bonnes: Re: total cost for virtex II pro FPGA
    130174: 08/03/17: austin: Re: total cost for virtex II pro FPGA
    130208: 08/03/17: bish: Re: total cost for virtex II pro FPGA
    130295: 08/03/19: David Binnie: Re: total cost for virtex II pro FPGA
    130422: 08/03/23: bish: Re: total cost for virtex II pro FPGA
    130436: 08/03/24: bish: Re: total cost for virtex II pro FPGA
    130456: 08/03/24: mh: Re: total cost for virtex II pro FPGA
    130476: 08/03/25: bish: Re: total cost for virtex II pro FPGA
130171: 08/03/17: Kolja Sulimma: Xilinx Webcase Workflow
    130173: 08/03/17: Antti: Re: Xilinx Webcase Workflow
        130180: 08/03/17: austin: Re: Xilinx Webcase Workflow
    130175: 08/03/17: Kolja Sulimma: Re: Xilinx Webcase Workflow
    130188: 08/03/17: MM: Re: Xilinx Webcase Workflow
    130213: 08/03/18: Helmut: Re: Xilinx Webcase Workflow
        130228: 08/03/18: austin: Re: Xilinx Webcase Workflow
    130233: 08/03/18: austin: Re: Xilinx Webcase Workflow
130176: 08/03/17: Dave H: Intermittent failure to start sw app on pwr-on, SysACE reset doesn't
130181: 08/03/17: FPGA: dual clock fifo
    130182: 08/03/17: John_H: Re: dual clock fifo
        130224: 08/03/18: John_H: Re: dual clock fifo
    130183: 08/03/17: FPGA: Re: dual clock fifo
    130189: 08/03/17: John_H: Re: dual clock fifo
    130192: 08/03/17: FPGA: Re: dual clock fifo
    130194: 08/03/17: John_H: Re: dual clock fifo
    130201: 08/03/17: David Spencer: Re: dual clock fifo
        130242: 08/03/18: glen herrmannsfeldt: Re: dual clock fifo
        130303: 08/03/19: Mike Treseler: Re: dual clock fifo
    130209: 08/03/17: Peter Alfke: Re: dual clock fifo
    130211: 08/03/18: bvkrock: Re: dual clock fifo
    130230: 08/03/18: Patrick Dubois: Re: dual clock fifo
    130231: 08/03/18: John_H: Re: dual clock fifo
    130234: 08/03/18: Peter Alfke: Re: dual clock fifo
    130236: 08/03/18: KJ: Re: dual clock fifo
    130244: 08/03/18: Peter Alfke: Re: dual clock fifo
    130290: 08/03/19: Patrick Dubois: Re: dual clock fifo
    130293: 08/03/19: KJ: Re: dual clock fifo
    130294: 08/03/19: Patrick Dubois: Re: dual clock fifo
    130338: 08/03/20: FPGA: Re: dual clock fifo
    130465: 08/03/25: Morten Leikvoll: Re: dual clock fifo
    130502: 08/03/25: Nico Coesel: Re: dual clock fifo
130195: 08/03/17: <chithrakn@gmail.com>: Chipscope
    130196: 08/03/17: austin: Re: Chipscope
    130204: 08/03/18: Symon: Re: Chipscope
    130212: 08/03/18: Helmut: Re: Chipscope
    130214: 08/03/18: vasu: Re: Chipscope
    130220: 08/03/18: Brian Drummond: Re: Chipscope
130207: 08/03/17: Abhi: Xilinx interview questions
    130219: 08/03/18: David Spencer: Re: Xilinx interview questions
    130229: 08/03/18: austin: Re: Xilinx interview questions
        130281: 08/03/19: Symon: Re: Xilinx interview questions
            130287: 08/03/19: <sky465nm@trline4.org>: Re: Xilinx interview questions
130216: 08/03/18: <markmcmahon@hotmail.com>: FSL or DMA w/ FIFO?
    130221: 08/03/18: Brian Drummond: Re: FSL or DMA w/ FIFO?
    130226: 08/03/18: <markmcmahon@hotmail.com>: Re: FSL or DMA w/ FIFO?
    130227: 08/03/18: Martin Thompson: Re: FSL or DMA w/ FIFO?
        130235: 08/03/18: Göran Bilski: Re: FSL or DMA w/ FIFO?
        130267: 08/03/19: Martin Thompson: Re: FSL or DMA w/ FIFO?
    130232: 08/03/18: <markmcmahon@hotmail.com>: Re: FSL or DMA w/ FIFO?
    130301: 08/03/19: John Williams: Re: FSL or DMA w/ FIFO?
130218: 08/03/18: John Williams: SGMII, xps_ll_temac and MDIO / MCD
    130222: 08/03/18: morphiend: Re: SGMII, xps_ll_temac and MDIO / MCD
    130545: 08/03/26: John Williams: Re: SGMII, xps_ll_temac and MDIO / MCD
130237: 08/03/18: <picnanard@yahoo.fr>: to view vhdl variable with gtkwave
    130239: 08/03/18: Mike Treseler: Re: to view vhdl variable with gtkwave
    130241: 08/03/18: <picnanard@yahoo.fr>: Re: to view vhdl variable with gtkwave
    130263: 08/03/19: <picnanard@yahoo.fr>: Re: to view vhdl variable with gtkwave
130243: 08/03/18: u_stadler@yahoo.de: vhdl type conversions
    130245: 08/03/18: <manfredk@internode.on.net>: Re: vhdl type conversions
    130246: 08/03/18: Jonathan Bromley: Re: vhdl type conversions
    130247: 08/03/18: Mike Treseler: Re: vhdl type conversions
    130248: 08/03/18: KJ: Re: vhdl type conversions
        130249: 08/03/18: Jonathan Bromley: Re: vhdl type conversions
            130250: 08/03/18: KJ: Re: vhdl type conversions
                130279: 08/03/19: Mike Treseler: Re: vhdl type conversions
                130410: 08/03/22: Jonathan Bromley: Re: vhdl type conversions
                    130426: 08/03/23: Mike Treseler: Re: vhdl type conversions
    130265: 08/03/19: u_stadler@yahoo.de: Re: vhdl type conversions
130252: 08/03/18: water9580@yahoo.com: serval PCIE issue
130253: 08/03/19: Marty Ryba: Optimizing an inferred counter
    130257: 08/03/18: Mike Treseler: Re: Optimizing an inferred counter
        130288: 08/03/19: <ghelbig@lycos.com>: Re: Optimizing an inferred counter
        130291: 08/03/19: Peter Alfke: Re: Optimizing an inferred counter
    130262: 08/03/19: PatC: Re: Optimizing an inferred counter
    130264: 08/03/19: Tricky: Re: Optimizing an inferred counter
    130266: 08/03/19: Jim Granville: Re: Optimizing an inferred counter
    130270: 08/03/19: Martin Thompson: Re: Optimizing an inferred counter
        130274: 08/03/19: Symon: Re: Optimizing an inferred counter
    130271: 08/03/19: Peter: Re: Optimizing an inferred counter
    130275: 08/03/19: KJ: Re: Optimizing an inferred counter
    130276: 08/03/19: Brian Drummond: Re: Optimizing an inferred counter
        130282: 08/03/19: <kennheinrich@sympatico.ca>: Re: Optimizing an inferred counter
            130314: 08/03/20: Martin Thompson: Re: Optimizing an inferred counter
                130323: 08/03/20: Martin Thompson: Re: Optimizing an inferred counter
        130318: 08/03/20: Andy: Re: Optimizing an inferred counter
        130353: 08/03/20: <kennheinrich@sympatico.ca>: Re: Optimizing an inferred counter
        130355: 08/03/20: <kennheinrich@sympatico.ca>: Re: Optimizing an inferred counter
    130286: 08/03/19: Peter Alfke: Re: Optimizing an inferred counter
130254: 08/03/18: Guirico C.: Using TimeQuest Timing Analyzer
    130255: 08/03/19: Rob: Re: Using TimeQuest Timing Analyzer
    130256: 08/03/18: =?ISO-8859-1?Q?Guilherme_Corr=EAa?=: Re: Using TimeQuest Timing Analyzer
    130278: 08/03/19: =?ISO-8859-1?Q?Guilherme_Corr=EAa?=: Re: Using TimeQuest Timing Analyzer
130258: 08/03/18: <jithinpremvas@gmail.com>: problem with edk9.2
    130259: 08/03/19: Zara: Re: problem with edk9.2
130261: 08/03/18: Antti: A Challenge for serialized processor design and implementation
    130268: 08/03/19: Rafael Deliano: Re: A Challenge for serialized processor design and implementation
    130269: 08/03/19: Jim Granville: Re: A Challenge for serialized processor design and implementation
    130280: 08/03/19: Ulf Samuelsson: Re: A Challenge for serialized processor design and implementation
        130292: 08/03/20: Jim Granville: Re: A Challenge for serialized processor design and implementation
            130298: 08/03/19: Walter Banks: Re: A Challenge for serialized processor design and implementation
                130302: 08/03/20: Jim Granville: Re: A Challenge for serialized processor design and implementation
                    130305: 08/03/20: Frank Buss: Re: A Challenge for serialized processor design and implementation
                        130306: 08/03/20: Jim Granville: Re: A Challenge for serialized processor design and implementation
                            130310: 08/03/20: <sky465nm@trline4.org>: Re: A Challenge for serialized processor design and implementation
                            130397: 08/03/22: David R Brooks: Re: A Challenge for serialized processor design and implementation
                                130463: 08/03/25: Jim Granville: Re: A Challenge for serialized processor design and implementation
                    130320: 08/03/20: Walter Banks: Re: A Challenge for serialized processor design and implementation
                    130322: 08/03/20: Walter Banks: Re: A Challenge for serialized processor design and implementation
                    130324: 08/03/20: John Devereux: Re: A Challenge for serialized processor design and implementation
                        130331: 08/03/20: Walter Banks: Re: A Challenge for serialized processor design and implementation
            130558: 08/03/27: Ulf Samuelsson: Re: A Challenge for serialized processor design and implementation
                130590: 08/03/28: Jim Granville: Re: A Challenge for serialized processor design and implementation
    130299: 08/03/19: Jecel: Re: A Challenge for serialized processor design and implementation
        130349: 08/03/20: Frank Buss: Re: A Challenge for serialized processor design and implementation
        130351: 08/03/20: msg: Re: A Challenge for serialized processor design and implementation
        130363: 08/03/21: Brian Drummond: Re: A Challenge for serialized processor design and implementation
            130369: 08/03/21: Steven Guccione: Re: A Challenge for serialized processor design and implementation
    130304: 08/03/19: rickman: Re: A Challenge for serialized processor design and implementation
    130307: 08/03/20: Antti: Re: A Challenge for serialized processor design and implementation
    130308: 08/03/20: Tommy Thorn: Re: A Challenge for serialized processor design and implementation
    130309: 08/03/20: Kolja Sulimma: Re: A Challenge for serialized processor design and implementation
    130311: 08/03/20: Steve Goodwin: Re: A Challenge for serialized processor design and implementation
    130330: 08/03/20: Steve Goodwin: Re: A Challenge for serialized processor design and implementation
    130335: 08/03/20: Peter Alfke: Re: A Challenge for serialized processor design and implementation
    130345: 08/03/20: Jecel: Re: A Challenge for serialized processor design and implementation
    130368: 08/03/21: rickman: Re: A Challenge for serialized processor design and implementation
    130391: 08/03/21: Antti: Re: A Challenge for serialized processor design and implementation
    130414: 08/03/22: Thad Smith: Re: A Challenge for serialized processor design and implementation
    130415: 08/03/22: <referringto@googlemail.com>: Re: A Challenge for serialized processor design and implementation
        130428: 08/03/23: glen herrmannsfeldt: Re: A Challenge for serialized processor design and implementation
            130464: 08/03/25: Jim Granville: Re: A Challenge for serialized processor design and implementation
    130435: 08/03/24: <referringto@googlemail.com>: Re: A Challenge for serialized processor design and implementation
    130516: 08/03/26: Albert van der Horst: Re: A Challenge for serialized processor design and implementation
    130546: 08/03/26: Ron N.: Re: A Challenge for serialized processor design and implementation
        130566: 08/03/27: David Brown: Re: A Challenge for serialized processor design and implementation
            130575: 08/03/27: Walter Banks: Re: A Challenge for serialized processor design and implementation
        130567: 08/03/27: Walter Banks: Re: A Challenge for serialized processor design and implementation
            130570: 08/03/27: Krzysztof Kepa: Re: A Challenge for serialized processor design and implementation
                130576: 08/03/27: Michael N. Moran: Re: A Challenge for serialized processor design and implementation
                    130579: 08/03/27: Krzysztof Kepa: Re: A Challenge for serialized processor design and implementation
                130577: 08/03/27: Krzysztof Kepa: Re: A Challenge for serialized processor design and implementation
                130578: 08/03/27: Walter Banks: Re: A Challenge for serialized processor design and implementation
            130572: 08/03/27: Spehro Pefhany: Re: A Challenge for serialized processor design and implementation
            130588: 08/03/27: Everett M. Greene: Re: A Challenge for serialized processor design and implementation
                130591: 08/03/27: Andy Botterill: Re: A Challenge for serialized processor design and implementation
                    130620: 08/03/28: Everett M. Greene: Re: A Challenge for serialized processor design and implementation
                130594: 08/03/27: Walter Banks: Re: A Challenge for serialized processor design and implementation
                130605: 08/03/28: David Brown: Re: A Challenge for serialized processor design and implementation
                    130621: 08/03/28: Everett M. Greene: Re: A Challenge for serialized processor design and implementation
                        130924: 08/04/05: glen herrmannsfeldt: Re: A Challenge for serialized processor design and implementation
                            130925: 08/04/05: Paul Keinanen: Re: A Challenge for serialized processor design and implementation
    130585: 08/03/27: Ron N.: Re: A Challenge for serialized processor design and implementation
    130595: 08/03/27: Walter Banks: Re: A Challenge for serialized processor design and implementation
    130628: 08/03/28: Ron N.: Re: A Challenge for serialized processor design and implementation
    130724: 08/03/31: rickman: Re: A Challenge for serialized processor design and implementation
    130727: 08/03/31: Antti: Re: A Challenge for serialized processor design and implementation
    130771: 08/04/01: rickman: Re: A Challenge for serialized processor design and implementation
    130856: 08/04/03: <referringto@googlemail.com>: Re: A Challenge for serialized processor design and implementation
    130857: 08/04/03: <referringto@googlemail.com>: Re: A Challenge for serialized processor design and implementation
        130864: 08/04/04: Jim Granville: Re: A Challenge for serialized processor design and implementation
            130883: 08/04/04: Jim Granville: Re: A Challenge for serialized processor design and implementation
            130934: 08/04/06: Jim Granville: Re: A Challenge for serialized processor design and implementation
    130873: 08/04/03: <referringto@googlemail.com>: Re: A Challenge for serialized processor design and implementation
    130988: 08/04/07: Ray Andraka: Re: A Challenge for serialized processor design and implementation
    131039: 08/04/09: Jim Granville: Re: A Challenge for serialized processor design and implementation
        131076: 08/04/10: Jim Granville: Re: A Challenge for serialized processor design and implementation
    131073: 08/04/09: rickman: Re: A Challenge for serialized processor design and implementation
    131075: 08/04/09: Antti: Re: A Challenge for serialized processor design and implementation
130272: 08/03/19: ratztafaz: ISE 10.0 finally with multi-threading and SV support ?
    130273: 08/03/19: Jon Beniston: Re: ISE 10.0 finally with multi-threading and SV support ?
    130277: 08/03/19: <sky465nm@trline4.org>: Re: ISE 10.0 finally with multi-threading and SV support ?
        130285: 08/03/19: Uwe Bonnes: Re: ISE 10.0 finally with multi-threading and SV support ?
            130297: 08/03/19: <sky465nm@trline4.org>: Re: ISE 10.0 finally with multi-threading and SV support ?
    130284: 08/03/19: ratztafaz: Re: ISE 10.0 finally with multi-threading and SV support ?
    130329: 08/03/20: Kolja Sulimma: Re: ISE 10.0 finally with multi-threading and SV support ?
        130513: 08/03/26: Andreas Ehliar: Re: ISE 10.0 finally with multi-threading and SV support ?
    130343: 08/03/20: <jb@capsec.org>: Re: ISE 10.0 finally with multi-threading and SV support ?
    130376: 08/03/21: Kolja Sulimma: Re: ISE 10.0 finally with multi-threading and SV support ?
    130396: 08/03/21: <aludwin@altera.com>: Re: ISE 10.0 finally with multi-threading and SV support ?
    130399: 08/03/21: <steve.lass@xilinx.com>: Re: ISE 10.0 finally with multi-threading and SV support ?
        130405: 08/03/22: Jonathan Bromley: Re: ISE 10.0 finally with multi-threading and SV support ?
    130420: 08/03/23: Kolja Sulimma: Re: ISE 10.0 finally with multi-threading and SV support ?
    130432: 08/03/23: Paul Leventis: Re: ISE 10.0 finally with multi-threading and SV support ?
    130438: 08/03/24: Kolja Sulimma: Re: ISE 10.0 finally with multi-threading and SV support ?
    130451: 08/03/24: <aludwin@altera.com>: Re: ISE 10.0 finally with multi-threading and SV support ?
    130478: 08/03/25: Kolja Sulimma: Re: ISE 10.0 finally with multi-threading and SV support ?
    130494: 08/03/25: Paul Leventis: Re: ISE 10.0 finally with multi-threading and SV support ?
    130514: 08/03/26: ratztafaz: Re: ISE 10.0 finally with multi-threading and SV support ?
    130521: 08/03/26: Kolja Sulimma: Re: ISE 10.0 finally with multi-threading and SV support ?
    130796: 08/04/01: Andy Peters: Re: ISE 10.0 finally with multi-threading and SV support ?
130283: 08/03/19: <robertwalczyk@gmail.com>: DDR SDRAM interface for Virtex II Pro and Spartan3a
    130337: 08/03/20: Nico Coesel: Re: DDR SDRAM interface for Virtex II Pro and Spartan3a
130289: 08/03/19: Subroto Datta: Re: Using TimeQuest Timing Analyzer
130296: 08/03/19: maxi: Altera EPM7032S reading checksum
    130312: 08/03/20: <SKatsyuba@gmail.com>: Re: Altera EPM7032S reading checksum
130300: 08/03/19: <bin.arthur@gmail.com>: Linux 2.6 PCI Device Driver on Virtex 4
    130598: 08/03/28: John Williams: Re: Linux 2.6 PCI Device Driver on Virtex 4
    130632: 08/03/28: <bin.arthur@gmail.com>: Re: Linux 2.6 PCI Device Driver on Virtex 4
130313: 08/03/20: <sky465nm@trline4.org>: SD-Card SDHC artificial 32GB limit
130315: 08/03/20: <sky465nm@trline4.org>: Configure Spartan-3E w SD-Card?
    130316: 08/03/20: Antti: Re: Configure Spartan-3E w SD-Card?
        130317: 08/03/20: <sky465nm@trline4.org>: Re: Configure Spartan-3E w SD-Card?
        130319: 08/03/20: Antti: Re: Configure Spartan-3E w SD-Card?
    130321: 08/03/20: <job@amontec.com>: Re: Configure Spartan-3E w SD-Card?
        130325: 08/03/20: Antti: Re: Configure Spartan-3E w SD-Card?
        130327: 08/03/20: <job@amontec.com>: Re: Configure Spartan-3E w SD-Card?
        130328: 08/03/20: Antti: Re: Configure Spartan-3E w SD-Card?
130326: 08/03/20: Paul Boven: Configuring a Spartan 3A1800 ExtremeDSP from Spartan3 cable?
    130347: 08/03/20: emeb: Re: Configuring a Spartan 3A1800 ExtremeDSP from Spartan3 cable?
        130689: 08/03/30: Paul Boven: Re: Configuring a Spartan 3A1800 ExtremeDSP from Spartan3 cable?
130332: 08/03/20: water9580@yahoo.com: PCI Express Configuration Testing
    130453: 08/03/24: water9580@yahoo.com: Re: PCI Express Configuration Testing
        130454: 08/03/24: John_H: Re: PCI Express Configuration Testing
            130538: 08/03/26: Rube Bumpkin: Re: PCI Express Configuration Testing
                130597: 08/03/27: Rube Bumpkin: Re: PCI Express Configuration Testing
                    130866: 08/04/03: Rube Bumpkin: Re: PCI Express Configuration Testing
    130506: 08/03/25: water9580@yahoo.com: Re: PCI Express Configuration Testing
    130548: 08/03/26: water9580@yahoo.com: Re: PCI Express Configuration Testing
    130755: 08/03/31: water9580@yahoo.com: Re: PCI Express Configuration Testing
130333: 08/03/20: ahosyney: Power Estimation of Microblaze (Power PC) based architectures
    130334: 08/03/20: ahosyney: Re: Power Estimation of Microblaze (Power PC) based architectures
    130379: 08/03/21: austin: Re: Power Estimation of Microblaze (Power PC) based architectures
    130511: 08/03/26: Philip Potter: Re: Power Estimation of Microblaze (Power PC) based architectures
    130851: 08/04/03: ahosyney: Re: Power Estimation of Microblaze (Power PC) based architectures
130336: 08/03/20: u_stadler@yahoo.de: timing and timing reports (again)
    130341: 08/03/20: Pat: Re: timing and timing reports (again)
        130417: 08/03/22: jtw: Re: timing and timing reports (again)
    130348: 08/03/20: u_stadler@yahoo.de: Re: timing and timing reports (again)
    130350: 08/03/20: u_stadler@yahoo.de: Re: timing and timing reports (again)
130339: 08/03/20: fl: Is there a means to conditional synthesis in VHDL?
    130340: 08/03/20: Jonathan Bromley: Re: Is there a means to conditional synthesis in VHDL?
    130344: 08/03/20: KJ: Re: Is there a means to conditional synthesis in VHDL?
    130362: 08/03/21: Martin Thompson: Re: Is there a means to conditional synthesis in VHDL?
    130377: 08/03/21: Kolja Sulimma: Re: Is there a means to conditional synthesis in VHDL?
130342: 08/03/20: Dave Pollum: Modelsim XE III 6.x - huge fonts
    130346: 08/03/20: Dave Pollum: Re: Modelsim XE III 6.x - huge fonts
        130427: 08/03/23: Jonathan Bromley: Re: Modelsim XE III 6.x - huge fonts
    130352: 08/03/20: Dave Pollum: Re: Modelsim XE III 6.x - huge fonts
    130423: 08/03/23: Dave Pollum: Re: Modelsim XE III 6.x - huge fonts
    130447: 08/03/24: Dave Pollum: Re: Modelsim XE III 6.x - huge fonts
130354: 08/03/20: Fei Liu: verilog question, break while loop to avoid combinational feedback
    130361: 08/03/21: Jonathan Bromley: Re: verilog question, break while loop to avoid combinational feedback during synthesis
        130366: 08/03/21: Fei Liu: Re: verilog question, break while loop to avoid combinational feedback
            130375: 08/03/21: Jonathan Bromley: Re: verilog question, break while loop to avoid combinational feedback during synthesis
    130392: 08/03/21: Gabor: Re: verilog question, break while loop to avoid combinational
130356: 08/03/20: Brian Davis: Synoplify ???
    130357: 08/03/20: John_H: Re: Synoplify ???
        130360: 08/03/21: Allan Herriman: Re: Synoplify ???
            130365: 08/03/21: <sky465nm@trline4.org>: Re: Synoplify ???
            130370: 08/03/21: Mike Treseler: Re: Synoplify ???
                130373: 08/03/21: David Spencer: Re: Synoplify ???
                130381: 08/03/21: Mike Treseler: Re: Synoplify ???
                    130559: 08/03/27: Kim Enkovaara: Re: Synoplify ???
                        130573: 08/03/27: Mike Treseler: Re: Synoplify ???
                130387: 08/03/21: Symon: Re: Synoplify ???
    130359: 08/03/21: HT-Lab: Re: Synoplify ???
    130380: 08/03/21: <ghelbig@lycos.com>: Re: Synoplify ???
130358: 08/03/21: Giuseppe Marullo: Spartan 3E intefacing for dummies
    130364: 08/03/21: <sky465nm@trline4.org>: Re: Spartan 3E intefacing for dummies
        130385: 08/03/21: Eric Crabill: Re: Spartan 3E intefacing for dummies
            130388: 08/03/21: David Spencer: Re: Spartan 3E intefacing for dummies
                130400: 08/03/22: <sky465nm@trline4.org>: Re: Spartan 3E intefacing for dummies
                130439: 08/03/24: David Spencer: Re: Spartan 3E intefacing for dummies
                    130443: 08/03/24: Andy Botterill: Re: Spartan 3E intefacing for dummies
                        130449: 08/03/24: Alex Freed: Re: Spartan 3E intefacing for dummies
                    130444: 08/03/24: Alex Freed: Re: Spartan 3E intefacing for dummies
    130394: 08/03/21: Peter Alfke: Re: Spartan 3E intefacing for dummies
    130395: 08/03/21: John Adair: Re: Spartan 3E intefacing for dummies
        130398: 08/03/22: Giuseppe Marullo: Re: Spartan 3E intefacing for dummies
            130406: 08/03/22: Giuseppe Marullo: Re: Spartan 3E intefacing for dummies
    130403: 08/03/22: mng: Re: Spartan 3E intefacing for dummies
    130448: 08/03/24: Peter Alfke: Re: Spartan 3E intefacing for dummies
130367: 08/03/21: u_stadler@yahoo.de: chip scope
    130374: 08/03/21: Symon: Re: chip scope
        130382: 08/03/21: Symon: Re: chip scope
    130378: 08/03/21: u_stadler@yahoo.de: Re: chip scope
130384: 08/03/21: kkoorndyk: Actel SX-A Timing Constraints Issues
    130386: 08/03/21: Mike Treseler: Re: Actel SX-A Timing Constraints Issues
    130389: 08/03/21: David Spencer: Re: Actel SX-A Timing Constraints Issues
    130390: 08/03/21: kkoorndyk: Re: Actel SX-A Timing Constraints Issues
    130457: 08/03/24: Thomas Stanka: Re: Actel SX-A Timing Constraints Issues
130401: 08/03/21: Fei Liu: problem testing the serial interface code from fpga4fun
    130416: 08/03/22: Fei Liu: Re: problem testing the serial interface code from fpga4fun
130402: 08/03/22: Joseph: Viewing internal signals with ModelSim
    130404: 08/03/22: HT-Lab: Re: Viewing internal signals with ModelSim
    130409: 08/03/23: David R Brooks: Re: Viewing internal signals with ModelSim
    130589: 08/03/27: Kevin Neilson: Re: Viewing internal signals with ModelSim
130408: 08/03/22: John Adair: Raggedstone1 OEM Pricing now released.
130411: 08/03/22: anilcelebi: High speed memory read and transfer via rocket IO..
    130412: 08/03/22: KJ: Re: High speed memory read and transfer via rocket IO..
    130413: 08/03/22: austin: Re: High speed memory read and transfer via rocket IO..
    130418: 08/03/23: anilcelebi: Re: High speed memory read and transfer via rocket IO..
    130419: 08/03/23: anilcelebi: Re: High speed memory read and transfer via rocket IO..
    130421: 08/03/23: Kolja Sulimma: Re: High speed memory read and transfer via rocket IO..
    130429: 08/03/23: anilcelebi: Re: High speed memory read and transfer via rocket IO..
130430: 08/03/23: BobW: Re: counterfeit Xilinx ?
130431: 08/03/23: Jon Elson: counterfeit Xilinx ?
    130433: 08/03/24: -jg: Re: counterfeit Xilinx ?
    130434: 08/03/24: <sky465nm@trline4.org>: Re: counterfeit Xilinx ?
        130441: 08/03/24: Jon Elson: Re: counterfeit Xilinx ?
            130442: 08/03/24: BobW: Re: counterfeit Xilinx ?
            130450: 08/03/24: <sky465nm@trline4.org>: Re: counterfeit Xilinx ?
            130493: 08/03/25: Jon Elson: Re: counterfeit Xilinx ?
                130498: 08/03/25: BobW: Re: counterfeit Xilinx ?
                    130507: 08/03/26: Jim Granville: Re: counterfeit Xilinx ?
                        130509: 08/03/25: Jon Elson: Re: counterfeit Xilinx ?
                    130508: 08/03/25: Jon Elson: Re: counterfeit Xilinx ?
    130446: 08/03/24: Peter Alfke: Re: counterfeit Xilinx ?
    130497: 08/03/25: Peter Alfke: Re: counterfeit Xilinx ?
    130504: 08/03/25: Peter Alfke: Re: counterfeit Xilinx ?
    130515: 08/03/26: Georg Acher: Re: counterfeit Xilinx ?
        130535: 08/03/26: Jon Elson: Re: counterfeit Xilinx ?
        130551: 08/03/26: Jon Elson: Re: counterfeit Xilinx ?
            130564: 08/03/27: Georg Acher: Re: counterfeit Xilinx ?
                130582: 08/03/27: Jon Elson: Re: counterfeit Xilinx ?
                    130826: 08/04/03: Jim Granville: Re: counterfeit Xilinx ?
                        130830: 08/04/03: Jim Granville: Re: counterfeit Xilinx ?
                            130854: 08/04/03: Jon Elson: Re: counterfeit Xilinx ?
    130523: 08/03/26: jon: Re: counterfeit Xilinx ?
    130822: 08/04/02: <craig.taylor@xilinx.com>: Re: counterfeit Xilinx ?
    130825: 08/04/02: Peter Alfke: Re: counterfeit Xilinx ?
    130846: 08/04/03: Craig: Re: counterfeit Xilinx ?
    130870: 08/04/03: John McCaskill: Re: counterfeit Xilinx ?
        130905: 08/04/04: Jon Elson: Re: counterfeit Xilinx ?
            130916: 08/04/05: Jim Granville: Re: counterfeit Xilinx ?
                130974: 08/04/07: Jon Elson: Re: counterfeit Xilinx ?
                    130977: 08/04/08: Jim Granville: Re: counterfeit Xilinx ?
            130973: 08/04/07: Jon Elson: Re: counterfeit Xilinx ?
                130976: 08/04/07: Uwe Bonnes: Re: counterfeit Xilinx ?
    130907: 08/04/04: John_H: Re: counterfeit Xilinx ?
    131489: 08/04/22: -jg: Re: counterfeit Xilinx ?
130437: 08/03/24: rponsard@gmail.com: using mpmc ddr2 controller with an other processor
    130440: 08/03/24: morphiend: Re: using mpmc ddr2 controller with an other processor
130445: 08/03/24: ni: BYTE shifter
    130452: 08/03/25: KJ: Re: BYTE shifter
    130487: 08/03/25: ni: Re: BYTE shifter
130455: 08/03/24: <mvjijuaie@gmail.com>: AWGN in vhdl
    130503: 08/03/25: Kevin Neilson: Re: AWGN in vhdl
130458: 08/03/24: Antti: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130459: 08/03/24: Antti: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
        130466: 08/03/25: Uwe Bonnes: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
            130472: 08/03/25: Symon: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
                130474: 08/03/25: <sky465nm@trline4.org>: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
                    130482: 08/03/25: David Brown: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
                        130488: 08/03/25: DJ Delorie: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
                            130510: 08/03/26: David Brown: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
        130475: 08/03/25: <sky465nm@trline4.org>: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
        130483: 08/03/25: Paul Boven: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130461: 08/03/25: Antti: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130462: 08/03/25: Antti: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130467: 08/03/25: Antti: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130468: 08/03/25: Antti: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130470: 08/03/25: John Adair: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130471: 08/03/25: Antti: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130479: 08/03/25: Kolja Sulimma: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130481: 08/03/25: Antti: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130484: 08/03/25: Steve Knapp: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
        130526: 08/03/26: Steve Knapp: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
        130528: 08/03/26: Steve Knapp: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130486: 08/03/25: Antti: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130489: 08/03/25: Peter Alfke: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130490: 08/03/25: Antti: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130626: 08/03/28: dalai lamah: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
        130887: 08/04/04: Symon: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
        130888: 08/04/04: David Brown: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
            130903: 08/04/04: dalai lamah: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
                130959: 08/04/07: David Brown: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
                    130964: 08/04/07: Symon: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
                        130965: 08/04/07: David Brown: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
                    130972: 08/04/07: dalai lamah: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130859: 08/04/03: <mdschulte@gmail.com>: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130460: 08/03/25: Catalin Patulea (eigma): Re: Remote access to Altera FPGA via jtagd in Linux
130473: 08/03/25: <wlpstxzhd@gmail.com>: Chipscope analyzer GUI problem in Linux
    130501: 08/03/25: Simon: Re: Chipscope analyzer GUI problem in Linux
130477: 08/03/25: chestnut: why Xilinx doesn't support Dual-Rank DIMM
130480: 08/03/25: <oscar.odetti@gmail.com>: EDK9.2 microblaze tutorial
    130530: 08/03/26: Pablo: Re: EDK9.2 microblaze tutorial
    130560: 08/03/27: <oscar.odetti@gmail.com>: Re: EDK9.2 microblaze tutorial
130485: 08/03/25: test: MP7 and Actel Fusion FPGA
130491: 08/03/25: soxmax: Timing constraints in ucf
    130495: 08/03/25: Paul Urbanus: Re: Timing constraints in ucf
    130496: 08/03/25: austin: Re: Timing constraints in ucf
        130505: 08/03/25: Paul Urbanus: Re: Timing constraints in ucf
            130519: 08/03/26: austin: Re: Timing constraints in ucf
            130544: 08/03/27: Symon: Re: Timing constraints in ucf
    130500: 08/03/25: MM: Re: Timing constraints in ucf
130492: 08/03/25: Antti: new Virtex-5 info
130499: 08/03/25: <RotorLe@gmail.com>: How to report LABs' fanout automatically
130512: 08/03/26: <shakith.fernando@gmail.com>: Serial Transmission w/o 8B/10B encoding
    130517: 08/03/26: BobW: Re: Serial Transmission w/o 8B/10B encoding
        130709: 08/03/30: TC: Re: Serial Transmission w/o 8B/10B encoding
            131070: 08/04/09: glen herrmannsfeldt: Re: Serial Transmission w/o 8B/10B encoding
            131102: 08/04/10: Eric Smith: Re: Serial Transmission w/o 8B/10B encoding
            131155: 08/04/13: glen herrmannsfeldt: Re: Serial Transmission w/o 8B/10B encoding
                131156: 08/04/13: Brian Drummond: Re: Serial Transmission w/o 8B/10B encoding
    130524: 08/03/26: Dave: Re: Serial Transmission w/o 8B/10B encoding
    130525: 08/03/26: <jeffjcannon@gmail.com>: Re: Serial Transmission w/o 8B/10B encoding
    131067: 08/04/09: <shakith.fernando@gmail.com>: Re: Serial Transmission w/o 8B/10B encoding
    131074: 08/04/09: Peter Alfke: Re: Serial Transmission w/o 8B/10B encoding
    131079: 08/04/09: <shakith.fernando@gmail.com>: Re: Serial Transmission w/o 8B/10B encoding
    131082: 08/04/09: Peter Alfke: Re: Serial Transmission w/o 8B/10B encoding
    131083: 08/04/09: Peter Alfke: Re: Serial Transmission w/o 8B/10B encoding
130518: 08/03/26: <SaTaN0rX@googlemail.com>: How to run a block with half the clockspeed on virtex 5
    130520: 08/03/26: Peter Alfke: Re: How to run a block with half the clockspeed on virtex 5
        130534: 08/03/26: Symon: Re: How to run a block with half the clockspeed on virtex 5
    130522: 08/03/26: <SaTaN0rX@googlemail.com>: Re: How to run a block with half the clockspeed on virtex 5
    130561: 08/03/27: <SaTaN0rX@googlemail.com>: Re: How to run a block with half the clockspeed on virtex 5
130527: 08/03/26: Pablo: Is it possible to set Instruction PowerPC Bus ONLY for 32 bits
130529: 08/03/26: PatC: Re: VHDL document generation utilities
130531: 08/03/26: MM: VHDL document generation utilities
    130532: 08/03/26: Mike Treseler: Re: VHDL document generation utilities
    130533: 08/03/26: dalai lamah: Re: VHDL document generation utilities
    130536: 08/03/26: Reuven: Re: VHDL document generation utilities
    130556: 08/03/27: <moogyd@yahoo.co.uk>: Re: VHDL document generation utilities
    130580: 08/03/27: Nico Coesel: Re: VHDL document generation utilities
        130584: 08/03/27: Mike Treseler: Re: VHDL document generation utilities
            130586: 08/03/27: KJ: Re: VHDL document generation utilities
            130617: 08/03/28: Nico Coesel: Re: VHDL document generation utilities
        130606: 08/03/28: David Brown: Re: VHDL document generation utilities
        132360: 08/05/23: Colin Paul Gloster: Re: VHDL document generation utilities
130537: 08/03/26: Ashok Chotai: Places to visit in Amsterdam and Brussells
    130539: 08/03/26: Alan Nishioka: Re: Places to visit in Amsterdam and Brussells
        130547: 08/03/26: BobW: Re: Places to visit in Amsterdam and Brussells
        130549: 08/03/26: BobW: Re: Places to visit in Amsterdam and Brussells
            130552: 08/03/27: MM: Re: Places to visit in Amsterdam and Brussells
                130553: 08/03/26: BobW: Re: Places to visit in Amsterdam and Brussells
                    130555: 08/03/27: MM: Re: Places to visit in Amsterdam and Brussells
                        130716: 08/03/31: Nial Stewart: Re: Places to visit in Amsterdam and Brussells
        130550: 08/03/26: MM: Re: Places to visit in Amsterdam and Brussells
        130602: 08/03/27: Alan Nishioka: Re: Places to visit in Amsterdam and Brussells
    130540: 08/03/26: Kevin Neilson: Re: Places to visit in Amsterdam and Brussells
    130554: 08/03/27: Andy Botterill: Re: Places to visit in Amsterdam and Brussells
        130583: 08/03/27: Peter Alfke: Re: Places to visit in Amsterdam and Brussells
    130618: 08/03/28: Nico Coesel: Re: Places to visit in Amsterdam and Brussells
130541: 08/03/26: sarah_s: Simulink(matlab)/FPGA serial port communication
    130542: 08/03/26: sarah_s: Re: Simulink(matlab)/FPGA serial port communication
130543: 08/03/26: sarah_s: Simulink(Matlab)/FPGA serial communication
    130574: 08/03/27: bertus: Re: Simulink(Matlab)/FPGA serial communication
    130600: 08/03/27: sarah_s: Re: Simulink(Matlab)/FPGA serial communication
    130601: 08/03/27: sarah_s: Re: Simulink(Matlab)/FPGA serial communication
    130604: 08/03/27: mng: Re: Simulink(Matlab)/FPGA serial communication
130557: 08/03/27: rponsard@gmail.com: ddr2 controller for xilinx 1800a dsp starter kit
130562: 08/03/27: <ashwinihs@gmail.com>: Xilinx ISE 9.2i out of memory
    130563: 08/03/27: Symon: Re: Xilinx ISE 9.2i out of memory
    130565: 08/03/27: Brian Drummond: Re: Xilinx ISE 9.2i out of memory
    130581: 08/03/27: morphiend: Re: Xilinx ISE 9.2i out of memory
    130593: 08/03/27: <jprovidenza@yahoo.com>: Re: Xilinx ISE 9.2i out of memory
130568: 08/03/27: bertus: zpu processor core
130569: 08/03/27: <ashwinihs@gmail.com>: Sub: Strange problem with Xilinx ISE 8.1 and Chipscope Pro 8.1
130571: 08/03/27: <ashwinihs@gmail.com>: [CORRECTED] Strange problem with Xilinx ISE 8.1 and Chipscope Pro 8.1
130587: 08/03/27: <scott.yuan523@gmail.com>: Dual Independent Aurora Links on One GTP Tile
130592: 08/03/27: grky: need help.....how do i download an image onto a virtex 4 fpga
    130599: 08/03/28: Symon: Re: need help.....how do i download an image onto a virtex 4 fpga
        130642: 08/03/29: Sean Durkin: Re: need help.....how do i download an image onto a virtex 4 fpga
130596: 08/03/27: <jayblue_16@yahoo.com>: Re: problem simulating in modelsim - swiftpli_mti.dll
130603: 08/03/27: maverick: FPGA board with an ADC
130607: 08/03/28: Sharan: CAM implementation using Dual port ram
    130616: 08/03/28: Jonathan Bromley: Re: CAM implementation using Dual port ram
130608: 08/03/28: <shakith.fernando@gmail.com>: PCI Express Switch
130609: 08/03/28: <ghori.asad@gmail.com>: JavaBotics Marmaduke board
130610: 08/03/28: Colin Paul Gloster: Sorry to Those Who Deem This to be Spam: Employment or Scholarship
    130611: 08/03/28: Jon Beniston: Re: Sorry to Those Who Deem This to be Spam: Employment or
    130612: 08/03/28: Symon: Re: Sorry to Those Who Deem This to be Spam: Employment or Scholarship Sought
        130893: 08/04/04: Colin Paul Gloster: Re: Sorry to Those Who Deem This to be Spam: Employment or Scholarship
    130640: 08/03/29: Uncle Noah: Re: Sorry to Those Who Deem This to be Spam: Employment or
    130894: 08/04/04: Colin Paul Gloster: Re: Sorry to Those Who Deem This to be Spam: Employment or Scholarship
130613: 08/03/28: bhb: problem with uartlite in microblaze
130614: 08/03/28: emeb: ISE 10.1 XST runs in background?
    130615: 08/03/28: emeb: Re: ISE 10.1 XST runs in background?
130619: 08/03/28: FPGA: quick question
    130622: 08/03/28: mk: Re: quick question
        130627: 08/03/28: Kevin Neilson: Re: quick question
            130636: 08/03/28: John_H: Re: quick question
    130738: 08/03/31: FPGA: Re: quick question
130623: 08/03/28: <jonas@mit.edu>: Webpack 10.1 on 64-bit linux
    130624: 08/03/28: <jonas@mit.edu>: Re: Webpack 10.1 on 64-bit linux
    130707: 08/03/30: pillar2012@gmail.com: Re: Webpack 10.1 on 64-bit linux
    130726: 08/03/31: <jonas@mit.edu>: Re: Webpack 10.1 on 64-bit linux
    130744: 08/03/31: pillar2012@gmail.com: Re: Webpack 10.1 on 64-bit linux
    130757: 08/03/31: <jonas@mit.edu>: Re: Webpack 10.1 on 64-bit linux
    130898: 08/04/04: pillar2012@gmail.com: Re: Webpack 10.1 on 64-bit linux
130625: 08/03/28: MM: Can't read external Flash in a V4 based PPC system through gdb
130629: 08/03/28: Dale: Having trouble building an old Xilinx Spartan3 FPGA project I did on
    130630: 08/03/28: Mike Treseler: Re: Having trouble building an old Xilinx Spartan3 FPGA project I
    130631: 08/03/28: <sky465nm@trline4.org>: Re: Having trouble building an old Xilinx Spartan3 FPGA project I did on ISE 8.2i and EDK8.2 for microblaze. Also have ISE9.2i installed.
    130633: 08/03/28: Dale: Re: Having trouble building an old Xilinx Spartan3 FPGA project I did
    130634: 08/03/28: MM: Re: Having trouble building an old Xilinx Spartan3 FPGA project I did on ISE 8.2i and EDK8.2 for microblaze. Also have ISE9.2i installed.
    130635: 08/03/28: MM: Re: Having trouble building an old Xilinx Spartan3 FPGA project I did on ISE 8.2i and EDK8.2 for microblaze. Also have ISE9.2i installed.
    130645: 08/03/29: Brian Drummond: Re: Having trouble building an old Xilinx Spartan3 FPGA project I did on ISE 8.2i and EDK8.2 for microblaze. Also have ISE9.2i installed.
130637: 08/03/29: Tony Burch: FPGA beginner video guide, blog comments by Max Maxfield
130638: 08/03/29: Tony Burch: Newbies: Answer to "What is an FPGA?" in video
    130639: 08/03/29: <sky465nm@trline4.org>: Re: Newbies: Answer to "What is an FPGA?" in video
        130654: 08/03/29: Mike Treseler: Re: Newbies: Answer to "What is an FPGA?" in video
    130672: 08/03/29: Dave Pollum: Re: Newbies: Answer to "What is an FPGA?" in video
130641: 08/03/29: Antti: async clk input, clock glitches
    130643: 08/03/29: Icky Thwacket: Re: async clk input, clock glitches
    130644: 08/03/29: Frank Buss: Re: async clk input, clock glitches
    130646: 08/03/29: Brian Drummond: Re: async clk input, clock glitches
    130647: 08/03/29: Symon: Re: async clk input, clock glitches
    130648: 08/03/29: <job@amontec.com>: Re: async clk input, clock glitches
    130651: 08/03/29: KJ: Re: async clk input, clock glitches
        130660: 08/03/29: KJ: Re: async clk input, clock glitches
            130677: 08/03/30: Icky Thwacket: Re: async clk input, clock glitches
                130679: 08/03/30: Icky Thwacket: Re: async clk input, clock glitches
                130681: 08/03/30: Falk Brunner: Re: async clk input, clock glitches
            130690: 08/03/30: KJ: Re: async clk input, clock glitches
            130692: 08/03/30: KJ: Re: async clk input, clock glitches
            130695: 08/03/30: KJ: Re: async clk input, clock glitches
                130698: 08/03/30: KJ: Re: async clk input, clock glitches
                    130699: 08/03/30: KJ: Re: async clk input, clock glitches
            130696: 08/03/31: Jim Granville: Re: async clk input, clock glitches
                130704: 08/03/31: Jim Granville: Re: async clk input, clock glitches
            130828: 08/04/02: Jon Elson: Re: async clk input, clock glitches
                130833: 08/04/03: Nial Stewart: Re: async clk input, clock glitches
                130842: 08/04/03: Symon: Re: async clk input, clock glitches
                130849: 08/04/03: Muzaffer Kal: Re: async clk input, clock glitches
        130666: 08/03/30: Jim Granville: Re: async clk input, clock glitches
        130667: 08/03/30: Jim Granville: Re: async clk input, clock glitches
        130827: 08/04/02: Jon Elson: Re: async clk input, clock glitches
    130653: 08/03/29: Peter Alfke: Re: async clk input, clock glitches
        130658: 08/03/29: mk: Re: async clk input, clock glitches
            130659: 08/03/29: mk: Re: async clk input, clock glitches
        130665: 08/03/30: Jim Granville: Re: async clk input, clock glitches
    130656: 08/03/29: Antti: Re: async clk input, clock glitches
    130657: 08/03/29: Antti: Re: async clk input, clock glitches
    130661: 08/03/29: Mike Treseler: Re: async clk input, clock glitches
        130663: 08/03/29: KJ: Re: async clk input, clock glitches
            130669: 08/03/30: Jim Granville: Re: async clk input, clock glitches
                130694: 08/03/30: KJ: Re: async clk input, clock glitches
                    130705: 08/03/31: Jim Granville: Re: async clk input, clock glitches
        130702: 08/03/30: KJ: Re: async clk input, clock glitches
    130662: 08/03/29: Antti: Re: async clk input, clock glitches
    130664: 08/03/29: Peter Alfke: Re: async clk input, clock glitches
    130675: 08/03/30: Antti: Re: async clk input, clock glitches
    130676: 08/03/30: Antti: Re: async clk input, clock glitches
    130678: 08/03/30: Antti: Re: async clk input, clock glitches
    130683: 08/03/30: Antti: Re: async clk input, clock glitches
    130684: 08/03/30: Antti: Re: async clk input, clock glitches
    130693: 08/03/30: Antti: Re: async clk input, clock glitches
    130697: 08/03/30: Antti: Re: async clk input, clock glitches
    130700: 08/03/30: <job@amontec.com>: Re: async clk input, clock glitches
    130701: 08/03/30: Antti: Re: async clk input, clock glitches
    130703: 08/03/30: Antti: Re: async clk input, clock glitches
    130769: 08/04/01: Nial Stewart: Antii, can you give us an update?
        130928: 08/04/05: Brian Drummond: Re: Antii, can you give us an update?
            130970: 08/04/07: Brian Drummond: Re: Antii, can you give us an update?
    130782: 08/04/01: Peter Alfke: Re: Antii, can you give us an update?
    130783: 08/04/01: Antti: Re: Antii, can you give us an update?
    130788: 08/04/01: KJ: Re: Antii, can you give us an update?
    130789: 08/04/01: Antti: Re: Antii, can you give us an update?
    130815: 08/04/02: Antti: Re: Antii, can you give us an update?
    130829: 08/04/02: Peter Alfke: Re: async clk input, clock glitches
    130831: 08/04/02: Peter Alfke: Re: async clk input, clock glitches
    130832: 08/04/03: Torsten Landschoff: Re: async clk input, clock glitches
    130921: 08/04/04: Antti: Re: Antii, can you give us an update?
    130929: 08/04/05: Antti: Re: Antii, can you give us an update?
    130943: 08/04/06: Antti: Re: Antii, can you give us an update?
130649: 08/03/29: emeb: ISE 10.1 - Initial experience
    130650: 08/03/29: Frank Buss: Re: ISE 10.1 - Initial experience
    130652: 08/03/29: <job@amontec.com>: Re: ISE 10.1 - Initial experience
        130670: 08/03/30: Jim Granville: Re: ISE 10.1 - Initial experience
            130671: 08/03/29: austin: Re: ISE 10.1 - Initial experience
                130686: 08/03/30: austin: Re: ISE 10.1 - Initial experience
                    130715: 08/03/31: Morten Leikvoll: Re: ISE 10.1 - Initial experience
                        130747: 08/04/01: Jim Granville: Re: ISE 10.1 - Initial experience
                        130787: 08/04/01: Sonal Santan: Re: ISE 10.1 - Initial experience
                    130762: 08/04/01: Jim Granville: Re: ISE 10.1 - Initial experience
    130673: 08/03/30: A.D.: Re: ISE 10.1 - Initial experience
    130674: 08/03/30: Antti: Re: ISE 10.1 - Initial experience
    130688: 08/03/30: Antti: Re: ISE 10.1 - Initial experience
    130691: 08/03/30: Alain: Re: ISE 10.1 - Initial experience
    130711: 08/03/31: Zara: Re: ISE 10.1 - Initial experience
    130723: 08/03/31: Kolja Sulimma: Re: ISE 10.1 - Initial experience
    130730: 08/03/31: Antti: Re: ISE 10.1 - Initial experience
    130733: 08/03/31: Antti: Re: ISE 10.1 - Initial experience
    130745: 08/03/31: Antti: Re: ISE 10.1 - Initial experience
    130751: 08/03/31: emeb: Re: ISE 10.1 - Initial experience
    130758: 08/04/01: Kolja Sulimma: Re: ISE 10.1 - Initial experience
    130764: 08/04/01: Kolja Sulimma: Re: ISE 10.1 - Initial experience
    130778: 08/04/01: emeb: Re: ISE 10.1 - Initial experience
    130795: 08/04/01: Andy Peters: Re: ISE 10.1 - Initial experience
    130817: 08/04/02: Andy Peters: Re: ISE 10.1 - Initial experience
130655: 08/03/29: Joe: Announcement: Releasing LogicSim 3.3 and WaveProbe 1.1
130680: 08/03/30: louis: After reset, the PC register of PPC is not back to 0Xfffffffc
    130721: 08/03/31: morphiend: Re: After reset, the PC register of PPC is not back to 0Xfffffffc
    130740: 08/03/31: louis: Re: After reset, the PC register of PPC is not back to 0Xfffffffc
130682: 08/03/30: move: Synthesisable Timer in VHDL
    130687: 08/03/30: KJ: Re: Synthesisable Timer in VHDL
    130712: 08/03/30: Dave Pollum: Re: Synthesisable Timer in VHDL
130685: 08/03/30: anilcelebi: System Generator Error
130706: 08/03/30: kislo: fpga reset (re-initialize) of spartan3e
    130710: 08/03/30: Antti: Re: fpga reset (re-initialize) of spartan3e
    130728: 08/03/31: David Spencer: Re: fpga reset (re-initialize) of spartan3e
    130731: 08/03/31: Antti: Re: fpga reset (re-initialize) of spartan3e
130708: 08/03/30: <admbarnett@gmail.com>: Writing to DDR RAM on Virtex II Pro Board on PLB Bus
    130713: 08/03/31: Pablo: Re: Writing to DDR RAM on Virtex II Pro Board on PLB Bus
    130718: 08/03/31: Andy: Re: Writing to DDR RAM on Virtex II Pro Board on PLB Bus
130714: 08/03/31: Sean Durkin: Using USB programming cables from Xilinx and Lattice on one Windows
    130719: 08/03/31: <sky465nm@trline4.org>: Re: Using USB programming cables from Xilinx and Lattice on one Windows machine
        130734: 08/03/31: Sean Durkin: Re: Using USB programming cables from Xilinx and Lattice on one Windows
            130743: 08/03/31: <sky465nm@trline4.org>: Re: Using USB programming cables from Xilinx and Lattice on one Windows machine
                130750: 08/03/31: Sean Durkin: Re: Using USB programming cables from Xilinx and Lattice on one Windows
                    130753: 08/04/01: <sky465nm@trline4.org>: Re: Using USB programming cables from Xilinx and Lattice on one Windows machine
        130754: 08/03/31: Brian Davis: Re: Using USB programming cables from Xilinx and Lattice on one
130717: 08/03/31: kislo: increase memory of microblaze
    130720: 08/03/31: morphiend: Re: increase memory of microblaze
    130722: 08/03/31: kislo: Re: increase memory of microblaze
    130760: 08/04/01: <ales.gorkic@gmail.com>: Re: increase memory of microblaze
130725: 08/03/31: Roger: ISE 64 bit
130729: 08/03/31: Mary Fisher: Re: thread problem?
130732: 08/03/31: austin: Welcome to our world - Blog
130735: 08/03/31: Andrew Greensted: JTAG: First of 4 Spartan-3E always UNKNOWN
    130736: 08/03/31: Antti: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
        130737: 08/03/31: Andrew Greensted: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
            130765: 08/04/01: Andrew Greensted: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
                130773: 08/04/01: Andrew Greensted: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
                    130794: 08/04/01: Nico Coesel: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
                        130838: 08/04/03: Andrew Greensted: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
            130766: 08/04/01: <sky465nm@trline4.org>: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
                130819: 08/04/02: <sky465nm@trline4.org>: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
        130741: 08/03/31: Antti: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
        130767: 08/04/01: Antti: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
    130774: 08/04/01: colin: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
    130792: 08/04/01: <job@amontec.com>: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
130739: 08/03/31: Paul Boven: Impact won't program XC3S200, does program XC3SD1800A
    130742: 08/03/31: Antti: Re: Impact won't program XC3S200, does program XC3SD1800A
    130749: 08/03/31: rponsard@gmail.com: Re: Impact won't program XC3S200, does program XC3SD1800A
130746: 08/03/31: grant0920: Partial reconfiguration by using ICAP
130748: 08/03/31: Sunn: Xilinx and Modelsim?
    130752: 08/03/31: <ghelbig@lycos.com>: Re: Xilinx and Modelsim?
        130756: 08/03/31: Jeff Cunningham: Re: Xilinx and Modelsim?
            130768: 08/04/01: Brian Drummond: Re: Xilinx and Modelsim?
    130772: 08/04/01: Dave Pollum: Re: Xilinx and Modelsim?
    131261: 08/04/17: waing gyi: Re: Xilinx and Modelsim?
    131266: 08/04/17: Chumnarn P.: Re: Xilinx and Modelsim?


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