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Threads Starting Apr 2007

117465: 07/04/01: news reader: How much time margin should I give to a SDRAM interface via FPGA?
    117466: 07/04/01: Daniel S.: Re: How much time margin should I give to a SDRAM interface via FPGA?
        117487: 07/04/02: news reader: Re: How much time margin should I give to a SDRAM interface via FPGA?
            117492: 07/04/02: Symon: Re: How much time margin should I give to a SDRAM interface via FPGA?
117467: 07/04/01: Shela: Question about initializing the ram value in test bench
    117468: 07/04/01: Mike Treseler: Re: Question about initializing the ram value in test bench
    117470: 07/04/01: Symon: Re: Question about initializing the ram value in test bench
117469: 07/04/01: =?utf-8?B?R2FMYUt0SWtVc+KEog==?=: DCM_STANDBY macro in Virtex-4
    117471: 07/04/01: Austin: Re: DCM_STANDBY macro in Virtex-4
        117489: 07/04/02: Austin Lesea: Re: DCM_STANDBY macro in Virtex-4
    117485: 07/04/02: =?utf-8?B?R2FMYUt0SWtVc+KEog==?=: Re: DCM_STANDBY macro in Virtex-4
    117511: 07/04/02: =?utf-8?B?R2FMYUt0SWtVc+KEog==?=: Re: DCM_STANDBY macro in Virtex-4
117473: 07/04/01: <manuel-lozano@mixmail.com>: broken mb-gcc -O2 ?
    117474: 07/04/01: Alan Nishioka: Re: broken mb-gcc -O2 ?
    117482: 07/04/02: <manuel-lozano@mixmail.com>: Re: broken mb-gcc -O2 ?
117475: 07/04/01: mayichao: how to use and calculate prom checksum in prm file.
117478: 07/04/01: Svenand: EDK 9.1i installation
    117763: 07/04/09: Eric Smith: Re: EDK 9.1i installation
117481: 07/04/02: Benjamin Todd: Re: Dear Xilinx
117484: 07/04/02: Amontec, Larry: SVF Player
117490: 07/04/02: <michel.talon@gmail.com>: verilog genvar, and 2D array access
    117491: 07/04/02: <michel.talon@gmail.com>: Re: verilog genvar, and 2D array access
117493: 07/04/02: Tommy Thorn: Re: Spartan-3A XC3S1400A development board?
117494: 07/04/02: Thuy Pham: Standard PCI Xilinx board with Ethernet port
    117495: 07/04/02: John Adair: Re: Standard PCI Xilinx board with Ethernet port
117497: 07/04/02: motty: MGT Digital Receiver Oversampling
117500: 07/04/02: <prasad.anirudh@gmail.com>: Dynamic Reconfig
    117535: 07/04/03: Neil Steiner: Re: Dynamic Reconfig
    117969: 07/04/14: <prasad.anirudh@gmail.com>: Re: Dynamic Reconfig
117501: 07/04/02: radarman: Does the XC3S250E-VQ100 exist?
    117502: 07/04/02: Uwe Bonnes: Re: Does the XC3S250E-VQ100 exist?
    117506: 07/04/02: jetq88: Re: Does the XC3S250E-VQ100 exist?
    117507: 07/04/02: John_H: Re: Does the XC3S250E-VQ100 exist?
        117594: 07/04/04: Uwe Bonnes: Re: Does the XC3S250E-VQ100 exist?
    117519: 07/04/03: Paul: Re: Does the XC3S250E-VQ100 exist?
    117587: 07/04/04: radarman: Re: Does the XC3S250E-VQ100 exist?
117503: 07/04/02: M. Hamed: X_OBUF and other error messages with ModelSim
    117549: 07/04/03: M. Hamed: Re: X_OBUF and other error messages with ModelSim
117510: 07/04/03: Andreas Koch: ISE 9.1i SP3 simulator problems on Linux
    117523: 07/04/03: Andreas Koch: Re: ISE 9.1i SP3 simulator problems on Linux
        117896: 07/04/12: Andreas Koch: Re: ISE 9.1i SP3 simulator problems on Linux
117512: 07/04/02: Gordon Freeman: Implement IIR Filter on FPGA
    117513: 07/04/03: John_H: Re: Implement IIR Filter on FPGA
        117596: 07/04/04: Daniel S.: Re: Implement IIR Filter on FPGA
            117624: 07/04/05: Brian Drummond: Re: Implement IIR Filter on FPGA
            117637: 07/04/05: Nico Coesel: Re: Implement IIR Filter on FPGA
    117556: 07/04/03: Gordon Freeman: Re: Implement IIR Filter on FPGA
    117617: 07/04/04: Gordon Freeman: Re: Implement IIR Filter on FPGA
117516: 07/04/03: Dolphin: re-assemble bootloader for NIOS Processor
    117517: 07/04/03: GMM50: Re: re-assemble bootloader for NIOS Processor
    117574: 07/04/04: Dolphin: Re: re-assemble bootloader for NIOS Processor
117521: 07/04/03: Andre Renee: Implementing a communication protocol for data transfer over TCP on an FPGA
    117522: 07/04/03: jetq88: Re: Implementing a communication protocol for data transfer over TCP on an FPGA
    117525: 07/04/03: Nick Maclaren: Re: Implementing a communication protocol for data transfer over TCP on an FPGA
        117529: 07/04/03: Andre Renee: Re: Implementing a communication protocol for data transfer over TCP on an FPGA
    117526: 07/04/03: Ben Jones: Re: Implementing a communication protocol for data transfer over TCP on an FPGA
    117527: 07/04/03: Tauno Voipio: Re: Implementing a communication protocol for data transfer over
    117530: 07/04/03: zcsizmadia@gmail.com: Re: Implementing a communication protocol for data transfer over TCP on an FPGA
    117615: 07/04/04: <already5chosen@yahoo.com>: Re: Implementing a communication protocol for data transfer over TCP on an FPGA
117524: 07/04/03: trackmanatISU@gmail.com: QUIP write_verilog.c
117531: 07/04/03: Jim Lewis: RFC: VHDL testbench enhancements
    117537: 07/04/03: Andy: Re: RFC: VHDL testbench enhancements
        117538: 07/04/03: Jim Lewis: Re: RFC: VHDL testbench enhancements
    117545: 07/04/03: Amal: Re: RFC: VHDL testbench enhancements
    117557: 07/04/03: Eli Bendersky: Re: RFC: VHDL testbench enhancements
    117565: 07/04/04: Martin Thompson: Re: RFC: VHDL testbench enhancements
117534: 07/04/03: Pablo: Boot PowerPC on VirtexIIPro
    117564: 07/04/04: Brian Drummond: Re: Boot PowerPC on VirtexIIPro
117544: 07/04/03: Matthias Einwag: Looking for Memory Recommendation for Spartan 3E 1200
    117546: 07/04/03: John_H: Re: Looking for Memory Recommendation for Spartan 3E 1200
    117551: 07/04/03: John McCaskill: Re: Looking for Memory Recommendation for Spartan 3E 1200
        117608: 07/04/04: Matthias Einwag: Re: Looking for Memory Recommendation for Spartan 3E 1200
    117588: 07/04/04: Nico Coesel: Re: Looking for Memory Recommendation for Spartan 3E 1200
        117607: 07/04/04: Matthias Einwag: Re: Looking for Memory Recommendation for Spartan 3E 1200
            117636: 07/04/05: Nico Coesel: Re: Looking for Memory Recommendation for Spartan 3E 1200
    117665: 07/04/06: Paul: Re: Looking for Memory Recommendation for Spartan 3E 1200
117548: 07/04/03: Taylor Hutt: Xilinx: WARNING:PhysDesignRules:372 (What the heck?)
    117627: 07/04/05: Benjamin Todd: Re: Xilinx: WARNING:PhysDesignRules:372 (What the heck?)
117558: 07/04/04: =?utf-8?B?R2FMYUt0SWtVc+KEog==?=: MIG under Linux
117560: 07/04/04: jajo: Conceptos about VCCINT,VCCAUX,etc
    117563: 07/04/04: jerzy.gbur@gmail.com: Re: Conceptos about VCCINT,VCCAUX,etc
117561: 07/04/04: roger: Problem with PHY clocks on Spartan 3E Starter Kit
    117764: 07/04/09: Eric Smith: Re: Problem with PHY clocks on Spartan 3E Starter Kit
117562: 07/04/04: Pablo: Can I boot PowerPC without JTAG?
    117570: 07/04/04: John McCaskill: Re: Can I boot PowerPC without JTAG?
117566: 07/04/04: <ryan_usenet@yahoo.com>: high number of multipliers / low cost
    117568: 07/04/04: Rob: Re: high number of multipliers / low cost
    117569: 07/04/04: Ben Jones: Re: high number of multipliers / low cost
    117571: 07/04/04: Sylvain Munaut: Re: high number of multipliers / low cost
    117577: 07/04/04: <ryan_usenet@yahoo.com>: Re: high number of multipliers / low cost
        117579: 07/04/04: Symon: Re: high number of multipliers / low cost
            117586: 07/04/04: Ben Jones: Re: high number of multipliers / low cost
                117591: 07/04/04: Ben Jones: Re: high number of multipliers / low cost
                117606: 07/04/04: Ray Andraka: Re: high number of multipliers / low cost
            117598: 07/04/04: Daniel S.: Re: high number of multipliers / low cost
            117603: 07/04/04: Ray Andraka: Re: high number of multipliers / low cost
        117581: 07/04/04: Austin Lesea: Re: high number of multipliers / low cost
            117597: 07/04/04: Sylvain Munaut: Re: high number of multipliers / low cost
    117582: 07/04/04: <ryan_usenet@yahoo.com>: Re: high number of multipliers / low cost
    117584: 07/04/04: John_H: Re: high number of multipliers / low cost
    117589: 07/04/04: <ryan_usenet@yahoo.com>: Re: high number of multipliers / low cost
    117590: 07/04/04: <ryan_usenet@yahoo.com>: Re: high number of multipliers / low cost
    117605: 07/04/04: Ray Andraka: Re: high number of multipliers / low cost
    117613: 07/04/04: <ryan_usenet@yahoo.com>: Re: high number of multipliers / low cost
117573: 07/04/04: Paul: Re: FPGA with 5V and PLCC package
117578: 07/04/04: cpope: fifo occupancy bigger than fifo size?
    117614: 07/04/04: cpope: Re: fifo occupancy bigger than fifo size?
        117626: 07/04/05: cpope: Re: fifo occupancy bigger than fifo size?
            117630: 07/04/05: John_H: Re: fifo occupancy bigger than fifo size?
    117616: 07/04/04: Peter Alfke: Re: fifo occupancy bigger than fifo size?
117580: 07/04/04: wallge: TFP410 acceptable video input timings (trying to run 1280x1024 at 60Hz with clock slower than 108 MHz)
    117583: 07/04/04: Ben Jones: Re: TFP410 acceptable video input timings (trying to run 1280x1024 at 60Hz with clock slower than 108 MHz)
    117682: 07/04/06: wallge: Re: TFP410 acceptable video input timings (trying to run 1280x1024 at 60Hz with clock slower than 108 MHz)
117585: 07/04/04: morpheus: Digital Receiver chip suggestion
    117600: 07/04/04: Ray Andraka: Re: Digital Receiver chip suggestion
        117629: 07/04/05: Ray Andraka: Re: Digital Receiver chip suggestion
    117620: 07/04/04: morpheus: Re: Digital Receiver chip suggestion
    117651: 07/04/06: Marty Ryba: Re: Digital Receiver chip suggestion
    117726: 07/04/08: morpheus: Re: Digital Receiver chip suggestion
117592: 07/04/04: Hrishi: Interfacing the DAC0808 to FPGA
    117602: 07/04/04: Nico Coesel: Re: Interfacing the DAC0808 to FPGA
117593: 07/04/04: Amal: Re: TI Tap Controller std8980
117599: 07/04/04: anand: Gray code in asynchronous FIFO design
    117604: 07/04/04: Gabor: Re: Gray code in asynchronous FIFO design
        117610: 07/04/04: John_H: Re: Gray code in asynchronous FIFO design
            117611: 07/04/04: John_H: Re: Gray code in asynchronous FIFO design
                117623: 07/04/05: Sylvain Munaut: Re: Gray code in asynchronous FIFO design
                    117638: 07/04/05: John_H: Re: Gray code in asynchronous FIFO design
            117635: 07/04/05: Symon: OT Re: Gray code in asynchronous FIFO design
                117639: 07/04/05: John_H: OT Re: Gray code in asynchronous FIFO design
                    117641: 07/04/05: Pete Fraser: Re: OT Re: Gray code in asynchronous FIFO design
                        117643: 07/04/05: John_H: Re: OT Re: Gray code in asynchronous FIFO design
                    117642: 07/04/05: Symon: Re: OT Re: Gray code in asynchronous FIFO design
                    117645: 07/04/05: Sylvain Munaut: Re: OT Re: Gray code in asynchronous FIFO design
                117646: 07/04/05: Nicolas Matringe: Re: OT Re: Gray code in asynchronous FIFO design
                    117661: 07/04/06: Symon: Re: OT Re: Gray code in asynchronous FIFO design.
    117609: 07/04/04: anand: Re: Gray code in asynchronous FIFO design
    117612: 07/04/04: anand: Re: Gray code in asynchronous FIFO design
    117621: 07/04/04: morpheus: Re: Gray code in asynchronous FIFO design
    117634: 07/04/05: morpheus: Re: Gray code in asynchronous FIFO design
    117664: 07/04/06: KJ: Re: OT Re: Gray code in asynchronous FIFO design.
117618: 07/04/04: CMOS: having a state machine in a datapath element a bad design practice?
    117619: 07/04/05: Jim Granville: Re: having a state machine in a datapath element a bad design practice?
    117640: 07/04/05: Mike Lewis: Re: having a state machine in a datapath element a bad design practice?
117625: 07/04/05: <tlenomade@googlemail.com>: suitability of systolic architecture on FPGA
    117628: 07/04/05: Gabor: Re: suitability of systolic architecture on FPGA
    117644: 07/04/05: Neil Steiner: Re: suitability of systolic architecture on FPGA
        117648: 07/04/05: Neil Steiner: Re: suitability of systolic architecture on FPGA
    117647: 07/04/05: Peter Alfke: Re: suitability of systolic architecture on FPGA
117632: 07/04/05: jetq88: what is the best practice to exchange data between microblaze softcore and customer hardware writen in VHDL
    117653: 07/04/05: Alan Nishioka: Re: what is the best practice to exchange data between microblaze softcore and customer hardware writen in VHDL
117649: 07/04/05: Kunal: PCI FPGA Dev Board Suggestions
    117650: 07/04/05: Kunal: Re: PCI FPGA Dev Board Suggestions
        117679: 07/04/06: Nico Coesel: Re: PCI FPGA Dev Board Suggestions
            117694: 07/04/07: Nico Coesel: Re: PCI FPGA Dev Board Suggestions
    117658: 07/04/06: John Adair: Re: PCI FPGA Dev Board Suggestions
    117659: 07/04/06: evilkidder@googlemail.com: Re: PCI FPGA Dev Board Suggestions
    117676: 07/04/06: Kunal: Re: PCI FPGA Dev Board Suggestions
    117692: 07/04/06: John Adair: Re: PCI FPGA Dev Board Suggestions
    117742: 07/04/09: Vivek Menon: Re: PCI FPGA Dev Board Suggestions
117652: 07/04/05: From_ASIC_2_FPGA: Transition from ASIC to FPGA
    117666: 07/04/06: Austin Lesea: Re: Transition from ASIC to FPGA
        117668: 07/04/06: Jan Gray: Re: Transition from ASIC to FPGA
        117673: 07/04/06: Ben Twijnstra: Re: Transition from ASIC to FPGA
            117684: 07/04/07: Ben Twijnstra: Re: Transition from ASIC to FPGA
                117689: 07/04/07: Jan Gray: Re: Transition from ASIC to FPGA
                    117698: 07/04/07: Nico Coesel: Re: Transition from ASIC to FPGA
            117693: 07/04/07: HT-Lab: Re: Transition from ASIC to FPGA
    117667: 07/04/06: From_ASIC_2_FPGA: Re: Transition from ASIC to FPGA
    117669: 07/04/06: <curiousjyo111@gmail.com>: Re: Transition from ASIC to FPGA
    117670: 07/04/06: <curiousjyo111@gmail.com>: Re: Transition from ASIC to FPGA
        117680: 07/04/06: Austin Lesea: Re: Transition from ASIC to FPGA
            117683: 07/04/06: John_H: Re: Transition from ASIC to FPGA
    117677: 07/04/06: John McCaskill: Re: Transition from ASIC to FPGA
    117678: 07/04/06: From_ASIC_2_FPGA: Re: Transition from ASIC to FPGA
    117681: 07/04/06: From_ASIC_2_FPGA: Re: Transition from ASIC to FPGA
    117686: 07/04/06: From_ASIC_2_FPGA: Re: Transition from ASIC to FPGA
    117687: 07/04/06: From_ASIC_2_FPGA: Re: Transition from ASIC to FPGA
    117690: 07/04/06: From_ASIC_2_FPGA: Re: Transition from ASIC to FPGA
    117691: 07/04/06: Tommy Thorn: Re: Transition from ASIC to FPGA
117654: 07/04/05: Dima: Memory Interface Recommendation for ML410 Design
117655: 07/04/05: <ashasravanthi@gmail.com>: virtex 4vfx12 evaluation kit schematics
    117662: 07/04/06: cpope: Re: virtex 4vfx12 evaluation kit schematics
117656: 07/04/06: Dolphin: Nios2: elf2hex settings for epcs bootloader
117657: 07/04/06: Dolphin: Nios2: elf2hex settings for epcs bootloader
117663: 07/04/06: Eli Hughes: Icarus Verilog
117671: 07/04/06: woutervh: XUP virtex-II pro
117672: 07/04/06: Krishna: How to use the 8LEDs on DIO4 when connected to Virtex 2 Pro kit?
    117674: 07/04/06: Mike Treseler: Re: How to use the 8LEDs on DIO4 when connected to Virtex 2 Pro kit?
117695: 07/04/07: wicky: can anyone give me a reference price of the following Xilinx boards?
    117701: 07/04/07: Pete Fraser: Re: can anyone give me a reference price of the following Xilinx boards?
    117703: 07/04/07: MH: Re: can anyone give me a reference price of the following Xilinx boards?
    117724: 07/04/08: wicky: Re: can anyone give me a reference price of the following Xilinx boards?
    117725: 07/04/08: wicky: Re: can anyone give me a reference price of the following Xilinx boards?
117696: 07/04/07: <Jedi>: ispLever FTP Download
117697: 07/04/07: Richard Pennington: A new way to define systems of systems?
    117699: 07/04/07: larwe: Re: A new way to define systems of systems?
        117700: 07/04/07: Richard Pennington: Re: A new way to define systems of systems?
    117702: 07/04/07: larwe: Re: A new way to define systems of systems?
    117711: 07/04/08: Paul E. Bennett: Re: A new way to define systems of systems?
        117713: 07/04/08: Richard Pennington: Re: A new way to define systems of systems?
            117715: 07/04/08: Paul E. Bennett: Re: A new way to define systems of systems?
            117716: 07/04/08: Richard Pennington: Re: A new way to define systems of systems?
                117717: 07/04/08: Nico Coesel: Re: A new way to define systems of systems?
                    117718: 07/04/08: Richard Pennington: Re: A new way to define systems of systems?
                117787: 07/04/10: Richard Pennington: Re: A new way to define systems of systems?
                    117874: 07/04/12: Richard Pennington: Re: A new way to define systems of systems?
                117832: 07/04/11: Colin Paul Gloster: Re: A new way to define systems of systems?
    117714: 07/04/08: fpgabuilder: Re: A new way to define systems of systems?
    117781: 07/04/10: fpgabuilder: Re: A new way to define systems of systems?
    117867: 07/04/11: fpgabuilder: Re: A new way to define systems of systems?
    117868: 07/04/11: fpgabuilder: Re: A new way to define systems of systems?
117704: 07/04/07: Adam Megacz: raggedstone + xc3sprog?
    117707: 07/04/07: John Adair: Re: raggedstone + xc3sprog?
    117721: 07/04/08: Adam Megacz: Re: raggedstone + xc3sprog? (solution and PHY question)
    117729: 07/04/09: John Adair: Re: raggedstone + xc3sprog? (solution and PHY question)
    117755: 07/04/09: Adam Megacz: Re: raggedstone + xc3sprog? (solution and PHY question)
    117767: 07/04/10: John Adair: Re: raggedstone + xc3sprog? (solution and PHY question)
117705: 07/04/07: Telenochek: Xilinx ISE constanly asking to regenerate a core file.
    117708: 07/04/07: Telenochek: Re: Xilinx ISE constanly asking to regenerate a core file.
        117709: 07/04/08: Sean Durkin: Re: Xilinx ISE constanly asking to regenerate a core file.
            117731: 07/04/09: John_H: Re: Xilinx ISE constanly asking to regenerate a core file.
    117730: 07/04/09: Paul: Re: Xilinx ISE constanly asking to regenerate a core file.
117710: 07/04/08: ram: query
117719: 07/04/08: Pedro: How do I use the Xilinx USB download cable for testing?
    117720: 07/04/08: Sylvain Munaut: Re: How do I use the Xilinx USB download cable for testing?
    117722: 07/04/08: Mike Treseler: Re: How do I use the Xilinx USB download cable for testing?
        117723: 07/04/08: Pedro: Re: How do I use the Xilinx USB download cable for testing?
            117895: 07/04/12: IEEE member: Re: How do I use the Xilinx USB download cable for testing?
                117906: 07/04/13: Petter Gustad: Re: How do I use the Xilinx USB download cable for testing?
    117743: 07/04/09: <user@domain.invalid>: Re: How do I use the Xilinx USB download cable for testing?
117728: 07/04/09: <rponsard@gmail.com>: Re: Dear Xilinx
117732: 07/04/09: Philip Pemberton: Clocking data into a shift register on positive AND negative edges
    117734: 07/04/09: John_H: Re: Clocking data into a shift register on positive AND negative edges
        117746: 07/04/09: Philip Pemberton: Re: Clocking data into a shift register on positive AND negative
            117748: 07/04/09: John_H: Re: Clocking data into a shift register on positive AND negative edges
    117737: 07/04/09: Ralf Hildebrandt: Re: Clocking data into a shift register on positive AND negative
    117739: 07/04/09: Daniel S.: Re: Clocking data into a shift register on positive AND negative
    117765: 07/04/09: Eric Smith: Re: Clocking data into a shift register on positive AND negative edges
117733: 07/04/09: axr0284: Measuring the period of a signal
    117735: 07/04/09: John_H: Re: Measuring the period of a signal
    117780: 07/04/10: Daniel S.: Re: Measuring the period of a signal
    117792: 07/04/10: axr0284: Re: Measuring the period of a signal
    117859: 07/04/11: -jg: Re: Measuring the period of a signal
117736: 07/04/09: <Jedi>: ByteBlaster Parallel Driver for Linux > 2.6.13
117738: 07/04/09: Thuy Pham: Looking for Xilinx fpga board that works in Linux and has Ethernet card
    117749: 07/04/09: John_H: Re: Looking for Xilinx fpga board that works in Linux and has Ethernet card
117740: 07/04/09: Matthew Hicks: MGT Clocking
    117752: 07/04/09: Ed McGettigan: Re: MGT Clocking
117741: 07/04/09: <cs_posting@hotmail.com>: Word sync in Cypress FX2 fifos /w 8 bit bus
    117745: 07/04/09: johnp: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
        117750: 07/04/09: CBFalconer: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
            117756: 07/04/09: John_H: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
            117760: 07/04/09: Donald: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
    117747: 07/04/09: <cs_posting@hotmail.com>: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
        117775: 07/04/10: c d saunter: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
    117751: 07/04/09: johnp: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
    117757: 07/04/09: <cs_posting@hotmail.com>: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
    117759: 07/04/09: Peter Alfke: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
117744: 07/04/09: M. Hamed: Modelsim Low and High violations
117753: 07/04/09: mans (use_my_name_here): record type port in vhdl and simulation in ISE
    117754: 07/04/09: Mike Treseler: Re: record type port in vhdl and simulation in ISE
    117783: 07/04/10: Duth: Re: record type port in vhdl and simulation in ISE
117761: 07/04/09: Andy: File open, read and write in Xilinx EDK 7.1
117766: 07/04/10: CMOS: is there any opensource alternatives to platformstudio and microblaze development?
    117774: 07/04/10: Gabor: Re: is there any opensource alternatives to platformstudio and microblaze development?
    117776: 07/04/10: CMOS: Re: is there any opensource alternatives to platformstudio and microblaze development?
    117777: 07/04/10: Patrick Dubois: Re: is there any opensource alternatives to platformstudio and microblaze development?
    117793: 07/04/10: John McCaskill: Re: is there any opensource alternatives to platformstudio and microblaze development?
117768: 07/04/10: mynewlifever@yahoo.com.cn: Why I cannot use the XAUI core(generated by xilinx)
    117784: 07/04/10: Ed McGettigan: Re: Why I cannot use the XAUI core(generated by xilinx)
    117785: 07/04/10: Duth: Re: Why I cannot use the XAUI core(generated by xilinx)
117769: 07/04/10: Colin Paul Gloster: C/C++ for hardware (from "Re: Embedded languages based on early Ada (from "Re: Preferred OS, processor family for running embedded Ada?")")
117770: 07/04/10: =?utf-8?B?R2FMYUt0SWtVc+KEog==?=: VIrtex-4 FIFO16
    117782: 07/04/10: Daniel S.: Re: VIrtex-4 FIFO16
    117851: 07/04/11: Paul: Re: VIrtex-4 FIFO16
117771: 07/04/10: PeterK: Newbie with bus width mismatch problem. Quartus II
    117778: 07/04/10: Subroto Datta: Re: Newbie with bus width mismatch problem. Quartus II
    117812: 07/04/11: Mark McDougall: Re: Newbie with bus width mismatch problem. Quartus II
        117826: 07/04/11: PeterK: Re: Newbie with bus width mismatch problem. Quartus II
117772: 07/04/10: Pablo: SetJmp/LongJmp for Microblaze
    117773: 07/04/10: Jon Beniston: Re: SetJmp/LongJmp for Microblaze
    117808: 07/04/11: John Williams: Re: SetJmp/LongJmp for Microblaze
117779: 07/04/10: Amal Khailtash: JTAG Tap Master (was: TI Tap Controller std8980)
117786: 07/04/10: <fancier.fpga@googlemail.com>: Ross Freeman - inventor of the FPGA
    117791: 07/04/10: Thomas Entner: Re: Ross Freeman - inventor of the FPGA
        117795: 07/04/10: Austin Lesea: Re: Ross Freeman - inventor of the FPGA
    117794: 07/04/10: <fancier.fpga@googlemail.com>: Re: Ross Freeman - inventor of the FPGA
    117798: 07/04/10: Peter Alfke: Re: Ross Freeman - inventor of the FPGA
    117806: 07/04/10: Bob Perlman: Re: Ross Freeman - inventor of the FPGA
117788: 07/04/10: eejw: System Generator pcore I/O performance results
    117789: 07/04/10: eejw: Re: System Generator pcore I/O performance results
        117870: 07/04/12: Göran Bilski: Re: System Generator pcore I/O performance results
    117814: 07/04/10: Newman: Re: System Generator pcore I/O performance results
    117815: 07/04/10: Newman: Re: System Generator pcore I/O performance results
    117840: 07/04/11: eejw: Re: System Generator pcore I/O performance results
    117842: 07/04/11: eejw: Re: System Generator pcore I/O performance results
    117902: 07/04/12: Newman: Re: System Generator pcore I/O performance results
117790: 07/04/10: John Gulbrandsen: Available: Detailed RISC CPU IP Core Design Documentation
117796: 07/04/10: Scott Willis: EDK 8.2 MicroBlaze Tutorial
117797: 07/04/10: <Amine.Miled@gmail.com>: Flip Flop problem (asynchronous or synchronous???? )
    117822: 07/04/11: Thomas Stanka: Re: Flip Flop problem (asynchronous or synchronous???? )
    117856: 07/04/11: <Amine.Miled@gmail.com>: Re: Flip Flop problem (asynchronous or synchronous???? )
117799: 07/04/10: H. Peter Anvin: CPLD + =?UTF-8?B?wrVDIHdpdGggcmVhc29uYWJseS1wcmljZWQgdG9vbHM/?=
    117802: 07/04/10: John McCaskill: =?iso-8859-1?q?Re:_CPLD_+_=B5C_with_reasonably-priced_tools=3F?=
    117805: 07/04/10: zcsizmadia@gmail.com: =?iso-8859-1?q?Re:_CPLD_+_=B5C_with_reasonably-priced_tools=3F?=
        117809: 07/04/10: H. Peter Anvin: Re: CPLD + =?ISO-8859-1?Q?=B5C_with_reasonably-priced_tool?=
            117817: 07/04/10: H. Peter Anvin: Re: CPLD + =?ISO-8859-1?Q?=B5C_with_reasonably-priced_tool?=
    117811: 07/04/10: zcsizmadia@gmail.com: =?iso-8859-1?q?Re:_CPLD_+_=B5C_with_reasonably-priced_tools=3F?=
    117841: 07/04/11: zcsizmadia@gmail.com: =?iso-8859-1?q?Re:_CPLD_+_=B5C_with_reasonably-priced_tools=3F?=
    117858: 07/04/11: -jg: =?iso-8859-1?q?Re:_CPLD_+_=B5C_with_reasonably-priced_tools=3F?=
        117889: 07/04/12: H. Peter Anvin: Re: CPLD + =?ISO-8859-1?Q?=B5C_with_reasonably-priced_tool?=
            117893: 07/04/12: Uwe Bonnes: Re: CPLD + µC with reasonably-priced tools?
    117860: 07/04/12: Symon: Re: CPLD + µC with reasonably-priced tools?
    117876: 07/04/12: Gabor: =?iso-8859-1?q?Re:_CPLD_+_=B5C_with_reasonably-priced_tools=3F?=
    118284: 07/04/21: <mikeotp999@yahoo.com.tw>: =?big5?q?Re:_CPLD_+_=A3gC_with_reasonably-priced_tools=3F?=
117800: 07/04/10: Peter Alfke: Re: Flip Flop problem (asynchronous or synchronous???? )
117801: 07/04/10: Alan Nishioka: Re: Flip Flop problem (asynchronous or synchronous???? )
    117804: 07/04/10: Austin Lesea: Re: Flip Flop problem (asynchronous or synchronous???? )
117803: 07/04/10: <Amine.Miled@gmail.com>: Re: Flip Flop problem (asynchronous or synchronous???? )
117807: 07/04/10: <Amine.Miled@gmail.com>: Re: Flip Flop problem (asynchronous or synchronous???? )
117810: 07/04/10: <Amine.Miled@gmail.com>: Re: Flip Flop problem (asynchronous or synchronous???? )
117813: 07/04/10: motty: Xilinx WebCase support
    117829: 07/04/11: Antti: Re: Xilinx WebCase support
    117831: 07/04/11: Helmut: Re: Xilinx WebCase support
    117834: 07/04/11: Gabor: Re: Xilinx WebCase support
    117838: 07/04/11: Austin Lesea: Re: Xilinx WebCase support
        117844: 07/04/11: Austin Lesea: Re: Xilinx WebCase support
            117852: 07/04/11: Austin Lesea: Re: Xilinx WebCase support
    117848: 07/04/11: motty: Re: Xilinx WebCase support
117816: 07/04/10: Dima: Please HELP: timing problems on Virtex-4FX
    117827: 07/04/11: Ben Jones: Re: Please HELP: timing problems on Virtex-4FX
        117872: 07/04/12: Ben Jones: Re: Please HELP: timing problems on Virtex-4FX
            117909: 07/04/13: Ben Jones: Re: Please HELP: timing problems on Virtex-4FX
    117847: 07/04/11: Dima: Re: Please HELP: timing problems on Virtex-4FX
    117905: 07/04/12: Dima: Re: Please HELP: timing problems on Virtex-4FX
117818: 07/04/11: Petter Gustad: Re: Query in Parallel CRC(urgent)
117819: 07/04/10: osr: Query in Parallel CRC(urgent)
    117843: 07/04/11: Colin Hankins: Re: Query in Parallel CRC(urgent)
117820: 07/04/10: nezhate: FIFO newbie question
    117833: 07/04/11: Dave Pollum: Re: FIFO newbie question
    117835: 07/04/11: nezhate: Re: FIFO newbie question
    117836: 07/04/11: comp.arch.fpga: Re: FIFO newbie question
    117837: 07/04/11: Gabor: Re: FIFO newbie question
117821: 07/04/11: kangwei365@gmail.com: Help!! FIR Polyphase second - order interpolator
    120069: 07/06/01: tsan: Re: Help!! FIR Polyphase second - order interpolator
117828: 07/04/11: Antti: ERROR: ::xilinx::Dpm::TOE::execInterrupt doesn't know what to do.
117830: 07/04/11: woutervh: Wanted: XUP Virtex II Pro DDR-controller
117845: 07/04/11: wallge: has anyone used mathstar field programmable object arrays?
    117855: 07/04/11: Gabor: Re: has anyone used mathstar field programmable object arrays?
        117935: 07/04/13: Ray Andraka: Re: has anyone used mathstar field programmable object arrays?
    117890: 07/04/12: wallge: Re: has anyone used mathstar field programmable object arrays?
117846: 07/04/11: Anne: POC at Element CXI
    117849: 07/04/11: Symon: OT. Re: POC at Element CXI
        117863: 07/04/11: Mike Treseler: Re: OT. Re: POC at Element CXI
    117853: 07/04/11: Gabor: Re: OT. Re: POC at Element CXI
117850: 07/04/11: Kunal: lwIP, temac, and DMA
117854: 07/04/11: <Jedi>: ispLever 6.1 complains about missing libc.so.6 on Gentoo 2006.1
    117857: 07/04/12: <Jedi>: Re: ispLever 6.1 complains about missing libc.so.6 on Gentoo 2006.1
117861: 07/04/11: M. Hamed: Timing violations though constraints have been met
    117864: 07/04/11: Mike Treseler: Re: Timing violations though constraints have been met
    117869: 07/04/12: Andreas Ehliar: Re: Timing violations though constraints have been met
    117887: 07/04/12: M. Hamed: Re: Timing violations though constraints have been met
117862: 07/04/11: johnp: XST and Verilog $readmemh
    117886: 07/04/12: johnp: Re: XST and Verilog $readmemh
117865: 07/04/11: Weng Tianxiang: Which are the best books about CORDIC algorithms and applications
    117877: 07/04/12: Subroto Datta: Re: Which are the best books about CORDIC algorithms and applications
        117880: 07/04/12: Ben Jones: Re: Which are the best books about CORDIC algorithms and applications
            117899: 07/04/12: Symon: Re: Which are the best books about CORDIC algorithms and applications
            117900: 07/04/12: Jonathan Bromley: Re: Which are the best books about CORDIC algorithms and applications
                117933: 07/04/13: Ray Andraka: Re: Which are the best books about CORDIC algorithms and applications
                    117942: 07/04/13: Jonathan Bromley: Re: Which are the best books about CORDIC algorithms and applications
            117931: 07/04/13: Ray Andraka: Re: Which are the best books about CORDIC algorithms and applications
    117878: 07/04/12: Weng Tianxiang: Re: Which are the best books about CORDIC algorithms and applications
    117894: 07/04/12: Weng Tianxiang: Re: Which are the best books about CORDIC algorithms and applications
    117929: 07/04/13: Walter Dvorak: Re: Which are the best books about CORDIC algorithms and applications
        117932: 07/04/13: Ray Andraka: Re: Which are the best books about CORDIC algorithms and applications
        117936: 07/04/13: Eric Smith: Re: Which are the best books about CORDIC algorithms and applications
    117938: 07/04/13: Weng Tianxiang: Re: Which are the best books about CORDIC algorithms and applications
    117939: 07/04/13: Weng Tianxiang: Re: Which are the best books about CORDIC algorithms and applications
117866: 07/04/11: <kanthi.siddela@gmail.com>: how two sine signals are multiplied in VHDL language
    117873: 07/04/12: Alan Myler (at home): Re: how two sine signals are multiplied in VHDL language
    117879: 07/04/12: Alan Nishioka: Re: how two sine signals are multiplied in VHDL language
117875: 07/04/12: <eascheiber@yahoo.com>: EDK + XMD
    117883: 07/04/12: Alan Nishioka: Re: EDK + XMD
117881: 07/04/12: <yuchiwai@gmail.com>: Changing LUT input size in synthesize
    117884: 07/04/12: Symon: Re: Changing LUT input size in synthesize
117882: 07/04/12: Scott Willis: Problem with EDK 8.2 MicroBlaze Tutorial
117888: 07/04/12: ferorcue: XPS behavioral simulation fails: the design is not loaded
    118105: 07/04/17: Newman: Re: XPS behavioral simulation fails: the design is not loaded
        118351: 07/04/24: Mike Treseler: Re: XPS behavioral simulation fails: the design is not loaded
    118344: 07/04/24: ferorcue: Re: XPS behavioral simulation fails: the design is not loaded
    120242: 07/06/04: ferorcue: Re: XPS behavioral simulation fails: the design is not loaded
117891: 07/04/12: M. Hamed: SETUP & HOLD time confusion
    117903: 07/04/12: Newman: Re: SETUP & HOLD time confusion
        117916: 07/04/13: Symon: Re: SETUP & HOLD time confusion
            117918: 07/04/13: Symon: Re: SETUP & HOLD time confusion
                117926: 07/04/13: Symon: Re: SETUP & HOLD time confusion
    117904: 07/04/12: Peter Alfke: Re: SETUP & HOLD time confusion
    117911: 07/04/13: Newman: Re: SETUP & HOLD time confusion
    117924: 07/04/13: Newman: Re: SETUP & HOLD time confusion
    117944: 07/04/13: M. Hamed: Re: SETUP & HOLD time confusion
    117946: 07/04/13: Brian Davis: Re: SETUP & HOLD time confusion
    118113: 07/04/17: Peter Alfke: Re: SETUP & HOLD time confusion
    118116: 07/04/17: Newman: Re: SETUP & HOLD time confusion
117892: 07/04/12: emu: spartan 3e availability
    117897: 07/04/12: Austin Lesea: Re: spartan 3e availability
        117921: 07/04/13: Austin Lesea: Re: spartan 3e availability
            117937: 07/04/13: Eric Smith: Distributor stock (was Re: spartan 3e availability)
                117943: 07/04/13: Austin Lesea: Re: Distributor stock (was Re: spartan 3e availability)
    117901: 07/04/12: emu: Re: spartan 3e availability
117898: 07/04/12: <elshoukry@gmail.com>: Back annotating to RTL
    118170: 07/04/18: fabbl: Re: Back annotating to RTL
    118185: 07/04/19: Andy: Re: Back annotating to RTL
117907: 07/04/13: Maik Ritter: Are there Quartus II Web Edition limitations?
    117910: 07/04/13: PeterK: Re: Are there Quartus II Web Edition limitations?
        117915: 07/04/13: David Brown: Re: Are there Quartus II Web Edition limitations?
            118003: 07/04/16: David Brown: Re: Are there Quartus II Web Edition limitations?
    117913: 07/04/13: Maik Ritter: Re: Are there Quartus II Web Edition limitations?
    117977: 07/04/15: Maik Ritter: Re: Are there Quartus II Web Edition limitations?
117912: 07/04/13: Pablo: No login in uClinux (Petalinux)
    117947: 07/04/13: <fpga_toys@yahoo.com>: Re: No login in uClinux (Petalinux)
117914: 07/04/13: LilacSkin: PLB Master to communicate with the BRAM
117917: 07/04/13: news reader: How do I constrain Xilinx to implement multi-cycle paths?
    117920: 07/04/13: Symon: Re: How do I constrain Xilinx to implement multi-cycle paths?
117919: 07/04/13: BERT: JTAG ID code 0xFFFFFFFF
    117922: 07/04/13: Benjamin Todd: Re: JTAG ID code 0xFFFFFFFF
        118022: 07/04/16: Benjamin Todd: Re: JTAG ID code 0xFFFFFFFF
    117923: 07/04/13: BERT: Re: JTAG ID code 0xFFFFFFFF
117925: 07/04/13: Thomas Heller: Simulating LogicCores with Webpack
117928: 07/04/13: dalai lamah: Order of the synchronous operations
    117930: 07/04/13: Daniel S.: Re: Order of the synchronous operations
        117952: 07/04/14: dalai lamah: Re: Order of the synchronous operations
            117953: 07/04/14: Daniel S.: Re: Order of the synchronous operations
                117957: 07/04/14: Mike Treseler: Re: Order of the synchronous operations
        117956: 07/04/14: Mike Treseler: Re: Order of the synchronous operations
            117960: 07/04/14: dalai lamah: Re: Order of the synchronous operations
                117964: 07/04/14: Jonathan Bromley: Re: Order of the synchronous operations
                    117965: 07/04/14: Mike Treseler: Re: Order of the synchronous operations
                    117981: 07/04/15: dalai lamah: Re: Order of the synchronous operations
                        117984: 07/04/15: Mike Treseler: Re: Order of the synchronous operations
            117961: 07/04/14: Daniel S.: Re: Order of the synchronous operations
                117963: 07/04/14: Jonathan Bromley: Re: Order of the synchronous operations
                    117970: 07/04/14: Daniel S.: Re: Order of the synchronous operations
                        117976: 07/04/15: Jonathan Bromley: Re: Order of the synchronous operations
                            117978: 07/04/15: Daniel S.: Re: Order of the synchronous operations
                                117979: 07/04/15: Jonathan Bromley: Re: Order of the synchronous operations
                                117982: 07/04/15: Mike Treseler: Re: Order of the synchronous operations
                117966: 07/04/14: Tim: Re: Order of the synchronous operations
    117941: 07/04/13: Jonathan Bromley: Re: Order of the synchronous operations
    118019: 07/04/16: Andy: Re: Order of the synchronous operations
117934: 07/04/13: M Ihsan Baig: SoC
    117940: 07/04/13: Jonathan Bromley: Re: SoC
117945: 07/04/13: Eric Smith: picoblaze C compiler download wanted
    117951: 07/04/14: -jg: Re: picoblaze C compiler download wanted
    117955: 07/04/14: Nico Coesel: Re: picoblaze C compiler download wanted
        117967: 07/04/14: Eric Smith: Re: picoblaze C compiler download wanted
    117958: 07/04/14: Symon: Re: picoblaze C compiler download wanted
        117968: 07/04/14: Eric Smith: Re: picoblaze C compiler download wanted
    117959: 07/04/14: <fpga_toys@yahoo.com>: Re: picoblaze C compiler download wanted
    118010: 07/04/16: Paul: Re: picoblaze C compiler download wanted
    118043: 07/04/16: <fpga_toys@yahoo.com>: Re: picoblaze C compiler download wanted
    118428: 07/04/26: Francesco: Re: picoblaze C compiler download wanted
        118452: 07/04/26: <dr@kbrx.com>: Re: picoblaze C compiler download wanted
        118505: 07/04/28: Eric Smith: Re: picoblaze C compiler download wanted
    118451: 07/04/26: <rponsard@gmail.com>: Re: picoblaze C compiler download wanted
    118821: 07/05/04: Francesco: Re: picoblaze C compiler download wanted
    118888: 07/05/06: <fpga_toys@yahoo.com>: Re: picoblaze C compiler download wanted
117962: 07/04/14: Pedro: ML506 Platform Flash
    117974: 07/04/14: sovan: Re: ML506 Platform Flash
117971: 07/04/14: Steve Battazzo: How many RAM words can I implement in my Xilinx FPGA?
    117972: 07/04/14: Steve Battazzo: Re: How many RAM words can I implement in my Xilinx FPGA? --NEVERMIND--
    117973: 07/04/15: Daniel S.: Re: How many RAM words can I implement in my Xilinx FPGA?
        117975: 07/04/14: Steve Battazzo: Re: How many RAM words can I implement in my Xilinx FPGA?
117980: 07/04/15: Uwe Bonnes: Pin Count requirements with MICO32
    117990: 07/04/16: David M. Palmer: Re: Pin Count requirements with MICO32
        117993: 07/04/16: Uwe Bonnes: Re: Pin Count requirements with MICO32
117983: 07/04/15: mmihai: [xilinx] par [placer] consistency
    118028: 07/04/16: Eric Brombaugh: Re: [xilinx] par [placer] consistency
        118080: 07/04/17: Brian Drummond: Re: par [placer] consistency
    118036: 07/04/16: John McGrath: Re: par [placer] consistency
    118040: 07/04/16: mmihai: Re: par [placer] consistency
    118045: 07/04/16: mmihai: Re: par [placer] consistency
    118084: 07/04/17: Gabor: Re: par [placer] consistency
117985: 07/04/15: <rohit2000s@yahoo.com>: Why 166Mhz DDR?
    117992: 07/04/16: comp.arch.fpga: Re: Why 166Mhz DDR?
        118021: 07/04/16: Benjamin Todd: Re: Why 166Mhz DDR?
    118008: 07/04/16: Symon: Re: Why 166Mhz DDR?
    118018: 07/04/16: <ghelbig@lycos.com>: Re: Why 166Mhz DDR?
        118034: 07/04/16: Daniel S.: Re: Why 166Mhz DDR?
            118108: 07/04/17: Daniel S.: Re: Why 166Mhz DDR?
    118033: 07/04/16: Daniel S.: Re: Why 166Mhz DDR?
    118037: 07/04/16: <katjasulimma@googlemail.com>: Re: Why 166Mhz DDR?
    118089: 07/04/17: <rohit2000s@yahoo.com>: Re: Why 166Mhz DDR?
117986: 07/04/15: Bhanu Chandra: Writing to BRAM using OPB
    117989: 07/04/15: sovan: Re: Writing to BRAM using OPB
    118029: 07/04/16: wsacul@gmail.com: Re: Writing to BRAM using OPB
117987: 07/04/15: <cpandya@yahoo.com>: FPGA High speed Transceivers for source synchronus bus application
    118051: 07/04/16: Jeff Cunningham: Re: FPGA High speed Transceivers for source synchronus bus application
        118081: 07/04/17: Test01: Re: FPGA High speed Transceivers for source synchronus bus
117988: 07/04/15: B. Joshua Rosen: Running Xilinx 9.1 GUIs on FC6
    118009: 07/04/16: <g.eckersley@ieee.org>: Re: Running Xilinx 9.1 GUIs on FC6
    118012: 07/04/16: Uwe Bonnes: Re: Running Xilinx 9.1 GUIs on FC6
    118020: 07/04/16: B. Joshua Rosen: Re: Running Xilinx 9.1 GUIs on FC6
    118048: 07/04/16: <g.eckersley@ieee.org>: Re: Running Xilinx 9.1 GUIs on FC6
117991: 07/04/15: lokesh: combinatorial vs sequential
    118016: 07/04/16: Ralf Hildebrandt: Re: combinatorial vs sequential
117994: 07/04/16: <sheikh.m.farhan@gmail.com>: OPB To Wishbone Bridge
    118025: 07/04/16: <jetmarc@hotmail.com>: Re: OPB To Wishbone Bridge
    118122: 07/04/17: <sheikh.m.farhan@gmail.com>: Re: OPB To Wishbone Bridge
    118123: 07/04/17: <sheikh.m.farhan@gmail.com>: Re: OPB To Wishbone Bridge
    118129: 07/04/18: <jetmarc@hotmail.com>: Re: OPB To Wishbone Bridge
    118136: 07/04/18: <sheikh.m.farhan@gmail.com>: Re: OPB To Wishbone Bridge
117995: 07/04/16: FPGA: Xilinx LogiCore FFT 3.2
    119156: 07/05/14: bijoy: Re: Xilinx LogiCore FFT 3.2
117996: 07/04/16: Nokia_E61i : I am waiting for you!!!!!!: How to design a SDIO peripheral card?
    117998: 07/04/16: Antti: Re: How to design a SDIO peripheral card?
        118001: 07/04/16: Mike Harrison: Re: How to design a SDIO peripheral card?
117997: 07/04/16: <ashasravanthi@gmail.com>: vpw/pwm controller
    118072: 07/04/17: Jonathan Bromley: Re: vpw/pwm controller
        118096: 07/04/17: Martin Thompson: Re: vpw/pwm controller
    118121: 07/04/17: <ashasravanthi@gmail.com>: Re: vpw/pwm controller
117999: 07/04/16: LilacSkin: PLB Master
    118000: 07/04/16: Ben Jones: Re: PLB Master
        118013: 07/04/16: Ben Jones: Re: PLB Master
    118004: 07/04/16: LilacSkin: Re: PLB Master
    118007: 07/04/16: LilacSkin: Re: PLB Master
    118017: 07/04/16: LilacSkin: Re: PLB Master
    118041: 07/04/16: Eli Hughes: Re: PLB Master
        118050: 07/04/16: Jeff Cunningham: Re: PLB Master
            118078: 07/04/17: Eli Hughes: Re: PLB Master
                118100: 07/04/17: Jeff Cunningham: Re: PLB Master
            118085: 07/04/17: Eli Hughes: Re: PLB Master
    118055: 07/04/17: LilacSkin: Re: PLB Master
    118059: 07/04/17: LilacSkin: Re: PLB Master
    118065: 07/04/17: Guru: Re: PLB Master
    118074: 07/04/17: LilacSkin: Re: PLB Master
118002: 07/04/16: <g.eckersley@ieee.org>: Xilinx ISE 9.1
    118006: 07/04/16: Georg Acher: Re: Xilinx ISE 9.1
        118014: 07/04/16: Andreas Ehliar: Re: Xilinx ISE 9.1
            118023: 07/04/16: Georg Acher: Re: Xilinx ISE 9.1
    118038: 07/04/16: tullio: Re: Xilinx ISE 9.1
    118047: 07/04/16: <g.eckersley@ieee.org>: Re: Xilinx ISE 9.1
118005: 07/04/16: vlsi_learner: dual port memory from single port RAM.
    118026: 07/04/16: Tim Wescott: Re: dual port memory from single port RAM.
    118035: 07/04/16: Petter Gustad: Re: dual port memory from single port RAM.
    118039: 07/04/16: Peter Alfke: Re: dual port memory from single port RAM.
    118053: 07/04/16: vlsi_learner: Re: dual port memory from single port RAM.
    118054: 07/04/16: Peter Alfke: Re: dual port memory from single port RAM.
    118068: 07/04/17: vlsi_learner: Re: dual port memory from single port RAM.
    118069: 07/04/17: vlsi_learner: Re: dual port memory from single port RAM.
    118179: 07/04/19: vssumesh: Re: dual port memory from single port RAM.
    118220: 07/04/19: Peter Alfke: Re: dual port memory from single port RAM.
118011: 07/04/16: =?iso-8859-1?B?RWRtb25kIENvdOk=?=: Embedding Altera SignalTap II on 1st synthesis/implementation pass
    118154: 07/04/18: <FightingQuaker1@gmail.com>: Re: Embedding Altera SignalTap II on 1st synthesis/implementation pass
    118210: 07/04/19: =?iso-8859-1?B?RWRtb25kIENvdOk=?=: Re: Embedding Altera SignalTap II on 1st synthesis/implementation pass
    118216: 07/04/19: <FightingQuaker1@gmail.com>: Re: Embedding Altera SignalTap II on 1st synthesis/implementation pass
118015: 07/04/16: Sebastien Bourdeauducq: Safety of bidirectional lines
    118031: 07/04/16: Daniel S.: Re: Safety of bidirectional lines
        118077: 07/04/17: Daniel S.: Re: Safety of bidirectional lines
            118079: 07/04/17: Symon: Re: Safety of bidirectional lines
                118083: 07/04/17: Symon: Re: Safety of bidirectional lines
                118107: 07/04/17: Daniel S.: Re: Safety of bidirectional lines
    118064: 07/04/17: Sebastien Bourdeauducq: Re: Safety of bidirectional lines
    118066: 07/04/17: Symon: Re: Safety of bidirectional lines
118024: 07/04/16: mans (myname_here): Matlab Simulink HDL coder generated code interface.
118027: 07/04/16: Richard Klingler: License Key based on WLAN/Bluetooth MAC
    118030: 07/04/16: Uwe Bonnes: Re: License Key based on WLAN/Bluetooth MAC
        118032: 07/04/16: Richard Klingler: Re: License Key based on WLAN/Bluetooth MAC
    118042: 07/04/16: Petter Gustad: Re: License Key based on WLAN/Bluetooth MAC
        118046: 07/04/16: Gregory C. Read: Re: License Key based on WLAN/Bluetooth MAC
        118413: 07/04/26: Richard Klingler: Re: License Key based on WLAN/Bluetooth MAC
118044: 07/04/16: Didi: Debug monitor for Freescale MPC5200
118049: 07/04/16: <zhangpei@gmail.com>: type/subtype definition in entity
    118063: 07/04/17: Alan Fitch: Re: type/subtype definition in entity
    118086: 07/04/17: Andy: Re: type/subtype definition in entity
    118115: 07/04/17: <zhangpei@gmail.com>: Re: type/subtype definition in entity
118056: 07/04/17: Jalen.Ong@gmail.com: Interfacing FPGA with TTL
    118088: 07/04/17: Dave Pollum: Re: Interfacing FPGA with TTL
118057: 07/04/17: Peter Mendham: plb_tft_cntlr_ref for an ML405 EDK Project
    118067: 07/04/17: Ben Jones: Re: plb_tft_cntlr_ref for an ML405 EDK Project
        118082: 07/04/17: Peter Mendham: Re: plb_tft_cntlr_ref for an ML405 EDK Project
            118087: 07/04/17: Ben Jones: Re: plb_tft_cntlr_ref for an ML405 EDK Project
                118091: 07/04/17: Peter Mendham: Re: plb_tft_cntlr_ref for an ML405 EDK Project
                    118099: 07/04/17: Ben Jones: Re: plb_tft_cntlr_ref for an ML405 EDK Project
                        118103: 07/04/17: Peter Mendham: Re: plb_tft_cntlr_ref for an ML405 EDK Project
118061: 07/04/17: <michel.talon@gmail.com>: define variable in ISE9.1 Tcl scripts
    118062: 07/04/17: Andreas Ehliar: Re: define variable in ISE9.1 Tcl scripts
118070: 07/04/17: Steve: xilinx unused I/O state
    118071: 07/04/17: Symon: Re: xilinx unused I/O state
        118095: 07/04/17: Symon: Re: xilinx unused I/O state
118076: 07/04/17: <Richard>: No Synplify evaluation?
    118104: 07/04/17: HT-Lab: Re: No Synplify evaluation?
118090: 07/04/17: Eli Hughes: 80000 Bit Shift Register
    118092: 07/04/17: Eli Hughes: 80000 Bit Shift Register - The Code
        118097: 07/04/17: Frank Buss: Re: 80000 Bit Shift Register - The Code
        118101: 07/04/17: Ben Jones: Re: 80000 Bit Shift Register - The Code
    118093: 07/04/17: Symon: Re: 80000 Bit Shift Register
    118094: 07/04/17: Frank Buss: Re: 80000 Bit Shift Register
    118098: 07/04/17: Petter Gustad: Re: 80000 Bit Shift Register
    118102: 07/04/17: Andy: Re: 80000 Bit Shift Register
    118106: 07/04/17: <langwadt@ieee.org>: Re: 80000 Bit Shift Register
    118110: 07/04/17: HT-Lab: Re: 80000 Bit Shift Register
        118111: 07/04/17: Eli Hughes: Re: 80000 Bit Shift Register
            118140: 07/04/18: Eli Hughes: Re: 80000 Bit Shift Register
                118165: 07/04/19: Jim Granville: Re: 80000 Bit Shift Register
                    118346: 07/04/24: Eli Hughes: Re: 80000 Bit Shift Register
    118166: 07/04/18: ajjc: Re: 80000 Bit Shift Register
118109: 07/04/17: <stenasc@yahoo.com>: ANN: Tyd-IP Code Generator V3.1 released
118112: 07/04/17: mans (myname_here): creating library in ISE 9
    118114: 07/04/17: Mike Treseler: Re: creating library in ISE 9
    118152: 07/04/18: Andy Peters: Re: creating library in ISE 9
118117: 07/04/17: M. Hamed: Block RAM strange behavior, address off by one
    118118: 07/04/17: Gabor: Re: Block RAM strange behavior, address off by one
    118119: 07/04/17: Peter Alfke: Re: Block RAM strange behavior, address off by one
    118125: 07/04/17: Newman: Re: Block RAM strange behavior, address off by one
    118145: 07/04/18: M. Hamed: Re: Block RAM strange behavior, address off by one
    118146: 07/04/18: Peter Alfke: Re: Block RAM strange behavior, address off by one
    118151: 07/04/18: M. Hamed: Re: Block RAM strange behavior, address off by one
    118156: 07/04/18: Peter Alfke: Re: Block RAM strange behavior, address off by one
    118161: 07/04/18: Newman: Re: Block RAM strange behavior, address off by one
    118163: 07/04/18: M. Hamed: Re: Block RAM strange behavior, address off by one
    118164: 07/04/18: Newman: Re: Block RAM strange behavior, address off by one
    118169: 07/04/18: M. Hamed: Re: Block RAM strange behavior, address off by one
118120: 07/04/17: hitsx@hit.edu.cn: Any recommendations for FPGA PCI development board?
    118211: 07/04/19: John Adair: Re: Any recommendations for FPGA PCI development board?
    118218: 07/04/19: hitsx@hit.edu.cn: Re: Any recommendations for FPGA PCI development board?
118124: 07/04/17: motty: ModelSim Waveform naming question
    118128: 07/04/18: backhus: Re: ModelSim Waveform naming question
    118134: 07/04/18: Andreas Ehliar: Re: ModelSim Waveform naming question
        118160: 07/04/18: Andreas Ehliar: Re: ModelSim Waveform naming question
    118135: 07/04/18: Jonathan Bromley: Re: ModelSim Waveform naming question
        118159: 07/04/18: Andreas Ehliar: ModelSim script for virtual type/function generation
    118139: 07/04/18: motty: Re: ModelSim Waveform naming question
    118307: 07/04/23: Kevin Neilson: Re: ModelSim Waveform naming question
118126: 07/04/18: David M. Palmer: Analog FPGAs: how fast?
118127: 07/04/17: ferorcue: BFM simulation and number of Masters?
    118141: 07/04/18: Mike Lewis: Re: BFM simulation and number of Masters?
118130: 07/04/18: mans (myname_here): ISE Smart Ident
    118131: 07/04/18: Sean Durkin: Re: ISE Smart Ident
    118153: 07/04/18: Andy Peters: Re: ISE Smart Ident
118132: 07/04/18: nezhate: Printing problem with Ise 9.1.03i
    118150: 07/04/18: Andy Peters: Re: Printing problem with Ise 9.1.03i
    118171: 07/04/18: nezhate: Re: Printing problem with Ise 9.1.03i
    118174: 07/04/18: nezhate: Re: Printing problem with Ise 9.1.03i
    118194: 07/04/19: B. Joshua Rosen: Re: Printing problem with Ise 9.1.03i
    118214: 07/04/19: Andy Peters: Re: Printing problem with Ise 9.1.03i
    118228: 07/04/20: nezhate: Re: Printing problem with Ise 9.1.03i
118133: 07/04/18: mans (myname_here): Compiling a library
    118187: 07/04/19: Duth: Re: Compiling a library
    118192: 07/04/19: M. Hamed: Re: Compiling a library
    118196: 07/04/19: Alex Colvin: Re: Compiling a library
118137: 07/04/18: X.Y.: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
    118138: 07/04/18: Symon: Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
        118142: 07/04/18: Eli Hughes: Re: Seeking the solutions of high speed interconnection for the long
    118143: 07/04/18: Tim: Re: Seeking the solutions of high speed interconnection for the long
    118155: 07/04/18: dalai lamah: Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
    118157: 07/04/18: Peter Alfke: Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
        118180: 07/04/19: Symon: Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
            118395: 07/04/25: John_H: Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
        119371: 07/05/17: glen herrmannsfeldt: Re: Seeking the solutions of high speed interconnection for the long
            119403: 07/05/17: PeteS: Re: Seeking the solutions of high speed interconnection for the long
                119425: 07/05/18: glen herrmannsfeldt: Re: Seeking the solutions of high speed interconnection for the long
        119372: 07/05/17: glen herrmannsfeldt: Re: Seeking the solutions of high speed interconnection for the long
    118172: 07/04/18: X.Y.: Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
    118173: 07/04/18: Peter Alfke: Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
    118175: 07/04/18: X.Y.: Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
    118273: 07/04/20: X.Y.: Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
118144: 07/04/18: hokutoi: There is something (other) like his?
118147: 07/04/18: chakra: Issues with the BBD file, using a core generated using ISE coregenerator
    118158: 07/04/18: chakra: Re: Issues with the BBD file, using a core generated using ISE coregenerator
118148: 07/04/18: Will: IOB and DIFFM/DIFFS
118149: 07/04/18: Thomas Heller: Problems in simulation (Webpack 9.1.03i)
    118186: 07/04/19: Duth: Re: Problems in simulation (Webpack 9.1.03i)
        118200: 07/04/19: Thomas Heller: Re: Problems in simulation (Webpack 9.1.03i)
118162: 07/04/18: Marc Battyani: Any recommendation for proto PCB
118167: 07/04/18: mans (myname_here): VHDL source code for polyphase filter
    118182: 07/04/19: <stenasc@yahoo.com>: Re: VHDL source code for polyphase filter
        118184: 07/04/19: mans (myname_here): Re: VHDL source code for polyphase filter
    118188: 07/04/19: <stenasc@yahoo.com>: Re: VHDL source code for polyphase filter
    118190: 07/04/19: Andy: Re: VHDL source code for polyphase filter
118168: 07/04/18: a: Question about Xilinx ISE (problem with signals trimming)
    118201: 07/04/19: Gabor: Re: Question about Xilinx ISE (problem with signals trimming)
        118202: 07/04/19: a: Re: Question about Xilinx ISE (problem with signals trimming)
118176: 07/04/19: Manfred Balik: Altera M4K memory usage
    118177: 07/04/19: Thomas Entner: Re: Altera M4K memory usage
        118181: 07/04/19: Manfred Balik: Re: Altera M4K memory usage
118178: 07/04/19: Wei Wang: Ask: why xilinx FPGA pin assignment couldn't pass p&r?
118183: 07/04/19: Martin Thompson: Re: 64 bit matrix multplication
    119369: 07/05/17: glen herrmannsfeldt: Re: 64 bit matrix multplication
118189: 07/04/19: Derek Simmons: Altera MPM7064LC84 vs EPM7064LC84
    118301: 07/04/23: <gregs@altera.com>: Re: Altera MPM7064LC84 vs EPM7064LC84
118191: 07/04/19: Kunal: Summer with fpgas
    118193: 07/04/19: Austin Lesea: Re: Summer with fpgas
        118199: 07/04/19: Mike Harrison: Re: Summer with fpgas
            118208: 07/04/19: Austin Lesea: Re: Summer with fpgas
                118238: 07/04/20: Eric Brombaugh: Re: Summer with fpgas
                118367: 07/04/24: Eric Smith: Re: Summer with fpgas
        118293: 07/04/23: Eli Hughes: Re: Summer with fpgas
            118306: 07/04/23: Eli Hughes: Re: Summer with fpgas
    118195: 07/04/19: <cs_posting@hotmail.com>: Re: Summer with fpgas
        118270: 07/04/20: Steve Battazzo: Re: Summer with fpgas
    118197: 07/04/19: <cs_posting@hotmail.com>: Re: Summer with fpgas
    118198: 07/04/19: <cs_posting@hotmail.com>: Re: Summer with fpgas
    118203: 07/04/19: Andreas Ehliar: Re: Summer with fpgas
        118215: 07/04/19: Austin Lesea: Re: Summer with fpgas
        118272: 07/04/21: David M. Palmer: Re: Summer with fpgas
    118219: 07/04/19: Kunal: Re: Summer with fpgas
    118234: 07/04/20: <cs_posting@hotmail.com>: Re: Summer with fpgas
    118297: 07/04/23: <cs_posting@hotmail.com>: Re: Summer with fpgas
118204: 07/04/19: Andreas Ehliar: Regarding drivers for FPGA based PCI cards
    118217: 07/04/20: Mark McDougall: Re: Regarding drivers for FPGA based PCI cards
    118224: 07/04/19: comp.arch.fpga: Re: Regarding drivers for FPGA based PCI cards
118205: 07/04/19: Kunal: Re: Summer with fpgas
118206: 07/04/19: <fsdgsdf@spone.com>: Spartan 3 IOSTANDARD vs VCCO
    118209: 07/04/19: Austin Lesea: Re: Spartan 3 IOSTANDARD vs VCCO
        118226: 07/04/20: <fsdgsdf@spone.com>: Re: Spartan 3 IOSTANDARD vs VCCO
118207: 07/04/19: Rebecca: Question about reset signal for several DCMs in EDK design.
    118212: 07/04/19: John McCaskill: Re: Question about reset signal for several DCMs in EDK design.
    118213: 07/04/19: Austin Lesea: Re: Question about reset signal for several DCMs in EDK design.
    118249: 07/04/20: Rebecca: Re: Question about reset signal for several DCMs in EDK design.
118221: 07/04/19: Paddy: xilprofile for edk 8.2
    118223: 07/04/19: Paddy: Re: xilprofile for edk 8.2
118222: 07/04/19: Jhoberg: Free Hardware
    118239: 07/04/20: Colin Paul Gloster: Re: Free Hardware
        118244: 07/04/20: DJ Delorie: Re: Free Hardware
            118246: 07/04/20: Symon: Re: Free Hardware
            118252: 07/04/20: Jan Panteltje: Re: Free Hardware
                118253: 07/04/20: Symon: Re: Free Hardware
                118257: 07/04/20: Jan Panteltje: Re: Free Hardware
            118290: 07/04/23: Colin Paul Gloster: Re: Free Hardware
    118245: 07/04/20: Antti: Re: Free Hardware
    118255: 07/04/20: <cs_posting@hotmail.com>: Re: Free Hardware
    118259: 07/04/20: Jhoberg: Re: Free Hardware
    118312: 07/04/23: Jhoberg: Re: Free Hardware
118225: 07/04/20: Perry: questions about pci conmmunications on a pcb board
118227: 07/04/20: Antti: ABC - Actel's PicoBlaze :) - anybody success with coreconsole?
    119844: 07/05/27: Vince: Re: ABC - Actel's PicoBlaze :) - anybody success with coreconsole?
118229: 07/04/20: John Adair: DARNAW! - PGA Style FPGA Module
    118230: 07/04/20: Symon: Re: DARNAW! - PGA Style FPGA Module
        118266: 07/04/20: Eric Crabill: Re: DARNAW! - PGA Style FPGA Module
    118233: 07/04/20: John Adair: Re: DARNAW! - PGA Style FPGA Module
    118260: 07/04/21: Jim Granville: Re: DARNAW! - PGA Style FPGA Module
        118347: 07/04/24: Eli Hughes: Re: DARNAW! - PGA Style FPGA Module
    118264: 07/04/20: Dave Pollum: Re: DARNAW! - PGA Style FPGA Module
    118274: 07/04/21: John Adair: Re: DARNAW! - PGA Style FPGA Module
    118276: 07/04/21: John Adair: Re: DARNAW! - PGA Style FPGA Module
    118279: 07/04/21: Dave Pollum: Re: DARNAW! - PGA Style FPGA Module
    118409: 07/04/26: Herbert Kleebauer: Re: DARNAW! - PGA Style FPGA Module
        118421: 07/04/26: John Adair: Re: DARNAW! - PGA Style FPGA Module
    121123: 07/06/26: Herbert Kleebauer: Re: DARNAW! - PGA Style FPGA Module
        121135: 07/06/26: PFC: Re: DARNAW! - PGA Style FPGA Module
118231: 07/04/20: maroni: Clock signal FPGA XC95288xl144
    118232: 07/04/20: Symon: Re: Clock signal FPGA XC95288xl144
    118263: 07/04/20: Dave Pollum: Re: Clock signal FPGA XC95288xl144
118235: 07/04/20: Pasacco: Virtex-4 module based partial reconfiguration problem
    118292: 07/04/23: mh: Re: Virtex-4 module based partial reconfiguration problem
118236: 07/04/20: Midou: FPGA Full Custum Design
    118248: 07/04/20: Antti: Re: FPGA Full Custum Design
118237: 07/04/20: <vhdldesigner.patrick@gmail.com>: Stratix II - Cyclone II GATE COUNT
    118247: 07/04/20: Antti: Re: Stratix II - Cyclone II GATE COUNT
    118287: 07/04/23: Karl: Re: Stratix II - Cyclone II GATE COUNT
118240: 07/04/20: <meo2662@gmail.com>: FPGA MAC for Point to Point Connection
118241: 07/04/21: Matt Sorrensen: FPGA Newbie
    118242: 07/04/20: John Adair: Re: FPGA Newbie
    118243: 07/04/20: Symon: Re: FPGA Newbie
        118271: 07/04/20: Jonathan Bromley: Re: FPGA Newbie
    118254: 07/04/20: Icky Thwacket: Re: FPGA Newbie
        118261: 07/04/21: Jim Granville: Re: FPGA Newbie
            118269: 07/04/21: Matt Sorrensen: Re: FPGA Newbie
                118277: 07/04/21: Jim Granville: Re: FPGA Newbie
                118296: 07/04/23: David Kelly: Re: FPGA Newbie
            118310: 07/04/24: Jim Granville: Re: FPGA Newbie
        118278: 07/04/21: Mike Harrison: Re: FPGA Newbie
    118298: 07/04/23: <cs_posting@hotmail.com>: Re: FPGA Newbie
118250: 07/04/20: Gabor: Re: FPGA Newbie
    118268: 07/04/21: Matt Sorrensen: Re: FPGA Newbie
118251: 07/04/20: Thomas Heller: Looking for a spartan 3 board
    118256: 07/04/20: Gabor: Re: Looking for a spartan 3 board
        118258: 07/04/20: Thomas Heller: Re: Looking for a spartan 3 board
    118275: 07/04/21: John Adair: Re: Looking for a spartan 3 board
118262: 07/04/20: Rebecca: Question about intalling EDK9.1i
118265: 07/04/20: Ed: Ouputs during startup and Programming
    118280: 07/04/21: Rob: Re: Ouputs during startup and Programming
        118288: 07/04/23: david.oriot: Re: Ouputs during startup and Programming
            118321: 07/04/23: Austin Lesea: Re: Ouputs during startup and Programming
            118322: 07/04/23: Rob: Re: Ouputs during startup and Programming
    118282: 07/04/21: Peter Alfke: Re: Ouputs during startup and Programming
    118313: 07/04/23: Newman: Re: Ouputs during startup and Programming
    118319: 07/04/23: Peter Alfke: Re: Ouputs during startup and Programming
    118324: 07/04/24: Jim Granville: Re: Ouputs during startup and Programming
118267: 07/04/20: Steve Battazzo: Memory generator IP core ISE Webpack
118281: 07/04/21: mans (myname_here): simulating with OSe 9.1.3
118283: 07/04/21: John Adair: Raggedstone1 LVDS Oscillator
118285: 07/04/22: MM: Symbol names in the Design Hierarchy Window of the Xilinx Floorplanner
    118286: 07/04/23: Andreas Ehliar: Re: Symbol names in the Design Hierarchy Window of the Xilinx Floorplanner
        118295: 07/04/23: MM: Re: Symbol names in the Design Hierarchy Window of the Xilinx Floorplanner
118289: 07/04/23: Richard Klingler: Lattice pricing
    118291: 07/04/23: Jim Granville: Re: Lattice pricing
118294: 07/04/23: mans (myname_here): VHDL editing with UltraEdit
    118300: 07/04/23: wallge: Re: VHDL editing with UltraEdit
        118352: 07/04/24: Andreas Ehliar: Re: VHDL editing with UltraEdit
        118355: 07/04/24: Nicolas Matringe: Re: VHDL editing with UltraEdit
            118372: 07/04/25: Martin Thompson: Re: VHDL editing with UltraEdit
                118382: 07/04/25: mans (myname_here): Re: VHDL editing with UltraEdit
                    118405: 07/04/26: Andreas Ehliar: Re: VHDL editing with UltraEdit
                    118408: 07/04/26: Martin Thompson: Re: VHDL editing with UltraEdit
        118417: 07/04/26: Colin Paul Gloster: Re: VHDL editing with UltraEdit
            118477: 07/04/27: Joseph Samson: Re: VHDL editing with UltraEdit
                118542: 07/04/29: Colin Paul Gloster: Re: VHDL editing with UltraEdit
                    118563: 07/04/30: Martin Thompson: Re: VHDL editing with UltraEdit
                118564: 07/04/30: Martin Thompson: Re: VHDL editing with UltraEdit
    118440: 07/04/26: Andy: Re: VHDL editing with UltraEdit
    118948: 07/05/07: JussiJ: Re: VHDL editing with UltraEdit
118299: 07/04/23: <ddallen@gmail.com>: DONE problems
    118305: 07/04/23: Gabor: Re: DONE problems
    118327: 07/04/23: <kevin@whitedigs.com>: Re: DONE problems
    118336: 07/04/24: Dave: Re: DONE problems
    118337: 07/04/24: Dave: Re: DONE problems
118302: 07/04/23: Pepi: Non-intrusive readback on FPGA configuration data
    118303: 07/04/23: Austin Lesea: Re: Non-intrusive readback on FPGA configuration data
        118304: 07/04/23: Austin Lesea: Re: Non-intrusive readback on FPGA configuration data
    118397: 07/04/25: Pepi: Re: Non-intrusive readback on FPGA configuration data
118308: 07/04/23: Hrishi: Problem with real data type
    118315: 07/04/23: MM: Re: Problem with real data type
        118338: 07/04/24: Colin Paul Gloster: VHDL support from vendors (from "Re: Problem with real data type")
    118323: 07/04/23: comp.arch.fpga: Re: Problem with real data type
118309: 07/04/23: Hrishi: Problem with real data type
    118317: 07/04/23: comp.arch.fpga: Re: Problem with real data type
    118335: 07/04/24: Colin Paul Gloster: Re: Problem with real data type
118311: 07/04/23: Test01: V5 GTP question
    118316: 07/04/23: Austin Lesea: Re: V5 GTP question
    118342: 07/04/24: Test01: Re: V5 GTP question
        118345: 07/04/24: Austin Lesea: Re: V5 GTP question
            118396: 07/04/25: Test01: Re: V5 GTP question
                118441: 07/04/26: Ed McGettigan: Re: V5 GTP question
                    118576: 07/04/30: Test01: Re: V5 GTP question
118314: 07/04/23: Jhoberg: free architecture
    118325: 07/04/23: Jhoberg: Re: free architecture
118318: 07/04/23: Udo: I/O-Standards: HSTL vs. SSTL and others...
    118320: 07/04/23: Austin Lesea: Re: I/O-Standards: HSTL vs. SSTL and others...
118326: 07/04/23: Manny: Slave PLB core interrupt
    118339: 07/04/24: <jetmarc@hotmail.com>: Re: Slave PLB core interrupt
    118364: 07/04/24: Manny: Re: Slave PLB core interrupt
118328: 07/04/24: Bryan: XTREME DSP Development Kit2 JTAG Problem
    118350: 07/04/24: <mtsukanov@gmail.com>: Re: XTREME DSP Development Kit2 JTAG Problem
118330: 07/04/24: Gordon Freeman: Take verilog code from Xilinx Core generator
    118333: 07/04/24: FPGA: Re: Take verilog code from Xilinx Core generator
        118390: 07/04/25: Mike Treseler: Re: Take verilog code from Xilinx Core generator
    118340: 07/04/24: Gordon Freeman: Re: Take verilog code from Xilinx Core generator
    118369: 07/04/25: FPGA: Re: Take verilog code from Xilinx Core generator
    118391: 07/04/25: <ghelbig@lycos.com>: Re: Take verilog code from Xilinx Core generator
    118746: 07/05/02: Gordon Freeman: Re: Take verilog code from Xilinx Core generator
    120067: 07/05/31: tsan: Re: Take verilog code from Xilinx Core generator
118331: 07/04/24: lzh08: I make a usb blaster for altera by myself!
    118334: 07/04/24: Symon: Re: I make a usb blaster for altera by myself!
    118398: 07/04/26: Mark McDougall: Re: I make a usb blaster for altera by myself!
118332: 07/04/24: FPGA: How to add customer peripheral with IP core to EDK?
    118388: 07/04/25: swamy_digital: Re: How to add customer peripheral with IP core to EDK?
118341: 07/04/24: Sheetal: FPGA and DAC for wave generation
    118348: 07/04/24: <cs_posting@hotmail.com>: Re: FPGA and DAC for wave generation
    118353: 07/04/24: Gabor: Re: FPGA and DAC for wave generation
    118358: 07/04/24: Peter Alfke: Re: FPGA and DAC for wave generation
    118361: 07/04/24: -jg: Re: FPGA and DAC for wave generation
118343: 07/04/24: js: Is anyone has experience to share OPB for 2 PowerPC in MPMC2 core
    118456: 07/04/26: leevv: Re: Is anyone has experience to share OPB for 2 PowerPC in MPMC2 core
118349: 07/04/24: Pablo: Increase memory resource at Xil_malloc.
118354: 07/04/24: Joseph H Allen: Altera DPA compatible with Xilinx IOSERDES?
118356: 07/04/24: Rebecca: EDK Simulation library compilation wizard can't find modelsim
    118418: 07/04/26: Newman: Re: EDK Simulation library compilation wizard can't find modelsim
    118431: 07/04/26: Rebecca: Re: EDK Simulation library compilation wizard can't find modelsim
118357: 07/04/24: Rebecca: The simulation library compilation wizard of EDK can't find modelsim
118359: 07/04/24: Matthew Hicks: Problem with PowerPC PIT interrupt
    118377: 07/04/25: Martin Thompson: Re: Problem with PowerPC PIT interrupt
        118394: 07/04/25: Matthew Hicks: Re: Problem with PowerPC PIT interrupt
    118401: 07/04/25: Alan Nishioka: Re: Problem with PowerPC PIT interrupt
    118402: 07/04/26: Matthew Hicks: Re: Problem with PowerPC PIT interrupt
        118404: 07/04/26: Matthew Hicks: Re: Problem with PowerPC PIT interrupt
        118434: 07/04/26: Alan Nishioka: Re: Problem with PowerPC PIT interrupt
        118455: 07/04/26: leevv: Re: Problem with PowerPC PIT interrupt
118360: 07/04/25: IB: XPS and inout ports: is it possible?
118362: 07/04/24: bjzhangwn@gmail.com: compact flash slave ip core
118363: 07/04/25: Bryan: Incorrect response from MAC FIR Low Pass Filter
    118376: 07/04/25: Martin Thompson: Re: Incorrect response from MAC FIR Low Pass Filter
        118406: 07/04/26: Bryan: Re: Incorrect response from MAC FIR Low Pass Filter
118365: 07/04/24: <sheikh.m.farhan@gmail.com>: Using PCI in EDK 8.21
118366: 07/04/24: <sheikh.m.farhan@gmail.com>: Using OPB PCI Bridge in EDK 8.2i
118368: 07/04/25: eric: Image compression on FPGA
    118371: 07/04/25: Thomas Entner: Re: Image compression on FPGA
    118502: 07/04/28: David M. Palmer: Re: Image compression on FPGA
118370: 07/04/25: Udo: Virtex-5 FX when ? (II)
    118373: 07/04/25: Sean Durkin: Re: Virtex-5 FX when ? (II)
    118412: 07/04/26: Antti: Re: Virtex-5 FX when ? (II)
118374: 07/04/25: Pasacco: physical chip size
    118457: 07/04/26: Peter Alfke: Re: physical chip size
        118518: 07/04/29: Jim Granville: Re: physical chip size
    118472: 07/04/27: comp.arch.fpga: Re: physical chip size
    118509: 07/04/28: Pasacco: Re: physical chip size
    118513: 07/04/28: Peter Alfke: Re: physical chip size
        118556: 07/04/29: Daniel S.: Re: physical chip size
    118526: 07/04/29: Pasacco: Re: physical chip size
    118529: 07/04/29: Peter Alfke: Re: physical chip size
    118540: 07/04/29: comp.arch.fpga: Re: physical chip size
118375: 07/04/25: Pasacco: Physical chip size
118378: 07/04/25: maverick: Using OPB PCI In EDK 8.1
118379: 07/04/25: =?euc-kr?B?uLa9rA==?=: OPB master and slave interface for DDR SDRAM controller
118380: 07/04/25: Pablo: Increase Memory Resource in SDRAM.
    118381: 07/04/25: Ben Jones: Re: Increase Memory Resource in SDRAM.
        118410: 07/04/26: Andreas Hofmann: Re: Increase Memory Resource in SDRAM.
            118465: 07/04/27: Andreas Hofmann: Re: Increase Memory Resource in SDRAM.
    118407: 07/04/26: Pablo: Re: Increase Memory Resource in SDRAM.
    118436: 07/04/26: Pablo: Re: Increase Memory Resource in SDRAM.
118384: 07/04/25: Roman: Problem with writing values to SRAM from XMD
    118416: 07/04/26: Newman: Re: Problem with writing values to SRAM from XMD
    118779: 07/05/03: Roman: Re: Problem with writing values to SRAM from XMD
118385: 07/04/25: <pantgom@gmail.com>: Memory Resource in SDRAM
118386: 07/04/25: zl: interrupt handler on the Xilkernel PPC405
    118414: 07/04/26: Roman: Re: interrupt handler on the Xilkernel PPC405
    118426: 07/04/26: zl: Re: interrupt handler on the Xilkernel PPC405
    118466: 07/04/27: zl: Re: interrupt handler on the Xilkernel PPC405
118387: 07/04/25: zl: interrupt handler on the Xilkernel PPC405
118389: 07/04/25: Mike Treseler: Re: The simulation library compilation wizard of EDK can't find modelsim
118392: 07/04/25: Andreas Ehliar: Re: Modelsim simulation progress in batch/command line mode?
    118399: 07/04/25: Jonathan Bromley: Re: Modelsim simulation progress in batch/command line mode?
118393: 07/04/25: M. Hamed: Modelsim simulation progress in batch/command line mode?
    118422: 07/04/26: Andreas Ehliar: Re: Modelsim simulation progress in batch/command line mode?
    118435: 07/04/26: NigelE: Re: Modelsim simulation progress in batch/command line mode?
    118438: 07/04/26: M. Hamed: Re: Modelsim simulation progress in batch/command line mode?
118400: 07/04/25: M. Hamed: Timing constraints with asynchronous clocks
    118423: 07/04/26: John_H: Re: Timing constraints with asynchronous clocks
    118442: 07/04/26: M. Hamed: Re: Timing constraints with asynchronous clocks
118403: 07/04/25: Venu: How to drop a Ethernet Packet in Xilinx EMAC
    118420: 07/04/26: Newman: Re: How to drop a Ethernet Packet in Xilinx EMAC
118411: 07/04/26: Markus Kuhn: Altera Quartus II v7.0 under openSUSE 10.2
    118517: 07/04/28: Ben Twijnstra: Re: Altera Quartus II v7.0 under openSUSE 10.2
118415: 07/04/26: Sven: How to configure SPI FLASH using Spartan-3E?
    118444: 07/04/26: Eric Crabill: Re: How to configure SPI FLASH using Spartan-3E?
        118462: 07/04/27: Sven: Re: How to configure SPI FLASH using Spartan-3E?
            118494: 07/04/27: Eric Crabill: Re: How to configure SPI FLASH using Spartan-3E?
118419: 07/04/26: Pablo: Is microblaze able to change heap_size?
    118427: 07/04/26: Ben Jones: Re: Is microblaze able to change heap_size?
        118470: 07/04/27: Ben Jones: Re: Is microblaze able to change heap_size?
            118615: 07/05/01: Ben Jones: Re: Is microblaze able to change heap_size?
    118464: 07/04/27: Pablo: Re: Is microblaze able to change heap_size?
    118574: 07/04/30: Pablo: Re: Is microblaze able to change heap_size?
    118621: 07/05/01: Pablo: Re: Is microblaze able to change heap_size?
118424: 07/04/26: <user@domain.invalid>: WebPACK 9.1i still makes errors with synthesis of BRAMS
    118425: 07/04/26: <user@domain.invalid>: Re: WebPACK 9.1i still makes errors with synthesis of BRAMS
118429: 07/04/26: Bob: Need help: Altera ALTPLL_RECONFIG state machine construction
    118813: 07/05/03: <vbetz@altera.com>: Re: Need help: Altera ALTPLL_RECONFIG state machine construction
118430: 07/04/26: S.j: pcis3base, cesys
118432: 07/04/26: Rebecca: Re: The simulation library compilation wizard of EDK can't find modelsim
118433: 07/04/26: <zibixx76@yahoo.com>: differential pins assignment in Synplify fro altera device
    118665: 07/05/01: <vbetz@altera.com>: Re: differential pins assignment in Synplify fro altera device
118437: 07/04/26: Rebecca: Re: The simulation library compilation wizard of EDK can't find modelsim
118439: 07/04/26: jmariano: Sscanf replacement for xilinx EDK
    118446: 07/04/26: Nico Coesel: Re: Sscanf replacement for xilinx EDK
    118448: 07/04/26: Gabor: Re: Sscanf replacement for xilinx EDK
    118449: 07/04/26: zcsizmadia@gmail.com: Re: Sscanf replacement for xilinx EDK
    118468: 07/04/27: jmariano: Re: Sscanf replacement for xilinx EDK
118443: 07/04/26: Rebecca: Question about the simulation library in EDK
118445: 07/04/26: Rebecca: Question about the simulation library in EDK
118447: 07/04/26: Rebecca: Question about the simulation library in EDK
    118454: 07/04/26: motty: Re: Question about the simulation library in EDK
    118476: 07/04/27: Rebecca: Re: Question about the simulation library in EDK
    118488: 07/04/27: motty: Re: Question about the simulation library in EDK
    118492: 07/04/27: Rebecca: Re: Question about the simulation library in EDK
118450: 07/04/26: <rponsard@gmail.com>: memory interface for DDR/DDR2 with xilinx spartan 3E/3A starter kits
118453: 07/04/26: jjlindula@hotmail.com: Quartus Fitter Seed Setting
    118460: 07/04/27: Ben Twijnstra: Re: Quartus Fitter Seed Setting
    118473: 07/04/27: <vbetz@altera.com>: Re: Quartus Fitter Seed Setting
118458: 07/04/26: mohan: Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?
    118467: 07/04/27: Colin Paul Gloster: Re: Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?
    118491: 07/04/27: <cs_posting@hotmail.com>: Re: Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?
    118500: 07/04/28: Daniel O'Connor: Re: Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?
118459: 07/04/26: Bob: N00b question about DCM
    118463: 07/04/27: Sylvain Munaut: Re: N00b question about DCM
    118484: 07/04/27: Mike Lundy: Re: N00b question about DCM
118461: 07/04/26: Adam Megacz: one extra slipway board from fccm
    118469: 07/04/27: Dave Pollum: Re: one extra slipway board from fccm
    118501: 07/04/27: <fpga_toys@yahoo.com>: Re: one extra slipway board from fccm
    118507: 07/04/28: comp.arch.fpga: Re: one extra slipway board from fccm
118471: 07/04/27: <jetmarc@hotmail.com>: Prope timing constraint for this pin?
118474: 07/04/27: fp: a question about DDFS
    118478: 07/04/27: Peter Alfke: Re: a question about DDFS
    118499: 07/04/27: fp: Re: a question about DDFS
118475: 07/04/27: bjzhangwn@gmail.com: chip to chip high speed interconnet bus
118479: 07/04/27: MNiegl: Problem cascading 2 DCMs
    118480: 07/04/27: Nico Coesel: Re: Problem cascading 2 DCMs
    118481: 07/04/27: Peter Alfke: Re: Problem cascading 2 DCMs
        118605: 07/05/01: John Williams: Re: Problem cascading 2 DCMs
            118628: 07/05/01: austin: Re: Problem cascading 2 DCMs
                118642: 07/05/01: austin: Re: Problem cascading 2 DCMs
                    118647: 07/05/01: austin: Re: Problem cascading 2 DCMs
    118482: 07/04/27: Austin Lesea: Re: Problem cascading 2 DCMs
        118496: 07/04/28: Alvin Andries: Re: Problem cascading 2 DCMs
    118483: 07/04/27: MNiegl: Re: Problem cascading 2 DCMs
    118485: 07/04/27: MNiegl: Re: Problem cascading 2 DCMs
    118504: 07/04/28: MNiegl: Re: Problem cascading 2 DCMs
    118508: 07/04/28: Symon: Re: Problem cascading 2 DCMs
    118525: 07/04/29: MNiegl: Re: Problem cascading 2 DCMs
    118528: 07/04/29: Gabor: Re: Problem cascading 2 DCMs
    118568: 07/04/30: MNiegl: Re: Problem cascading 2 DCMs
    118577: 07/04/30: Rob Dimond: Re: Problem cascading 2 DCMs
    118578: 07/04/30: MNiegl: Re: Problem cascading 2 DCMs
    118588: 07/04/30: Erik Widding: Re: Problem cascading 2 DCMs
    118639: 07/05/01: MNiegl: Re: Problem cascading 2 DCMs
    118644: 07/05/01: MNiegl: Re: Problem cascading 2 DCMs
    118693: 07/05/02: MNiegl: Re: Problem cascading 2 DCMs
118486: 07/04/27: mludwig: constraints for design-generated clock
118487: 07/04/27: <bfroemel@gmail.com>: Killed a Stratix-II Nios II Altera devkit, How to repair?
    118489: 07/04/27: <bfroemel@gmail.com>: Re: Killed a Stratix-II Nios II Altera devkit, How to repair?
        118490: 07/04/27: John_H: Re: Killed a Stratix-II Nios II Altera devkit, How to repair?
    118643: 07/05/01: Pepi: Re: Killed a Stratix-II Nios II Altera devkit, How to repair?
118493: 07/04/27: M. Hamed: Placement error for adjacent pins
    118510: 07/04/28: Gabor: Re: Placement error for adjacent pins
        118515: 07/04/28: Nico Coesel: Re: Placement error for adjacent pins
    118512: 07/04/28: M. Hamed: Re: Placement error for adjacent pins
    118516: 07/04/28: Gabor: Re: Placement error for adjacent pins
118495: 07/04/27: <janbeck@gmail.com>: Is there a reset signal available in verilog in Xilinx FPGAs?
    118497: 07/04/27: Mike Lundy: Re: Is there a reset signal available in verilog in Xilinx FPGAs?
    118498: 07/04/27: Duane Clark: Re: Is there a reset signal available in verilog in Xilinx FPGAs?
118503: 07/04/28: <eapen.abraham@gmail.com>: TigerSHARC TS201 to PLX 9656
    118514: 07/04/28: Gabor: Re: TigerSHARC TS201 to PLX 9656
    118524: 07/04/29: <eapen.abraham@gmail.com>: Re: TigerSHARC TS201 to PLX 9656
    118565: 07/04/30: colin: Re: TigerSHARC TS201 to PLX 9656
        118586: 07/04/30: Ron Huizen: Re: TigerSHARC TS201 to PLX 9656
    118614: 07/05/01: <eapen.abraham@gmail.com>: Re: TigerSHARC TS201 to PLX 9656
118506: 07/04/28: Antti: How many Xilinx devkits does one need?
    118638: 07/05/01: Eric Crabill: Re: How many Xilinx devkits does one need?
    118680: 07/05/02: Antti: Re: How many Xilinx devkits does one need?
118511: 07/04/28: Joseph H Allen: fast arbiters (was Re: How to design an abitration cicuit...)
    118631: 07/05/01: Quang Anh: Re: fast arbiters (was Re: How to design an abitration cicuit...)
        118709: 07/05/02: Joseph H Allen: Re: fast arbiters (was Re: How to design an abitration cicuit...)
            118794: 07/05/03: Joseph H Allen: Re: fast arbiters (was Re: How to design an abitration cicuit...)
    118772: 07/05/03: romi: Re: fast arbiters (was Re: How to design an abitration cicuit...)
    119091: 07/05/11: Quang Anh: Re: fast arbiters (was Re: How to design an abitration cicuit...)
118519: 07/04/28: Eric Smith: driving Spartan-3 input from 74LS TTL
    118521: 07/04/29: Jim Granville: Re: driving Spartan-3 input from 74LS TTL
        118545: 07/04/29: Eric Smith: Re: driving Spartan-3 input from 74LS TTL
            118560: 07/04/30: Nico Coesel: Re: driving Spartan-3 input from 74LS TTL
                118567: 07/04/30: Jim Granville: Re: driving Spartan-3 input from 74LS TTL
            118602: 07/04/30: Eric Smith: Re: driving Spartan-3 input from 74LS TTL
            119121: 07/05/12: Eric Smith: Re: driving Spartan-3 input from 74LS TTL
                119136: 07/05/13: Jim Granville: Re: driving Spartan-3 input from 74LS TTL
118520: 07/04/28: Robert Harrell: CMUcam2 and a XUP-V2Pro
118522: 07/04/28: Peter Alfke: Re: driving Spartan-3 input from 74LS TTL
118523: 07/04/28: fluxgate: Interconnect architectures : Aurora and SPI-S
118527: 07/04/29: Pasacco: Macro modified after Map ?
118530: 07/04/29: Mad I.D.: DS18B20 connection on FPGA?
    118559: 07/04/30: Jeff Cunningham: Re: DS18B20 connection on FPGA?
118531: 07/04/29: <Anson.Stuggart@gmail.com>: debounce state diagram FSM
    118532: 07/04/29: Peter Alfke: Re: debounce state diagram FSM
        118537: 07/04/29: John Popelish: Re: debounce state diagram FSM
            118593: 07/04/30: Default User: Re: debounce state diagram FSM
    118533: 07/04/29: <billwang05@gmail.com>: Re: debounce state diagram FSM
    118534: 07/04/29: Mike Treseler: Re: debounce state diagram FSM
    118535: 07/04/29: John Popelish: Re: debounce state diagram FSM
        118548: 07/04/29: John Popelish: Re: debounce state diagram FSM
            118552: 07/04/29: John Popelish: Re: debounce state diagram FSM
            118553: 07/04/29: John Popelish: Re: debounce state diagram FSM
            118594: 07/04/30: Flash Gordon: Re: debounce state diagram FSM
    118536: 07/04/29: John O'Flaherty: Re: debounce state diagram FSM
    118538: 07/04/29: <Anson.Stuggart@gmail.com>: Re: debounce state diagram FSM
    118539: 07/04/30: Jim Granville: Re: debounce state diagram FSM
    118541: 07/04/29: Flash Gordon: Re: debounce state diagram FSM
    118543: 07/04/29: Keith Thompson: Re: debounce state diagram FSM
    118544: 07/04/29: Fred Bloggs: Re: debounce state diagram FSM
    118547: 07/04/29: Amit: Re: debounce state diagram FSM
    118549: 07/04/29: Amit: Re: debounce state diagram FSM
    118550: 07/04/29: Amit: Re: debounce state diagram FSM
    118551: 07/04/29: <Anson.Stuggart@gmail.com>: Re: debounce state diagram FSM
    118554: 07/04/29: Amit: Re: debounce state diagram FSM
    118555: 07/04/29: Amit: Re: debounce state diagram FSM
    118557: 07/04/29: <Anson.Stuggart@gmail.com>: Re: debounce state diagram FSM
    118558: 07/04/29: <billwang05@gmail.com>: Re: debounce state diagram FSM
    118587: 07/04/30: jens: Re: debounce state diagram FSM
    118589: 07/04/30: petrus bitbyter: Re: debounce state diagram FSM
        118600: 07/04/30: John Popelish: Re: debounce state diagram FSM
            118603: 07/04/30: Default User: Re: debounce state diagram FSM
                118604: 07/04/30: John Popelish: Re: debounce state diagram FSM
                    118609: 07/05/01: Jim Granville: Re: debounce state diagram FSM
                        118610: 07/05/01: Matthew Hicks: Re: debounce state diagram FSM
                118649: 07/05/01: petrus bitbyter: Re: debounce state diagram FSM
                    118686: 07/05/02: jasen: Re: debounce state diagram FSM
        118606: 07/04/30: CBFalconer: Re: debounce state diagram FSM
            118655: 07/05/01: jasen: Re: debounce state diagram FSM
                118701: 07/05/02: CBFalconer: Re: debounce state diagram FSM
            118876: 07/05/05: Fred Bloggs: Re: debounce state diagram FSM
                118877: 07/05/05: Richard Heathfield: Re: debounce state diagram FSM
                    118878: 07/05/05: Fred Bloggs: Re: debounce state diagram FSM
    118591: 07/04/30: <jpopelish@rica.net>: Re: debounce state diagram FSM
    118607: 07/04/30: Peter Alfke: Re: debounce state diagram FSM
    118651: 07/05/01: Robin: Re: debounce state diagram FSM
        118652: 07/05/01: John Popelish: Re: debounce state diagram FSM
            118654: 07/05/01: John Larkin: Re: debounce state diagram FSM
        118656: 07/05/02: petrus bitbyter: Re: debounce state diagram FSM
            118658: 07/05/01: John Larkin: Re: debounce state diagram FSM
        118657: 07/05/01: Keith Thompson: Re: debounce state diagram FSM
            118659: 07/05/01: John Larkin: Re: debounce state diagram FSM
                118664: 07/05/01: Keith Thompson: Re: debounce state diagram FSM
                    118733: 07/05/02: Jim Lewis: Re: debounce state diagram FSM - topical
                        118735: 07/05/02: Flash Gordon: Re: debounce state diagram FSM - topical
                            118740: 07/05/02: CBFalconer: Re: debounce state diagram FSM - topical
                                118786: 07/05/03: Default User: Re: debounce state diagram FSM - topical
                            118741: 07/05/02: John Larkin: Re: debounce state diagram FSM - topical
                                118748: 07/05/03: Flash Gordon: Re: debounce state diagram FSM - topical
                                    118781: 07/05/03: John Larkin: Re: debounce state diagram FSM - topical
                        118736: 07/05/02: Default User: Re: debounce state diagram FSM - topical
                    118737: 07/05/02: Default User: Re: debounce state diagram FSM
                118679: 07/05/02: Flash Gordon: Re: debounce state diagram FSM
                    118731: 07/05/02: John Larkin: Re: debounce state diagram FSM
                        118732: 07/05/02: Flash Gordon: Re: debounce state diagram FSM
            118660: 07/05/01: CBFalconer: Re: debounce state diagram FSM
                118663: 07/05/01: Keith Thompson: Re: debounce state diagram FSM
                    118666: 07/05/02: Jim Granville: Re: debounce state diagram FSM
                        118668: 07/05/01: Keith Thompson: Re: debounce state diagram FSM
                            118678: 07/05/02: Flash Gordon: Re: debounce state diagram FSM
                                118738: 07/05/03: Flash Gordon: Re: debounce state diagram FSM
                                    118795: 07/05/03: Flash Gordon: Re: debounce state diagram FSM
                    118702: 07/05/02: CBFalconer: Re: debounce state diagram FSM
        118687: 07/05/02: jasen: Re: debounce state diagram FSM
    118667: 07/05/01: Peter Nilsson: Re: debounce state diagram FSM
    118683: 07/05/02: Robin: Re: debounce state diagram FSM
    118879: 07/05/05: christian.bau: Re: debounce state diagram FSM
118546: 07/04/29: Peter Alfke: Re: driving Spartan-3 input from 74LS TTL
118561: 07/04/30: <eapen.abraham@gmail.com>: Serial FPDP
118562: 07/04/30: <ashasravanthi@gmail.com>: SAE j1850 pwm protocol controller ip core
118566: 07/04/30: Antti: Xilinx software quality - how low can it go ?!
    118569: 07/04/30: Tim: Re: Xilinx software quality - how low can it go ?!
    118570: 07/04/30: Antti: Re: Xilinx software quality - how low can it go ?!
    118571: 07/04/30: comp.arch.fpga: Re: Xilinx software quality - how low can it go ?!
    118572: 07/04/30: Antti: Re: Xilinx software quality - how low can it go ?!
    118579: 07/04/30: <cs_posting@hotmail.com>: Re: Xilinx software quality - how low can it go ?!
    118581: 07/04/30: Martin Thompson: Re: Xilinx software quality - how low can it go ?!
    118612: 07/04/30: Antti: Re: Xilinx software quality - how low can it go ?!
    118620: 07/05/01: Symon: Re: Xilinx software quality - how low can it go ?!
    118626: 07/05/01: <steven.elzinga@gmail.com>: Re: Xilinx software quality - how low can it go ?!
    118671: 07/05/01: <fpga_toys@yahoo.com>: Re: Xilinx software quality - how low can it go ?!
    118675: 07/05/01: Antti: Re: Xilinx software quality - how low can it go ?!
    118727: 07/05/02: dalai lamah: Re: Xilinx software quality - how low can it go ?!
        118776: 07/05/03: Ben Jones: Re: Xilinx software quality - how low can it go ?!
            118787: 07/05/03: Ben Jones: Re: Xilinx software quality - how low can it go ?!
    118773: 07/05/03: Antti: Re: Xilinx software quality - how low can it go ?!
    118774: 07/05/03: Frank Buss: Re: Xilinx software quality - how low can it go ?!
        118935: 07/05/07: austin: Re: Xilinx software quality - how low can it go ?!
        118938: 07/05/07: <steve.lass@xilinx.com>: Re: Xilinx software quality - how low can it go ?!
            118944: 07/05/07: Ray Andraka: Re: Xilinx software quality - how low can it go ?!
            118945: 07/05/08: Jim Granville: Re: Xilinx software quality - how low can it go ?!
            118957: 07/05/08: Symon: Re: Xilinx software quality - how low can it go ?!
            118964: 07/05/08: Ray Andraka: Re: Xilinx software quality - how low can it go ?!
                118967: 07/05/08: Symon: Re: Xilinx software quality - how low can it go ?!
                    118972: 07/05/08: Ray Andraka: Re: Xilinx software quality - how low can it go ?!
            118997: 07/05/09: Ben Jones: Re: Xilinx software quality - how low can it go ?!
                119007: 07/05/09: Andreas Ehliar: Re: Xilinx software quality - how low can it go ?!
                    119015: 07/05/09: Ben Jones: Re: Open Source (was: Xilinx software quality - how low can it go ?!)
                    119033: 07/05/09: Eric Smith: Re: Xilinx software quality - how low can it go ?!
                        119035: 07/05/10: Andreas Ehliar: Re: Xilinx software quality - how low can it go ?!
                        119036: 07/05/10: Andreas Ehliar: Re: Xilinx software quality - how low can it go ?!
                            119042: 07/05/10: Andreas Ehliar: Re: Xilinx software quality - how low can it go ?!
                119040: 07/05/10: David M. Palmer: Re: Xilinx software quality - how low can it go ?!
                119080: 07/05/11: WiMos: Re: Xilinx software quality - how low can it go ?!
                    119082: 07/05/11: Ben Jones: Re: Xilinx software quality - how low can it go ?!
                        119086: 07/05/11: Andreas Ehliar: Re: Xilinx software quality - how low can it go ?!
                            119095: 07/05/11: Ben Jones: Re: Xilinx software quality - how low can it go ?!
            119012: 07/05/09: Chris: Re: Xilinx software quality - how low can it go ?!
            119101: 07/05/11: Uwe Bonnes: Re: Xilinx software quality - how low can it go ?!
                119157: 07/05/14: Uwe Bonnes: Re: Xilinx software quality - how low can it go ?!
                    119186: 07/05/15: Jim Granville: Re: Xilinx software quality - how low can it go ?!
            119205: 07/05/15: <ammonton@cc.full.stop.helsinki.fi>: Re: Xilinx software quality - how low can it go ?!
    118780: 07/05/03: Antti: Re: Xilinx software quality - how low can it go ?!
    118782: 07/05/03: Antti: Re: Xilinx software quality - how low can it go ?!
    118789: 07/05/03: Antti: Re: Xilinx software quality - how low can it go ?!
    118790: 07/05/03: Antti: Re: Xilinx software quality - how low can it go ?!
    118886: 07/05/05: <fpga_toys@yahoo.com>: Re: Xilinx software quality - how low can it go ?!
    118924: 07/05/07: Mike Lundy: Re: Xilinx software quality - how low can it go ?!
    118947: 07/05/07: Bob: Re: Xilinx software quality - how low can it go ?!
    118960: 07/05/08: Antti: Re: Xilinx software quality - how low can it go ?!
    118963: 07/05/08: Antti: Re: Xilinx software quality - how low can it go ?!
    118965: 07/05/08: Antti: Re: Xilinx software quality - how low can it go ?!
    118977: 07/05/08: Mike Lundy: Re: Xilinx software quality - how low can it go ?!
    118978: 07/05/08: Antti: Re: Xilinx software quality - how low can it go ?!
    118980: 07/05/08: Mike Lundy: Re: Xilinx software quality - how low can it go ?!
    118990: 07/05/08: Adam Megacz: Re: FPGA software quality - how low can it go ?!
        118998: 07/05/09: Symon: Re: FPGA software quality - how low can it go ?!
    119000: 07/05/09: Manny: Re: Xilinx software quality - how low can it go ?!
    119013: 07/05/09: <fpga_toys@yahoo.com>: Re: Xilinx software quality - how low can it go ?!
    119021: 07/05/09: bengineerd: Re: Open Source (was: Xilinx software quality - how low can it go ?!)
    119024: 07/05/09: <fpga_toys@yahoo.com>: Re: Open Source (was: Xilinx software quality - how low can it go ?!)
    119155: 07/05/14: Antti: Re: Xilinx software quality - how low can it go ?!
    119160: 07/05/14: Antti: Re: Xilinx software quality - how low can it go ?!
    119166: 07/05/14: Didi: Re: Xilinx software quality - how low can it go ?!
118573: 07/04/30: mludwig: weird PACE Error, not one google result
    118627: 07/05/01: Jonathan Bromley: Re: weird PACE Error, not one google result
    118632: 07/05/01: mludwig: Re: weird PACE Error, not one google result
    119496: 07/05/21: Ligeti: Re: weird PACE Error, not one google result
    120075: 07/05/31: <ashes.man@gmail.com>: Re: weird PACE Error, not one google result
    120090: 07/05/31: <ashes.man@gmail.com>: Re: weird PACE Error, not one google result
    121096: 07/06/25: <collinds104@yahoo.co.uk>: Re: weird PACE Error, not one google result
    122081: 07/07/19: <DomGiambo@gmail.com>: Re: weird PACE Error, not one google result
118575: 07/04/30: Antti: DDR2 with Spartan-3A anybody having success??
    118597: 07/04/30: <rponsard@gmail.com>: Re: DDR2 with Spartan-3A anybody having success??
        118669: 07/05/02: Alex Gibson: Re: DDR2 with Spartan-3A anybody having success??
            118691: 07/05/02: Jim Granville: Re: DDR2 with Spartan-3A anybody having success??
    118598: 07/04/30: <rponsard@gmail.com>: Re: DDR2 with Spartan-3A anybody having success??
    118611: 07/04/30: Antti: Re: DDR2 with Spartan-3A anybody having success??
    118677: 07/05/01: Antti: Re: DDR2 with Spartan-3A anybody having success??
    118696: 07/05/02: Antti: Re: DDR2 with Spartan-3A anybody having success??
    118707: 07/05/02: <rponsard@gmail.com>: Re: DDR2 with Spartan-3A anybody having success??
    118708: 07/05/02: Antti: Re: DDR2 with Spartan-3A anybody having success??
    118713: 07/05/02: <rponsard@gmail.com>: Re: DDR2 with Spartan-3A anybody having success??
118580: 07/04/30: Morten Leikvoll: ise9.1i regid not working on x64
    118633: 07/05/01: kmlpatel@gmail.com: Re: ise9.1i regid not working on x64
118582: 07/04/30: <rogodani@gmail.com>: Please help me fast !!!!!
    118583: 07/04/30: Benjamin Todd: Re: Please help me fast !!!!!
    118584: 07/04/30: John_H: Re: Please help me fast !!!!!
    118585: 07/04/30: Paul: Re: Please help me fast !!!!!
    118596: 07/04/30: tersono: Re: Please help me fast !!!!!
        118608: 07/04/30: Mike Treseler: Re: Please help me fast !!!!!
    118599: 07/04/30: Jeff Cunningham: Re: Please help me fast !!!!!
118590: 07/04/30: axr0284: synthesis tools
    118592: 07/04/30: Jon Beniston: Re: synthesis tools
    118595: 07/04/30: Mike Treseler: Re: synthesis tools
    118613: 07/05/01: <eapen.abraham@gmail.com>: Re: synthesis tools
    118619: 07/05/01: HT-Lab: Re: synthesis tools
        118640: 07/05/01: Petter Gustad: Re: synthesis tools
    118623: 07/05/01: Andy: Re: synthesis tools
    118624: 07/05/01: axr0284: Re: synthesis tools
    118650: 07/05/01: Andy: Re: synthesis tools


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