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Security thru obscurity has always made victims of the honest by limiting their options. It's also slows, or prevents, real security that develops from good vendor and customer partnerships.Article: 117951
Eric Smith wrote: > I was hoping to download Francesco Poderico's Picoblaze C compiler > today, but unfortunately his domain is expired. Google didn't > turn up any other sites from which I can download it; does anyone > know of such a location, or would anyone be willing to make it > available online or send me a copy? (Provided that doing so > doesn't violate any license terms.) Shouldn't this be something Xilinx should sponser ? Seems a shame a tool like this vanishes, for want of a liltte infrastructure ? Or, I suppose Lattice could be interested in a Mico8 variant of this compiler, as they are quite similar cores, and Lattice are proven open-source friendly ? -jg.Article: 117952
Un bel giorno Daniel S. digiṭ: > Variable assignments are processed sequentially while signal assignments > are processed synchronously I didn't know that! I (almost) always use signals instead of variables, therefore I've never had a chance to notice the difference. > Since not all synthesis and simulation tools agree on how to deal with > variables in synthesizable code, some weird bugs can come up so it is > generally better to use signals which more closely (less ambiguously) > represents how synchronous hardware works. I agree. I barely can see how variables can be implemented in a real design, if they work that way; probably most of the times the tools just convert them as signals, like Xilinx MAP and PAR apparently do. Thank you! -- emboliaschizoide.splinder.comArticle: 117953
dalai lamah wrote: > Un bel giorno Daniel S. digiṭ: > >> Variable assignments are processed sequentially while signal assignments >> are processed synchronously > > I didn't know that! I (almost) always use signals instead of variables, > therefore I've never had a chance to notice the difference. Originally, variables were intended only for testbench usage to simplify dynamic sequential test sequences. >> Since not all synthesis and simulation tools agree on how to deal with >> variables in synthesizable code, some weird bugs can come up so it is >> generally better to use signals which more closely (less ambiguously) >> represents how synchronous hardware works. > > I agree. I barely can see how variables can be implemented in a real > design, if they work that way; probably most of the times the tools just > convert them as signals, like Xilinx MAP and PAR apparently do. As far as synthesis is concerned, both signals and variables become nets and FFs, the only difference between the two is how assignments are handled. Signals get their new value after the trigger event has been processed while variables get their new value immediately after assignment. For synthesizable constructs, the tools simply duplicate or cascade logic and FFs to mimic the sequential variable assignments. BTW, in my original reply I overlooked the "='0'" and wrote thinking your were checking the LSB for '1' so everything is backwards.Article: 117954
> Security thru obscurity has always made victims of the honest by > limiting their options. It's also slows, or prevents, real security > that develops from good vendor and customer partnerships. I fully agree with this view, but that's beside the point. The business for FPGA IP is certainly inherently flawed, but it does exist, and there's no reason for the vendors to harm it themselves. JBArticle: 117955
Eric Smith <eric@brouhaha.com> wrote: >I was hoping to download Francesco Poderico's Picoblaze C compiler >today, but unfortunately his domain is expired. Google didn't >turn up any other sites from which I can download it; does anyone >know of such a location, or would anyone be willing to make it >available online or send me a copy? (Provided that doing so >doesn't violate any license terms.) Are you sure you want to use that compiler? Last time I checked it didn't seem very usefull (no optimisations at all). You're probably better of writing your program in assembly language. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 117956
Daniel S. wrote: > Since not all synthesis and simulation tools agree on how to deal with > variables in synthesizable code, some weird bugs can come up so it is > generally better to use signals which more closely (less ambiguously) > represents how synchronous hardware works. Here are my examples of designs using variables exclusively: http://home.comcast.net/~mike_treseler/ These examples have been tested on almost all the the FPGA synthesis tools, and these agree perfectly on how to deal with variables. Modelsim also agrees. Do you have a single example to support your assertion above? -- Mike TreselerArticle: 117957
Daniel S. wrote:
> Originally, variables were intended only for testbench usage to simplify
> dynamic sequential test sequences.
Originally, VHDL was intended to document the *behavior* of ASICs.
Simulators based on VHDL came later.
-- Mike Treseler
Article: 117958Google is your friend. http://www.asm.ro/fpga/ HTH, SymsArticle: 117959
On Apr 14, 7:17 am, n...@puntnl.niks (Nico Coesel) wrote: > Are you sure you want to use that compiler? Last time I checked it > didn't seem very usefull (no optimisations at all). You're probably > better of writing your program in assembly language. For nearly 30 years there have been various C compilers for small micro's, ever since Ron Cain knocked off the Small-C compiler for the 8080 with a little help from me (a free SRI International PDP-11 unix account as long as the compiler was public domain). These compilers do not need to be perfect, or even great, just correct, to quickly knock off projects that would take weeks in assembler. For most, careful coding will get your project 95% of the way toward good/excellent performance, with a small amount of asm functions and tweeking at the end to meet timing goals. For a tiny PB PLD project, it might not be practical ... for a larger PB Spartan project, it might be the only quick prototyping choice that makes sense, from early concept to production.Article: 117960
Un bel giorno Mike Treseler digiṭ: > These examples have been tested on almost all the the > FPGA synthesis tools, and these agree > perfectly on how to deal with variables. > Modelsim also agrees. If you try my example with the post-translated or the post-PAR model generated by Xilinx tools, you will get the same result by putting the increment operation before or after the if statement: [...] elsif CLK='1' and CLK'event then CNT := CNT+1; if CNT(0)='0' then O <= '1'; end if; end if; [...] Works the same as: [...] elsif CLK='1' and CLK'event then if CNT(0)='0' then O <= '1'; end if; CNT := CNT+1; end if; [...] -- emboliaschizoide.splinder.comArticle: 117961
Mike Treseler wrote: > Daniel S. wrote: > >> Since not all synthesis and simulation tools agree on how to deal with >> variables in synthesizable code, some weird bugs can come up so it is >> generally better to use signals which more closely (less ambiguously) >> represents how synchronous hardware works. > > Here are my examples of designs using variables exclusively: > http://home.comcast.net/~mike_treseler/ > These examples have been tested on almost all the the > FPGA synthesis tools, and these agree > perfectly on how to deal with variables. > Modelsim also agrees. > Do you have a single example to support > your assertion above? I do not use variables in my designs, none of the people I have worked with and none of the projects I have worked on so far used variables in synthesizable code either. Variables for synthesis might work but none of the people I have ever worked with ever recommended it and many have reported problems of one sort or another with that - variables used to be testbench-only after all. This was years ago but the general mindset for the major projects I have worked on is to never use a feature that once proved to cause unnecessary simulation or synthesis problems... at the very least not until many tool revisions after the last known related bugs had been fixed - researcher hate hunting down tool bugs and ASIC people hate bumping tape-outs due to last minute bugs or scrapping masks/wafers because third-party tool bugs related to some new feature were found a little too late. Even if variables have been fully supported by all simulation and synthesis tools for the last couple of years, it does not reduce their potential for inducing unnecessary confusion - newbies already get confused enough with simple HDL-based RTL design as it is and I cannot think of any good reason (other than academic) to use variables instead of signals for synthesis. IMO, variables for synthesis are a mostly unnecessary and potentially confusing convenience.Article: 117962
This is a multi-part message in MIME format. ------=_NextPart_000_0006_01C77E8F.C010AD50 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hello Has anyone figured out how to program and configure from the Platform = Flash on the ML506. I have spent a lot of quality time with the = ML505/ML506 Getting Started Tutorial (ug348.pdf) without luck. There is a dip switch (SW3), the Impact settings and a pair of XCF32P = flashes. I just want to configure from one of the flashes on power up. If anyone can tell me the exact settings that make the flashes usable I = would be very grateful. Pete ------=_NextPart_000_0006_01C77E8F.C010AD50 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; = charset=3Diso-8859-1"> <META content=3D"MSHTML 6.00.2900.3059" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY> <DIV><FONT face=3DArial size=3D2>Hello</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>Has anyone figured out how to program = and configure=20 from the Platform Flash on the ML506. I have spent a lot of quality time = with=20 the </FONT><FONT face=3DArial size=3D2>ML505/ML506 </FONT><FONT = face=3DArial=20 size=3D2>Getting Started </FONT><FONT face=3DArial size=3D2>Tutorial=20 (ug348.pdf) without luck.</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>There is a dip switch (SW3), the Impact = settings=20 and a pair of XCF32P flashes.</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>I just want to configure from one of = the flashes on=20 power up.</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>If anyone can tell me the exact = settings that make=20 the flashes usable I would be very grateful.</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2> Pete</FONT></DIV></BODY></HTML> ------=_NextPart_000_0006_01C77E8F.C010AD50--Article: 117963
On Sat, 14 Apr 2007 14:20:21 -0400, "Daniel S." <digitalmastrmind_no_spam@hotmail.com> wrote: [...] >IMO, variables for synthesis are a mostly unnecessary and potentially >confusing convenience. You are not alone in your point of view, but I profoundly disagree and I think you are missing some important opportunities for simplifying and clarifying your RTL. If you restrict yourself only to signals, you are in effect laying-out every register in the design by hand. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 117964
On Sat, 14 Apr 2007 18:12:33 GMT, dalai lamah <antonio12358@hotmail.com> wrote: >If you try my example with the post-translated or the post-PAR model >generated by Xilinx tools, you will get the same result by putting the >increment operation before or after the if statement: > >[...] > elsif CLK='1' and CLK'event then > CNT := CNT+1; > if CNT(0)='0' then > O <= '1'; > end if; > end if; >[...] > >Works the same as: > >[...] > elsif CLK='1' and CLK'event then > if CNT(0)='0' then > O <= '1'; > end if; > CNT := CNT+1; > end if; >[...] This is simply untrue. They give completely different results. At least, it was untrue when I tried it using ISE 8.2i-SP2 (I haven't got around to upgrading to version 9 yet). In both cases ISE gave me exactly the result I would expect. Please double-check that you haven't done something strange. In particular, please check that your test stimulus does not release reset too close to an active clock edge. The counter and flip-flop devices need some recovery time after reset is released before they will respond reliably to a clock, but in a behavioural RTL simulation that recovery time is zero. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 117965
Jonathan Bromley wrote: > This is simply untrue. They give completely different results. Yes. Quartus and ISE both give different results for the cases cited. The "count last" case puts the counter in front of the registers: http://home.comcast.net/~mike_treseler/cnt_last.pdf The "count first" case puts the counter in the middle: http://home.comcast.net/~mike_treseler/cnt_first.pdf -- Mike TreselerArticle: 117966
Daniel S. wrote:
> IMO, variables for synthesis are a mostly unnecessary and potentially
> confusing convenience.
I use them all the time. As a practical aid to clear code ;-)
Here is a simple process which increments/decrements a count. Much
simpler with a variable.
process (Clk)
variable delta: integer range -1 to +1;
begin
if rising_edge(Clk) then
delta := 0;
if Write then
.....;
delta := delta+1;
end if;
if Read then
.....;
delta := delta-1;
end if;
Count <= Count + delta;
end if;
end process;
--
Tim
Article: 117967Nico Coesel wrote: > Are you sure you want to use that compiler? I wanted to give it a try for use writing quick-and-dirty test programs. It's probably fine for that. EricArticle: 117968
Symon wrote: > Google is your friend. > http://www.asm.ro/fpga/ Thanks! Google definitely is my friend, but somehow I didn't spot that one in the search results.Article: 117969
Hi Niel, Can you send across the example on power PC ,right now I am just trying to verify to see if this works.Really appreciate your help. Best Regards, -Anirudh On Apr 2, 3:45 pm, prasad.anir...@gmail.com wrote: > Hello, > > I would really appreciate if you could give me some insight on the > following > > -Can you guide me to a link/example which runs thru the process of > dynamic reconfiguration on Virtex2/4 step by step.I read and > understood the paper you guys pointed to. > > http://www.itee.uq.edu.au/~listarch/partial-reconfig/archive/2006/04/... > > I have also read the documentation on the Xilinx website(userguide > etc).I would like to see > an example implementation(could be trivial example).Else if you guys > could give me some suggestions on a trivial example for me to test and > see that partial dynamic reconfig actually works using the ICAP. > > -Also,from the paper I would assume that the patial bitstreams would > be generated using the FPGA editor from Xilinx.Now assuming I want to > have a set of bit streams loaded on to the Internal memory buffer of > the microblaze,How do I do that i.e how do I store the bit streams on > the microblaze(internal memory).I am using an ML310 board. > > Thanks!Article: 117970
Jonathan Bromley wrote: > On Sat, 14 Apr 2007 14:20:21 -0400, "Daniel S." > <digitalmastrmind_no_spam@hotmail.com> wrote: > > [...] >> IMO, variables for synthesis are a mostly unnecessary and potentially >> confusing convenience. > > You are not alone in your point of view, but I profoundly > disagree and I think you are missing some important > opportunities for simplifying and clarifying your RTL. > If you restrict yourself only to signals, you are in > effect laying-out every register in the design by hand. Explicitly laying down as many of the registers from an RTL design as possible is a nearly universally accepted design practice even if it does not yield the shortest/cleanest/simplest code. It also cuts down on the number of nameless nets in the output. What sort and how much of this code simplification are we talking about? For the stuff I can think of, it simply boils down to splitting the combinational and register parts... this can indeed account for a fair number of extra lines (four lines to implement a counter instead of two) but is otherwise trivial.Article: 117971
I would like to make a dual-port RAM inside my FPGA... I am using a Spartan 3 1000K gate model... I know it takes a pretty good number of macrocells to do this but I don't quite know enough on the low level of the architecture of a macrocell to understand what the limitations are. If possible I would like to have about 60KB of memory, in the form of 30K x 16. Thanks for your time.. SteveArticle: 117972
Aha. I did the first thing you're supposed to do when you have a question like this-- Look at the datasheet (duh!). It appears that there is more than enough block RAM inside the chip for what I would like to do. Steve Steve Battazzo wrote: > I would like to make a dual-port RAM inside my FPGA... > I am using a Spartan 3 1000K gate model... > I know it takes a pretty good number of macrocells to do this but I > don't quite know enough on the low level of the architecture of a > macrocell to understand what the limitations are. > If possible I would like to have about 60KB of memory, in the form of > 30K x 16. > > Thanks for your time.. > > SteveArticle: 117973
Steve Battazzo wrote: > I would like to make a dual-port RAM inside my FPGA... > I am using a Spartan 3 1000K gate model... > I know it takes a pretty good number of macrocells to do this but I > don't quite know enough on the low level of the architecture of a > macrocell to understand what the limitations are. > If possible I would like to have about 60KB of memory, in the form of > 30K x 16. Look at the product guides for the Spartan 3(E)... http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3_fpgas/overview.htm#s3table http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3e_fpgas/overview.htm#s3eTable With the XC3S1000, you get 432kbits of Block RAM (384kbits usable in x16 configuration) and 120kbits of distributed RAM. To achieve 30Kx16, you need at least 480kbits - this practically means consuming the whole FPGA as a single RAM with nearly no room left for other functionality, assuming the extra logic needed to manage the distributed memory still fits. More likely than not, you will need to step up - the XC3S1200E would be the smallest S3 FPGA that could definitely fit this RAM with some room to spare. Since large distributed memories have significant logic footprint (muxes, control signal fan-out, etc.) combined with either long access latencies (input + output pipelining) or slow performance (large non-pipelined muxes and decoders), you will have to look at the XC3S1500 or XC3S1600E if you need your memory to be fast and low-latency: these are the two smallest S3 devices that can implement your RAM entirely within Block RAMs.Article: 117974
On Apr 14, 1:23 pm, "Pedro" <pete.dud...@comcast.net> wrote: > Hello > > Has anyone figured out how to program and configure from the Platform Flash on the ML506. I have spent a lot of quality time with the ML505/ML506 Getting Started Tutorial (ug348.pdf) without luck. > > There is a dip switch (SW3), the Impact settings and a pair of XCF32P flashes. > > I just want to configure from one of the flashes on power up. > > If anyone can tell me the exact settings that make the flashes usable I would be very grateful. > > Pete I am using ML505 and I configure the fpga from PROM in Parallel mode. SW3 Setting is following 1 Off 2 Off 3 Off 4 On 5 Off 6 Off 7 Off 8 Off ML505 Evaluation Platform User Guide (ug347) Explains the DIP settings required for different modes of configuration. -Sovan.
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