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Threads Starting Jul 1999

17107: 99/07/01: Anurag: FPGAs v/s DSPs in Cell phones
    17109: 99/06/30: Ray Andraka: Re: FPGAs v/s DSPs in Cell phones
    17116: 99/07/01: Mark Woods: Re: FPGAs v/s DSPs in Cell phones
17114: 99/07/01: Philip Freidin: New tools for FPGA design
17117: 99/07/01: Steven Derrien: Heat disspa
    17119: 99/07/01: Ray Andraka: Re: Heat disspa
    17121: 99/07/01: Olaf: Re: Heat disspa
17118: 99/07/01: Karim LIMAM: Altera 10K prices
    17128: 99/07/01: bob elkind: Re: Altera 10K prices
    17154: 99/07/05: lewis chen: Re: Altera 10K prices
        17208: 99/07/09: Karim LIMAM: Re: Altera 10K prices
17122: 99/07/01: Radosalw Gasiorek: 82XX INTEL
17127: 99/07/01: Martin Maurer: ABL-Problem (XILINX CPLD)
    17137: 99/07/02: Benedikt Huber: Re: ABL-Problem (XILINX CPLD)
17131: 99/07/01: Joseph H Allen: neuron logic
    17144: 99/07/02: Wade D. Peterson: Re: neuron logic
17146: 99/07/03: Roland Paterson-Jones: Q: Floating point on fpga?
    17148: 99/07/03: Jan Gray: Re: Floating point on fpga, and serial FP adders
        17165: 99/07/06: Trevor Landon: Re: Floating point on fpga, Counters?
            17166: 99/07/06: Rickman: Re: Floating point on fpga, Counters?
            17170: 99/07/06: Ray Andraka: Re: Floating point on fpga, Counters?
                17177: 99/07/07: Trevor Landon: Re: Floating point on fpga, Counters?
                    17183: 99/07/07: Peter Alfke: Re: Floating point on fpga, Counters?
                    17359: 99/07/22: Scott Hauck: Re: Floating point on fpga, Counters?
            17188: 99/07/07: <ldoolitt@recycle>: Re: Floating point on fpga, Counters?
                17189: 99/07/07: Ray Andraka: Re: Floating point on fpga, Counters?
    17156: 99/07/05: muzo: Re: Q: Floating point on fpga?
17147: 99/07/03: <ronak@hclt.com>: Using Block SelectRAM+ in Virtex
    17152: 99/07/05: Le mer Michel: Re: Using Block SelectRAM+ in Virtex
        17167: 99/07/06: Paulo Dutra: Re: Using Block SelectRAM+ in Virtex
17153: 99/07/05: Andreas Koch: Virtex: Excessive PAR run-times without user-feedback?
    17158: 99/07/06: Le mer Michel: Re: Virtex: Excessive PAR run-times without user-feedback?
    17195: 99/07/08: <help@for.you>: Re: Virtex: Excessive PAR run-times without user-feedback?
17157: 99/07/05: David Heller: A better way to access this newsgroup
    17163: 99/07/06: Steve Nordhauser: Re: A better way to access this newsgroup
17159: 99/07/06: <lingleq@my-deja.com>: Xilink FPGA
    17161: 99/07/06: Ilia Oussorov: Re: Xilink FPGA
    17162: 99/07/06: Ray Andraka: Re: Xilink FPGA
17160: 99/07/06: <csoolan@dso.org.sg>: Benchmark circuits - in VHDL for FPGA
    17206: 99/07/08: Wade D. Peterson: Re: Benchmark circuits - in VHDL for FPGA
        17210: 99/07/09: Alasdair MacLean: Re: Benchmark circuits - in VHDL for FPGA
        17229: 99/07/12: Herman Schmit: Re: Benchmark circuits - in VHDL for FPGA
17164: 99/07/06: Victor Levandovsky: Need informations (articles, on-line) about fast adders and multipliers
    17169: 99/07/06: Ray Andraka: Re: Need informations (articles, on-line) about fast adders and multipliers
17173: 99/07/07: shaw: Can i use verilog write testbench in altera?
17174: 99/07/07: Hermann Winkler: Tristate Register in Xilinx 4000XLA IO block
    17182: 99/07/07: Brian Philofsky: Re: Tristate Register in Xilinx 4000XLA IO block
    17194: 99/07/07: Phil Hays: Re: Tristate Register in Xilinx 4000XLA IO block
17175: 99/07/07: mel: Programming Xilinx without Foundation
    17184: 99/07/07: Brian Philofsky: Re: Programming Xilinx without Foundation
        17199: 99/07/08: mel: Re: Programming Xilinx without Foundation
    17198: 99/07/08: Le mer Michel: Re: Programming Xilinx without Foundation
        17200: 99/07/08: mel: Re: Programming Xilinx without Foundation
17181: 99/07/07: Brian Boorman: Re: ENJOY MY AMATEUR WEB SITE.
17185: 99/07/07: Jan Gray: Alto in an FPGA (was CPU's directly executing HLL's)
    17186: 99/07/07: Paul Wallich: Re: Alto in an FPGA (was CPU's directly executing HLL's)
        17253: 99/07/14: Donald Gillies: Re: Alto in an FPGA (was CPU's directly executing HLL's)
            17255: 99/07/14: Dave Curbow: Re: Alto in an FPGA (was CPU's directly executing HLL's)
                17258: 99/07/15: Bruce Hoult: Re: Alto in an FPGA (was CPU's directly executing HLL's)
                    17274: 99/07/15: Zalman Stern: Re: Alto in an FPGA (was CPU's directly executing HLL's)
                17262: 99/07/15: Huge: Re: Alto in an FPGA (was CPU's directly executing HLL's)
            17257: 99/07/15: Bruce Hoult: Re: Alto in an FPGA (was CPU's directly executing HLL's)
17187: 99/07/07: Jo Van Langendonck: PCI interface
    17191: 99/07/07: Austin Franklin: Re: PCI interface
        17207: 99/07/08: Jim McManus: Re: PCI interface
            17216: 99/07/09: Austin Franklin: Re: PCI interface
                17222: 99/07/10: Jim McManus: Re: PCI interface
                    17226: 99/07/12: Austin Franklin: Re: PCI interface
                    17242: 99/07/14: Rickman: Re: PCI interface
                        17276: 99/07/15: Jim McManus: Re: PCI interface
                            17278: 99/07/15: Rickman: Re: PCI interface
            17228: 99/07/12: Bob Bauman: Re: PCI interface
                17277: 99/07/15: Jim McManus: Re: PCI interface
    17197: 99/07/08: Rickman: Re: PCI interface
17201: 99/07/08: Jan Vermaete: IEEE1394 core
17204: 99/07/08: Jorge Guajardo: CHES Conference Preliminary Program
17205: 99/07/08: Abraham Roth: fpga 10k50 and up prototype with a/d d/a
    17286: 99/07/17: Mark Grindell: Re: fpga 10k50 and up prototype with a/d d/a
        17287: 99/07/17: Ray Andraka: Re: fpga 10k50 and up prototype with a/d d/a
            17341: 99/07/21: Ray Andraka: Re: fpga 10k50 and up prototype with a/d d/a
            17347: 99/07/22: Mark Grindell: Re: fpga 10k50 and up prototype with a/d d/a
17209: 99/07/09: Utku Ozcan: how to choose only a set of pins
    17211: 99/07/09: Jamie Sanderson: Re: how to choose only a set of pins
        17213: 99/07/09: Utku Ozcan: Re: how to choose only a set of pins
            17214: 99/07/09: Brian Boorman: Re: how to choose only a set of pins
                17217: 99/07/09: Utku Ozcan: Re: how to choose only a set of pins
            17215: 99/07/09: Brian Philofsky: Re: how to choose only a set of pins
    17224: 99/07/12: Le mer Michel: Re: how to choose only a set of pins
17212: 99/07/09: Lasse Langwadt Christensen: Re: how to get money surfing the net...
17219: 99/07/09: Margaret Dailey: Designers wanted
17220: 99/07/10: <johnsimpson@postmaster.co.uk>: MayanSports Sportsbook offers NASCAR & Golf betting
17221: 99/07/09: Alvin E. Toda: IEEE P1532
17223: 99/07/11: Mike DeLaney: FPGA Eng(s) interested in an excellent opportunity
17225: 99/07/12: Sandra Dominikus: Xilinx On-Chip-Oscillator
    17251: 99/07/15: Ken Yasui: Re: Xilinx On-Chip-Oscillator
17227: 99/07/12: Herman Schmit: CFP: FPGA 2000
17230: 99/07/12: Jamil Khatib: Memory cores
17231: 99/07/12: <ecla@world.std.com>: Boston, MA: Senior ASIC Designer
17233: 99/07/13: Philemon John Chose: Why can't output flops be pulled into the IOB's when a module is floorplanned?
    17234: 99/07/13: Winefred Washington: Re: Why can't output flops be pulled into the IOB's when a module is floorplanned?
17235: 99/07/13: Jamil Khatib: OpenIP Call for contribution
17236: 99/07/13: Luis Yanes: Digital modulator? Synthesisable Sin(x) funct.
    17284: 99/07/16: Rickman: Re: Digital modulator? Synthesisable Sin(x) funct.
        17446: 99/07/28: Luis Yanes: Re: Digital modulator? Synthesisable Sin(x) funct.
    17285: 99/07/17: Ray Andraka: Re: Digital modulator? Synthesisable Sin(x) funct.
        17447: 99/07/28: Luis Yanes: Re: Digital modulator? Synthesisable Sin(x) funct.
            17449: 99/07/28: Ray Andraka: Re: Digital modulator? Synthesisable Sin(x) funct.
                17464: 99/07/29: Luis Yanes: Re: Digital modulator? Synthesisable Sin(x) funct.
                    17488: 99/07/31: Ray Andraka: Re: Digital modulator? Synthesisable Sin(x) funct.
                        17494: 99/08/02: Luis Yanes: Re: Digital modulator? Synthesisable Sin(x) funct.
                17495: 99/08/02: Luis Yanes: Re: Digital modulator? Synthesisable Sin(x) funct.
                    17506: 99/08/03: Ray Andraka: Re: Digital modulator? Synthesisable Sin(x) funct.
17237: 99/07/13: Don Husby: Dongle problems.
    17238: 99/07/13: Ray Andraka: Re: Dongle problems.
    17243: 99/07/14: Rickman: Re: Dongle problems.
        17248: 99/07/14: Ray Andraka: Re: Dongle problems.
            17259: 99/07/15: Rickman: Re: Dongle problems.
                17261: 99/07/15: Ray Andraka: Re: Dongle problems.
            17265: 99/07/15: Martin Guibert: Re: Dongle problems.
                17269: 99/07/15: Ray Andraka: Re: Dongle problems.
                17272: 99/07/15: bob elkind: Re: Dongle problems.
                    17279: 99/07/15: Rickman: Re: Dongle problems.
    17247: 99/07/14: Stuart Clubb: Re: Dongle problems.
        17249: 99/07/14: Ray Andraka: Re: Dongle problems.
            17268: 99/07/15: Stuart Clubb: Re: Dongle problems.
                17270: 99/07/15: Ray Andraka: Re: Dongle problems.
                    17280: 99/07/15: Rickman: Re: Dongle problems.
    17342: 99/07/21: EKC: Re: Dongle problems.
        17343: 99/07/21: Steven K. Knapp: Re: Dongle problems.
17240: 99/07/14: Asher C. Martin: MULTIPLE PIN ASSIGNMENTS QUESTION (ALTERA MAX+PLUS II)
    17246: 99/07/14: Andy Peters: Re: MULTIPLE PIN ASSIGNMENTS QUESTION (ALTERA MAX+PLUS II)
        17254: 99/07/15: Carlhermann Schlehaus: Re: MULTIPLE PIN ASSIGNMENTS QUESTION (ALTERA MAX+PLUS II)
            17273: 99/07/15: Ray Andraka: Re: MULTIPLE PIN ASSIGNMENTS QUESTION (ALTERA MAX+PLUS II)
    17275: 99/07/15: Asher C. Martin: SOLUTION: MULTIPLE PIN ASSIGNMENTS QUESTION (ALTERA MAX+PLUS II)
17241: 99/07/14: Robert Morse: ISA PnP core
    17250: 99/07/14: Ray Andraka: Re: ISA PnP core
        17260: 99/07/15: Robert Morse: Re: ISA PnP core
            17271: 99/07/15: Ray Andraka: Re: ISA PnP core
17244: 99/07/14: Ingo Purnhagen: Mixed Design Problem (FPGA Express/ACTEL)
    17281: 99/07/15: Michael Ayton: Re: Mixed Design Problem (FPGA Express/ACTEL)
17245: 99/07/14: <yorams70@my-deja.com>: Virtual CPU of SUMMIT design
    17266: 99/07/15: <dlsnell@my-deja.com>: Re: Virtual CPU of SUMMIT design
17252: 99/07/15: Michael Barr: Embedded Systems Resources
17256: 99/07/15: NPK: Easy money !!! and it's REAL
    17263: 99/07/15: martin lytz: Re: Easy money !!! and it's REAL
17264: 99/07/15: In2Home User: I was wondering if anyone could help..
17267: 99/07/15: Yonatan Mittlefehldt: Beginner in need of help
    17283: 99/07/16: Steven K. Knapp: Re: Beginner in need of help
17282: 99/07/16: Frank A. Vorstenbosch: Components for sale (London, UK)
17288: 99/07/17: Brad Taylor: Chemical FPGAs
    17348: 99/07/22: Mark Grindell: Re: Chemical FPGAs
17289: 99/07/19: bill morris: Frequency Multiplier in XC4000
17290: 99/07/19: bill morris: Frequency multiplier in XC4000
    17293: 99/07/19: Earthlink News: Re: Frequency multiplier in XC4000
        17296: 99/07/19: Ray Andraka: Re: Frequency multiplier in XC4000
        17310: 99/07/20: Earthlink News: Re: Frequency multiplier in XC4000
            17313: 99/07/20: Peter Alfke: Re: Frequency multiplier in XC4000
    17294: 99/07/19: Peter Alfke: Re: Frequency multiplier in XC4000
        17325: 99/07/21: David Decker: Re: Frequency multiplier in XC4000
17291: 99/07/19: bill morris: Frequency multiplier in XC4000
    17301: 99/07/19: Peter Alfke: Re: Frequency multiplier in XC4000
    17395: 99/07/24: Tom Bishop: Re: Frequency multiplier in XC4000
17292: 99/07/19: <chipfactory@hotmail.com>: License sharing for synopsys/cadence/modeltech
    17297: 99/07/19: Jay Lessert: Re: License sharing for synopsys/cadence/modeltech
        17298: 99/07/19: David Rogoff: Re: License sharing for synopsys/cadence/modeltech
            17299: 99/07/19: R. Mark Gogolewski: Re: License sharing for synopsys/cadence/modeltech
                17303: 99/07/19: Wade D. Peterson: Re: License sharing for synopsys/cadence/modeltech
                    17306: 99/07/20: R. Mark Gogolewski: Re: License sharing for synopsys/cadence/modeltech
            17316: 99/07/20: Jay Lessert: Re: License sharing for synopsys/cadence/modeltech
    17300: 99/07/19: Tim Davis: Re: License sharing for synopsys/cadence/modeltech
    17302: 99/07/19: Andy Peters: Re: License sharing for synopsys/cadence/modeltech
    17308: 99/07/20: Steve Bird: Re: License sharing for synopsys/cadence/modeltech
    17351: 99/07/22: Peter Beukelman: Re: License sharing for synopsys/cadence/modeltech
        17360: 99/07/22: Brian Philofsky: Re: License sharing for synopsys/cadence/modeltech
17295: 99/07/19: <rajesh52@hotmail.com>: Verilog FAQ
17304: 99/07/19: Nicholas Brown: Xilinx/Synopsys License Problem
    17305: 99/07/19: Ray Andraka: Re: Xilinx/Synopsys License Problem
        17309: 99/07/20: Nicholas Brown: Re: Xilinx/Synopsys License Problem
    17312: 99/07/20: Craig Slorach: Re: Xilinx/Synopsys License Problem
    17315: 99/07/20: Mark Condit: Re: Xilinx/Synopsys License Problem
        17329: 99/07/21: Rickman: Re: Xilinx/Synopsys License Problem
    17338: 99/07/21: Dave Vanden Bout: Re: Xilinx/Synopsys License Problem
        17511: 99/08/03: Nicholas Brown: Re: Xilinx/Synopsys License Problem
            17513: 99/08/04: Arve Ronning: Re: Xilinx/Synopsys License Problem
17307: 99/07/20: Anthony Ellis - LogicWorks: What happened to Esprimo?
17311: 99/07/20: Blake Nelson: "Contract Outsourcing?!"
    17396: 99/07/23: Margaret Dailey: Re: "Contract Outsourcing?!"
17314: 99/07/20: Mark Kinsley: Solaris vs. NT
    17317: 99/07/20: Jake Janovetz: Re: Solaris vs. NT
        17319: 99/07/21: Mark Kinsley: Re: Solaris vs. NT
            17321: 99/07/20: Edward L. Hepler: Re: Solaris vs. NT
            17323: 99/07/21: Jerry Zdenek: Re: Solaris vs. NT
                17331: 99/07/21: Wen-King Su: Re: Solaris vs. NT
                    17346: 99/07/22: rk: Re: Solaris vs. NT
                        17352: 99/07/22: Wen-King Su: Re: Solaris vs. NT
            17332: 99/07/21: Don Husby: Re: Solaris vs. NT
                17340: 99/07/22: Zoltan Kocsi: Re: Solaris vs. NT
                    17349: 99/07/22: Jamie Lokier: Re: Solaris vs. NT
                    17350: 99/07/22: Ray Andraka: Re: Solaris vs. NT
                    17354: 99/07/22: Don Husby: Re: Solaris vs. NT
                        17357: 99/07/22: Paul Baxter: Re: Solaris vs. NT
                            17358: 99/07/22: Paul Baxter: Re: Solaris vs. NT
                        17362: 99/07/22: Andy Peters: Re: Solaris vs. NT
                        17368: 99/07/22: Jake Janovetz: Re: Solaris vs. NT
                        17370: 99/07/22: rk: Re: Solaris vs. NT
                        17390: 99/07/23: Austin Franklin: Re: Solaris vs. NT
                        17399: 99/07/24: Zoltan Kocsi: Re: Solaris vs. NT
                            17401: 99/07/24: rk: Re: Solaris vs. NT
                17367: 99/07/22: Jake Janovetz: Re: Solaris vs. NT
    17318: 99/07/20: B. Joshua Rosen: Re: Solaris vs. NT, use Linux
    17320: 99/07/20: rk: Re: Solaris vs. NT
    17322: 99/07/21: Zoltan Kocsi: Re: Solaris vs. NT
    17327: 99/07/21: Thomas Reinemann: Re: Solaris vs. NT
    17420: 99/07/26: Alex Makris: Re: Solaris vs. NT
        17544: 99/08/09: Thomas Reinemann: Re: Solaris vs. NT
    17640: 99/08/17: <ar679deja@my-deja.com>: Quartus Problems
17324: 99/07/21: Klaus Falser: Xilinx CPLD ChipViewer
17326: 99/07/21: <david_hinds@my-deja.com>: Synplify - Optimizing Out A Bus
    17335: 99/07/21: Lewis, Mike: Re: Synplify - Optimizing Out A Bus
17328: 99/07/21: <david_hinds@my-deja.com>: Synplify - Optimizing out a Bus.
17330: 99/07/21: Gareth Jones: Free Filter Synthesis Software
17333: 99/07/21: Gordon Brebner: Special Issue on Reconfigurable Systems
17334: 99/07/21: David Norton: C language to programmable logic
    17336: 99/07/21: Tim Callahan: Re: C language to programmable logic
    17337: 99/07/21: Ray Andraka: Re: C language to programmable logic
17339: 99/07/21: Nicholas Brown: Xilinx Foundation Beginner Question
    17344: 99/07/22: Philip Freidin: Re: Xilinx Foundation Beginner Question
    17345: 99/07/21: Dave Vanden Bout: Re: Xilinx Foundation Beginner Question
    17361: 99/07/22: Nicholas Brown: Re: Question Resolved, Thanks
17353: 99/07/22: Eduardo Augusto Bezerra: Looking for proceedings
    17355: 99/07/22: Scott Hauck: Re: Looking for proceedings
    17382: 99/07/23: Steven K. Knapp: Re: Looking for proceedings
    17413: 99/07/26: Kiran Bond: Re: Looking for proceedings
17356: 99/07/22: Friedhelm Rünz: Workstation with Synopsys license server
    17364: 99/07/22: ken ryan: Re: Workstation with Synopsys license server
    17383: 99/07/23: Paul Hands: Re: Workstation with Synopsys license server
17363: 99/07/22: John Cooley: The User Written "DAC Trip Report" Is At http://www.DeepChip.com
17365: 99/07/22: <anl@completebbs.com>: tiles-rus 8405
    17366: 99/07/22: Ray Andraka: Re: tiles-rus 8405
17369: 99/07/22: Adam J. Elbirt: Embedded RAM in Virtex Chips
17371: 99/07/22: Khan Kibria: PCI Controller chip Announcement
17372: 99/07/22: James G: Low Cost latched I/O
    17378: 99/07/23: Brian Boorman: Re: Low Cost latched I/O
    17380: 99/07/23: Mikeandmax: Re: Low Cost latched I/O
    17381: 99/07/23: Steven K. Knapp: Re: Low Cost latched I/O
17373: 99/07/23: Drizzt: Hardware FFT Design?
    17391: 99/07/23: Jonathan M Hill: Re: Hardware FFT Design?
        17393: 99/07/23: Ray Andraka: Re: Hardware FFT Design?
17374: 99/07/23: chris pitzel: Re: PCI Controller chip Announcement
17375: 99/07/23: <herry@poste.isima.fr>: Using Xilinx Foundation & Mentor Graphics
    17411: 99/07/26: Le mer Michel: Re: Using Xilinx Foundation & Mentor Graphics
17376: 99/07/23: Steven Derrien: Designing a Virtex board
    17377: 99/07/23: Ray Andraka: Re: Designing a Virtex board
    17412: 99/07/26: Le mer Michel: Re: Designing a Virtex board
        17564: 99/08/10: Magnus Homann: Re: Designing a Virtex board
17379: 99/07/23: Wade D. Peterson: System-on-Chip and its effect on VMEbus / uC Bus Products
17384: 99/07/23: Asher C. Martin: CAN WE HAVE SIGNALS WITH MULTIPLE SOURCES IN VHDL?
    17387: 99/07/23: Ray Andraka: Re: CAN WE HAVE SIGNALS WITH MULTIPLE SOURCES IN VHDL?
    17388: 99/07/23: Alvin E. Toda: Re: CAN WE HAVE SIGNALS WITH MULTIPLE SOURCES IN VHDL?
17385: 99/07/23: Steve: What does a SpartanXL look like prior to configuration?
    17386: 99/07/23: Ray Andraka: Re: What does a SpartanXL look like prior to configuration?
17389: 99/07/23: <pbfrtl@NO.MAIL>: EVERYTHING YOU WANT !!!! 7306
    17392: 99/07/24: Tony: Re: EVERYTHING YOU WANT !!!! 7306
        17394: 99/07/24: Mike Albaugh: Re: EVERYTHING YOU WANT !!!! 7306
17397: 99/07/23: Margaret Dailey: Mixed Signal Design Engineers Wanted
17398: 99/07/24: ant: How to get Foundation synthesis result(gate level layout)?
    17408: 99/07/24: Nick Hartl: Re: How to get Foundation synthesis result(gate level layout)?
17400: 99/07/24: <mriely@cstp.umkc.edu>: GET FRESHLY GROUND COFFEE ONLINE 50923
17402: 99/07/24: <86gfd@dscg8.com>: 18+ ONLY 27425
17403: 99/07/24: <75if@dsdfs.com>: XXX 6579
17404: 99/07/24: <975d8@dfdfws.com>: Sexy Stuff 59821
17405: 99/07/24: Wade D. Peterson: Microcomputer buses for use inside FPGA/ASIC devices?
    17406: 99/07/25: Jan Gray: Re: Microcomputer buses for use inside FPGA/ASIC devices?
        17407: 99/07/25: Jan Gray: Re: Microcomputer buses for use inside FPGA/ASIC devices?
        17409: 99/07/25: Wade D. Peterson: Re: Microcomputer buses for use inside FPGA/ASIC devices?
            17424: 99/07/27: Jan Gray: Re: Microcomputer buses for use inside FPGA/ASIC devices?
                17429: 99/07/27: Wade D. Peterson: Re: Microcomputer buses for use inside FPGA/ASIC devices?
    17418: 99/07/26: Wade D. Peterson: Re: Microcomputer buses for use inside FPGA/ASIC devices?
    17435: 99/07/27: Wade D. Peterson: Re: Microcomputer buses for use inside FPGA/ASIC devices?
        17454: 99/07/29: Hans: Re: Microcomputer buses for use inside FPGA/ASIC devices?
            17474: 99/07/30: Wade D. Peterson: Re: Microcomputer buses for use inside FPGA/ASIC devices?
                17481: 99/07/30: Hans: Re: Microcomputer buses for use inside FPGA/ASIC devices?
                    17482: 99/07/30: Wade D. Peterson: Re: Microcomputer buses for use inside FPGA/ASIC devices?
    17436: 99/07/28: Anthony Ellis - LogicWorks: Re: Microcomputer buses for use inside FPGA/ASIC devices?
        17440: 99/07/28: Wade D. Peterson: Re: Microcomputer buses for use inside FPGA/ASIC devices?
            17453: 99/07/29: Anthony Ellis - LogicWorks: Re: Microcomputer buses for use inside FPGA/ASIC devices?
                17459: 99/07/29: Wade D. Peterson: Re: Microcomputer buses for use inside FPGA/ASIC devices?
17410: 99/07/25: Robert Pasenko: Thesis Work
17414: 99/07/26: ELYUMA: Interesting Links
17415: 99/07/26: Courtenay Johnson: Xilinx Virtex Block Select RAM, is is reg or flow thru output
    17417: 99/07/26: Paul Butler: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
        17419: 99/07/26: Peter Alfke: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
            17422: 99/07/26: Paul Butler: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
        17448: 99/07/28: James Yeh: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
            17450: 99/07/28: Peter Alfke: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
                17457: 99/07/29: Brian Drummond: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
                    17461: 99/07/29: Ed Mcgettigan: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
                    17462: 99/07/29: Peter Alfke: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
            17475: 99/07/30: Paul Butler: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
                17478: 99/07/30: Lewis, Mike: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
                    17487: 99/07/30: Ray Andraka: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
    17421: 99/07/26: Ed Mcgettigan: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
17416: 99/07/26: ProSyst: Epld to Fpga design.
    17467: 99/07/29: Andy Peters: Re: Epld to Fpga design.
17423: 99/07/26: Zhibin Dai: XACT vs. Workview office
    17427: 99/07/27: Ray Andraka: Re: XACT vs. Workview office
        17433: 99/07/27: rodger: Re: XACT vs. Workview office
17425: 99/07/27: Eirik Esp: NRZ Deserializing in Virtex
    17426: 99/07/27: Allan Herriman: Re: NRZ Deserializing in Virtex
    17428: 99/07/27: Ray Andraka: Re: NRZ Deserializing in Virtex
    17431: 99/07/27: Peter Alfke: Re: NRZ Deserializing in Virtex
        17432: 99/07/27: muzo: Re: NRZ Deserializing in Virtex
            17452: 99/07/29: Allan Herriman: Re: NRZ Deserializing in Virtex
    17469: 99/07/30: Hal Murray: Re: NRZ Deserializing in Virtex
    17596: 99/08/12: Darrin Nagy: Re: NRZ Deserializing in Virtex
17430: 99/07/27: Nicholas Brown: Xilinx Fountation 1.5 Question
17434: 99/07/27: Tom McLaughlin: APEX initial values
    17458: 99/07/29: Stuart Clubb: Re: APEX initial values
17437: 99/07/28: Nicolas Matringe: Problem with Max+PlusII / Flex10k
    17438: 99/07/28: Alex Makris: Re: Problem with Max+PlusII / Flex10k
    17439: 99/07/28: Peter Sřrensen: Re: Problem with Max+PlusII / Flex10k
    17441: 99/07/28: Rickman: Re: Problem with Max+PlusII / Flex10k
        17444: 99/07/28: Nicolas Matringe: Re: Problem with Max+PlusII / Flex10k
            17468: 99/07/30: Carlhermann Schlehaus: Re: Problem with Max+PlusII / Flex10k
    17442: 99/07/28: <mench@mench.com>: Re: Problem with Max+PlusII / Flex10k
    17443: 99/07/28: Renaud Pacalet: Re: Problem with Max+PlusII / Flex10k
    17534: 99/08/06: Rob Anderson: Re: Problem with Max+PlusII / Flex10k
17445: 99/07/28: Jim Frenzel: Partial Reconfiguration?
    17451: 99/07/28: Rickman: Re: Partial Reconfiguration?
    17456: 99/07/29: Ray Andraka: Re: Partial Reconfiguration?
        17465: 99/07/30: Tom Kean: Re: Partial Reconfiguration?
            17466: 99/07/29: Ray Andraka: Re: Partial Reconfiguration?
    17460: 99/07/29: Brian Dipert: Re: Partial Reconfiguration?
    17509: 99/08/03: <M.Vasilko@computer.org>: Re: Partial Reconfiguration?
17455: 99/07/29: Gareth Jones: FilterExpress Filter Synthesis Software
17463: 99/07/29: Jeff Streznetcky: Xilinx timing constraints question
17470: 99/07/30: Mark Grindell: Semi-deterministic behaviour in FPGA's
    17471: 99/07/30: Rickman: Re: Semi-deterministic behaviour in FPGA's
        17472: 99/07/30: Ray Andraka: Re: Semi-deterministic behaviour in FPGA's
            17473: 99/07/30: Ray Andraka: Re: Semi-deterministic behaviour in FPGA's
        17476: 99/07/30: David Kessner: Re: Semi-deterministic behaviour in FPGA's
            17484: 99/07/31: Hal Murray: Re: Semi-deterministic behaviour in FPGA's
                17491: 99/07/31: Marc Delvaux: Re: Semi-deterministic behaviour in FPGA's
                    17493: 99/07/31: Ray Andraka: Re: Semi-deterministic behaviour in FPGA's
                        17497: 99/08/02: Bob Pearson: Re: Semi-deterministic behaviour in FPGA's
                        17498: 99/08/02: Marc Delvaux: Re: Semi-deterministic behaviour in FPGA's
                            17499: 99/08/02: Ray Andraka: Re: Semi-deterministic behaviour in FPGA's
        17477: 99/07/30: Jonah Thomas: Re: Semi-deterministic behaviour in FPGA's
        17479: 99/07/30: <ldoolitt@recycle>: Re: Semi-deterministic behaviour in FPGA's
        17490: 99/07/31: Lasse Langwadt Christensen: Re: Semi-deterministic behaviour in FPGA's
    17489: 99/07/31: Allan Herriman: Re: Semi-deterministic behaviour in FPGA's
17480: 99/07/30: Bret Eddinger: nuneric_std package in Foundation 1.5
    17486: 99/07/30: Andy Peters: Re: nuneric_std package in Foundation 1.5
        17500: 99/08/02: David Dye: Re: nuneric_std package in Foundation 1.5
            17510: 99/08/03: Andy Peters: Re: nuneric_std package in Foundation 1.5
17483: 99/07/30: <rajesh52@hotmail.com>: Verilog FAQ.
17485: 99/07/30: B. Joshua Rosen: Xilinx FPGA Editor works under wine
17492: 99/07/31: Marketer: Aesthetic software


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