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Threads Starting Jan 2000

19601: 00/01/03: John Larkin: Actel repair assistance
19607: 00/01/04: MK Yap: Decoding RSPC (Reed Solomon Product Code)
    19614: 00/01/04: John Janusson: Re: Decoding RSPC (Reed Solomon Product Code)
        19638: 00/01/05: Christof Paar: Re: Decoding RSPC (Reed Solomon Product Code)
    19724: 00/01/10: <jhirbawi@yahoo.com>: Re: Decoding RSPC (Reed Solomon Product Code)
        19726: 00/01/10: MK Yap: Re: Decoding RSPC (Reed Solomon Product Code)
            19751: 00/01/11: MK Yap: Re: Decoding RSPC (Reed Solomon Product Code)
19617: 00/01/04: IC-BOOK: Bad ALTERA data
19621: 00/01/04: Steve Sweet: Altera, Lattice, Xilinx
19622: 00/01/04: Eileen Haldeman: synthesis opportunities
    19632: 00/01/04: Randy Yates: Re: synthesis opportunities
19623: 00/01/05: <erika_uk@my-deja.com>: GSR pulse
19625: 00/01/05: <elynum@my-deja.com>: timing diagrams
    19738: 00/01/10: Srinivasan Venkataramanan: Re: timing diagrams
    19892: 00/01/17: Kang Liat Chuan: Re: timing diagrams
        19895: 00/01/16: Ray Andraka: Re: timing diagrams
19626: 00/01/05: <erika_uk@my-deja.com>: CLKDLL
19627: 00/01/05: <erika_uk@my-deja.com>: STARTUP
    19634: 00/01/04: Ray Andraka: Re: STARTUP
19628: 00/01/05: <erika_uk@my-deja.com>: STARTUP
19631: 00/01/05: #YEO WEE KWONG#: REad function query
19636: 00/01/05: Stef Winteraeken: Lattice Vantis GDX
19639: 00/01/05: <jlamontagne@my-deja.com>: FPGA and SW Engineering opportunities in CT
19644: 00/01/06: Victor the Cleaner: Desperate Xilinx problem SOLVED!
    19650: 00/01/06: Ron Wierckx: Re: Desperate Xilinx problem SOLVED!
    19663: 00/01/07: Stewart, Nial [HAL02:HH00:EXCH]: Re: Desperate Xilinx problem SOLVED!
    19955: 00/01/20: Turboproc: Re: Desperate Xilinx problem SOLVED!
        19988: 00/01/21: Victor the Cleaner: Re: Desperate Xilinx problem SOLVED!
19645: 00/01/06: Marc Battyani: BGA sockets and Virtex
    19646: 00/01/06: Olaf: Re: BGA sockets and Virtex
    19649: 00/01/06: Peter A Dudley: Re: BGA sockets and Virtex
        19783: 00/01/12: Whygee: Re: BGA sockets and Virtex
        19784: 00/01/12: Whygee: Re: BGA sockets and Virtex
19651: 00/01/06: Matt Billenstein: Virtex 5V io
    19653: 00/01/06: Ed Mcgettigan: Re: Virtex 5V io
        19658: 00/01/07: Rick Filipkiewicz: Re: Virtex 5V io
19652: 00/01/07: Matt Billenstein: Virtex real time debugging
    19659: 00/01/07: Etienne Racine: Re: Virtex real time debugging
    19687: 00/01/08: Ray Andraka: Re: Virtex real time debugging
19654: 00/01/07: Rickman: Lucent Orca designs
    19655: 00/01/07: Ray Andraka: Re: Lucent Orca designs
    19656: 00/01/07: Dave Storrar: Re: Lucent Orca designs
    19758: 00/01/11: Bob Wagner: Re: Lucent Orca designs
        19763: 00/01/11: <elynum@my-deja.com>: Re: Lucent Orca designs
            19767: 00/01/11: Don Husby: Re: Lucent Orca designs
        20117: 00/01/27: Rickman: Re: Lucent Orca designs
            20181: 00/01/30: pmueller: Re: Lucent Orca designs
                20196: 00/01/31: Don Husby: Re: Lucent Orca designs
                    20202: 00/01/31: pmueller: Re: Lucent Orca designs
19660: 00/01/07: Kai Troester: Disable clockbuffer for only a single flip-flop
    19662: 00/01/07: Ray Andraka: Re: Disable clockbuffer for only a single flip-flop
    19664: 00/01/07: rk: Re: Disable clockbuffer for only a single flip-flop
    19665: 00/01/07: Bob Perlman: Re: Disable clockbuffer for only a single flip-flop
    19668: 00/01/07: Dave Decker: Re: Disable clockbuffer for only a single flip-flop
    19679: 00/01/07: <eml@riverside-machines.com.NOSPAM>: Re: Disable clockbuffer for only a single flip-flop
        19683: 00/01/07: Peter Alfke: Re: Disable clockbuffer for only a single flip-flop
        19684: 00/01/08: Ray Andraka: Re: Disable clockbuffer for only a single flip-flop
            19685: 00/01/07: Andy Peters: Re: Disable clockbuffer for only a single flip-flop
                19686: 00/01/08: Ray Andraka: Re: Disable clockbuffer for only a single flip-flop
                19695: 00/01/08: <eml@riverside-machines.com.NOSPAM>: Re: Disable clockbuffer for only a single flip-flop
            19694: 00/01/08: <eml@riverside-machines.com.NOSPAM>: Re: Disable clockbuffer for only a single flip-flop
                19700: 00/01/09: Ray Andraka: Re: Disable clockbuffer for only a single flip-flop
                19701: 00/01/09: Ray Andraka: Re: Disable clockbuffer for only a single flip-flop
                    19716: 00/01/09: Joel Kolstad: Re: Disable clockbuffer for only a single flip-flop
                        19723: 00/01/09: Ray Andraka: Re: Disable clockbuffer for only a single flip-flop
                19702: 00/01/09: Ray Andraka: Re: Disable clockbuffer for only a single flip-flop
                19703: 00/01/09: Ray Andraka: Re: Disable clockbuffer for only a single flip-flop
                19704: 00/01/09: Ray Andraka: Re: Disable clockbuffer for only a single flip-flop
                19705: 00/01/09: Ray Andraka: Re: Disable clockbuffer for only a single flip-flop
                19706: 00/01/09: Ray Andraka: Re: Disable clockbuffer for only a single flip-flop
                19707: 00/01/09: Ray Andraka: Re: Disable clockbuffer for only a single flip-flop
                19708: 00/01/09: Ray Andraka: Re: Disable clockbuffer for only a single flip-flop
                19709: 00/01/09: Ray Andraka: Re: Disable clockbuffer for only a single flip-flop
                19710: 00/01/09: Ray Andraka: Re: Disable clockbuffer for only a single flip-flop
19667: 00/01/07: <WalterChristler@rufgfofsj.org>: .,.IF AOL WAS A CAR..,,
19669: 00/01/07: Tim: Earn Extra Cash
19673: 00/01/07: Xanatos: Newbie question on CPU's
    19680: 00/01/07: Robert Sefton: Re: Newbie question on CPU's
    19681: 00/01/07: Michael Ellis: Re: Newbie question on CPU's
    19696: 00/01/08: Steve Casselman: Re: Newbie question on CPU's
        19698: 00/01/08: Joel Kolstad: Re: Newbie question on CPU's
19674: 00/01/07: trlcoms(news): orca3t125 clock problems
    19760: 00/01/11: Bob Wagner: Re: orca3t125 clock problems
19675: 00/01/07: Rick Filipkiewicz: Xilinx Spartan2
    19691: 00/01/08: Allan Herriman: Re: Xilinx Spartan2
    19725: 00/01/10: Nicolas Matringe: Re: Xilinx Spartan2
    19798: 00/01/12: Mike Butts: Re: Xilinx Spartan2
        19803: 00/01/12: Ray Andraka: Re: Xilinx Spartan2
            19845: 00/01/13: Mike Butts: Re: Xilinx Spartan2
    19801: 00/01/12: Greg Neff: Re: Xilinx Spartan2
        19807: 00/01/12: Peter Alfke: Re: Xilinx Spartan2
            19834: 00/01/13: Greg Neff: Re: Xilinx Spartan2
                19857: 00/01/14: Allan Herriman: Re: Xilinx Spartan2
                    19867: 00/01/14: Greg Neff: Re: Xilinx Spartan2
                        19870: 00/01/14: Peter Alfke: Re: Xilinx Spartan2
                            19871: 00/01/14: Greg Neff: Re: Xilinx Spartan2
                                19873: 00/01/14: Peter Alfke: Re: Xilinx Spartan2
                                    19910: 00/01/17: Greg Neff: Re: Xilinx Spartan2
                                        19914: 00/01/17: Tom Burgess: Re: Xilinx Spartan2
    19875: 00/01/15: dmac: Re: Xilinx Spartan2
19676: 00/01/07: Christoph Cronimund: Versatile digital filter for signal processing systems
    19729: 00/01/10: Damjan Lampret: Re: Versatile digital filter for signal processing systems
19688: 00/01/08: George: XC4000 Configuration Bitstream structure
    19734: 00/01/10: Andy Peters: Re: XC4000 Configuration Bitstream structure
        19735: 00/01/10: Ray Andraka: Re: XC4000 Configuration Bitstream structure
        19737: 00/01/10: Nicholas C. Weaver: Re: XC4000 Configuration Bitstream structure
    19761: 00/01/11: George: Re: XC4000 Configuration Bitstream structure
        19764: 00/01/11: Ray Andraka: Re: XC4000 Configuration Bitstream structure
            19765: 00/01/11: Nicholas C. Weaver: Re: XC4000 Configuration Bitstream structure
19692: 00/01/08: Kresten Nørgaard: 100 MHz counters
    19693: 00/01/08: Ray Andraka: Re: 100 MHz counters
    19733: 00/01/10: Andy Peters: Re: 100 MHz counters
        19768: 00/01/11: Kresten Nørgaard: Re: 100 MHz counters
            19770: 00/01/11: Andy Peters: Re: 100 MHz counters
            19775: 00/01/11: Ray Andraka: Re: 100 MHz counters
                19799: 00/01/12: Peter Alfke: Re: 100 MHz counters
                    19804: 00/01/12: Ray Andraka: Re: 100 MHz counters
19697: 00/01/08: Berni Joss: Optimizing VHDL for Altera
    19699: 00/01/08: Ray Andraka: Re: Optimizing VHDL for Altera
    19711: 00/01/09: Ray Andraka: Re: Optimizing VHDL for Altera
        19715: 00/01/09: Berni Joss: Re: Optimizing VHDL for Altera
            19718: 00/01/09: <mcjy@my-deja.com>: Re: Optimizing VHDL for Altera
            19722: 00/01/09: Ray Andraka: Re: Optimizing VHDL for Altera
                19740: 00/01/10: Berni Joss: Re: Optimizing VHDL for Altera
                    19743: 00/01/11: Ray Andraka: Re: Optimizing VHDL for Altera
19712: 00/01/09: Sergey Vlasov: How to upgrade Foundation 1.4 to build Spartan-XL code?
    19721: 00/01/09: Ray Andraka: Re: How to upgrade Foundation 1.4 to build Spartan-XL code?
19717: 00/01/09: Jess: Make thousands$$$$ form only $6!!!!!!!!!!!!!!!!!
    19720: 00/01/09: John Larkin: Re: Make thousands$$$$ form only $6!!!!!!!!!!!!!!!!!
19719: 00/01/09: Robert Larkin: On chip Oscillator
    19739: 00/01/10: Peter Alfke: Re: On chip Oscillator
19727: 00/01/10: Jamil Khaib: PCI/USB project started
    19773: 00/01/11: <mcjy@my-deja.com>: Re: PCI/USB project started
        19786: 00/01/12: Damjan Lampret: Re: PCI/USB project started
        19787: 00/01/12: Jamil Khaib: Re: PCI/USB project started
19728: 00/01/10: Kai Troester: THANX: Disable clockbuffer for only a single flip-flop
    19744: 00/01/11: Ray Andraka: Re: THANX: Disable clockbuffer for only a single flip-flop
19730: 00/01/10: Damjan Lampret: fastest 32 bit RISC
    19820: 00/01/13: Ulf Samuelsson: Re: fastest 32 bit RISC
        19826: 00/01/13: Ray Andraka: Re: fastest 32 bit RISC
            19839: 00/01/14: Jan Gray: Re: fastest 32 bit RISC
                19846: 00/01/14: Damjan Lampret: Re: fastest 32 bit RISC
                    19850: 00/01/14: Jan Gray: Re: fastest 32 bit RISC
                        19858: 00/01/14: Simon Bacon: Re: fastest 32 bit RISC
            19852: 00/01/14: Ulf Samuelsson: Re: fastest 32 bit RISC
                19862: 00/01/14: Ray Andraka: Re: fastest 32 bit RISC
        19828: 00/01/13: Damjan Lampret: Re: fastest 32 bit RISC
            19853: 00/01/14: Ulf Samuelsson: Re: fastest 32 bit RISC
                19859: 00/01/14: Damjan Lampret: Re: fastest 32 bit RISC
19732: 00/01/10: Matt Billenstein: Virtex Temperature Sensing diode pins DXP, DXN
    19736: 00/01/10: Ray Andraka: Re: Virtex Temperature Sensing diode pins DXP, DXN
        19741: 00/01/10: Peter Alfke: Re: Virtex Temperature Sensing diode pins DXP, DXN
        19776: 00/01/11: Mike Roberts: Re: Virtex Temperature Sensing diode pins DXP, DXN
    19742: 00/01/11: Bob Doyle: Re: Virtex Temperature Sensing diode pins DXP, DXN
    19746: 00/01/11: Allan Herriman: Re: Virtex Temperature Sensing diode pins DXP, DXN
        19932: 00/01/19: Allan Herriman: Re: Virtex Temperature Sensing diode pins DXP, DXN
19745: 00/01/11: Jamil Khaib: HW resources increased
    19749: 00/01/11: Pat: Re: HW resources increased
        19756: 00/01/11: Paul Butler: Re: HW resources increased
            19759: 00/01/11: Peter da Silva: Re: HW resources increased
                19762: 00/01/11: Jonathan Bromley: Re: HW resources increased
                    19772: 00/01/11: Peter da Silva: Re: HW resources increased
                19771: 00/01/11: Paul Butler: Re: HW resources increased
                    19794: 00/01/12: Peter da Silva: Re: HW resources increased
                        19805: 00/01/12: Marinos J. Yannikos: Re: HW resources increased
                            19808: 00/01/12: Jeffrey S. Dutky: Re: HW resources increased
                            19823: 00/01/13: Sander Vesik: Re: HW resources increased
                                19824: 00/01/13: Marinos J. Yannikos: Re: HW resources increased
                                    19829: 00/01/13: Sander Vesik: Re: HW resources increased
                                    19840: 00/01/14: Jeffrey S. Dutky: Re: HW resources increased
                            19860: 00/01/14: Peter da Silva: Re: HW resources increased
                            19886: 00/01/16: Greg Alexander: Re: HW resources increased
    19766: 00/01/11: Ian Kemmish: Re: HW resources increased
        19788: 00/01/12: Ketil Z Malde: Re: HW resources increased
            19796: 00/01/12: Larry Elmore: Re: HW resources increased
                19814: 00/01/13: Ketil Z Malde: Re: HW resources increased
        19887: 00/01/16: Greg Alexander: Re: HW resources increased
            19891: 00/01/16: Chris Morgan: Re: HW resources increased
                19893: 00/01/16: Greg Alexander: Re: HW resources increased
                    19898: 00/01/16: Chris Morgan: Re: HW resources increased
            19915: 00/01/18: Peter Seebach: Re: HW resources increased
    19782: 00/01/12: Michael Vincze: Re: HW resources increased
    19876: 00/01/15: <andy_ash@my-deja.com>: Re: HW resources increased
19747: 00/01/11: Simon D. Wibowo: SDRAM controller ?
    19757: 00/01/11: Ray Andraka: Re: SDRAM controller ?
    19810: 00/01/12: Joel Kolstad: Re: SDRAM controller ?
    19811: 00/01/12: Joel Kolstad: Re: SDRAM controller ?
19748: 00/01/11: Peter Lang: PCI Bus Problems with Burst Transfers
    19818: 00/01/13: Peter Lang: Re: PCI Bus Problems with Burst Transfers
        19822: 00/01/13: Thomas Rathgen: Re: PCI Bus Problems with Burst Transfers
            19837: 00/01/13: John L. Smith: Re: PCI Bus Problems with Burst Transfers
                19851: 00/01/14: Peter Lang: Re: PCI Bus Problems with Burst Transfers
    19821: 00/01/13: Joseph H Allen: Re: PCI Bus Problems with Burst Transfers
    19830: 00/01/13: Dan Rymarz: Re: PCI Bus Problems with Burst Transfers
    19865: 00/01/14: Austin Franklin: Re: PCI Bus Problems with Burst Transfers
19752: 00/01/11: Damjan Lampret: RISC in FPGA?
19753: 00/01/11: Nicolas Matringe: Altera Flex10K bitstream compatibility ?
    19774: 00/01/11: Ying C.: Re: Altera Flex10K bitstream compatibility ?
        19809: 00/01/13: Steve Rencontre: Re: Altera Flex10K bitstream compatibility ?
19755: 00/01/11: Graham Seaman: CPLD interconnect?
19769: 00/01/11: Tom Leacock: Configuring virtex devices
19779: 00/01/11: <blaster52>: freemoneyfast
19780: 00/01/11: <eric>: freemoneyfast
19781: 00/01/11: Phil Hays: Assignment of pins for thousand+ pin packages
    19785: 00/01/12: Andreas Doering: Re: Assignment of pins for thousand+ pin packages
    19789: 00/01/12: Paul Walker: Re: Assignment of pins for thousand+ pin packages
        20001: 00/01/21: Phil Hays: Re: Assignment of pins for thousand+ pin packages
    19806: 00/01/12: Jonathan Bromley: Re: Assignment of pins for thousand+ pin packages
19790: 00/01/12: <himalayas@my-deja.com>: Help for EDIF format !
    19792: 00/01/12: Philip Freidin: Re: Help for EDIF format !
        19793: 00/01/12: <himalayas@my-deja.com>: Re: Help for EDIF format !
            19816: 00/01/13: Philip Freidin: Re: Help for EDIF format !
19791: 00/01/12: DG_1 (@remove.this): Re: hardware related questions
19795: 00/01/12: myself: hc11 core & fpga or cpld
    19925: 00/01/18: Steven K. Knapp: Re: hc11 core & fpga or cpld
        19926: 00/01/18: Richard Erlacher: Re: hc11 core & fpga or cpld
19797: 00/01/12: Michael Eisenring: Benchmarks
    19896: 00/01/16: Number Cruncher: Re: Benchmarks
        19923: 00/01/18: Brian Dipert: Re: Benchmarks
19802: 00/01/12: <elynum@my-deja.com>: Lattice
    19832: 00/01/13: Andy Peters: Re: Lattice
        19835: 00/01/13: <elynum@my-deja.com>: Re: Lattice
            19861: 00/01/14: David Frith: Re: Lattice
                19864: 00/01/14: <elynum@my-deja.com>: Re: Lattice
                19879: 00/01/15: Kresten Nørgaard: Re: Lattice
19812: 00/01/13: Richard Lamoreaux: Reliability of programming SRAM FPGAs
    19813: 00/01/13: Ray Andraka: Re: Reliability of programming SRAM FPGAs
        19815: 00/01/13: Nicolas Matringe: Re: Reliability of programming SRAM FPGAs
    19836: 00/01/13: Dan Rymarz: Re: Reliability of programming SRAM FPGAs
    19838: 00/01/13: Greg Neff: Re: Reliability of programming SRAM FPGAs
        19841: 00/01/13: Peter Alfke: Re: Reliability of programming SRAM FPGAs
        19854: 00/01/14: rk: Re: Reliability of programming SRAM FPGAs
            19855: 00/01/14: rk: Re: Reliability of programming SRAM FPGAs
19819: 00/01/13: Jamil Khaib: call for comments
19827: 00/01/13: <elynum@my-deja.com>: fpga board
    19848: 00/01/14: Ray Andraka: Re: fpga board
19833: 00/01/13: Philippe Robert: DDC Core for FPGA
    19849: 00/01/14: Ray Andraka: Re: DDC Core for FPGA
    20223: 00/02/01: <philippe_molson@my-deja.com>: Re: DDC Core for FPGA
19843: 00/01/13: Jon Huppenthal: FPGA Design Jobs in Colorado
19847: 00/01/14: Juergen Marquardt: 8259 interrupt controller functionality
19863: 00/01/14: <dave_admin@my-deja.com>: Please help : Translogic's .ini files
    19916: 00/01/18: <dave_admin@my-deja.com>: Please help : Translogic's .ini files
        19997: 00/01/21: <dave_admin@my-deja.com>: Re: Please help : Translogic's .ini files
19866: 00/01/14: <UsenetCentralControl_comp@nacxtttol.gov>: ..,,.. Warning To @Home Users - Your ISP Is SPAM CENTRAL ...,,
19868: 00/01/14: Ram Meenakshisundaram: XACT where is it??
    19872: 00/01/15: <rmeenaks@olf.com>: XACT & XC4000E - Need help
        19878: 00/01/15: Ray Andraka: Re: XACT & XC4000E - Need help
            19885: 00/01/16: <rmeenaks@olf.com>: Re: XACT & XC4000E - Need help
                19889: 00/01/16: Ray Andraka: Re: XACT & XC4000E - Need help
19869: 00/01/15: hengchi: fuzzy logic in FPGas
19874: 00/01/15: J.R.: EARN MONEY EASILY-READ THIS!!
19880: 00/01/15: David Barcelo: FPGA + ethernet
    19881: 00/01/15: Dave Vanden Bout: Re: FPGA + ethernet
        19900: 00/01/17: #YEO WEE KWONG#: Further to board
            19901: 00/01/16: Dave Vanden Bout: Re: Further to board
            19902: 00/01/16: Dave Vanden Bout: Re: Further to board
    19882: 00/01/15: Dave Vanden Bout: Re: FPGA + ethernet
19883: 00/01/15: <arsh@x-stream.se>: Partly reprogrammable FPGAs
    19884: 00/01/16: Nicholas C. Weaver: Re: Partly reprogrammable FPGAs
        19888: 00/01/16: Ray Andraka: Re: Partly reprogrammable FPGAs
    19906: 00/01/17: Jamil Khaib: Re: Partly reprogrammable FPGAs
        19924: 00/01/18: Brian Dipert: Re: Partly reprogrammable FPGAs
            20212: 00/02/01: LuisGomezMelis: RE:INTERNET CONSULTANT NEEDED
19890: 00/01/16: Domagoj Babic: Random Number Generator
    19894: 00/01/16: Ray Andraka: Re: Random Number Generator
        19897: 00/01/16: John Larkin: Re: Random Number Generator
            19899: 00/01/17: Ray Andraka: Re: Random Number Generator
                19903: 00/01/17: Andreas Doering: Re: Random Number Generator
            19917: 00/01/18: Dave Decker: Re: Random Number Generator
                19922: 00/01/18: Ray Andraka: Re: Random Number Generator
                    19928: 00/01/18: John Larkin: Re: Random Number Generator
                        19931: 00/01/19: Hal Murray: Re: Random Number Generator
                            19933: 00/01/19: Ray Andraka: Re: Random Number Generator
                            19941: 00/01/19: John Larkin: Re: Random Number Generator
                                19951: 00/01/20: Hal Murray: Re: Random Number Generator
                                    19967: 00/01/20: John Larkin: Re: Random Number Generator
                                        19991: 00/01/21: Hal Murray: Re: Random Number Generator
        19907: 00/01/17: Etienne Racine: Re: Random Number Generator
            19909: 00/01/17: Ray Andraka: Re: Random Number Generator
19904: 00/01/17: Jamil Khaib: Design flow needed
19905: 00/01/17: <mehmeto@my-deja.com>: Viterbi decoder in FPGA
    19908: 00/01/17: Ray Andraka: Re: Viterbi decoder in FPGA
        19929: 00/01/18: Stuart Clubb: Re: Viterbi decoder in FPGA
    19913: 00/01/17: muzo: Re: Viterbi decoder in FPGA
    19927: 00/01/18: Jerry English: Re: Viterbi decoder in FPGA
    20088: 00/01/26: Thomas Burchard: Re: Viterbi decoder in FPGA
19911: 00/01/17: <rajesh52@hotmail.com>: Verilog FAQ
19912: 00/01/17: Dan Kuechle: Wanted: Xilinx XCV400-6FG676C for prototype
19918: 00/01/18: MK Yap: Which VHDL synthesizer/compiler?
19919: 00/01/18: Jason Lohn: CFP: The Second NASA/DoD Workshop on Evolvable Hardware
19920: 00/01/18: Jamil Khaib: Cores interfaces
    19930: 00/01/19: Jonas Thor: Re: Cores interfaces
19921: 00/01/18: Rick Filipkiewicz: Virtex to ASIC conversion
    19940: 00/01/19: Stuart Clubb: Re: Virtex to ASIC conversion
19934: 00/01/19: Kevin Lyons: Anyone interested?
19935: 00/01/19: Matt Billenstein: Virtex Fine Pitch BGA pcb layout
    20002: 00/01/22: Keith R. Williams: Re: Virtex Fine Pitch BGA pcb layout
        20004: 00/01/22: <bob_42690@my-deja.com>: Re: Virtex Fine Pitch BGA pcb layout
            20005: 00/01/22: John Larkin: Re: Virtex Fine Pitch BGA pcb layout
                20007: 00/01/23: Keith R. Williams: Re: Virtex Fine Pitch BGA pcb layout
                    20009: 00/01/22: John Larkin: Re: Virtex Fine Pitch BGA pcb layout
                        20012: 00/01/23: Keith R. Williams: Re: Virtex Fine Pitch BGA pcb layout
                            20015: 00/01/23: John Larkin: Re: Virtex Fine Pitch BGA pcb layout
                                20036: 00/01/25: Keith R. Williams: Re: Virtex Fine Pitch BGA pcb layout
                                    20040: 00/01/25: Bob Perlman: Re: Virtex Fine Pitch BGA pcb layout
                                        20041: 00/01/25: Keith R. Williams: Re: Virtex Fine Pitch BGA pcb layout
                                        20055: 00/01/25: <eml@riverside-machines.com.NOSPAM>: Re: Virtex Fine Pitch BGA pcb layout
                                        20061: 00/01/25: John Larkin: Re: Virtex Fine Pitch BGA pcb layout
                                            20069: 00/01/26: <eml@riverside-machines.com.NOSPAM>: Re: Virtex Fine Pitch BGA pcb layout
                                                20072: 00/01/26: John Larkin: Re: Virtex Fine Pitch BGA pcb layout
                                            20081: 00/01/26: Bob Perlman: Re: Virtex Fine Pitch BGA pcb layout
                                                20091: 00/01/27: Joseph H Allen: Re: Virtex Fine Pitch BGA pcb layout
                        20033: 00/01/24: Joseph H Allen: Re: Virtex Fine Pitch BGA pcb layout
        20094: 00/01/27: Matt Billenstein: Re: Virtex Fine Pitch BGA pcb layout
            20364: 00/02/07: Greg Neff: Re: Virtex Fine Pitch BGA pcb layout
    20034: 00/01/24: Joseph H Allen: Re: Virtex Fine Pitch BGA pcb layout
19936: 00/01/19: Oh Sheau Pyng: Need advice on timing problem
    19937: 00/01/19: Ray Andraka: Re: Need advice on timing problem
        19950: 00/01/20: Oh Sheau Pyng: Need advice on timing problem
19938: 00/01/19: Pierre VERNEL: configurable 8-16 bits processor IP
19939: 00/01/19: Paul Walker: Patent licences for circuits in FPGA
    19942: 00/01/19: Austin Franklin: Re: Patent licenses for circuits in FPGA
        19957: 00/01/20: Graham Seaman: Re: Patent licenses for circuits in FPGA
    19972: 00/01/21: Mark Summerfield: Re: Patent licences for circuits in FPGA
19943: 00/01/19: Austin Franklin: looping FIFO?
    19944: 00/01/19: Ray Andraka: Re: looping FIFO?
        19947: 00/01/20: Austin Franklin: Re: looping FIFO?
            19949: 00/01/20: Hal Murray: Re: looping FIFO?
                19964: 00/01/20: Paul Urbanus: Re: looping FIFO?
            19973: 00/01/21: Mark Summerfield: Re: looping FIFO?
                19974: 00/01/20: Austin Franklin: Re: looping FIFO?
                19975: 00/01/20: Peter Alfke: Re: looping FIFO?
        19960: 00/01/20: rk: Re: looping FIFO?
    19946: 00/01/20: Allan Herriman: Re: looping FIFO?
        19948: 00/01/20: Austin Franklin: Re: looping FIFO?
    19954: 00/01/20: Anthony Ellis - LogicWorks: Re: looping FIFO?
    20169: 00/01/30: Douglas W. Olsen: Re: looping FIFO?
        20173: 00/01/30: Ray Andraka: Re: looping FIFO?
19945: 00/01/20: giuseppe giachella: Altera Quartus vs Xilinx Place and Route tools (help needed)
    19962: 00/01/20: Xanatos: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
    19995: 00/01/21: Nikolay: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
        20087: 00/01/26: Nicholas C. Weaver: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
        20101: 00/01/27: Magnus Homann: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
            20111: 00/01/27: Ray Andraka: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
            20112: 00/01/27: Ray Andraka: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                20115: 00/01/27: Magnus Homann: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                    20116: 00/01/27: Nicholas C. Weaver: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                    20122: 00/01/27: Peter Alfke: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                        20131: 00/01/27: Ben Sanchez: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                            20132: 00/01/28: Peter Alfke: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                            20151: 00/01/28: Peter Alfke: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                                20152: 00/01/28: Ben Sanchez: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                    20128: 00/01/28: Ray Andraka: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                20129: 00/01/28: Allan Herriman: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                    20149: 00/01/28: Ray Andraka: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                        20176: 00/01/30: Allan Herriman: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                            20205: 00/01/31: Peter Alfke: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                                20209: 00/01/31: doug: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                                    20214: 00/02/01: Ray Andraka: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                        20188: 00/01/31: Allan Herriman: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                        20195: 00/01/31: Don Husby: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                            20199: 00/01/31: Ray Andraka: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                                20221: 00/02/01: Don Husby: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                                    21005: 00/03/02: Rickman: New name: DLLs, PLLs and videotape...
                                        21007: 00/03/02: Peter Alfke: Re: New name: DLLs, PLLs and videotape...
                                            21012: 00/03/02: muzo: Re: New name: DLLs, PLLs and videotape...
                                        21022: 00/03/03: Don Husby: Re: New name: DLLs, PLLs and videotape...
                                            21044: 00/03/03: Rickman: Re: New name: DLLs, PLLs and videotape...
                                                21047: 00/03/04: Jim Granville: Re: New name: DLLs, PLLs and videotape...
                                                21079: 00/03/06: Don Husby: Re: New name: DLLs, PLLs and videotape...
                                                    21082: 00/03/06: Peter Alfke: Re: New name: DLLs, PLLs and videotape...
                                                        21087: 00/03/06: Don Husby: Re: New name: DLLs, PLLs and videotape...
                                                            21111: 00/03/07: Peter Alfke: Re: New name: DLLs, PLLs and videotape...
                                                                21120: 00/03/07: Don Husby: Re: New name: DLLs, PLLs and videotape...
                            20228: 00/02/01: Anthony Ellis - LogicWorks: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
                                20911: 00/02/27: John: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
    20086: 00/01/26: Steve Dewey: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
    20089: 00/01/26: Ray Andraka: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
19952: 00/01/20: Ray Andraka: help: signal stuck at 'U' inside generate statement
    19987: 00/01/20: Bonio Lopez: Re: help: signal stuck at 'U' inside generate statement
        19994: 00/01/21: Ray Andraka: Re: help: signal stuck at 'U' inside generate statement
    19990: 00/01/21: <eml@riverside-machines.com.NOSPAM>: Re: help: signal stuck at 'U' inside generate statement
        19993: 00/01/21: Ray Andraka: Re: help: signal stuck at 'U' inside generate statement
19953: 00/01/20: Anthony Ellis - LogicWorks: WebFitter???
    19968: 00/01/20: John Larkin: Re: WebFitter???
    19998: 00/01/21: Stephanie Tapp: Re: WebFitter???
    20010: 00/01/23: Jamil Khaib: Re: WebFitter???
19956: 00/01/20: Steele Chen: which PLD support Hot-swap
    19959: 00/01/20: rk: Re: which PLD support Hot-swap
    19966: 00/01/20: Jim McManus: Re: which PLD support Hot-swap
19958: 00/01/20: Andreas Doering: Indexing functions
    19963: 00/01/20: Andreas Gieriet: Re: Indexing functions
    19971: 00/01/21: Mark Summerfield: Re: Indexing functions
        19989: 00/01/21: Phil Endecott: Re: Indexing functions
            20043: 00/01/25: Andreas Doering: Re: Indexing functions
        20018: 00/01/24: Nikolay: Re: Indexing functions
19961: 00/01/20: <jens_strauss@my-deja.com>: Correlator with VHDL
19965: 00/01/20: George: Xilinx vs. other FPGAs manufactrers
    19969: 00/01/20: Ray Andraka: Re: Xilinx vs. other FPGAs manufactrers
        19976: 00/01/21: dmac: Re: Xilinx vs. other FPGAs manufactrers
        19977: 00/01/20: peter dudley: Re: Xilinx vs. other FPGAs manufactrers
        19992: 00/01/21: Hal Murray: Re: Xilinx vs. other FPGAs manufactrers
            20022: 00/01/24: <rob_dickinson@my-deja.com>: Re: Xilinx vs. other FPGAs manufactrers
        20027: 00/01/24: Tyrone Thompson: Re: Xilinx vs. other FPGAs manufactrers
            20030: 00/01/24: Ray Andraka: Re: Xilinx vs. other FPGAs manufactrers
            20032: 00/01/24: Peter Alfke: Re: Xilinx vs. other FPGAs manufactrers
        20044: 00/01/25: Ben Sanchez: Re: Xilinx vs. other FPGAs manufactrers
19970: 00/01/20: Arrigo Benedetti: odd behavior of Virtex RAM Block model
    19978: 00/01/21: Ray Andraka: Re: odd behavior of Virtex RAM Block model
        20413: 00/02/09: <qwerty@scottfamily.cc>: Re: odd behavior of Virtex RAM Block model
            20422: 00/02/09: Arrigo Benedetti: Re: odd behavior of Virtex RAM Block model
19979: 00/01/21: Sherdyn: Biphase mark decoder
    19980: 00/01/21: Hal Murray: Re: Biphase mark decoder
    19982: 00/01/21: Kelly Hall: Re: Biphase mark decoder
        19983: 00/01/21: Sherdyn: Re: Biphase mark decoder
            19985: 00/01/21: Anthony Ellis - LogicWorks: Re: Biphase mark decoder
                19986: 00/01/21: Kelly Hall: Re: Biphase mark decoder
            20008: 00/01/23: Richard Erlacher: Re: Biphase mark decoder
                20013: 00/01/24: Sherdyn: Re: Biphase mark decoder
                    20014: 00/01/24: Peter Alfke: Re: Biphase mark decoder
    19984: 00/01/21: Anthony Ellis - LogicWorks: Re: Biphase mark decoder
19981: 00/01/20: Huesung Kim: [Q] Reconfigurable cache architecture
19996: 00/01/21: <erika_uk@my-deja.com>: timing simulation
19999: 00/01/22: <mu0lia0ni@my-deja.com>: Transmeta CM & Conf. Comp?
    20000: 00/01/22: Ray Andraka: Re: Transmeta CM & Conf. Comp?
    20003: 00/01/22: Tim Tyler: Re: Transmeta CM & Conf. Comp?
        20011: 00/01/23: Tim Callahan: Re: Transmeta CM & Conf. Comp?
20006: 00/01/23: Ing. Salvatore Di Fazio: Cypress programming information for old 370i devices.
20016: 00/01/24: Shawn D'Alimonte: Easy to program PLD
    20017: 00/01/24: Klaus Falser: Re: Easy to program PLD
        20050: 00/01/25: Shawn D'Alimonte: Re: Easy to program PLD
    20037: 00/01/24: Mike Roberts: Re: Easy to program PLD
20019: 00/01/24: Phil Endecott: Xilinx programming from a Linux PC
    20023: 00/01/24: Sigurd Urdahl: Re: Xilinx programming from a Linux PC
    20054: 00/01/25: rodger: Re: Xilinx programming from a Linux PC
        20057: 00/01/25: Larry Doolittle: Re: Xilinx programming from a Linux PC
            20059: 00/01/25: Steve Casselman: Re: Xilinx programming from a Linux PC
            20070: 00/01/26: <eml@riverside-machines.com.NOSPAM>: Re: Xilinx programming from a Linux PC
    20172: 00/01/29: B. Joshua Rosen: Re: Xilinx programming from a Linux PC
    20192: 00/01/31: Phil Endecott: Re: Xilinx programming from a Linux PC
20020: 00/01/24: Thomas Sitt: How to access standard sdram ?
    20024: 00/01/24: Mike Treseler: Re: How to access standard sdram ?
    20028: 00/01/24: Ray Andraka: Re: How to access standard sdram ?
        20038: 00/01/25: Free Spirit: Re: How to access standard sdram ?
            20045: 00/01/25: Rick Filipkiewicz: Re: How to access standard sdram ?
            20062: 00/01/25: Joel Kolstad: Re: How to access standard sdram ?
20021: 00/01/24: PYD: Polynomial calculation on FPGA ???
    20029: 00/01/24: Ray Andraka: Re: Polynomial calculation on FPGA ???
20025: 00/01/24: Tim Kippen: FPGA to manage serial DAQ?
    20031: 00/01/24: Ray Andraka: Re: FPGA to manage serial DAQ?
        20042: 00/01/25: Ulrich Stauss: Re: FPGA to manage serial DAQ?
20026: 00/01/24: Michael Barr: Embedded Glossary and Bibliography
20035: 00/01/24: funky jim: actel desktop uniinstall?
20039: 00/01/25: raja: global clock distribution
20046: 00/01/25: Peter Fenn: Atmel config PROMs
    20053: 00/01/25: Peter Alfke: Re: Atmel config PROMs
    20065: 00/01/26: <dulik@my-deja.com>: Re: Atmel config PROMs
        20067: 00/01/26: Rick Filipkiewicz: Re: Atmel config PROMs
            20145: 00/01/28: Werner Dreher: Re: Atmel config PROMs
20047: 00/01/25: Gunter =?iso-8859-1?Q?F=F6ttinger?=: Combination of FPGA and DSP
20048: 00/01/25: Steven Sanders: Xilinx Foundation: VHDL to symbol
    20049: 00/01/25: Tow, Shane [WWP:1X10:EXCH]: Re: Xilinx Foundation: VHDL to symbol
    20052: 00/01/25: Holger Kleinert: Re: Xilinx Foundation: VHDL to symbol
    20071: 00/01/26: Alex Sherstuk: Re: Xilinx Foundation: VHDL to symbol
20056: 00/01/25: <eml@riverside-machines.com.NOSPAM>: Anyone changed an NT disk serial number?
    20064: 00/01/26: Steve Bird: Re: Anyone changed an NT disk serial number?
        20068: 00/01/26: Jo Depreitere: Re: Anyone changed an NT disk serial number?
            20073: 00/01/26: Jerry English: Re: Anyone changed an NT disk serial number?
    20099: 00/01/27: Steve Bird: Re: Anyone changed an NT disk serial number?
    20103: 00/01/27: <eml@riverside-machines.com.NOSPAM>: Re: Anyone changed an NT disk serial number?
        20290: 00/02/04: Austin Franklin: Re: Anyone changed an NT disk serial number?
20058: 00/01/25: Chuck Carlson: xilinx foundation: map exceptions
20060: 00/01/25: John Schewel: CFP - Reconfigurable Technology
20063: 00/01/26: =?iso-8859-1?Q?J=E9r=E9mie?= WEBER: Pin to pin
    20092: 00/01/27: Philip Freidin: Re: Pin to pin
    20093: 00/01/27: Matt Billenstein: Re: Pin to pin
20066: 00/01/26: <dulik@my-deja.com>: Anyone has Synplify 5.1 eval ?
20074: 00/01/26: Don Golding: Has anyone created VHDL code to interface to a 68HC11 SPI port yet?
    20125: 00/01/27: Tyrone Thompson: Re: Has anyone created VHDL code to interface to a 68HC11 SPI port yet?
20075: 00/01/27: Pradeep Rao: Reed Solomon codes and Intelsat specs
20076: 00/01/26: giuseppe giachella: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20077: 00/01/26: George: EEPROM based FPGAs
    20078: 00/01/26: Ray Andraka: Re: EEPROM based FPGAs
    20083: 00/01/26: rk: Re: EEPROM based FPGAs
        20084: 00/01/26: rk: Re: EEPROM based FPGAs
    20197: 00/01/31: Steven K. Knapp: Re: EEPROM based FPGAs
20079: 00/01/26: <anoriaki@comp.ufscar.br>: FPGA's reconfigurable modes
20080: 00/01/26: Ray Andraka: GSR in HDL on instantiated flip-flop primitives
    20095: 00/01/26: Simon Bacon: Re: GSR in HDL on instantiated flip-flop primitives
        20108: 00/01/27: Ray Andraka: Re: GSR in HDL on instantiated flip-flop primitives
            20118: 00/01/27: Simon Bacon: Re: GSR in HDL on instantiated flip-flop primitives
                20126: 00/01/28: Ray Andraka: Re: GSR in HDL on instantiated flip-flop primitives
    20104: 00/01/27: <eml@riverside-machines.com.NOSPAM>: Re: GSR in HDL on instantiated flip-flop primitives
        20109: 00/01/27: Ray Andraka: Re: GSR in HDL on instantiated flip-flop primitives
20085: 00/01/26: Steve Dewey: What has happened to freecore.com ?
    20097: 00/01/27: Andreas Heiner: Re: What has happened to freecore.com ?
        20110: 00/01/27: Ray Andraka: Re: What has happened to freecore.com ?
    20119: 00/01/27: Stefan Ludwig: Re: What has happened to freecore.com ?
    20168: 00/01/29: Rune Baeverrud: Re: What has happened to freecore.com ?
20090: 00/01/27: raja: CARRY CHAIN CIRCUIT in ORCA 3T
    20120: 00/01/27: Rickman: Re: CARRY CHAIN CIRCUIT in ORCA 3T
    20121: 00/01/27: Rickman: Re: CARRY CHAIN CIRCUIT in ORCA 3T
20096: 00/01/26: Simon Bacon: Secondary Clock Distribution in Virtex
20098: 00/01/27: Holger Azenhofer: microcontroller in vhdl
    20100: 00/01/27: Nicolas Matringe: Re: microcontroller in vhdl
    20106: 00/01/27: Edwin Naroska: Re: microcontroller in vhdl
20102: 00/01/27: #XUE ZHONG#: Lattice isp & FPGA
    20189: 00/01/30: Steven K. Knapp: Re: Lattice isp & FPGA
    20232: 00/02/01: Number Cruncher: Re: Lattice isp & FPGA
20105: 00/01/27: Bonio Lopez: Why Sinplicity make combinatorial loops from latches ?
    20107: 00/01/27: Don Husby: Re: Why Sinplicity make combinatorial loops from latches ?
        20137: 00/01/28: Bonio Lopez: Re: Why Sinplicity make combinatorial loops from latches ?
    20187: 00/01/30: Steven K. Knapp: Re: Why Sinplicity make combinatorial loops from latches ?
20113: 00/01/27: JPC: displaying an internal node with Quartus simulation
20114: 00/01/27: <eda1000@my-deja.com>: licenses
    20139: 00/01/28: Keith Jasinski, Jr.: Re: licenses
20124: 00/01/27: Lee Cao: ADC to DSP... FIFO?
    20127: 00/01/27: Peter Alfke: Re: ADC to DSP... FIFO?
        20136: 00/01/28: russell shaw: Re: ADC to DSP... FIFO?
            20148: 00/01/28: Jerry Avins: Re: ADC to DSP... FIFO?
                20153: 00/01/29: russell shaw: Re: ADC to DSP... FIFO?
                    20155: 00/01/28: Peter Alfke: Re: ADC to DSP... FIFO?
                        20157: 00/01/28: Peter Alfke: Re: ADC to DSP... FIFO?
                        20163: 00/01/29: Rickman: Re: ADC to DSP... FIFO?
                            20164: 00/01/29: Rickman: Re: ADC to DSP... FIFO?
                                20165: 00/01/29: Rickman: Re: ADC to DSP... FIFO?
                            20167: 00/01/29: Ray Andraka: Re: ADC to DSP... FIFO?
                                20217: 00/02/01: rk: Re: ADC to DSP... FIFO?
                                    20352: 00/02/07: Paul Butler: Re: ADC to DSP... FIFO?
                                        20363: 00/02/07: Mike Treseler: Re: ADC to DSP... FIFO?
                                        20369: 00/02/07: Rickman: Re: ADC to DSP... FIFO?
                                            20371: 00/02/08: rk: Re: ADC to DSP... FIFO?
                                                20383: 00/02/08: Paul Butler: Re: ADC to DSP... FIFO?
                                                    20401: 00/02/08: rk: Re: ADC to DSP... FIFO?
                                                        20415: 00/02/09: Jerry Avins: Re: ADC to DSP... FIFO?
                                            20384: 00/02/08: Ray Andraka: Re: ADC to DSP... FIFO?
                                                20403: 00/02/09: Hal Murray: Re: ADC to DSP... FIFO?
                                                    20404: 00/02/08: rk: Re: ADC to DSP... FIFO?
                                            20385: 00/02/08: Paul Butler: Re: ADC to DSP... FIFO?
                                                20396: 00/02/08: Rickman: Re: ADC to DSP... FIFO?
                            20185: 00/01/31: russell shaw: Re: ADC to DSP... FIFO?
    20130: 00/01/28: Saddle: Re: ADC to DSP... FIFO?
    20138: 00/01/28: Keith Wootten: Re: ADC to DSP... FIFO?
        20147: 00/01/28: <csjacobs@my-deja.com>: Re: ADC to DSP... FIFO?
    20161: 00/01/29: Ken Krabacher: Re: ADC to DSP... FIFO?
20133: 00/01/28: K: LVPECL I/O interface
    20135: 00/01/28: Ben Sanchez: Re: LVPECL I/O interface
        20141: 00/01/28: Theron Hicks: Re: LVPECL I/O interface
            20162: 00/01/29: Keith R. Williams: Re: LVPECL I/O interface
        20142: 00/01/28: Theron Hicks: Re: LVPECL I/O interface
20134: 00/01/28: ¹Ú±¸¿ë: ARM core?
    20144: 00/01/28: Tim Tyler: Re: ARM core?
        20193: 00/01/31: Sprow: Re: ARM core?
    20178: 00/01/30: Mark Harvey: Re: ARM core?
20140: 00/01/28: Mike Horwath: Program Xilinx Through TI DSP Serial McBSP
    20177: 00/01/29: Joel Kolstad: Re: Program Xilinx Through TI DSP Serial McBSP
20143: 00/01/28: Rastislav Struharik: Spartan XL
    20156: 00/01/29: Holger Kleinert: Re: Spartan XL
20146: 00/01/28: Shawki Areibi: Xilinx vs Altera
    20175: 00/01/30: raja: Re: Xilinx vs Altera
    20180: 00/01/30: <danberquet@my-deja.com>: Re: Xilinx vs Altera
    20361: 00/02/07: John Janusson: Re: Xilinx vs Altera
        20433: 00/02/10: Mark Harvey: Re: Xilinx vs Altera
        23854: 00/07/12: Masaaki: Re: Xilinx vs Altera
20150: 00/01/28: <afarrahi@my-deja.com>: GLSVLSI-2000 Advance Registeration
20154: 00/01/28: Larry Doolittle: Spartan II availability and pricing
    20158: 00/01/29: Ray Andraka: Re: Spartan II availability and pricing
    20183: 00/01/30: Brian Dipert: Re: Spartan II availability and pricing
    20255: 00/02/02: Larry Doolittle: Re: Spartan II availability and pricing
        20392: 00/02/08: Larry Doolittle: Re: Spartan II availability and pricing
            20395: 00/02/08: Peter Alfke: Re: Spartan II availability and pricing
                20398: 00/02/08: Larry Doolittle: Re: Spartan II availability and pricing
                    20400: 00/02/08: Peter Alfke: Re: Spartan II availability and pricing
            20397: 00/02/08: Greg Neff: Re: Spartan II availability and pricing
                20399: 00/02/09: Larry Doolittle: Re: Spartan II availability and pricing
20159: 00/01/28: Madison: Testbenches
    20160: 00/01/29: Bob Perlman: Re: Testbenches
    20179: 00/01/30: Mark Harvey: Re: Testbenches
        21048: 00/03/04: William LenihanIii: Re: Testbenches
20166: 00/01/29: Anna Schmitt: picoJava & Xilinx
    20170: 00/01/29: Steve Casselman: Re: picoJava & Xilinx
20171: 00/01/29: Chuck Carlson: Can Foundation import Viewlogic?
    20174: 00/01/30: Ray Andraka: Re: Can Foundation import Viewlogic?
20182: 00/01/30: Dave Vanden Bout: Re: Which FPGA to learn with?
    20190: 00/01/30: Joel Kolstad: Re: Which FPGA to learn with?
        20194: 00/01/31: Dave Vanden Bout: Re: Which FPGA to learn with?
            20237: 00/02/01: Joel Kolstad: Re: Which FPGA to learn with?
                20245: 00/02/02: Dave Vanden Bout: Re: Which FPGA to learn with?
                20246: 00/02/02: Dave Vanden Bout: Re: Which FPGA to learn with?
        20200: 00/01/31: Ray Andraka: Re: Which FPGA to learn with?
20184: 00/01/30: Ralph Mason: Which FPGA to learn with?
    20222: 00/02/01: amigabill: Re: Which FPGA to learn with?
    20416: 00/02/09: <another_bbrekke@my-deja.com>: Using Xilinx Serial EEPROMs
20186: 00/01/30: B. Joshua Rosen: Announcement: Xilinx on Linux HowTo
    20191: 00/01/31: Erik de Castro Lopo: Re: Announcement: Xilinx on Linux HowTo
    20240: 00/02/02: <eml@riverside-machines.com.NOSPAM>: Re: Announcement: Xilinx on Linux HowTo
        20244: 00/02/02: Uwe Bonnes: Re: Announcement: Xilinx on Linux HowTo
        20263: 00/02/02: B. Joshua Rosen: Re: Announcement: Xilinx on Linux HowTo
20198: 00/01/31: Adrian Dunn: Actel proAsic availability, experiences?
20201: 00/01/31: Cecile Chicheportiche: Xilinx memory instantiation (VHDL, FPGA Express 3.3)
20203: 00/01/31: Steve Diferdinando: Virtex DLL inoperability
    20204: 00/01/31: Ed Mcgettigan: Re: Virtex DLL inoperability
    20206: 00/01/31: Ray Andraka: Re: Virtex DLL inoperability
    20253: 00/02/02: Winzker: Re: Virtex DLL inoperability
    20590: 00/02/15: david gilchrist: Re: Virtex DLL inoperability
        20593: 00/02/15: Simon Goble: Re: Virtex DLL inoperability
        20618: 00/02/16: Ray Andraka: Re: Virtex DLL inoperability
        21313: 00/03/16: David Gilchrist: Re: Virtex DLL inoperability
            21345: 00/03/17: Austin Franklin: Re: Virtex DLL inoperability
            21371: 00/03/20: Winzker: Re: Virtex DLL inoperability
                21403: 00/03/22: Greg Alexander: Re: Virtex DLL inoperability
                    21404: 00/03/22: Peter Alfke: Re: Virtex DLL inoperability
                    21421: 00/03/22: Ray Andraka: Re: Virtex DLL inoperability
                        21423: 00/03/22: Rickman: Re: Virtex DLL inoperability
                        21445: 00/03/22: Greg Alexander: Re: Virtex DLL inoperability
                            21448: 00/03/22: Ray Andraka: Re: Virtex DLL inoperability
                    21644: 00/03/27: Winzker: Re: Virtex DLL inoperability
20207: 00/01/31: <clay@ewbridge.com>: AMD SCxxx + Xilinx XCSxx
20208: 00/01/31: <clay@ewbridge.com>: AMD SCxxx + Xilinx XCSxx
20213: 00/01/31: Navaneethan Sundaramoorthy: Help with xdl -ncd2xdl


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