Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Threads Starting May 2006

101429: 06/05/01: Gavin Melville: Where has the ChipViewer gone
101434: 06/05/01: Marco T.: Question about the ip I developed
    101435: 06/05/01: Antti Lukats: Re: Question about the ip I developed
        101436: 06/05/01: Marco T.: Re: Question about the ip I developed
            101437: 06/05/01: Ralf Hildebrandt: Re: Question about the ip I developed
        101439: 06/05/01: Fred: Re: Question about the ip I developed
            101440: 06/05/01: int19h: Re: Question about the ip I developed
                101442: 06/05/01: Fred: Re: Question about the ip I developed
                    101497: 06/05/02: Symon: Re: Question about the ip I developed
                        101523: 06/05/02: Fred: Re: Question about the ip I developed
    101460: 06/05/01: Skeets: Re: Question about the ip I developed
101446: 06/05/01: boru: ERROR:iMPACT:1210 - '1':Boundary-scan chain test failed at bit position '1'
    101448: 06/05/01: John_H: Re: ERROR:iMPACT:1210 - '1':Boundary-scan chain test failed at bit position '1'
    101751: 06/05/05: Andrew Lohbihler: Re: ERROR:iMPACT:1210 - '1':Boundary-scan chain test failed at bit position '1'
101447: 06/05/01: Roger Bourne: Output bus bit resolution of a digital filter
    101504: 06/05/02: <stenasc@yahoo.com>: Re: Output bus bit resolution of a digital filter
101450: 06/05/01: Eli Hughes: ISE 8.1 Comment Bug, Very hideous
    101452: 06/05/01: Eli Hughes: Re: ISE 8.1 Comment Bug, Very hideous
        101466: 06/05/01: Eli Hughes: Re: ISE 8.1 Comment Bug, Very hideous
            101547: 06/05/03: Jim Granville: Re: ISE 8.1 Comment Bug, Very hideous
        101470: 06/05/02: Jim Granville: Re: ISE 8.1 Comment Bug, Very hideous
    101453: 06/05/01: Antti: Re: ISE 8.1 Comment Bug, Very hideous
    101461: 06/05/01: Jeff Brower: Re: ISE 8.1 Comment Bug, Very hideous
    101472: 06/05/01: jimwu88NOOOSPAM@yahoo.com: Re: ISE 8.1 Comment Bug, Very hideous
    101477: 06/05/01: Andy Peters: Re: ISE 8.1 Comment Bug, Very hideous
    101519: 06/05/02: Jeff Brower: Re: ISE 8.1 Comment Bug, Very hideous
    101537: 06/05/02: <kash.jt@gmail.com>: Re: ISE 8.1 Comment Bug, Very hideous
    101545: 06/05/02: Duth: Re: ISE 8.1 Comment Bug, Very hideous
101457: 06/05/02: Tony Burch: BurchED FPGA Expansion Modules, 4-for-1 offer
    101670: 06/05/05: Tony Burch: Re: BurchED FPGA Expansion Modules, 4-for-1 offer
        101805: 06/05/07: Tony Burch: Re: BurchED FPGA Expansion Modules, 4-for-1 offer
            101820: 06/05/07: Kryten: Re: BurchED FPGA Expansion Modules, 4-for-1 offer
101476: 06/05/01: <brehob@gmail.com>: quartus 5.1 assignment_defaults.qdf
101481: 06/05/01: Fizzy: BFM and ISE simulator
101487: 06/05/01: <vladimir@baykov.de>: 50-th Anniversary of the CORDIC Algorithm
    101551: 06/05/02: Ray Andraka: Re: 50-th Anniversary of the CORDIC Algorithm
    101568: 06/05/03: henk: Re: 50-th Anniversary of the CORDIC Algorithm
    101570: 06/05/03: <vladimir@baykov.de>: Re: 50-th Anniversary of the CORDIC Algorithm
101488: 06/05/01: <alessandro.strazzero@gmail.com>: RESET pin on NIOS II processor
    101532: 06/05/02: radarman: Re: RESET pin on NIOS II processor
101492: 06/05/02: Fizzy: Deadlock PLB
    101536: 06/05/02: MM: Re: Deadlock PLB
101508: 06/05/02: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Problem with DCM simulation models
    103813: 06/06/12: <Michael_R_Hicks-NR@raytheon.com>: Re: Problem with DCM simulation models
101511: 06/05/02: Dave: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
    101513: 06/05/02: Nicolas Matringe: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
    101514: 06/05/02: Peter Alfke: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
    101516: 06/05/02: Dave: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
    101517: 06/05/02: Jeff Brower: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
    101541: 06/05/03: Jim Granville: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
        101569: 06/05/03: Jim Granville: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
            101573: 06/05/03: Kolja Sulimma: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
                101575: 06/05/03: Kolja Sulimma: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
    101562: 06/05/03: Dave: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
    101563: 06/05/03: Dave: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
    101571: 06/05/03: Dave: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
    101574: 06/05/03: Dave: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
    101578: 06/05/03: Gabor: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
101512: 06/05/02: Christopher Cole: windrvr for Linux broken in 2.6.16
    101525: 06/05/02: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: windrvr for Linux broken in 2.6.16
        102962: 06/05/24: Daniel O'Connor: Re: windrvr for Linux broken in 2.6.16
            103041: 06/05/25: Laurent Pinchart: Re: windrvr for Linux broken in 2.6.16
    101628: 06/05/03: Dan McDonald: Re: windrvr for Linux broken in 2.6.16
101520: 06/05/02: Nirav Raval: ESL and Spartan Starter Kit
101522: 06/05/02: Gattu: ESL using Spartan 3/3E kits
101527: 06/05/02: Antti: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101528: 06/05/02: CMOS: mux problem
101533: 06/05/02: Weng Tianxiang: Improvement suggestions for Xilinx ChipScope
    101539: 06/05/02: Symon: Re: Improvement suggestions for Xilinx ChipScope
        101567: 06/05/03: Kolja Sulimma: Re: Improvement suggestions for Xilinx ChipScope
101540: 06/05/02: <shawnn@gmail.com>: bizzare unexplained random errors w/ Lattice 4256V CPLD
    101542: 06/05/02: Gabor: Re: bizzare unexplained random errors w/ Lattice 4256V CPLD
    101543: 06/05/03: Jim Granville: Re: bizzare unexplained random errors w/ Lattice 4256V CPLD
    101548: 06/05/02: bart: Re: bizzare unexplained random errors w/ Lattice 4256V CPLD
    101662: 06/05/04: <shawnn@gmail.com>: Re: bizzare unexplained random errors w/ Lattice 4256V CPLD
101544: 06/05/02: Fizzy: EDK and SYSGEN
    101549: 06/05/02: <edvenson@gmail.com>: Re: EDK and SYSGEN
    101556: 06/05/02: Fizzy: Re: EDK and SYSGEN
    101610: 06/05/03: <edvenson@gmail.com>: Re: EDK and SYSGEN
101550: 06/05/02: boru: boundary scan through Virtex
101554: 06/05/02: Guru Prasad: detailed description on the archetecture of FPGA's/CPLD's
    101572: 06/05/03: Aurelian Lazarut: Re: detailed description on the archetecture of FPGA's/CPLD's
    101719: 06/05/05: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: detailed description on the archetecture of FPGA's/CPLD's
    101730: 06/05/05: <MikeShepherd564@btinternet.com>: Re: detailed description on the archetecture of FPGA's/CPLD's
101555: 06/05/02: <vladimir@baykov.de>: Table-lookup CORDIC
101561: 06/05/03: Rainier: How to open an ISE 8.1 project in ISE 7.1?
    101565: 06/05/03: Antti: Re: How to open an ISE 8.1 project in ISE 7.1?
    101577: 06/05/03: Nial Stewart: Re: How to open an ISE 8.1 project in ISE 7.1?
    101580: 06/05/03: Antti: Re: How to open an ISE 8.1 project in ISE 7.1?
    101581: 06/05/03: Ricky Su: Re: How to open an ISE 8.1 project in ISE 7.1?
    101603: 06/05/03: Fabio Rodrigues de la Rocha: Re: How to open an ISE 8.1 project in ISE 7.1?
    101626: 06/05/03: Jeff Brower: Re: How to open an ISE 8.1 project in ISE 7.1?
101564: 06/05/03: Antti: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101660: 06/05/04: c d saunter: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101576: 06/05/03: al99999: Virtex 4 LX25
    101655: 06/05/04: jimwu88NOOOSPAM@yahoo.com: Re: Virtex 4 LX25
    101728: 06/05/05: al99999: Re: Virtex 4 LX25
    101735: 06/05/05: jimwu88NOOOSPAM@yahoo.com: Re: Virtex 4 LX25
    101739: 06/05/05: al99999: Re: Virtex 4 LX25
    101741: 06/05/05: Peter Alfke: Re: Virtex 4 LX25
    101754: 06/05/05: al99999: Re: Virtex 4 LX25
101579: 06/05/03: samtee: ISE8.1 inout, tristate Problem?Please help!
    101582: 06/05/03: Benjamin Todd: Re: ISE8.1 inout, tristate Problem?Please help!
        101617: 06/05/04: samtee: Re: ISE8.1 inout, tristate Problem?Please help!
            101634: 06/05/04: sam: Re: ISE8.1 inout, tristate Problem?Please help!
                101646: 06/05/04: Benjamin Todd: Re: ISE8.1 inout, tristate Problem?Please help!
    101624: 06/05/03: Jeff Brower: Re: ISE8.1 inout, tristate Problem?Please help!
101583: 06/05/03: <Robin.Emery@gmail.com>: Unreactive Output Pins on Xilinx Virtex-II
    101587: 06/05/03: Stephen Craven: Re: Unreactive Output Pins on Xilinx Virtex-II
        101614: 06/05/04: Jim Granville: Re: Unreactive Output Pins on Xilinx Virtex-II
        101635: 06/05/04: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Re: Unreactive Output Pins on Xilinx Virtex-II
    101592: 06/05/03: Peter Alfke: Re: Unreactive Output Pins on Xilinx Virtex-II
    101593: 06/05/03: Robin Emery: Re: Unreactive Output Pins on Xilinx Virtex-II
    101595: 06/05/03: Robin Emery: Re: Unreactive Output Pins on Xilinx Virtex-II
    101607: 06/05/03: Peter Alfke: Re: Unreactive Output Pins on Xilinx Virtex-II
    101637: 06/05/04: ALuPin@web.de: Re: Unreactive Output Pins on Xilinx Virtex-II
    102086: 06/05/10: Robin Emery: Re: Unreactive Output Pins on Xilinx Virtex-II
101588: 06/05/03: Antti: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101589: 06/05/03: christophe ALEXANDRE: ML405 board
    101591: 06/05/03: Antti: Re: ML405 board
    101596: 06/05/03: Ed McGettigan: Re: ML405 board
        101769: 06/05/05: Ed McGettigan: Re: ML405 board
    101733: 06/05/05: christophe ALEXANDRE: Re: ML405 board
101594: 06/05/03: Antti: Measuring Light with LED and FPGA
    101597: 06/05/03: Tommy Thorn: Re: Measuring Light with LED and FPGA
        101598: 06/05/03: Antti Lukats: Re: Measuring Light with LED and FPGA
    101606: 06/05/04: Jim Granville: Re: Measuring Light with LED and FPGA
    101616: 06/05/03: Mike Harrison: Re: Measuring Light with LED and FPGA
        101618: 06/05/03: John Larkin: Re: Measuring Light with LED and FPGA
        101621: 06/05/04: Jim Granville: Re: Measuring Light with LED and FPGA
            101809: 06/05/07: Jim Granville: Re: Measuring Light with LED and FPGA
    101807: 06/05/07: Antti: Re: Measuring Light with LED and FPGA
101599: 06/05/03: CMOS: ports of multidimentional arrays in verilog.
    101619: 06/05/04: John_H: Re: ports of multidimentional arrays in verilog.
    101623: 06/05/03: Jeff Brower: Re: ports of multidimentional arrays in verilog.
101600: 06/05/03: Prodatron / SymbiosiS: CPC TREX 24MHz Turbo Core available PLUS complete source code
101601: 06/05/03: Matt Blanton: xst segmentation fault
    101602: 06/05/03: Antti Lukats: Re: xst segmentation fault
        101615: 06/05/03: Matt Blanton: Re: xst segmentation fault
101604: 06/05/03: Colin Hankins: How to create a fixed netlist IP core?
101608: 06/05/03: <kulkarni.shailesh@gmail.com>: Interfacing Spartan 3 board to PC parallel port??
    101609: 06/05/03: Eli Hughes: Re: Interfacing Spartan 3 board to PC parallel port??
        101612: 06/05/03: Uwe Bonnes: Re: Interfacing Spartan 3 board to PC parallel port??
    101611: 06/05/03: Andy Peters: Re: Interfacing Spartan 3 board to PC parallel port??
    101613: 06/05/04: Jim Granville: Re: Interfacing Spartan 3 board to PC parallel port??
        101632: 06/05/04: Jim Granville: Re: Interfacing Spartan 3 board to PC parallel port??
            101636: 06/05/04: Kolja Sulimma: Re: Interfacing Spartan 3 board to PC parallel port??
    101625: 06/05/03: Newman: Re: Interfacing Spartan 3 board to PC parallel port??
    101627: 06/05/03: Newman: Re: Interfacing Spartan 3 board to PC parallel port??
    101630: 06/05/03: <kulkarni.shailesh@gmail.com>: Re: Interfacing Spartan 3 board to PC parallel port??
    101631: 06/05/03: Walter: Re: Interfacing Spartan 3 board to PC parallel port??
101620: 06/05/03: Ron: Xilinx 3s8000?
    101622: 06/05/04: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Xilinx 3s8000?
    101629: 06/05/03: Peter Alfke: Re: Xilinx 3s8000?
    101638: 06/05/04: Mike Harrison: Re: Xilinx 3s8000?
        101649: 06/05/04: Ron: Re: Xilinx 3s8000?
            101661: 06/05/04: Austin Lesea: Re: Xilinx 3s8000?
                101665: 06/05/04: Lukasz Salwinski: Re: Xilinx 3s8000?
                    101681: 06/05/04: Austin Lesea: Re: Xilinx 3s8000?
                        101692: 06/05/04: Lukasz Salwinski: Re: Xilinx 3s8000?
                            101693: 06/05/04: Austin Lesea: Re: Xilinx 3s8000?
                                101747: 06/05/05: Lukasz Salwinski: Re: Xilinx 3s8000?
                101677: 06/05/04: Ron: Re: Xilinx 3s8000?
                    101683: 06/05/04: Austin Lesea: Re: Xilinx 3s8000?
                        101752: 06/05/05: Ron: Re: Xilinx 3s8000?
                            101755: 06/05/05: Ron: Re: Xilinx 3s8000?
                                101764: 06/05/05: John_H: Re: Xilinx 3s8000?
                                101766: 06/05/05: Eric Smith: Re: Xilinx 3s8000?
                            101759: 06/05/05: Austin Lesea: <ignore thread>
                                101761: 06/05/05: Ron: Re: <ignore thread>
                            101763: 06/05/05: John_H: Re: Xilinx 3s8000?
                            101768: 06/05/05: Tobias Weingartner: Re: Xilinx 3s8000?
                                101773: 06/05/05: Ron: Re: Xilinx 3s8000?
                                    101777: 06/05/06: Thomas Womack: Re: Xilinx 3s8000?
                                        101779: 06/05/06: Ron: Re: Xilinx 3s8000?
                                            101831: 06/05/07: Ron: Re: Xilinx 3s8000?
                                                101840: 06/05/08: Jim Granville: Re: Xilinx 3s8000?
                                                    101848: 06/05/07: Ron: Re: Xilinx 3s8000?
                                                        101854: 06/05/08: Jim Granville: Re: Xilinx 3s8000?
                                                            101862: 06/05/07: Ron: Re: Xilinx 3s8000?
                                                            101884: 06/05/08: Falk Brunner: Re: Xilinx 3s8000?
                                                101846: 06/05/07: Ron: Re: Xilinx 3s8000?
                                            101880: 06/05/08: Thomas Womack: Re: Xilinx 3s8000?
                                                101932: 06/05/08: Ron: Re: Xilinx 3s8000?
                                                    101942: 06/05/08: Ron: Re: Xilinx 3s8000?
                                                        101943: 06/05/08: Mike Harrison: Re: Xilinx 3s8000?
                                                            101947: 06/05/08: Ron: Re: Xilinx 3s8000?
                                                                101948: 06/05/08: Ron: Re: Xilinx 3s8000?
                                                                    101956: 06/05/08: Ron: Re: Xilinx 3s8000?
                                                                        101962: 06/05/09: Jim Granville: Re: Xilinx 3s8000?
                                                                        101974: 06/05/09: Jim Granville: Re: Xilinx 3s8000?
                                                                            102058: 06/05/10: David M. Palmer: Re: Xilinx 3s8000?
                                                                            102066: 06/05/10: =?ISO-8859-1?Q?Michael_Sch=F6berl?=: Re: Xilinx 3s8000?
                                                                                102239: 06/05/12: Philip Freidin: Re: Xilinx 3s8000?
                                                                        102084: 06/05/10: c d saunter: Re: Xilinx 3s8000?
                                                                101960: 06/05/08: Jerry Coffin: Re: Xilinx 3s8000?
                                                                    101963: 06/05/08: Ron: Re: Xilinx 3s8000?
                                                                        101964: 06/05/09: Jim Granville: Re: Xilinx 3s8000?
                                                        101998: 06/05/09: Thomas Womack: Re: Xilinx 3s8000?
                                                            102034: 06/05/09: Ron: Re: Xilinx 3s8000?
                                                    102087: 06/05/10: Ron: Re: Xilinx 3s8000?
                    101757: 06/05/05: Ron: Re: Xilinx 3s8000?
                    101771: 06/05/05: Austin Lesea: Re: Xilinx 3s8000?
                        101781: 06/05/06: Austin Lesea: Re: Xilinx 3s8000?
                    101772: 06/05/06: Rob: Re: Xilinx 3s8000?
                        101780: 06/05/06: Rob: Re: Xilinx 3s8000?
    101684: 06/05/04: Peter Alfke: Re: Xilinx 3s8000?
    101685: 06/05/04: <metamazster@gmail.com>: Re: Xilinx 3s8000?
    101696: 06/05/04: <fpga_toys@yahoo.com>: Re: Xilinx 3s8000?
    101731: 06/05/05: c d saunter: Re: Xilinx 3s8000?
        101827: 06/05/07: Paul Hartke: Re: Xilinx 3s8000?
    101753: 06/05/05: Peter Alfke: Re: Xilinx 3s8000?
    101774: 06/05/06: <fpga_toys@yahoo.com>: Re: Xilinx 3s8000?
    101775: 06/05/06: <fpga_toys@yahoo.com>: Re: Xilinx 3s8000?
    101806: 06/05/07: <fpga_toys@yahoo.com>: Re: Xilinx 3s8000?
    101832: 06/05/07: Peter Alfke: Re: Xilinx 3s8000?
    101833: 06/05/07: johnp: Re: Xilinx 3s8000?
    101835: 06/05/07: <fpga_toys@yahoo.com>: Re: Xilinx 3s8000?
    101841: 06/05/07: <fpga_toys@yahoo.com>: Re: Xilinx 3s8000?
    101849: 06/05/07: Peter Alfke: Re: Xilinx 3s8000?
    101860: 06/05/07: <fpga_toys@yahoo.com>: Re: Xilinx 3s8000?
    101882: 06/05/08: frank: Re: Xilinx 3s8000?
        101937: 06/05/08: Ron: Re: Xilinx 3s8000?
    101939: 06/05/08: Isaac Bosompem: Re: Xilinx 3s8000?
    101955: 06/05/08: Peter Alfke: Re: Xilinx 3s8000?
    101959: 06/05/08: radarman: Re: Xilinx 3s8000?
    101965: 06/05/08: Peter Alfke: Re: Xilinx 3s8000?
    101967: 06/05/08: Peter Alfke: Re: Xilinx 3s8000?
    102004: 06/05/09: Jeff Brower: Re: Xilinx 3s8000?
    102006: 06/05/09: radarman: Re: Xilinx 3s8000?
    102015: 06/05/09: Jeff Brower: Re: Xilinx 3s8000?
    102018: 06/05/09: Isaac Bosompem: Re: Xilinx 3s8000?
    102024: 06/05/09: JJ: Re: Xilinx 3s8000?
    102050: 06/05/09: radarman: Re: Xilinx 3s8000?
    102073: 06/05/10: radarman: Re: Xilinx 3s8000?
    102116: 06/05/10: <fpga_toys@yahoo.com>: Re: Xilinx 3s8000?
    102126: 06/05/10: JJ: Re: Xilinx 3s8000?
    102173: 06/05/11: <robnstef@frontiernet.net>: Re: Xilinx 3s8000?
        102188: 06/05/11: Ron: Re: Xilinx 3s8000?
    102191: 06/05/11: <robnstef@frontiernet.net>: Re: Xilinx 3s8000?
    102213: 06/05/11: Jeff Brower: Re: Xilinx 3s8000?
    102214: 06/05/11: Jeff Brower: Re: Xilinx 3s8000?
    102240: 06/05/12: John McGrath: Re: Xilinx 3s8000?
101633: 06/05/03: <ankur101@gmail.com>: Voltage Regulator on the XSA-50 board
101639: 06/05/04: Dave: Phase alignment of DCMs on different boards/devices
    101644: 06/05/04: Rene Tschaggelar: Re: Phase alignment of DCMs on different boards/devices
    101658: 06/05/04: Peter Alfke: Re: Phase alignment of DCMs on different boards/devices
        101714: 06/05/05: Rene Tschaggelar: Re: Phase alignment of DCMs on different boards/devices
    101713: 06/05/05: Dave: Re: Phase alignment of DCMs on different boards/devices
101643: 06/05/04: Alan Nishioka: Re: xst segmentation fault
101647: 06/05/04: Jan Decaluwe: Cordic-based Sine Computer in MyHDL
    101648: 06/05/04: Kolja Sulimma: Re: Cordic-based Sine Computer in MyHDL
        101650: 06/05/04: Symon: Re: Cordic-based Sine Computer in MyHDL
            101653: 06/05/04: Kolja Sulimma: Re: Cordic-based Sine Computer in MyHDL
                101674: 06/05/04: Mike Treseler: Re: Cordic-based Sine Computer in MyHDL
                    101679: 06/05/04: Symon: Re: Cordic-based Sine Computer in MyHDL
    101668: 06/05/04: Mike Treseler: Re: Cordic-based Sine Computer in MyHDL
        101721: 06/05/05: Jan Decaluwe: Re: Cordic-based Sine Computer in MyHDL
            101749: 06/05/05: Mike Treseler: Re: Cordic-based Sine Computer in MyHDL
101652: 06/05/04: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: CPU resource type
    101664: 06/05/04: Alan Nishioka: Re: CPU resource type
        101667: 06/05/04: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: CPU resource type
    101675: 06/05/04: Jon Elson: Re: CPU resource type
    101789: 06/05/06: Isaac Bosompem: Re: CPU resource type
101654: 06/05/04: max_mont: EPLD Lattice Prog Problem
101656: 06/05/04: Symon: ChipScope 8.1i. Timing has got worse?
    101657: 06/05/04: Symon: Re: ChipScope 8.1i. Timing has got worse?
        101659: 06/05/04: Symon: Re: ChipScope 8.1i. Timing has got worse?
101663: 06/05/04: <shawnn@gmail.com>: async. load line on shift register
    101666: 06/05/04: <shawnn@gmail.com>: Re: async. load line on shift register
    101671: 06/05/04: Peter Alfke: Re: async. load line on shift register
    101687: 06/05/04: Dave Pollum: Re: async. load line on shift register
101669: 06/05/04: Paul: =?utf-8?q?how_to_set_a_I/O_as_3-state_in_xilinx_FPGA=EF=BC=9F?=
    101688: 06/05/04: Dave Pollum: =?utf-8?q?Re:_how_to_set_a_I/O_as_3-state_in_xilinx_FPGA=EF=BC=9F?=
        101799: 06/05/07: Alif Wahid: Re: how to set a I/O as 3-state in xilinx =?UTF-8?B?RlBHQe+8nw==?=
101672: 06/05/04: Jim_L_Williams@hotmail.com: New To FPGA, Program question
    101673: 06/05/04: Jon Elson: Re: New To FPGA, Program question
        101682: 06/05/04: Eli Hughes: Re: New To FPGA, Program question
        101732: 06/05/05: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: New To FPGA, Program question
    101690: 06/05/04: bart: Re: New To FPGA, Program question
    101737: 06/05/05: Enno Luebbers: Re: New To FPGA, Program question
101676: 06/05/04: Sid: 87C52 & 87C51 core
    101678: 06/05/05: Jim Granville: Re: 87C52 & 87C51 core
    101686: 06/05/04: Eric Smith: Re: 87C52 & 87C51 core
        101767: 06/05/05: Eric Smith: Re: 87C52 & 87C51 core
            102119: 06/05/10: Antti Lukats: Re: 87C52 & 87C51 core
    101756: 06/05/05: Sid: Re: 87C52 & 87C51 core
    102101: 06/05/10: bart: Re: 87C52 & 87C51 core
101689: 06/05/04: nospam: LVDS inputs on Cyclone II
    101691: 06/05/04: Austin Lesea: Re: LVDS inputs on Cyclone II
        101694: 06/05/05: Jim Granville: Re: LVDS inputs on Cyclone II
        101703: 06/05/05: nospam: Re: LVDS inputs on Cyclone II
        101707: 06/05/05: Rob: Re: LVDS inputs on Cyclone II
        101709: 06/05/05: Bob: Re: LVDS inputs on Cyclone II
            101742: 06/05/05: Austin Lesea: Re: LVDS inputs on Cyclone II
    101695: 06/05/05: Jim Granville: Re: LVDS inputs on Cyclone II
        101700: 06/05/04: Austin Lesea: Re: LVDS inputs on Cyclone II
            101705: 06/05/05: Jim Granville: Re: LVDS inputs on Cyclone II
            101723: 06/05/05: Symon: Re: LVDS inputs on Cyclone II
        101704: 06/05/05: nospam: Re: LVDS inputs on Cyclone II
    101708: 06/05/05: Rob: Re: LVDS inputs on Cyclone II
    101748: 06/05/05: Piotr Wyderski: Re: LVDS inputs on Cyclone II
    101760: 06/05/05: Ben Twijnstra: Re: LVDS inputs on Cyclone II
101697: 06/05/04: Weng Tianxiang: RFID chip has battary in it or not
    101698: 06/05/04: Ray Andraka: Re: RFID chip has battary in it or not
        101710: 06/05/05: Ralf Hildebrandt: Re: RFID chip has battary in it or not
            101736: 06/05/05: Brian Drummond: Re: RFID chip has battary in it or not
                101738: 06/05/05: Symon: Re: RFID chip has battary in it or not
                    101877: 06/05/08: Symon: Re: RFID chip has battary in it or not
    101702: 06/05/04: Weng Tianxiang: Re: RFID chip has battary in it or not
    101803: 06/05/06: JJ: Re: RFID chip has battary in it or not
    101804: 06/05/06: JJ: Re: RFID chip has battary in it or not
    101971: 06/05/08: JJ: Re: RFID chip has battary in it or not
101706: 06/05/04: motty: OPB clocking question
101712: 06/05/04: Prakash: Xilinx-XUPV2P- AC97 Audio BSP
101715: 06/05/05: Peter Mendham: Xilinx SelectMAP Question
    101716: 06/05/05: Antti: Re: Xilinx SelectMAP Question
        101717: 06/05/05: Peter Mendham: Re: Xilinx SelectMAP Question
            101718: 06/05/05: Aurelian Lazarut: Re: Xilinx SelectMAP Question
                101720: 06/05/05: Aurelian Lazarut: Re: Xilinx SelectMAP Question
                    101726: 06/05/05: Peter Mendham: Re: Xilinx SelectMAP Question
                        101743: 06/05/05: Aurelian Lazarut: Re: Xilinx SelectMAP Question
                            101870: 06/05/08: Peter Mendham: Re: Xilinx SelectMAP Question
                        101758: 06/05/06: Jim Granville: Re: Xilinx SelectMAP Question
                            101762: 06/05/05: Antti Lukats: Re: Xilinx SelectMAP Question
        101744: 06/05/05: Aurelian Lazarut: Re: Xilinx SelectMAP Question
            101745: 06/05/05: Aurelian Lazarut: Re: Xilinx SelectMAP Question
    101722: 06/05/05: jenze: Re: Xilinx SelectMAP Question
    101724: 06/05/05: Antti: Re: Xilinx SelectMAP Question
    101725: 06/05/05: Antti: Re: Xilinx SelectMAP Question
    101729: 06/05/05: Antti: Re: Xilinx SelectMAP Question
101734: 06/05/05: motty: Xilinx document timing diagrams?
    101787: 06/05/06: Alan Nishioka: Re: Xilinx document timing diagrams?
101770: 06/05/05: Alan Nishioka: Anyone use Xilinx ppc405 profiling tools?
    101778: 06/05/06: dp: Re: Anyone use Xilinx ppc405 profiling tools?
    101782: 06/05/06: Alan Nishioka: Re: Anyone use Xilinx ppc405 profiling tools?
    101852: 06/05/07: Alan Nishioka: Re: Anyone use Xilinx ppc405 profiling tools?
    101866: 06/05/08: Antti: Re: Anyone use Xilinx ppc405 profiling tools?
    101892: 06/05/08: dp: Re: Anyone use Xilinx ppc405 profiling tools?
    101949: 06/05/08: Joseph: Re: Anyone use Xilinx ppc405 profiling tools?
    102013: 06/05/09: Joel: Re: Anyone use Xilinx ppc405 profiling tools?
    102038: 06/05/09: Alan Nishioka: Re: Anyone use Xilinx ppc405 profiling tools?
    102936: 06/05/23: Joseph: Re: Anyone use Xilinx ppc405 profiling tools?
101783: 06/05/06: Jeremy Ralph: FPGA-based hardware accelerator for PC
    101784: 06/05/06: Falk Brunner: Re: FPGA-based hardware accelerator for PC
        101797: 06/05/07: Alif Wahid: Re: FPGA-based hardware accelerator for PC
        101812: 06/05/07: Falk Brunner: Re: FPGA-based hardware accelerator for PC
    101785: 06/05/06: Piotr Wyderski: Re: FPGA-based hardware accelerator for PC
        101815: 06/05/07: Piotr Wyderski: Re: FPGA-based hardware accelerator for PC
            101919: 06/05/08: Piotr Wyderski: Re: FPGA-based hardware accelerator for PC
                101988: 06/05/09: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: FPGA-based hardware accelerator for PC
        101865: 06/05/08: Andreas Ehliar: Re: FPGA-based hardware accelerator for PC
            101920: 06/05/08: Piotr Wyderski: Re: FPGA-based hardware accelerator for PC
                101946: 06/05/09: Phil Tomson: Re: FPGA-based hardware accelerator for PC
            101945: 06/05/09: Phil Tomson: Re: FPGA-based hardware accelerator for PC
        101873: 06/05/08: Adam Megacz: Re: FPGA-based hardware accelerator for PC
    101790: 06/05/06: Jeremy Ralph: Re: FPGA-based hardware accelerator for PC
    101792: 06/05/06: Jeremy Ralph: Re: FPGA-based hardware accelerator for PC
    101794: 06/05/06: JJ: Re: FPGA-based hardware accelerator for PC
        101798: 06/05/07: Alif Wahid: Re: FPGA-based hardware accelerator for PC
            101864: 06/05/08: Andreas Ehliar: Re: FPGA-based hardware accelerator for PC
            101951: 06/05/09: Phil Tomson: Re: FPGA-based hardware accelerator for PC
                102048: 06/05/10: Phil Tomson: Re: FPGA-based hardware accelerator for PC
        101950: 06/05/09: Phil Tomson: Re: FPGA-based hardware accelerator for PC
            102051: 06/05/10: Phil Tomson: Re: FPGA-based hardware accelerator for PC
    101800: 06/05/06: JJ: Re: FPGA-based hardware accelerator for PC
    101830: 06/05/07: JJ: Re: FPGA-based hardware accelerator for PC
    101867: 06/05/08: <fpga_toys@yahoo.com>: Re: FPGA-based hardware accelerator for PC
    101901: 06/05/08: Wayne: Re: FPGA-based hardware accelerator for PC
    101917: 06/05/08: Jeremy Ralph: Re: FPGA-based hardware accelerator for PC
    101927: 06/05/08: JJ: Re: FPGA-based hardware accelerator for PC
    101928: 06/05/08: JJ: Re: FPGA-based hardware accelerator for PC
    101930: 06/05/08: JJ: Re: FPGA-based hardware accelerator for PC
    101966: 06/05/08: JJ: Re: FPGA-based hardware accelerator for PC
    101969: 06/05/08: JJ: Re: FPGA-based hardware accelerator for PC
    102002: 06/05/09: JJ: Re: FPGA-based hardware accelerator for PC
    102009: 06/05/09: bart: Re: FPGA-based hardware accelerator for PC
    102068: 06/05/10: <fpga_toys@yahoo.com>: Re: FPGA-based hardware accelerator for PC
    102106: 06/05/10: JJ: Re: FPGA-based hardware accelerator for PC
    102108: 06/05/10: JJ: Re: FPGA-based hardware accelerator for PC
    102110: 06/05/10: Jeremy Ralph: Re: FPGA-based hardware accelerator for PC
    103137: 06/05/25: Jeremy Ralph: Re: FPGA-based hardware accelerator for PC
101786: 06/05/06: BoroToro: Spartan 3e starter kit & Multimedia
    101793: 06/05/07: RedskullDC: Re: Spartan 3e starter kit & Multimedia
    101796: 06/05/06: David M. Palmer: Re: Spartan 3e starter kit & Multimedia
        101802: 06/05/07: Jim Granville: Re: Spartan 3e starter kit & Multimedia
        101822: 06/05/07: c d saunter: Re: Spartan 3e starter kit & Multimedia
            101961: 06/05/08: David M. Palmer: Re: Spartan 3e starter kit & Multimedia
                102057: 06/05/10: David M. Palmer: Re: Spartan 3e starter kit & Multimedia
    101954: 06/05/08: radarman: Re: Spartan 3e starter kit & Multimedia
    101990: 06/05/09: radarman: Re: Spartan 3e starter kit & Multimedia
    102044: 06/05/09: BoroToro: Re: Spartan 3e starter kit & Multimedia
101808: 06/05/07: Jep: flashing a led
    101811: 06/05/07: Jim Granville: Re: flashing a led
    101813: 06/05/07: Falk Brunner: Re: flashing a led
    101818: 06/05/07: Zara: Re: flashing a led
    101826: 06/05/07: Weddick: Re: flashing a led
    101828: 06/05/07: Ralf Hildebrandt: Re: flashing a led
    101834: 06/05/07: Jep: Re: flashing a led
    101936: 06/05/08: Marlboro: Re: flashing a led
    101940: 06/05/08: Peter Alfke: Re: flashing a led
101814: 06/05/07: Franco Tiratore: FPGA implementation of an OFDM-based modem
101816: 06/05/07: YiQi: A constant value of 0 in block
    101819: 06/05/07: YiQi: Re: A constant value of 0 in block
        101824: 06/05/07: Mike Treseler: Re: A constant value of 0 in block
    101853: 06/05/07: YiQi: Re: A constant value of 0 in block
101817: 06/05/07: YiQi: EDIFParser in JHDL / EDIF simulator?
101821: 06/05/07: Weng Tianxiang: The differences between behaviors of 'std_logic_vector' and 'unsigned'
    101823: 06/05/07: Mike Treseler: Re: The differences between behaviors of 'std_logic_vector' and 'unsigned'
    101825: 06/05/07: Weng Tianxiang: Re: The differences between behaviors of 'std_logic_vector' and 'unsigned'
101829: 06/05/07: Peter Alfke: Re: Xilinx 3s8000?
101836: 06/05/07: mammo: Funky experiment on a Spartan II FPGA
    101837: 06/05/07: Peter Alfke: Re: Funky experiment on a Spartan II FPGA
        101845: 06/05/08: Jim Granville: Re: Funky experiment on a Spartan II FPGA
    101838: 06/05/08: Jim Granville: Re: Funky experiment on a Spartan II FPGA
        101843: 06/05/08: Jim Granville: Re: Funky experiment on a Spartan II FPGA
    101839: 06/05/07: mammo: Re: Funky experiment on a Spartan II FPGA
    101842: 06/05/07: Peter Alfke: Re: Funky experiment on a Spartan II FPGA
    101844: 06/05/07: <fpga_toys@yahoo.com>: Re: Funky experiment on a Spartan II FPGA
        101883: 06/05/08: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Funky experiment on a Spartan II FPGA
            101977: 06/05/09: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Funky experiment on a Spartan II FPGA
                102022: 06/05/09: Austin Lesea: Re: Funky experiment on a Spartan II FPGA
                    102028: 06/05/09: John_H: Re: Funky experiment on a Spartan II FPGA
                        102030: 06/05/09: Austin Lesea: Re: Funky experiment on a Spartan II FPGA
    101857: 06/05/07: mammo: Re: Funky experiment on a Spartan II FPGA
    101922: 06/05/08: <lenz19@gmx.de>: Re: Funky experiment on a Spartan II FPGA
    101941: 06/05/08: Peter Alfke: Re: Funky experiment on a Spartan II FPGA
    101993: 06/05/09: Peter Alfke: Re: Funky experiment on a Spartan II FPGA
    102021: 06/05/09: <lenz19@gmx.de>: Re: Funky experiment on a Spartan II FPGA
    102036: 06/05/09: Peter Alfke: Re: Funky experiment on a Spartan II FPGA
101847: 06/05/07: Andrew FPGA: Can an FPGA be operated reliably in a car wheel?
    101850: 06/05/08: <MikeShepherd564@btinternet.com>: Re: Can an FPGA be operated reliably in a car wheel?
        101958: 06/05/09: Bob: Re: Can an FPGA be operated reliably in a car wheel?
            101991: 06/05/09: nospam: Re: Can an FPGA be operated reliably in a car wheel?
    101856: 06/05/07: Andrew FPGA: Re: Can an FPGA be operated reliably in a car wheel?
        101872: 06/05/08: c d saunter: Re: Can an FPGA be operated reliably in a car wheel?
    101858: 06/05/07: Peter Alfke: Re: Can an FPGA be operated reliably in a car wheel?
    101859: 06/05/08: John_H: Re: Can an FPGA be operated reliably in a car wheel?
    101874: 06/05/08: Mike Harrison: Re: Can an FPGA be operated reliably in a car wheel?
    101876: 06/05/08: Rene Tschaggelar: Re: Can an FPGA be operated reliably in a car wheel?
        101881: 06/05/08: Thomas Womack: Re: Can an FPGA be operated reliably in a car wheel?
            101885: 06/05/08: Rene Tschaggelar: Re: Can an FPGA be operated reliably in a car wheel?
                101889: 06/05/08: Thomas Womack: Re: Can an FPGA be operated reliably in a car wheel?
        101886: 06/05/08: Symon: Re: Can an FPGA be operated reliably in a car wheel?
            101888: 06/05/08: Symon: Re: Can an FPGA be operated reliably in a car wheel?
                101891: 06/05/08: Symon: Re: Can an FPGA be operated reliably in a car wheel?
                    101893: 06/05/08: Jan Panteltje: Re: Can an FPGA be operated reliably in a car wheel?
                101895: 06/05/08: Rene Tschaggelar: Re: Can an FPGA be operated reliably in a car wheel?
                    101899: 06/05/08: Symon: Re: Can an FPGA be operated reliably in a car wheel?
                        101921: 06/05/08: Symon: Re: Can an FPGA be operated reliably in a car wheel?
                            101924: 06/05/08: Symon: Re: Can an FPGA be operated reliably in a car wheel?
                                101926: 06/05/08: Austin Lesea: Re: Can an FPGA be operated reliably in a car wheel?
                                    101929: 06/05/08: Jan Panteltje: Re: Can an FPGA be operated reliably in a car wheel?
                                    101987: 06/05/09: Martin Thompson: Re: Can an FPGA be operated reliably in a car wheel?
                                        101994: 06/05/09: Austin Lesea: Re: Can an FPGA be operated reliably in a car wheel?
                                        101995: 06/05/09: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Re: Can an FPGA be operated reliably in a car wheel?
                                            102000: 06/05/09: Symon: Re: Can an FPGA be operated reliably in a car wheel?
                                                102060: 06/05/10: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Re: Can an FPGA be operated reliably in a car wheel?
                                101931: 06/05/08: John_H: Re: Can an FPGA be operated reliably in a car wheel?
                            101934: 06/05/09: Jim Granville: Re: Can an FPGA be operated reliably in a car wheel?
            101894: 06/05/08: John_H: Re: Can an FPGA be operated reliably in a car wheel?
                101898: 06/05/08: Symon: Re: Can an FPGA be operated reliably in a car wheel?
                    101900: 06/05/08: Symon: Re: Can an FPGA be operated reliably in a car wheel?
                        101915: 06/05/08: John_H: Re: Can an FPGA be operated reliably in a car wheel?
    101878: 06/05/08: <fpga_toys@yahoo.com>: Re: Can an FPGA be operated reliably in a car wheel?
    101916: 06/05/08: <fpga_toys@yahoo.com>: Re: Can an FPGA be operated reliably in a car wheel?
    101918: 06/05/08: Peter Alfke: Re: Can an FPGA be operated reliably in a car wheel?
    101923: 06/05/08: Peter Alfke: Re: Can an FPGA be operated reliably in a car wheel?
    101925: 06/05/08: <cs_posting@hotmail.com>: Re: Can an FPGA be operated reliably in a car wheel?
    101968: 06/05/08: Peter Alfke: Re: Can an FPGA be operated reliably in a car wheel?
    101972: 06/05/08: Peter Alfke: Re: Can an FPGA be operated reliably in a car wheel?
    102011: 06/05/09: <fpga_toys@yahoo.com>: Re: Can an FPGA be operated reliably in a car wheel?
101851: 06/05/07: chakra: booting problem ML300 :eth0: Could not read PHY control register; err
    101875: 06/05/08: Aurelian Lazarut: Re: booting problem ML300 :eth0: Could not read PHY control register;
    101913: 06/05/08: Peter Ryser: Re: booting problem ML300 :eth0: Could not read PHY control register;
    102128: 06/05/10: chakra: Re: booting problem ML300 :eth0: Could not read PHY control register; err
    102344: 06/05/15: chakra: Re: booting problem ML300 :eth0: Could not read PHY control register; err
101861: 06/05/07: water7: PCI Core compatibility
    101863: 06/05/07: Antti: Re: PCI Core compatibility
    101868: 06/05/08: water7: Re: PCI Core compatibility
    101869: 06/05/08: water7: Re: PCI Core compatibility
101871: 06/05/08: zeeman_be: Strange power up issue on Virtex4
    101887: 06/05/08: Anonymous: Re: Strange power up issue on Virtex4
    101890: 06/05/08: zeeman_be: Re: Strange power up issue on Virtex4
    101897: 06/05/08: Aurelian Lazarut: Re: Strange power up issue on Virtex4
        101912: 06/05/08: Aurelian Lazarut: Re: Strange power up issue on Virtex4
    101902: 06/05/08: zeeman_be: Re: Strange power up issue on Virtex4
    101903: 06/05/08: Antti: Re: Strange power up issue on Virtex4
    101907: 06/05/08: zeeman_be: Re: Strange power up issue on Virtex4
    101909: 06/05/08: Antti: Re: Strange power up issue on Virtex4
    101914: 06/05/08: zeeman_be: Re: Strange power up issue on Virtex4
101896: 06/05/08: jmariano: Installing BFM toolkit
    101970: 06/05/08: jenze: Re: Installing BFM toolkit
    102160: 06/05/11: jmariano: Re: Installing BFM toolkit
    102185: 06/05/11: jenze: Re: Installing BFM toolkit
101904: 06/05/08: wpiman@aol.com: Programming the JTAG flash in circuit
    101905: 06/05/08: johnp: Re: Programming the JTAG flash in circuit
    102079: 06/05/10: dscolson@rcn.com: Re: Programming the JTAG flash in circuit
    102273: 06/05/13: Ulf Samuelsson: Re: Programming the JTAG flash in circuit
101908: 06/05/08: SongDragon: PCI Express and DMA
    101910: 06/05/08: Jerry Coffin: Re: PCI Express and DMA
    101911: 06/05/08: John_H: Re: PCI Express and DMA
    101953: 06/05/09: Mark McDougall: Re: PCI Express and DMA
        102001: 06/05/09: SongDragon: Re: PCI Express and DMA
            102041: 06/05/10: Mark McDougall: Re: PCI Express and DMA
                102042: 06/05/10: Mark McDougall: Re: PCI Express and DMA
                    102130: 06/05/11: Mark McDougall: Re: PCI Express and DMA
            103540: 06/06/05: Kevin Irick: Re: PCI Express and DMA
    102065: 06/05/10: Antti: Re: PCI Express and DMA
101933: 06/05/09: Jim Granville: Putting the Ring into Ring oscillators
    101944: 06/05/08: Mike Harrison: Re: Putting the Ring into Ring oscillators
        101957: 06/05/08: John Larkin: Re: Putting the Ring into Ring oscillators
    101952: 06/05/09: Ulrich Bangert: Re: Putting the Ring into Ring oscillators
    101973: 06/05/09: Kolja Sulimma: Re: Putting the Ring into Ring oscillators
        101975: 06/05/09: Jim Granville: Re: Putting the Ring into Ring oscillators
            101999: 06/05/09: Kolja Sulimma: Re: Putting the Ring into Ring oscillators
                102017: 06/05/10: Jim Granville: Re: Putting the Ring into Ring oscillators
                    102026: 06/05/09: Kolja Sulimma: Re: Putting the Ring into Ring oscillators
101935: 06/05/08: Mike Harrison: UK source for Digilent S3 board?
    101983: 06/05/09: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: UK source for Digilent S3 board?
        101997: 06/05/09: Mike Harrison: Re: UK source for Digilent S3 board?
101938: 06/05/08: Peter Alfke: Re: Xilinx 3s8000?
101976: 06/05/09: ALuPin@web.de: Crossing clock domains
    101978: 06/05/09: Symon: Re: Crossing clock domains
        101984: 06/05/09: Symon: Re: Crossing clock domains
    101979: 06/05/09: ALuPin@web.de: Re: Crossing clock domains
    101980: 06/05/09: c d saunter: Re: Crossing clock domains
    101986: 06/05/09: ALuPin@web.de: Re: Crossing clock domains
    101996: 06/05/09: Peter Alfke: Re: Crossing clock domains
    102266: 06/05/12: Philip Freidin: Re: Crossing clock domains
101981: 06/05/09: =?iso-8859-1?B?VPRG?=: Chipscope and FPGA
    101982: 06/05/09: Antti: Re: Chipscope and FPGA
101985: 06/05/09: kaps: help me to about clock in fpga
    102007: 06/05/09: Slurp: Re: help me to about clock in fpga
        102012: 06/05/09: <MikeShepherd564@btinternet.com>: Re: help me to about clock in fpga
            102019: 06/05/09: Slurp: Re: help me to about clock in fpga
101989: 06/05/09: Johnschool: Using vector condition at transition in StateCAD
101992: 06/05/09: Sanka Piyaratna: Xilinx ISE 8.1 Makefile
    102005: 06/05/09: Sean Durkin: Re: Xilinx ISE 8.1 Makefile
        102074: 06/05/10: Joseph Samson: Re: Xilinx ISE 8.1 Makefile
    102014: 06/05/09: John Retta: Re: Xilinx ISE 8.1 Makefile
    102061: 06/05/10: backhus: Re: Xilinx ISE 8.1 Makefile
        102067: 06/05/10: =?ISO-8859-1?Q?Michael_Sch=F6berl?=: Re: Xilinx ISE 8.1 Makefile
    102142: 06/05/11: Zara: Re: Xilinx ISE 8.1 Makefile
    102194: 06/05/11: Jim Wu: Re: Xilinx ISE 8.1 Makefile
102003: 06/05/09: <topweaver@hotmail.com>: TME Free Verilog/VHDL framework generation tool
102008: 06/05/09: George Orwell: Max operating freq in a breadboard
102010: 06/05/09: Anonymous: ml-403 and USB
    102029: 06/05/10: John Williams: Re: ml-403 and USB
102016: 06/05/09: Luke: Superscalar Out-of-Order Processor on an FPGA
    102020: 06/05/09: Stephen Craven: Re: Superscalar Out-of-Order Processor on an FPGA
    102023: 06/05/09: JJ: Re: Superscalar Out-of-Order Processor on an FPGA
        102037: 06/05/09: Eric Smith: Re: Superscalar Out-of-Order Processor on an FPGA
            102080: 06/05/10: =?ISO-8859-1?Q?G=F6ran_Bilski?=: Re: Superscalar Out-of-Order Processor on an FPGA
                102091: 06/05/10: Falk Brunner: Re: Superscalar Out-of-Order Processor on an FPGA
        102047: 06/05/10: Jim Granville: Re: Superscalar Out-of-Order Processor on an FPGA
            102121: 06/05/11: Jim Granville: Re: Superscalar Out-of-Order Processor on an FPGA
    102025: 06/05/09: Luke: Re: Superscalar Out-of-Order Processor on an FPGA
    102027: 06/05/09: Luke: Re: Superscalar Out-of-Order Processor on an FPGA
    102033: 06/05/09: JJ: Re: Superscalar Out-of-Order Processor on an FPGA
    102035: 06/05/09: Luke: Re: Superscalar Out-of-Order Processor on an FPGA
    102039: 06/05/09: Luke: Re: Superscalar Out-of-Order Processor on an FPGA
    102045: 06/05/09: JJ: Re: Superscalar Out-of-Order Processor on an FPGA
    102054: 06/05/10: Henry Wong: Re: Superscalar Out-of-Order Processor on an FPGA
        102675: 06/05/19: Eric Smith: Re: Superscalar Out-of-Order Processor on an FPGA
            102755: 06/05/19: Eric Smith: Re: Superscalar Out-of-Order Processor on an FPGA
            102827: 06/05/21: Tommy Thorn: Re: Superscalar Out-of-Order Processor on an FPGA
                102905: 06/05/23: Eric Smith: Re: Superscalar Out-of-Order Processor on an FPGA
                    102911: 06/05/23: Kolja Sulimma: Re: Superscalar Out-of-Order Processor on an FPGA
                    102939: 06/05/23: Dave: Re: Superscalar Out-of-Order Processor on an FPGA
                        103030: 06/05/24: Eric Smith: Re: Superscalar Out-of-Order Processor on an FPGA
                            103033: 06/05/24: Austin Lesea: Re: Superscalar Out-of-Order Processor on an FPGA
                        103034: 06/05/24: Eric Smith: Re: Superscalar Out-of-Order Processor on an FPGA
            103044: 06/05/25: Henry Wong: Re: Superscalar Out-of-Order Processor on an FPGA
                103219: 06/05/29: Ben Jones: Re: Superscalar Out-of-Order Processor on an FPGA
            103206: 06/05/29: Daniel O'Connor: Re: Superscalar Out-of-Order Processor on an FPGA
    102072: 06/05/10: Luke: Re: Superscalar Out-of-Order Processor on an FPGA
    102097: 06/05/10: Luke: Re: Superscalar Out-of-Order Processor on an FPGA
    102102: 06/05/10: JJ: Re: Superscalar Out-of-Order Processor on an FPGA
    102109: 06/05/10: Stephen Craven: Re: Superscalar Out-of-Order Processor on an FPGA
    102120: 06/05/10: JJ: Re: Superscalar Out-of-Order Processor on an FPGA
    102124: 06/05/10: Isaac Bosompem: Re: Superscalar Out-of-Order Processor on an FPGA
    102125: 06/05/10: Isaac Bosompem: Re: Superscalar Out-of-Order Processor on an FPGA
    102631: 06/05/18: alpha: Re: Superscalar Out-of-Order Processor on an FPGA
    102747: 06/05/19: alpha: Re: Superscalar Out-of-Order Processor on an FPGA
    102900: 06/05/22: alpha: Re: Superscalar Out-of-Order Processor on an FPGA
    102920: 06/05/23: Uncle Noah: Re: Superscalar Out-of-Order Processor on an FPGA
    102941: 06/05/23: alpha: Re: Superscalar Out-of-Order Processor on an FPGA
    102942: 06/05/23: JJ: Re: Superscalar Out-of-Order Processor on an FPGA
    103164: 06/05/26: alpha: Re: Superscalar Out-of-Order Processor on an FPGA
102031: 06/05/09: DC: constraints for DDR bus with 133MHz write and 66Mhz read clocks
    102032: 06/05/09: John_H: Re: constraints for DDR bus with 133MHz write and 66Mhz read clocks
        102043: 06/05/10: John_H: Re: constraints for DDR bus with 133MHz write and 66Mhz read clocks
    102040: 06/05/09: DC: Re: constraints for DDR bus with 133MHz write and 66Mhz read clocks
102046: 06/05/09: <sandeepbabel@gmail.com>: simulation works fine but the actual chip doesnt work
    102052: 06/05/10: Mark McDougall: Re: simulation works fine but the actual chip doesnt work
        102202: 06/05/12: Mark McDougall: Re: simulation works fine but the actual chip doesnt work
    102199: 06/05/11: <sandeepbabel@gmail.com>: Re: simulation works fine but the actual chip doesnt work
    102217: 06/05/11: sandeep: Re: simulation works fine but the actual chip doesnt work
    102218: 06/05/11: sandeep: Re: simulation works fine but the actual chip doesnt work
    102350: 06/05/15: sandeep: Re: simulation works fine but the actual chip doesnt work
102049: 06/05/09: Keith Williams: Altera Max Plus II to Quartus migration tool
    102063: 06/05/10: Ben Twijnstra: Re: Altera Max Plus II to Quartus migration tool
    102111: 06/05/10: Subroto Datta: Re: Altera Max Plus II to Quartus migration tool
    102132: 06/05/10: Keith Williams: Re: Altera Max Plus II to Quartus migration tool
102053: 06/05/09: Ashish: Interrupt signal sampling (Level or edge?)
    102055: 06/05/09: <ghelbig@gmail.com>: Re: Interrupt signal sampling (Level or edge?)
    102056: 06/05/09: Ashish: Re: Interrupt signal sampling (Level or edge?)
    102136: 06/05/10: <ghelbig@lycos.com>: Re: Interrupt signal sampling (Level or edge?)
    102137: 06/05/10: Peter Alfke: Re: Interrupt signal sampling (Level or edge?)
    102143: 06/05/10: Ashish: Re: Interrupt signal sampling (Level or edge?)
    102144: 06/05/11: Jim Granville: Re: Interrupt signal sampling (Level or edge?)
102059: 06/05/09: vssumesh: Routing problem in PAR.
    102062: 06/05/10: vssumesh: Re: Routing problem in PAR.
    102122: 06/05/10: Jim Wu: Re: Routing problem in PAR.
102064: 06/05/10: Raymond: Unable to debug MicroBlaze in SDK (Eclipse) and the Software debugger
102069: 06/05/10: phoenix: jhdlbits: source files
102070: 06/05/10: YiQi: EDIF simulator???
102071: 06/05/10: Leon: Quartus II 6.0 available
    102078: 06/05/10: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Quartus II 6.0 available
        102093: 06/05/10: Uwe Bonnes: Re: Quartus II 6.0 available
            102095: 06/05/10: Mike Treseler: Re: Quartus II 6.0 available
    102096: 06/05/10: Jan Panteltje: Re: Quartus II 6.0 available
102075: 06/05/10: Eli Hughes: CoolRunner XPLA3 getting axed?
    102081: 06/05/10: Falk Brunner: Re: CoolRunner XPLA3 getting axed?
        102082: 06/05/10: Eli Hughes: Re: CoolRunner XPLA3 getting axed?
            102085: 06/05/10: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: CoolRunner XPLA3 getting axed?
            102088: 06/05/10: Falk Brunner: Re: CoolRunner XPLA3 getting axed?
                102162: 06/05/11: Martin Thompson: Re: CoolRunner XPLA3 getting axed?
                    102174: 06/05/11: nospam: Re: CoolRunner XPLA3 getting axed?
                    102179: 06/05/11: Falk Brunner: Re: CoolRunner XPLA3 getting axed?
                        102238: 06/05/12: Martin Thompson: Re: CoolRunner XPLA3 getting axed?
                    102237: 06/05/12: Mike Harrison: Re: CoolRunner XPLA3 getting axed?
    102092: 06/05/10: dp: Re: CoolRunner XPLA3 getting axed?
        102094: 06/05/10: Falk Brunner: Re: CoolRunner XPLA3 getting axed?
            102099: 06/05/10: Eli Hughes: Re: CoolRunner XPLA3 getting axed?
                102103: 06/05/10: Austin Lesea: Re: CoolRunner XPLA3 getting axed?
                    102113: 06/05/11: Jim Granville: Re: CoolRunner XPLA3 getting axed?
            102112: 06/05/11: Jim Granville: Re: CoolRunner XPLA3 getting axed?
                102123: 06/05/11: Jim Granville: Re: CoolRunner XPLA3 getting axed?
            102156: 06/05/11: Mike Harrison: Re: CoolRunner XPLA3 getting axed?
    102098: 06/05/10: Peter Alfke: Re: CoolRunner XPLA3 getting axed?
    102100: 06/05/10: bart: Re: CoolRunner XPLA3 getting axed?
        102105: 06/05/10: Eli Hughes: Re: CoolRunner XPLA3 getting axed?
    102115: 06/05/10: Peter Alfke: Re: CoolRunner XPLA3 getting axed?
    102181: 06/05/11: Antti: Re: CoolRunner XPLA3 getting axed?
    102182: 06/05/11: bart: Re: CoolRunner XPLA3 getting axed?
102076: 06/05/10: Franco Tiratore: [Newbie] 64-point complex FFT with 32 bit floating-point representation
    102118: 06/05/10: dal: Re: [Newbie] 64-point complex FFT with 32 bit floating-point representation
        102159: 06/05/11: Andy Ray: Re: 64-point complex FFT with 32 bit floating-point representation
    102151: 06/05/11: Franco Tiratore: Re: 64-point complex FFT with 32 bit floating-point representation
    102154: 06/05/11: A.D.: Re: [Newbie] 64-point complex FFT with 32 bit floating-point representation
    102163: 06/05/11: Franco Tiratore: Re: 64-point complex FFT with 32 bit floating-point representation
    102165: 06/05/11: Franco Tiratore: Re: 64-point complex FFT with 32 bit floating-point representation
    102184: 06/05/11: Ray Andraka: Re: [Newbie] 64-point complex FFT with 32 bit floating-point representation
        102243: 06/05/12: Ray Andraka: Re: 64-point complex FFT with 32 bit floating-point representation
    102224: 06/05/12: Franco Tiratore: Re: 64-point complex FFT with 32 bit floating-point representation
    102249: 06/05/12: Franco Tiratore: Re: 64-point complex FFT with 32 bit floating-point representation
102077: 06/05/10: Eli Hughes: Altera Equiv.
    102114: 06/05/11: Jim Granville: Re: Altera Equiv.
    102131: 06/05/11: Rob: Re: Altera Equiv.
        102205: 06/05/12: Rob: Re: Altera Equiv.
    102198: 06/05/11: Paul Leventis: Re: Altera Equiv.
    102605: 06/05/17: Atmel_PLDs_Rock: Re: Altera Equiv.
102083: 06/05/10: dp: Re: CoolRunner XPLA3 getting axed?
    102090: 06/05/10: Falk Brunner: Re: CoolRunner XPLA3 getting axed?
102089: 06/05/10: Antti: Re: CoolRunner XPLA3 getting axed?
102107: 06/05/10: Peter Alfke: CoolRunner XPLA3 thriving for many years to come
    102117: 06/05/10: Antti Lukats: Re: CoolRunner XPLA3 thriving for many years to come
        102127: 06/05/11: Jim Granville: Re: CoolRunner XPLA3 thriving for many years to come
    102135: 06/05/10: Peter Alfke: Re: CoolRunner XPLA3 thriving for many years to come
102133: 06/05/10: srini: Xilinx warning for DCM
    102138: 06/05/10: Peter Alfke: Re: Xilinx warning for DCM
        102178: 06/05/11: Austin Lesea: Re: Xilinx warning for DCM
102134: 06/05/10: binaryboy: reverse engineering ?
    102139: 06/05/10: <fpga_toys@yahoo.com>: Re: reverse engineering ?
        102180: 06/05/11: Austin Lesea: Re: reverse engineering ?
            102192: 06/05/11: Austin Lesea: Re: reverse engineering ?
            102200: 06/05/11: Austin Lesea: Re: reverse engineering ?
                102219: 06/05/12: Jim Granville: Re: reverse engineering ?
                102223: 06/05/12: David Brown: Re: reverse engineering ?
    102186: 06/05/11: JJ: Re: reverse engineering ?
        102204: 06/05/12: <MikeShepherd564@btinternet.com>: Re: reverse engineering ?
            102269: 06/05/12: Eric Smith: Re: reverse engineering ?
                102286: 06/05/14: <MikeShepherd564@btinternet.com>: Re: reverse engineering ?
                    102382: 06/05/15: <MikeShepherd564@btinternet.com>: Re: reverse engineering ?
            102292: 06/05/14: dp: Re: reverse engineering ?
            102302: 06/05/14: <fpga_toys@yahoo.com>: Re: reverse engineering ?
    102187: 06/05/11: <fpga_toys@yahoo.com>: Re: reverse engineering ?
    102189: 06/05/11: <fpga_toys@yahoo.com>: Re: reverse engineering ?
    102190: 06/05/11: <fpga_toys@yahoo.com>: Re: reverse engineering ?
    102193: 06/05/11: <fpga_toys@yahoo.com>: Re: reverse engineering ?
    102197: 06/05/11: <fpga_toys@yahoo.com>: Re: reverse engineering ?
    102206: 06/05/11: <fpga_toys@yahoo.com>: Re: reverse engineering ?
    102208: 06/05/11: JJ: Re: reverse engineering ?
    102209: 06/05/11: <fpga_toys@yahoo.com>: Re: reverse engineering ?
    102211: 06/05/11: <fpga_toys@yahoo.com>: Re: reverse engineering ?
        102412: 06/05/15: dp: Re: reverse engineering ?
    102212: 06/05/11: JJ: Re: reverse engineering ?
    102216: 06/05/11: <fpga_toys@yahoo.com>: Re: reverse engineering ?
    102221: 06/05/11: <fpga_toys@yahoo.com>: Re: reverse engineering ?
    102226: 06/05/12: <fpga_toys@yahoo.com>: Re: reverse engineering ?
    102267: 06/05/12: Weng Tianxiang: Re: reverse engineering ?
    102268: 06/05/12: dp: Re: reverse engineering ?
    102274: 06/05/13: Weng Tianxiang: Re: reverse engineering ?
    102280: 06/05/13: <fpga_toys@yahoo.com>: Re: reverse engineering ?
    102610: 06/05/17: <fpga_toys@yahoo.com>: Re: reverse engineering ?
102140: 06/05/10: Devlin: How can I deal with the output signal in testbech?
    102161: 06/05/11: Devlin: Re: How can I deal with the output signal in testbech?
102141: 06/05/10: Devlin: How can I get internal signal in modelsim.(Xlinx ISE),timing-simulation
102145: 06/05/11: Mark McDougall: XCFxxP Plaform Flash Device Questions
    102146: 06/05/11: Alan Nishioka: Re: XCFxxP Plaform Flash Device Questions
        102147: 06/05/11: Mark McDougall: Re: XCFxxP Plaform Flash Device Questions
    102150: 06/05/11: Antti: Re: XCFxxP Plaform Flash Device Questions
    102171: 06/05/11: Alan Nishioka: Re: XCFxxP Plaform Flash Device Questions
102148: 06/05/11: Marko S: sqrt(a^2 + b^2) in synthesizable VHDL?
    102152: 06/05/11: =?ISO-8859-15?Q?Michael_Sch=F6berl?=: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
        102158: 06/05/11: Symon: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
            102166: 06/05/11: Marko S: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
                102183: 06/05/11: Ray Andraka: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
                    102234: 06/05/12: Trainee: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
                102207: 06/05/12: jtw: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
    102153: 06/05/11: Ad: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
    102155: 06/05/11: Kolja Sulimma: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
    102157: 06/05/11: Ad: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
    102196: 06/05/11: gaurav.vaidya2000@gmail.com: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
        102255: 06/05/12: Slurp: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
102149: 06/05/11: Antti: MicroBlaze GPIO 1-bit [resistor], funny story :)
102164: 06/05/11: Peter Mendham: Power for Spartan 3
    102314: 06/05/15: John Adair: Re: Power for Spartan 3
        102318: 06/05/15: Peter Mendham: Re: Power for Spartan 3
            102322: 06/05/15: Aurelian Lazarut: Re: Power for Spartan 3
                102333: 06/05/15: Peter Mendham: Re: Power for Spartan 3
            102335: 06/05/15: John Adair: Re: Power for Spartan 3
            102342: 06/05/15: Greg Neff: Re: Power for Spartan 3
                102432: 06/05/16: Peter Mendham: Re: Power for Spartan 3
        102332: 06/05/15: Peter Mendham: Re: Power for Spartan 3
            102396: 06/05/16: Jim Granville: Re: Power for Spartan 3
                102431: 06/05/16: Peter Mendham: Re: Power for Spartan 3
                    102511: 06/05/17: Martin Thompson: Re: Power for Spartan 3
            102510: 06/05/17: Peter Mendham: Re: Power for Spartan 3
                102539: 06/05/17: Greg Neff: Re: Power for Spartan 3
                    102621: 06/05/18: Peter Mendham: Re: Power for Spartan 3
    102316: 06/05/15: rickman: Re: Power for Spartan 3
    102448: 06/05/16: rickman: Re: Power for Spartan 3
102167: 06/05/11: Marko S: ISE 8.1 error, help. Or where is the path?
    102169: 06/05/11: Aurelian Lazarut: Re: ISE 8.1 error, help. Or where is the path?
        102170: 06/05/11: Marko S: Re: ISE 8.1 error, help. Or where is the path?
102168: 06/05/11: srini: Synplify - Not satisfactory results with re-timing option
    102172: 06/05/11: Amal: Re: Synplify - Not satisfactory results with re-timing option
    102177: 06/05/11: Hans: Re: Synplify - Not satisfactory results with re-timing option
    102215: 06/05/11: Phil Hays: Re: Synplify - Not satisfactory results with re-timing option
        102271: 06/05/13: Phil Hays: Re: Synplify - Not satisfactory results with re-timing option
    102228: 06/05/12: srini: Re: Synplify - Not satisfactory results with re-timing option
102175: 06/05/11: Antti: Re: CoolRunner XPLA3 getting axed?
102176: 06/05/11: Subhasri krishnan: can increase simulation run time while running modelsim?
    102195: 06/05/11: gaurav.vaidya2000@gmail.com: Re: can increase simulation run time while running modelsim?
    102203: 06/05/11: Andy Peters: Re: can increase simulation run time while running modelsim?
102201: 06/05/11: Luke: Multiple Write Port Register Files
    102210: 06/05/11: JJ: Re: Multiple Write Port Register Files
        102242: 06/05/12: John_H: Re: Multiple Write Port Register Files
    102258: 06/05/12: Luke: Re: Multiple Write Port Register Files
102220: 06/05/12: Jean Nicolle: JTAG tutorial
    102227: 06/05/12: <MikeShepherd564@btinternet.com>: Re: JTAG tutorial
        102260: 06/05/12: Jean Nicolle: Re: JTAG tutorial
    102232: 06/05/12: Jan Panteltje: Re: JTAG tutorial
    102236: 06/05/12: Eli Hughes: Re: JTAG tutorial
        102261: 06/05/12: Jean Nicolle: Re: JTAG tutorial
            102326: 06/05/15: Matt Clement: Re: JTAG tutorial
    102245: 06/05/12: Ad: Re: JTAG tutorial
102222: 06/05/12: Ashish: clock multiplier in spartan 2
    102225: 06/05/12: Ico: Re: clock multiplier in spartan 2
    102229: 06/05/12: Ashish: Re: clock multiplier in spartan 2
    102263: 06/05/12: Gabor: Re: clock multiplier in spartan 2
    102264: 06/05/12: Peter Alfke: Re: clock multiplier in spartan 2
102230: 06/05/12: srini: How to check IOB register packing?
    102233: 06/05/12: Joseph Samson: Re: How to check IOB register packing?
        102252: 06/05/12: Joseph Samson: Re: How to check IOB register packing?
    102235: 06/05/12: Jim Wu: Re: How to check IOB register packing?
        102244: 06/05/12: Ray Andraka: Re: How to check IOB register packing?
            102272: 06/05/13: Phil Hays: Re: How to check IOB register packing?
                102307: 06/05/14: Bob Perlman: Re: How to check IOB register packing?
    102246: 06/05/12: srini: Re: How to check IOB register packing?
    102251: 06/05/12: John_H: Re: How to check IOB register packing?
        102253: 06/05/12: Symon: Re: How to check IOB register packing?
    102283: 06/05/13: srini: Re: How to check IOB register packing?
    102306: 06/05/14: srini: Re: How to check IOB register packing?
102231: 06/05/12: YiQi: difference of variable and signal
    102265: 06/05/12: Jim_B: Re: difference of variable and signal
        102317: 06/05/15: Falk Salewski: Re: difference of variable and signal
            102320: 06/05/15: Falk Brunner: Re: difference of variable and signal
                102328: 06/05/15: Ralf Hildebrandt: Re: difference of variable and signal
    102270: 06/05/12: YiQi: Re: difference of variable and signal
    102324: 06/05/15: YiQi: Re: difference of variable and signal
102241: 06/05/12: srini: How to decide Fanout limit?
    102247: 06/05/12: Rene Tschaggelar: Re: How to decide Fanout limit?
    102248: 06/05/12: Brannon: Re: How to decide Fanout limit?
    102250: 06/05/12: John_H: Re: How to decide Fanout limit?
        102290: 06/05/14: John_H: Re: How to decide Fanout limit?
            102300: 06/05/14: Austin Lesea: Re: How to decide Fanout limit?
        102758: 06/05/19: Ken McElvain: Re: How to decide Fanout limit?
    102284: 06/05/14: srini: Re: How to decide Fanout limit?
    102305: 06/05/14: srini: Re: How to decide Fanout limit?
102254: 06/05/12: Colin Hankins: Synchronous Scrambler
    102256: 06/05/12: Austin Lesea: Re: Synchronous Scrambler
    102323: 06/05/15: sovan: Re: Synchronous Scrambler
    102336: 06/05/15: Colin Hankins: Re: Synchronous Scrambler
102259: 06/05/12: Hari Kannan: ISE 7.1 synthesis problems
    102262: 06/05/12: unfrostedpoptart: Re: ISE 7.1 synthesis problems
102275: 06/05/13: <roiavidan@gmail.com>: altera cyclone memory example
    102276: 06/05/13: Antti: Re: altera cyclone memory example
    102277: 06/05/13: David Brown: Re: altera cyclone memory example
    102279: 06/05/13: Rob: Re: altera cyclone memory example
        102312: 06/05/15: =?ISO-8859-1?Q?Michael_Sch=F6berl?=: Re: altera cyclone memory example
        104184: 06/06/20: Jerry: Re: altera cyclone memory example
    102288: 06/05/14: <roiavidan@gmail.com>: Re: altera cyclone memory example
    102289: 06/05/14: Antti: Re: altera cyclone memory example
102278: 06/05/13: Jack Daly: Trouble understanding Synplicity timing report
    102281: 06/05/13: Jack Daly: Re: Trouble understanding Synplicity timing report
102282: 06/05/13: light: filter design
    102285: 06/05/14: <MikeShepherd564@btinternet.com>: Re: filter design
    102414: 06/05/15: light: Re: filter design
102287: 06/05/14: Wiljan: Picture frame
102291: 06/05/14: Piotr Wyderski: Spartan 3E
    102293: 06/05/14: Uwe Bonnes: Re: Spartan 3E
        102294: 06/05/14: Piotr Wyderski: Re: Spartan 3E
            102297: 06/05/14: Uwe Bonnes: Re: Spartan 3E
            102298: 06/05/14: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Spartan 3E
    102301: 06/05/14: Austin Lesea: Re: Spartan 3E
        102476: 06/05/16: Tobias Weingartner: Re: Spartan 3E
            102479: 06/05/16: Falk Brunner: Re: Spartan 3E
            102484: 06/05/16: Uwe Bonnes: Re: Spartan 3E
    102493: 06/05/16: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan 3E
        102777: 06/05/20: Piotr Wyderski: Re: Spartan 3E
102295: 06/05/14: Xavier T: Raggedstone IO bracket ?
    102313: 06/05/15: John Adair: Re: Raggedstone IO bracket ?
    102578: 06/05/17: Xavier T: Re: Raggedstone IO bracket ?
102296: 06/05/14: Xavier T: Amontec Komodo board ?
    102310: 06/05/14: Antti: Re: Amontec Komodo board ?
102299: 06/05/14: Andreas Ehliar: Floating point reality check
    102303: 06/05/14: Ray Andraka: Re: Floating point reality check
        102418: 06/05/15: Kevin Neilson: Re: Floating point reality check
            102447: 06/05/16: Ray Andraka: Re: Floating point reality check
                102465: 06/05/16: Per =?iso-8859-1?Q?Karlstr=F6m?=: Re: Floating point reality check
                    103136: 06/05/25: Ray Andraka: Re: Floating point reality check
102304: 06/05/14: vlir_c8: Files.ucf QAM Demodulators for Xtreme DSP Development KIT
102308: 06/05/14: <shawnn@gmail.com>: getting good deals on small qty?
    102309: 06/05/14: Antti: Re: getting good deals on small qty?
    102353: 06/05/15: dalai lamah: Re: getting good deals on small qty?
    102369: 06/05/15: <shawnn@gmail.com>: Re: getting good deals on small qty?
    102388: 06/05/15: Peter Alfke: Re: getting good deals on small qty?
        102433: 06/05/16: Nial Stewart: Re: getting good deals on small qty?
            102505: 06/05/17: <MikeShepherd564@btinternet.com>: Re: getting good deals on small qty?
            102546: 06/05/17: =?ISO-8859-1?Q?Michael_Sch=F6berl?=: Re: getting good deals on small qty?
                102567: 06/05/17: Uwe Bonnes: Re: getting good deals on small qty?
                102960: 06/05/24: Daniel O'Connor: Re: getting good deals on small qty?
                    102968: 06/05/24: Uwe Bonnes: Re: getting good deals on small qty?
    102393: 06/05/15: <shawnn@gmail.com>: Re: getting good deals on small qty?
    102400: 06/05/15: Antti: Re: getting good deals on small qty?
    102441: 06/05/16: gallen: Re: getting good deals on small qty?
    102483: 06/05/16: Jeff Brower: Re: getting good deals on small qty?
    102485: 06/05/16: bart: Re: getting good deals on small qty?
    102487: 06/05/16: Peter Alfke: Re: getting good deals on small qty?
    102551: 06/05/17: Peter Alfke: Re: getting good deals on small qty?
    102604: 06/05/17: Atmel_PLDs_Rock: Re: getting good deals on small qty?
        102623: 06/05/18: Uwe Bonnes: Re: getting good deals on small qty?
102311: 06/05/14: srini: How to decide Setup/Hold time values ?
    102331: 06/05/15: Phil Hays: Re: How to decide Setup/Hold time values ?
102315: 06/05/15: Falk Salewski: safety critical applications with FPGAs/CPLDs
    102321: 06/05/15: Ad: Re: safety critical applications with FPGAs/CPLDs
        102427: 06/05/16: Falk Salewski: Re: safety critical applications with FPGAs/CPLDs
    102429: 06/05/16: Ad: Re: safety critical applications with FPGAs/CPLDs
102319: 06/05/15: Jim Wu: Re: Assigning MGT's in sample Aurora Design
102325: 06/05/15: Morten Leikvoll: Make a signal free for glitches?
    102346: 06/05/15: Falk Brunner: Re: Make a signal free for glitches?
    102363: 06/05/15: Peter Alfke: Re: Make a signal free for glitches?
        102421: 06/05/16: Morten Leikvoll: Re: Make a signal free for glitches?
        102422: 06/05/16: Morten Leikvoll: Re: Make a signal free for glitches?
            102570: 06/05/17: Eric Smith: Re: Make a signal free for glitches?
                102694: 06/05/19: Morten Leikvoll: Re: Make a signal free for glitches?
        102613: 06/05/18: Jim Granville: Re: Make a signal free for glitches?
    102442: 06/05/16: Peter Alfke: Re: Make a signal free for glitches?
    102576: 06/05/17: Peter Alfke: Re: Make a signal free for glitches?
    102612: 06/05/17: <fpga_toys@yahoo.com>: Re: Make a signal free for glitches?
    102697: 06/05/19: Antti: Re: Make a signal free for glitches?
102327: 06/05/15: Marco: pull-ups and jtag questions
    102329: 06/05/15: Antti: Re: pull-ups and jtag questions
    102330: 06/05/15: Ad: Re: pull-ups and jtag questions
    102334: 06/05/15: Marco: Re: pull-ups and jtag questions
    102337: 06/05/15: Ad: Re: pull-ups and jtag questions
102338: 06/05/15: <soar2morrow@yahoo.com>: IEEE-1394 (aka FireWire) Core
    102525: 06/05/17: Felix Bertram: Re: IEEE-1394 (aka FireWire) Core
        102547: 06/05/17: =?ISO-8859-1?Q?Michael_Sch=F6berl?=: Re: IEEE-1394 (aka FireWire) Core
            102557: 06/05/17: =?ISO-8859-1?Q?St=E9phane_Goujet?=: Re: IEEE-1394 (aka FireWire) Core
            102561: 06/05/17: MM: Re: IEEE-1394 (aka FireWire) Core
            102579: 06/05/17: Felix Bertram: Re: IEEE-1394 (aka FireWire) Core
    102584: 06/05/17: Andy Peters: Re: IEEE-1394 (aka FireWire) Core
    102599: 06/05/17: <soar2morrow@yahoo.com>: Re: IEEE-1394 (aka FireWire) Core
102339: 06/05/15: ryanrs: Virtex 5 announced
    102345: 06/05/15: Austin Lesea: Re: Virtex 5 announced
        102347: 06/05/15: Josh Rosen: Re: Virtex 5 announced
            102349: 06/05/15: Austin Lesea: Re: Virtex 5 announced
                102355: 06/05/15: <lb.edc@telenet.be>: Re: Virtex 5 announced
                    102361: 06/05/15: Austin Lesea: Re: Virtex 5 announced and sampling
                        102365: 06/05/15: Austin Lesea: Re: Virtex 5 announced and sampling ... and real!
                            102372: 06/05/15: John_H: Re: Virtex 5 announced and sampling ... and real!
                                102381: 06/05/16: Jim Granville: Re: Virtex 5 announced and sampling ... and real!
                                    102392: 06/05/15: Austin Lesea: Re: Virtex 5 announced and sampling ... and real!
                                        102404: 06/05/16: Jim Granville: Re: Virtex 5 announced and sampling ... and real!
                                        103309: 06/05/30: Austin Lesea: Re: Virtex 5 announced and sampling ... and real!
                                            103310: 06/05/30: Austin Lesea: Re: Virtex 5 announced and sampling ... and real!
                                            103315: 06/05/31: Jim Granville: Re: Virtex 5 announced and sampling ... and real!
                            102385: 06/05/15: Uwe Bonnes: Re: Virtex 5 announced and sampling ... and real!
                                102394: 06/05/15: Austin Lesea: Re: Virtex 5 announced and sampling ... and real!
                                    102406: 06/05/15: John_H: Re: Virtex 5 announced and sampling ... and real!
                                        102411: 06/05/15: Austin Lesea: Re: Virtex 5 announced and sampling ... and real!
                        102370: 06/05/15: David Brown: Re: Virtex 5 announced and sampling
                        102373: 06/05/15: Kolja Sulimma: Re: Virtex 5 announced and sampling
                            102387: 06/05/15: Antti Lukats: Re: Virtex 5 announced and sampling
                        102374: 06/05/15: Ed McGettigan: Re: Virtex 5 announced and sampling
                            102377: 06/05/15: Kolja Sulimma: Re: Virtex 5 announced and sampling
                            102386: 06/05/15: Antti Lukats: Re: Virtex 5 announced and sampling
                                102395: 06/05/15: Antti Lukats: Re: Virtex 5 announced and sampling
                                102398: 06/05/16: Jim Granville: Re: Virtex 5 announced and sampling
                                    102399: 06/05/15: Antti Lukats: Re: Virtex 5 announced and sampling
                                        102402: 06/05/15: Austin Lesea: Re: Virtex 5 announced and sampling
                                    102410: 06/05/16: Jim Granville: Re: Virtex 5 announced and sampling
                                    102462: 06/05/16: Marc Reinig: Re: Virtex 5 announced and sampling
                                        102464: 06/05/16: Austin Lesea: Re: Virtex 5 announced and sampling
                                        103040: 06/05/24: Ray Andraka: Re: Virtex 5 announced and sampling
                                102407: 06/05/15: John_H: Re: Virtex 5 announced and sampling
                                    102437: 06/05/16: Kolja Sulimma: Re: Virtex 5 announced and sampling
                        102376: 06/05/15: Falk Brunner: Re: Virtex 5 announced and sampling
                            102380: 06/05/15: Austin Lesea: Re: Virtex 5 announced and sampling
                        102401: 06/05/15: Austin Lesea: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
                            102403: 06/05/15: Josh Rosen: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
                            102594: 06/05/18: Ben Twijnstra: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
                                102597: 06/05/17: Austin Lesea: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
                                    102654: 06/05/18: Austin Lesea: Re: Virtex 5 announced and sampling: now we just wait?
                                    102666: 06/05/19: Jim Granville: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
                                    102701: 06/05/19: Tim: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
                                    102712: 06/05/19: David Brown: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
                                    102791: 06/05/21: Jim Granville: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
                                        102882: 06/05/22: Eric Smith: QuickLogic PolarPro (was Re: Virtex 5 announced and sampling: apologia for FX woes on V4)
                102356: 06/05/15: Austin Lesea: Re: Virtex 5 announced
        102357: 06/05/15: Austin Lesea: Re: Virtex 5 announced
            102368: 06/05/15: Austin Lesea: Re: Virtex 5 announced
        102359: 06/05/15: Kolja Sulimma: Re: Virtex 5 announced
            102362: 06/05/15: Austin Lesea: Re: Virtex 5 announced
        102371: 06/05/15: Ed McGettigan: Re: Virtex 5 announced
        102379: 06/05/16: Jim Granville: Re: Virtex 5 announced
    102351: 06/05/15: Antti: Re: Virtex 5 announced
    102352: 06/05/15: Antti: Re: Virtex 5 announced
    102354: 06/05/15: Antti: Re: Virtex 5 announced
    102358: 06/05/15: Antti: Re: Virtex 5 announced
    102360: 06/05/15: Antti: Re: Virtex 5 announced
    102364: 06/05/15: Antti: Re: Virtex 5 announced
    102366: 06/05/15: Antti: Re: Virtex 5 announced and sampling
    102367: 06/05/15: dscolson@rcn.com: Re: Virtex 5 announced
        102375: 06/05/15: Kolja Sulimma: Re: Virtex 5 announced
            103039: 06/05/24: Ray Andraka: Re: Virtex 5 announced
                103131: 06/05/25: Ray Andraka: Re: Virtex 5 announced
    102384: 06/05/15: Peter Alfke: Re: Virtex 5 announced
    102389: 06/05/15: Jon Beniston: Re: Virtex 5 announced and sampling
    102390: 06/05/15: Peter Alfke: Re: Virtex 5 announced and sampling
    102391: 06/05/15: <google@gornall.net>: Re: Virtex 5 announced and sampling ... and real!
    102409: 06/05/15: Peter Alfke: Re: Virtex 5 announced and sampling
    102444: 06/05/16: Antti: Re: Virtex 5 announced
    102445: 06/05/16: Antti: Re: Virtex 5 announced and sampling
    102454: 06/05/16: Peter Alfke: Re: Virtex 5 announced and sampling
    102456: 06/05/16: Antti: Re: Virtex 5 announced and sampling
    102458: 06/05/16: Peter Alfke: Re: Virtex 5 announced and sampling
    102459: 06/05/16: Antti: Re: Virtex 5 announced and sampling
    102463: 06/05/16: Peter Alfke: Re: Virtex 5 announced and sampling
    102600: 06/05/17: Paul Leventis: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
    102614: 06/05/17: Antti: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
    102633: 06/05/18: Paul Leventis: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
    102634: 06/05/18: Antti: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
    102650: 06/05/18: Paul Leventis: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
    102703: 06/05/19: Antti: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
    103091: 06/05/25: Marlboro: Re: Virtex 5 announced
    103114: 06/05/25: Stephen Craven: Re: Virtex 5 announced
    103307: 06/05/30: Love Singhal: Re: Virtex 5 announced and sampling ... and real!
102340: 06/05/15: jasonal: uClinux on MicroBlaze: Can't ping now
102341: 06/05/15: Paul: Need help with old Xilinx project
102343: 06/05/15: Paul: Xilinx XC4000 series
    102348: 06/05/15: Josh Rosen: Re: Xilinx XC4000 series
102378: 06/05/15: Brandon: New Virtex4 Project, CoreGen
102383: 06/05/15: Laurent Pinchart: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102415: 06/05/15: <ghelbig@lycos.com>: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
        102425: 06/05/16: Laurent Pinchart: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
            102488: 06/05/17: Laurent Pinchart: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
                102489: 06/05/16: Ed McGettigan: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
                    102490: 06/05/17: Laurent Pinchart: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
                        102495: 06/05/16: Ed McGettigan: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
                            102500: 06/05/17: Sylvain Munaut: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
                                102508: 06/05/17: Laurent Pinchart: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
                                    102542: 06/05/17: Ed McGettigan: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
                                        102595: 06/05/17: Tobias Weingartner: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
                                            102601: 06/05/18: Laurent Pinchart: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
                                        102626: 06/05/18: Andreas Ehliar: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
                            102526: 06/05/17: Felix Bertram: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
                                102543: 06/05/17: Ed McGettigan: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
                                    102583: 06/05/17: Felix Bertram: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
                                    102603: 06/05/17: Ed McGettigan: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
                                        102615: 06/05/17: Ed McGettigan: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
                                            102673: 06/05/18: Eric Smith: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
                                        102616: 06/05/17: Ed McGettigan: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
                        102507: 06/05/17: Uwe Bonnes: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
                            102509: 06/05/17: Laurent Pinchart: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
                                102520: 06/05/17: Uwe Bonnes: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
                            155798: 13/09/07: Uwe Bonnes: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
                    102573: 06/05/17: Eric Smith: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
                102645: 06/05/18: Peter Wallace: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
        102428: 06/05/16: Laurent Pinchart: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
        102572: 06/05/17: Eric Smith: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
            102622: 06/05/18: Mike Harrison: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
        155797: 13/09/06: Luis Alberto Guanuco: Re: Xilinx Platform Cable USB protocol specifications and/or
    102426: 06/05/16: Antti: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102470: 06/05/16: <ghelbig@lycos.com>: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102496: 06/05/16: mmihai: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102501: 06/05/16: <ghelbig@lycos.com>: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102593: 06/05/17: <fpga_toys@yahoo.com>: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102606: 06/05/17: <fpga_toys@yahoo.com>: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102607: 06/05/17: <fpga_toys@yahoo.com>: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102617: 06/05/18: <fpga_toys@yahoo.com>: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102652: 06/05/18: <fpga_toys@yahoo.com>: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
102397: 06/05/15: <andrew.hood@gmail.com>: Microblaze dcm_module problems
    102468: 06/05/16: Guru: Re: Microblaze dcm_module problems
    102473: 06/05/16: <andrew.hood@gmail.com>: Re: Microblaze dcm_module problems
102405: 06/05/15: Brad Smallridge: USB2 camera to Xilinx ML40x boards
    102416: 06/05/15: Kevin Neilson: Re: USB2 camera to Xilinx ML40x boards
        102455: 06/05/16: Laurent Pinchart: Re: USB2 camera to Xilinx ML40x boards
    102430: 06/05/16: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: USB2 camera to Xilinx ML40x boards
        102457: 06/05/16: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: USB2 camera to Xilinx ML40x boards
        102461: 06/05/16: Laurent Pinchart: Re: USB2 camera to Xilinx ML40x boards
    102451: 06/05/16: <soar2morrow@yahoo.com>: Re: USB2 camera to Xilinx ML40x boards
    102591: 06/05/18: John Williams: Re: USB2 camera to Xilinx ML40x boards
102408: 06/05/15: rickman: Actel Fusion FPGAs
    102413: 06/05/15: rickman: Re: Actel Fusion FPGAs
    102417: 06/05/15: Andrew FPGA: Re: Actel Fusion FPGAs
    102420: 06/05/15: Antti: Re: Actel Fusion FPGAs
        102466: 06/05/17: Jim Granville: Re: Actel Fusion FPGAs
            102467: 06/05/17: Jim Granville: Re: Actel Fusion FPGAs
    102424: 06/05/16: Thomas Reinemann: Re: Actel Fusion FPGAs
    102449: 06/05/16: rickman: Re: Actel Fusion FPGAs
    102452: 06/05/16: Antti: Re: Actel Fusion FPGAs
    102469: 06/05/16: Antti: Re: Actel Fusion FPGAs
102419: 06/05/15: srini: Synplify Pro warning - cudnt understand
102423: 06/05/15: praveen.sethuram@gmail.com: requirements to select FPGA using LVDS
    102499: 06/05/17: Rob: Re: requirements to select FPGA using LVDS
    102692: 06/05/19: praveen.sethuram@gmail.com: Re: requirements to select FPGA using LVDS
102434: 06/05/16: BigWorm: Xilinx or Altera...
    102460: 06/05/16: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Xilinx or Altera...
        102472: 06/05/16: Slurp: Re: Xilinx or Altera...
            102482: 06/05/16: <lb.edc@telenet.be>: Re: Xilinx or Altera...
                102506: 06/05/17: <lb.edc@telenet.be>: Re: Xilinx or Altera...
            102552: 06/05/17: Slurp: Re: Xilinx or Altera...
    102475: 06/05/16: Peter Alfke: Re: Xilinx or Altera...
    102486: 06/05/16: Peter Alfke: Re: Xilinx or Altera...
    102491: 06/05/16: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Xilinx or Altera...
    102498: 06/05/16: Paul Leventis: Re: Xilinx or Altera...
102435: 06/05/16: Scope: WARNING:iMPACT:923 - Can not find cable, check cable setup !
    102450: 06/05/16: Brian Drummond: Re: WARNING:iMPACT:923 - Can not find cable, check cable setup !
        102512: 06/05/17: Scope: Re: WARNING:iMPACT:923 - Can not find cable, check cable setup !
102436: 06/05/16: Scope: I can't connect to my Spartan 3 !!! ( Digilent starter kit )
    102438: 06/05/16: Antti: Re: I can't connect to my Spartan 3 !!! ( Digilent starter kit )
102439: 06/05/16: YiQi: sending multiple char on RS232
    102440: 06/05/16: <MikeShepherd564@btinternet.com>: Re: sending multiple char on RS232
        102948: 06/05/23: Mr_chips: Re: sending multiple char on RS232
    102443: 06/05/16: YiQi: Re: sending multiple char on RS232
    102446: 06/05/16: YiQi: Re: sending multiple char on RS232
    102453: 06/05/16: YiQi: Re: sending multiple char on RS232
    102545: 06/05/17: Dave Pollum: Re: sending multiple char on RS232
    102877: 06/05/22: YiQi: Re: sending multiple char on RS232
    102891: 06/05/22: YiQi: Re: sending multiple char on RS232
    103207: 06/05/28: YiQi: Re: sending multiple char on RS232
    103209: 06/05/28: YiQi: Re: sending multiple char on RS232
102471: 06/05/16: Guru: Virtex4 FX12 dynamic clock divider
    102474: 06/05/16: Peter Alfke: Re: Virtex4 FX12 dynamic clock divider
        102515: 06/05/17: Falk Brunner: Re: Virtex4 FX12 dynamic clock divider
        102519: 06/05/17: Falk Brunner: Re: Virtex4 FX12 dynamic clock divider
    102478: 06/05/16: Falk Brunner: Re: Virtex4 FX12 dynamic clock divider
    102492: 06/05/16: Erik Widding: Re: Virtex4 FX12 dynamic clock divider
    102494: 06/05/16: Peter Alfke: Re: Virtex4 FX12 dynamic clock divider
    102513: 06/05/17: Guru: Re: Virtex4 FX12 dynamic clock divider
    102514: 06/05/17: Antti: Re: Virtex4 FX12 dynamic clock divider
    102517: 06/05/17: Guru: Re: Virtex4 FX12 dynamic clock divider
    102524: 06/05/17: Guru: Re: Virtex4 FX12 dynamic clock divider
    102574: 06/05/17: Erik Widding: Re: Virtex4 FX12 dynamic clock divider
    102700: 06/05/19: Guru: Re: Virtex4 FX12 dynamic clock divider
102477: 06/05/16: Fizzy: Shared Memory
102480: 06/05/16: Fizzy: XilKernel and Budgeting
102481: 06/05/16: Peter Alfke: Re: Spartan 3E
102497: 06/05/16: Fizzy: SPI master
    102503: 06/05/16: Marco: Re: SPI master
102502: 06/05/16: <socaciu.claudiu@gmail.com>: hy I need a code example for spartan 3 series in Xilinx regarding the implementation of a PID alghoritm
    102504: 06/05/17: <MikeShepherd564@btinternet.com>: Re: hy I need a code example for spartan 3 series in Xilinx regarding the implementation of a PID alghoritm
        102516: 06/05/17: Falk Brunner: Re: hy I need a code example for spartan 3 series in Xilinx regarding
102518: 06/05/17: Scope: ADC implementation on FPGA ?
    102531: 06/05/17: Kolja Sulimma: Re: ADC implementation on FPGA ?
    102534: 06/05/17: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: ADC implementation on FPGA ?
        102624: 06/05/18: Scope: Re: ADC implementation on FPGA ?
            102630: 06/05/18: Jim Granville: Re: ADC implementation on FPGA ?
                102649: 06/05/18: <lb.edc@telenet.be>: Re: ADC implementation on FPGA ?
                    102653: 06/05/18: Austin Lesea: Re: ADC implementation on FPGA ?
            102711: 06/05/19: Rene Tschaggelar: Re: ADC implementation on FPGA ?
                102718: 06/05/19: Falk Brunner: Re: ADC implementation on FPGA ?
102521: 06/05/17: Peter Mendham: EdaXML
102522: 06/05/17: <airtom@gmail.com>: disappointing 550Mhz performance of V5 DSP slices
    102523: 06/05/17: Ben Jones: Re: "disappointing" 550Mhz performance of V5 DSP slices
        102536: 06/05/17: Falk Brunner: Re: "disappointing" 550Mhz performance of V5 DSP slices
            102541: 06/05/17: <MikeShepherd564@btinternet.com>: Re: "disappointing" 550Mhz performance of V5 DSP slices
                102554: 06/05/17: Falk Brunner: Re: "disappointing" 550Mhz performance of V5 DSP slices
        102538: 06/05/17: Austin Lesea: Re: "disappointing" performance
            102553: 06/05/17: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: "disappointing" performance
            102555: 06/05/17: Falk Brunner: Re: "disappointing" performance
            102565: 06/05/17: Kees van Reeuwijk: Re: "disappointing" performance
            102620: 06/05/18: Peter Mendham: Re: "disappointing" performance
                102641: 06/05/18: Austin Lesea: Re: "disappointing" performance
                102642: 06/05/18: Austin Lesea: Re: "disappointing" performance
                    102677: 06/05/19: Peter Mendham: Re: "disappointing" performance
                    102690: 06/05/19: Peter Mendham: Re: "disappointing" performance
            102749: 06/05/19: c d saunter: Re: "disappointing" performance
                102754: 06/05/19: Austin Lesea: Re: "disappointing" performance
    102527: 06/05/17: <airtom@gmail.com>: Re: "disappointing" 550Mhz performance of V5 DSP slices
    102532: 06/05/17: Stephen Craven: Re: "disappointing" 550Mhz performance of V5 DSP slices
    102550: 06/05/17: Peter Alfke: Re: "disappointing" performance
    102558: 06/05/17: JJ: Re: disappointing 550Mhz performance of V5 DSP slices
        102564: 06/05/17: Jan Panteltje: Re: disappointing 550Mhz performance of V5 DSP slices
            102575: 06/05/18: Jim Granville: Re: disappointing 550Mhz performance of V5 DSP slices
                102582: 06/05/17: Jan Panteltje: Re: disappointing 550Mhz performance of V5 DSP slices
            102586: 06/05/17: Eric Smith: Re: disappointing 550Mhz performance of V5 DSP slices
                102587: 06/05/17: Jan Panteltje: Re: disappointing 550Mhz performance of V5 DSP slices
                    102588: 06/05/17: Eric Smith: Re: disappointing 550Mhz performance of V5 DSP slices
                        102590: 06/05/17: Jan Panteltje: Re: disappointing 550Mhz performance of V5 DSP slices
                            102596: 06/05/17: Austin Lesea: Reality of V5 as ES
                                102637: 06/05/18: Austin Lesea: Re: Reality of V5 as ES
    102577: 06/05/17: JJ: Re: disappointing 550Mhz performance of V5 DSP slices
    102581: 06/05/17: JJ: Re: "disappointing" performance
    102619: 06/05/18: <fpga_toys@yahoo.com>: Re: "disappointing" performance
    102632: 06/05/18: Marc Randolph: Re: Reality of V5 as ES
    102683: 06/05/19: <fpga_toys@yahoo.com>: Re: "disappointing" performance
    102753: 06/05/19: <fpga_toys@yahoo.com>: Re: "disappointing" performance
    102757: 06/05/19: <fpga_toys@yahoo.com>: Re: "disappointing" performance
    102762: 06/05/19: Peter Alfke: Re: "disappointing" performance
    102766: 06/05/19: <fpga_toys@yahoo.com>: Re: "disappointing" performance
    102771: 06/05/19: <fpga_toys@yahoo.com>: Re: "disappointing" performance
    102890: 06/05/22: <fpga_toys@yahoo.com>: Re: "disappointing" performance
102528: 06/05/17: Jon Beniston: SystemACE bootloader for PowerPC on Virtex4 FX
    102529: 06/05/17: Antti: Re: SystemACE bootloader for PowerPC on Virtex4 FX
    102540: 06/05/17: Siva Velusamy: Re: SystemACE bootloader for PowerPC on Virtex4 FX
        102548: 06/05/17: Peter Ryser: Re: SystemACE bootloader for PowerPC on Virtex4 FX
            102569: 06/05/17: Antti Lukats: Re: SystemACE bootloader for PowerPC on Virtex4 FX
                102585: 06/05/17: Peter Ryser: Re: SystemACE bootloader for PowerPC on Virtex4 FX
            102598: 06/05/17: Peter Ryser: Re: SystemACE bootloader for PowerPC on Virtex4 FX
                102608: 06/05/17: Peter Ryser: Re: SystemACE bootloader for PowerPC on Virtex4 FX
                    102643: 06/05/18: Peter Ryser: Re: SystemACE bootloader for PowerPC on Virtex4 FX
        102549: 06/05/17: Antti Lukats: Re: SystemACE bootloader for PowerPC on Virtex4 FX
            102568: 06/05/17: Antti Lukats: Re: SystemACE bootloader for PowerPC on Virtex4 FX
    102544: 06/05/17: Jon Beniston: Re: SystemACE bootloader for PowerPC on Virtex4 FX
    102556: 06/05/17: Jon Beniston: Re: SystemACE bootloader for PowerPC on Virtex4 FX
    102559: 06/05/17: Jon Beniston: Re: SystemACE bootloader for PowerPC on Virtex4 FX
    102627: 06/05/18: Jon Beniston: Re: SystemACE bootloader for PowerPC on Virtex4 FX
    102628: 06/05/18: Jon Beniston: Re: SystemACE bootloader for PowerPC on Virtex4 FX
    102629: 06/05/18: Antti: Re: SystemACE bootloader for PowerPC on Virtex4 FX
    102713: 06/05/19: Jon Beniston: Re: SystemACE bootloader for PowerPC on Virtex4 FX
102530: 06/05/17: devb: ANNC: ISE/WebPACK 8.1i tutorial available
102533: 06/05/17: Eli Hughes: CoolRunner Pins during Programming
    102537: 06/05/17: Falk Brunner: Re: CoolRunner Pins during Programming
102535: 06/05/17: Brijesh: Hold Time Violations in Virtex4
    102562: 06/05/17: Jim Wu: Re: Hold Time Violations in Virtex4
102560: 06/05/17: Fizzy: DCM
    102563: 06/05/17: Falk Brunner: Re: DCM
    102566: 06/05/17: John_H: Re: DCM
102571: 06/05/17: <joey@joescan.com>: Cyclone II PCI & Pin Swapping
    102602: 06/05/17: Paul Leventis: Re: Cyclone II PCI & Pin Swapping
102580: 06/05/17: MM: Looking for DDC/DUC customizable cores
102589: 06/05/17: Todd Fleming: Verilog Draggable Window Library
    102592: 06/05/17: Stephen Craven: Re: Verilog Draggable Window Library
102609: 06/05/18: Bob: V4 system synchronous input setup/hold and clock-to-out time calculations?
102611: 06/05/17: Brian Davis: Update: Simple ADS5273 -> Xilinx Interconnect Model
102618: 06/05/18: <huymEmail@gmail.com>: Where can i get "Quartus II Device Information for UNIX & Linux CD"
    102635: 06/05/18: Subroto Datta: Re: Where can i get "Quartus II Device Information for UNIX & Linux CD"
    102672: 06/05/18: huymEmail@gmail.com: Re: Where can i get "Quartus II Device Information for UNIX & Linux CD"
102625: 06/05/18: Tomasz Dziecielewski: Clocking ZBT RAM via DCM on ML40x board
    102639: 06/05/18: Brad Smallridge: Re: Clocking ZBT RAM via DCM on ML40x board
        102682: 06/05/19: Tomasz Dziecielewski: Re: Clocking ZBT RAM via DCM on ML40x board
            102750: 06/05/19: Brad Smallridge: Re: Clocking ZBT RAM via DCM on ML40x board
102636: 06/05/18: <muthusnv@gmail.com>: OFFSET constraints with derived clocks - Xilinx FPGA
    102647: 06/05/18: Duane Clark: Re: OFFSET constraints with derived clocks - Xilinx FPGA
102638: 06/05/18: Eli Hughes: FPGA Configuration Question
    102640: 06/05/18: Falk Brunner: Re: FPGA Configuration Question
    102644: 06/05/18: dand2k: Re: FPGA Configuration Question
    102678: 06/05/19: Peter Mendham: Re: FPGA Configuration Question
    102679: 06/05/19: Ad: Re: FPGA Configuration Question
102646: 06/05/18: jvdh: Spartan 3 Readback
    102648: 06/05/18: dand2k: Re: Spartan 3 Readback
        102667: 06/05/18: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Spartan 3 Readback
            102676: 06/05/19: Eric Smith: Re: Spartan 3 Readback
    102680: 06/05/19: Antti: Re: Spartan 3 Readback
    102699: 06/05/19: jvdh: Re: Spartan 3 Readback
    102704: 06/05/19: jvdh: Re: Spartan 3 Readback
    102705: 06/05/19: Antti: Re: Spartan 3 Readback
    102740: 06/05/19: jvdh: Re: Spartan 3 Readback
102651: 06/05/18: Roger Bourne: Output gain adjuster of digital filters
    102681: 06/05/19: Jon Harris: Re: Output gain adjuster of digital filters
    102706: 06/05/19: Rune Allnor: Re: Output gain adjuster of digital filters
    102725: 06/05/19: Jerry Avins: Re: Output gain adjuster of digital filters
        102726: 06/05/19: Steve Underwood: Re: Output gain adjuster of digital filters
            102741: 06/05/19: Jerry Avins: Re: Output gain adjuster of digital filters
102655: 06/05/18: Fizzy: DCM and Clock
    102656: 06/05/18: Peter Alfke: Re: DCM and Clock
        102660: 06/05/19: Falk Brunner: Re: DCM and Clock
            102663: 06/05/18: Austin Lesea: Re: DCM and Clock
                102668: 06/05/18: Austin Lesea: Re: DCM and Clock
            102693: 06/05/19: Falk Brunner: Re: DCM and Clock
        102707: 06/05/19: Piotr Wyderski: Re: DCM and Clock
    102657: 06/05/18: Fizzy: Re: DCM and Clock
    102659: 06/05/18: Duane Clark: Re: DCM and Clock
        102661: 06/05/18: Austin Lesea: Re: DCM and Clock
    102662: 06/05/18: Fizzy: Re: DCM and Clock
    102665: 06/05/18: Fizzy: Re: DCM and Clock
102658: 06/05/18: acd: V5 and carry lookahead
    102664: 06/05/18: Peter Alfke: Re: V5 and carry lookahead
        102695: 06/05/19: Ben Jones: Re: V5 and carry lookahead
            102732: 06/05/19: Ben Jones: Re: V5 and carry lookahead
    102671: 06/05/18: <fpga_toys@yahoo.com>: Re: V5 and carry lookahead
    102714: 06/05/19: <fpga_toys@yahoo.com>: Re: V5 and carry lookahead
    102763: 06/05/19: <fpga_toys@yahoo.com>: Re: V5 and carry lookahead
102669: 06/05/18: <patches11@gmail.com>: Processing DVI signals with an FPGA
    102723: 06/05/19: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Processing DVI signals with an FPGA
    102730: 06/05/19: Martin Thompson: Re: Processing DVI signals with an FPGA
102670: 06/05/18: radarman: Spartan 3e sample: pack power control with M(1)?
    102720: 06/05/19: rickman: Re: Spartan 3e sample: pack power control with M(1)?
    102735: 06/05/19: radarman: Re: Spartan 3e sample: pack power control with M(1)?
102674: 06/05/18: savs: Error in XPS 7.1 mb_opb_wrapper
    102744: 06/05/19: zeeman_be: Re: Error in XPS 7.1 mb_opb_wrapper
    102831: 06/05/22: savs: Re: Error in XPS 7.1 mb_opb_wrapper
102684: 06/05/19: Antti: EDK OPB DDR2 IP Core, looking for tested example
    102708: 06/05/19: Antti: Re: EDK OPB DDR2 IP Core, looking for tested example
102685: 06/05/19: Scope: generate a square signal with a 3.8 ns "plate"
    102689: 06/05/19: Peter Mendham: Re: generate a square signal with a 3.8 ns "plate"
        102696: 06/05/19: Scope: Re: generate a square signal with a 3.8 ns
    102709: 06/05/19: Kolja Sulimma: Re: generate a square signal with a 3.8 ns "plate"
        102715: 06/05/19: Scope: Re: generate a square signal with a 3.8 ns
            102719: 06/05/19: Falk Brunner: Re: generate a square signal with a 3.8 ns
                102721: 06/05/19: Scope: Re: generate a square signal with a 3.8 ns
                    102734: 06/05/19: Falk Brunner: Re: generate a square signal with a 3.8 ns
            102743: 06/05/19: Kolja Sulimma: Re: generate a square signal with a 3.8 ns
102686: 06/05/19: DeMarcus: Memory Interface: Standards
102687: 06/05/19: <max.giacometti@libero.it>: Ethernet & ML401
    102688: 06/05/19: Jon Beniston: Re: Ethernet & ML401
        102716: 06/05/19: Marco T.: Re: Ethernet & ML401
            102731: 06/05/19: Marco T.: Re: Ethernet & ML401
                102756: 06/05/19: Eric Smith: Re: Ethernet & ML401
                    102773: 06/05/20: Marco T.: Re: Ethernet & ML401
    102691: 06/05/19: <max.giacometti@libero.it>: Re: Ethernet & ML401
    102728: 06/05/19: <max.giacometti@libero.it>: Re: Ethernet & ML401
    102737: 06/05/19: <max.giacometti@libero.it>: Re: Ethernet & ML401
102698: 06/05/19: =?iso-8859-1?B?SGFucyBI/GJuZXI=?=: LISP Workshop at ECOOP06
    102736: 06/05/19: Colin Paul Gloster: Re: LISP Workshop at ECOOP06
        102828: 06/05/21: Tommy Thorn: Re: LISP Workshop at ECOOP06
        106256: 06/08/10: Sander Vesik: Re: LISP Workshop at ECOOP06
    102772: 06/05/19: =?iso-8859-1?B?SGFucyBI/GJuZXI=?=: Re: LISP Workshop at ECOOP06
    102853: 06/05/22: Rob Thorpe: Re: LISP Workshop at ECOOP06
    103070: 06/05/25: Frank Buss: Re: LISP Workshop at ECOOP06
102702: 06/05/19: <max.giacometti@libero.it>: Use USB ports on ML401
    102710: 06/05/19: Antti: Re: Use USB ports on ML401
    102717: 06/05/19: Marco T.: Re: Use USB ports on ML401
102722: 06/05/19: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Xilinx-ise, invert input?
    102724: 06/05/19: Antti: Re: Xilinx-ise, invert input?
        102729: 06/05/19: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Xilinx-ise, invert input?
    102733: 06/05/19: Antti: Re: Xilinx-ise, invert input?
102738: 06/05/19: Nigel: CPLD (CoolRunner) failures.
    102764: 06/05/19: Atmel_PLDs_Rock: Re: CPLD (CoolRunner) failures.
        102765: 06/05/20: Falk Brunner: Re: CPLD (CoolRunner) failures.
102739: 06/05/19: Franco Tiratore: [Newbie] Suitable FPGA for my project
    102742: 06/05/19: Falk Brunner: Re: [Newbie] Suitable FPGA for my project
        102746: 06/05/19: Falk Brunner: Re: Suitable FPGA for my project
            102779: 06/05/20: Franco Tiratore: Re: Suitable FPGA for my project
                102780: 06/05/20: Falk Brunner: Re: Suitable FPGA for my project
                    102815: 06/05/21: Franco Tiratore: Re: Suitable FPGA for my project
                102801: 06/05/21: John Adair: Re: [Newbie] Suitable FPGA for my project
                    102805: 06/05/21: Dave: Re: [Newbie] Suitable FPGA for my project
    102745: 06/05/19: Franco Tiratore: Re: Suitable FPGA for my project
102748: 06/05/19: John_H: Xilinx/Synplicity LUT Placement
    103132: 06/05/25: Ray Andraka: Re: Xilinx/Synplicity LUT Placement
        103156: 06/05/26: John_H: Re: Xilinx/Synplicity LUT Placement
            103167: 06/05/26: Ray Andraka: Re: Xilinx/Synplicity LUT Placement
                103173: 06/05/27: John_H: Re: Xilinx/Synplicity LUT Placement
102751: 06/05/20: Jim Granville: Re: CPLD (CoolRunner failures)
    102769: 06/05/20: Jim Granville: Re: CPLD (CoolRunner failures)
        102797: 06/05/21: Jim Granville: Re: CPLD (CoolRunner failures)
            102888: 06/05/23: Jim Granville: Re: CPLD (CoolRunner failures)
            102898: 06/05/22: Spehro Pefhany: Re: CPLD (CoolRunner failures)
        102799: 06/05/21: <MikeShepherd564@btinternet.com>: Re: CPLD (CoolRunner failures)
        102800: 06/05/21: Spehro Pefhany: Re: CPLD (CoolRunner failures)
            102802: 06/05/21: Jim Granville: Re: CPLD (CoolRunner failures)
            102804: 06/05/21: Falk Brunner: Re: CPLD (CoolRunner failures)
                102806: 06/05/21: Spehro Pefhany: Re: CPLD (CoolRunner failures)
                    102807: 06/05/21: Falk Brunner: Re: CPLD (CoolRunner failures)
102752: 06/05/19: Fizzy: PLB clocking
    102759: 06/05/19: Falk Brunner: Re: PLB clocking
    102770: 06/05/19: motty: Re: PLB clocking
102760: 06/05/19: leevv: xilinx V4 obufds_25 and 3.3 V
    102775: 06/05/20: Antti Lukats: Re: xilinx V4 obufds_25 and 3.3 V
        102785: 06/05/20: leevv: Re: xilinx V4 obufds_25 and 3.3 V
102761: 06/05/19: Paul Carpenter: Re: CPLD (CoolRunner failures)
102767: 06/05/19: bart: ispLEVER Starter 6.0 FPGA Design Software Available
    102774: 06/05/20: Antti Lukats: Re: ispLEVER Starter 6.0 FPGA Design Software Available
        102823: 06/05/21: <lb.edc@telenet.be>: Re: ispLEVER Starter 6.0 FPGA Design Software Available
    102776: 06/05/20: <fpga_toys@yahoo.com>: Re: ispLEVER Starter 6.0 FPGA Design Software Available
    102778: 06/05/20: Piotr Wyderski: Re: ispLEVER Starter 6.0 FPGA Design Software Available
        102824: 06/05/21: <lb.edc@telenet.be>: Re: ispLEVER Starter 6.0 FPGA Design Software Available
            102850: 06/05/22: <lb.edc@telenet.be>: Re: ispLEVER Starter 6.0 FPGA Design Software Available
                102884: 06/05/22: Ben Twijnstra: Re: ispLEVER Starter 6.0 FPGA Design Software Available
            102861: 06/05/22: Piotr Wyderski: Re: ispLEVER Starter 6.0 FPGA Design Software Available
        103134: 06/05/25: Ron: Re: ispLEVER Starter 6.0 FPGA Design Software Available
    102846: 06/05/22: johnp: Re: ispLEVER Starter 6.0 FPGA Design Software Available
    102863: 06/05/22: Antti: Re: ispLEVER Starter 6.0 FPGA Design Software Available
    102875: 06/05/22: johnp: Re: ispLEVER Starter 6.0 FPGA Design Software Available
102768: 06/05/19: rickman: Why do the electronics manufacturers have to spam me?
    102781: 06/05/20: ziggy: Re: Why do the electronics manufacturers have to spam me?
    102782: 06/05/20: radarman: Re: Why do the electronics manufacturers have to spam me?
    102784: 06/05/20: <MikeShepherd564@btinternet.com>: Re: Why do the electronics manufacturers have to spam me?
        102789: 06/05/21: Jim Granville: Re: Why do the electronics manufacturers have to spam me?
    102835: 06/05/22: Symon: Re: Why do the electronics manufacturers have to spam me?
    103135: 06/05/25: Ron: Re: Why do the electronics manufacturers have to spam me?
102783: 06/05/20: Jeff Brower: initial block processing in XST 8.1
    102792: 06/05/21: John_H: Re: initial block processing in XST 8.1
    102843: 06/05/22: Jeff Brower: Re: initial block processing in XST 8.1
102786: 06/05/20: Antti: Re: xilinx V4 obufds_25 and 3.3 V
102787: 06/05/20: Dennis: Signal 2 clocks long but only one clock possible
    102788: 06/05/20: Peter Alfke: Re: Signal 2 clocks long but only one clock possible
    102790: 06/05/20: johnp: Re: Signal 2 clocks long but only one clock possible
    102819: 06/05/21: Dennis: Re: Signal 2 clocks long but only one clock possible
    102845: 06/05/22: johnp: Re: Signal 2 clocks long but only one clock possible
    102986: 06/05/24: Dennis: Re: Signal 2 clocks long but only one clock possible
    102998: 06/05/24: johnp: Re: Signal 2 clocks long but only one clock possible
    103002: 06/05/24: Dennis: Re: Signal 2 clocks long but only one clock possible
102793: 06/05/20: <kishore2k4@gmail.com>: JTAG chaining of two different Xilinx Spartan 3E boards
    102796: 06/05/21: Bob: Re: JTAG chaining of two different Xilinx Spartan 3E boards
    102811: 06/05/21: radarman: Re: JTAG chaining of two different Xilinx Spartan 3E boards
102794: 06/05/20: Nigel: Re: CPLD (CoolRunner failures)
102795: 06/05/20: Peter Alfke: Re: CPLD (CoolRunner failures)
102798: 06/05/20: bjzhangwn: Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga
    102818: 06/05/21: Antti: Re: Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga
        102820: 06/05/21: Kolja Sulimma: Re: Have someone implementate the cpu86 or sparc embeded processor
    102821: 06/05/21: Antti: Re: Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga
    102836: 06/05/22: Jon Beniston: Re: Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga
    102838: 06/05/22: Antti: Re: Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga
    103476: 06/06/03: Antti: Re: Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga
102803: 06/05/21: hitsx@hit.edu.cn: MicroBlaze as SubModule Problem
    102810: 06/05/21: hitsx@hit.edu.cn: Re: MicroBlaze as SubModule Problem
    102812: 06/05/21: hitsx@hit.edu.cn: Re: MicroBlaze as SubModule Problem
    102813: 06/05/21: Antti: Re: MicroBlaze as SubModule Problem
    102814: 06/05/21: Antti: Re: MicroBlaze as SubModule Problem
    102922: 06/05/23: hitsx@hit.edu.cn: Re: MicroBlaze as SubModule Problem
102808: 06/05/21: Mark Murray: Quartus ByteBlaster in Active Serial Programming mode not working
    102809: 06/05/21: Antti: Re: Quartus ByteBlaster in Active Serial Programming mode not working
        102817: 06/05/21: Mark Murray: Re: Quartus ByteBlaster in Active Serial Programming mode not working
    102830: 06/05/21: <venkatec@gmail.com>: gate level simulation
102816: 06/05/21: Paul Carpenter: Re: CPLD (CoolRunner failures)
102822: 06/05/21: Antti: How simple can FPGA design be? (Mission Possible 2006)
    102825: 06/05/21: Nial Stewart: Re: How simple can FPGA design be? (Mission Possible 2006)
    102826: 06/05/21: Nial Stewart: Forgot to say....
    102829: 06/05/22: int19h: Re: How simple can FPGA design be? (Mission Possible 2006)
102832: 06/05/22: Tim Verstraete: [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins
    102833: 06/05/22: Antti: Re: DDR2 SDRAM controller + dual purpose pins
    102834: 06/05/22: Tim Verstraete: Re: DDR2 SDRAM controller + dual purpose pins
    102842: 06/05/22: Brian Davis: Re: [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins
    102859: 06/05/22: Tim Verstraete: Re: [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins
    102862: 06/05/22: Brian Davis: Re: [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins
    102866: 06/05/22: Tim Verstraete: Re: DDR2 SDRAM controller + dual purpose pins
    103224: 06/05/29: Tim Verstraete: Re: DDR2 SDRAM controller + dual purpose pins
    104141: 06/06/19: Rajendra: Re: [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins
102837: 06/05/22: Grata: MicroBlaze and IIC
    102839: 06/05/22: Antti: Re: MicroBlaze and IIC
102840: 06/05/22: Raymond: Unknown Processor Version (8)
    102860: 06/05/22: Antti: Re: Unknown Processor Version (8)
    102908: 06/05/23: Raymond: Re: Unknown Processor Version (8)
    102910: 06/05/23: Raymond: Re: Unknown Processor Version (8)
102841: 06/05/22: Sanka Piyaratna: incremental chip building in ISE
102844: 06/05/22: Mellby: Urgent help programming SPI-flash trough JTAG (Spartan3E)
    102847: 06/05/22: Mellby: Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
    102848: 06/05/22: Antti: Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
    102894: 06/05/22: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
        102906: 06/05/23: Petter Gustad: Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
    102902: 06/05/22: Antti: Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
    102904: 06/05/23: Antti: Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
102849: 06/05/22: <rob.misc@gmail.com>: Independent clock FIFOs
    102851: 06/05/22: Peter Alfke: Re: Independent clock FIFOs
        102991: 06/05/24: Falk Brunner: Re: Independent clock FIFOs
            102994: 06/05/24: Ben Jones: Re: Independent clock FIFOs
                103151: 06/05/26: Terry Brown: Re: Independent clock FIFOs
                    103152: 06/05/26: Mike Treseler: Re: Independent clock FIFOs
                        103188: 06/05/27: Terry Brown: Re: Independent clock FIFOs
    102989: 06/05/24: <rob.misc@gmail.com>: Re: Independent clock FIFOs
    103191: 06/05/27: Peter Alfke: Re: Independent clock FIFOs
    103348: 06/05/31: Rob Misc: Re: Independent clock FIFOs
102852: 06/05/22: Anonymous: xilinx pricing discrepancy
    102856: 06/05/22: Antti: Re: xilinx pricing discrepancy
    102858: 06/05/22: John Adair: Re: xilinx pricing discrepancy
        102869: 06/05/22: Anonymous: Re: xilinx pricing discrepancy
            102874: 06/05/22: John Adair: Re: xilinx pricing discrepancy
                102876: 06/05/22: Ed McGettigan: Re: xilinx pricing discrepancy
                    102893: 06/05/23: Tim: Re: xilinx pricing discrepancy
            103035: 06/05/24: Anonymous: Re: xilinx pricing discrepancy
                103069: 06/05/25: Anonymous: Re: xilinx pricing discrepancy
        102903: 06/05/23: Kolja Sulimma: Re: xilinx pricing discrepancy
    102880: 06/05/22: Bob Perlman: Re: xilinx pricing discrepancy
        102915: 06/05/23: <MikeShepherd564@btinternet.com>: Re: xilinx pricing discrepancy
    102892: 06/05/22: <fpga_toys@yahoo.com>: Re: xilinx pricing discrepancy
    102919: 06/05/23: Marc Randolph: Re: xilinx pricing discrepancy
    102921: 06/05/23: <fpga_toys@yahoo.com>: Re: xilinx pricing discrepancy
    102923: 06/05/23: <fpga_toys@yahoo.com>: Re: xilinx pricing discrepancy
    102951: 06/05/23: Peter Alfke: Re: xilinx pricing discrepancy
    102952: 06/05/23: <fpga_toys@yahoo.com>: Re: xilinx pricing discrepancy
    102954: 06/05/23: Peter Alfke: Re: xilinx pricing discrepancy
    102957: 06/05/23: <fpga_toys@yahoo.com>: Re: xilinx pricing discrepancy
    102963: 06/05/23: Peter Alfke: Re: xilinx pricing discrepancy
    103037: 06/05/24: Peter Alfke: Re: xilinx pricing discrepancy
102854: 06/05/22: Nigel: Re: CPLD (CoolRunner failures)
102855: 06/05/22: Nigel: Re: CPLD (CoolRunner failures)
102857: 06/05/22: Peter Alfke: Re: CPLD (CoolRunner failures)
102864: 06/05/22: Telenochek: Building a board with Spartan 3 FPGA.
    102865: 06/05/22: Antti: Re: Building a board with Spartan 3 FPGA.
    102867: 06/05/22: John_H: Re: Building a board with Spartan 3 FPGA.
        102870: 06/05/22: John_H: Re: Building a board with Spartan 3 FPGA.
            102878: 06/05/22: Jon Elson: Re: Building a board with Spartan 3 FPGA.
                102885: 06/05/22: John_H: Re: Building a board with Spartan 3 FPGA.
    102868: 06/05/22: Telenochek: Re: Building a board with Spartan 3 FPGA.
    102871: 06/05/22: Antti: Re: Building a board with Spartan 3 FPGA.
    102872: 06/05/22: Telenochek: Re: Building a board with Spartan 3 FPGA.
    102873: 06/05/22: Telenochek: Re: Building a board with Spartan 3 FPGA.
    102883: 06/05/22: Andy: Re: Building a board with Spartan 3 FPGA.
    102886: 06/05/22: Telenochek: Re: Building a board with Spartan 3 FPGA.
    102929: 06/05/23: MM: Re: Building a board with Spartan 3 FPGA.
102879: 06/05/22: Eshwar: FPGA PCIe core connectivity w/ a PC
102881: 06/05/22: KJ: Possible output drive strength when using Micron DDR and Stratix II DDR Controller
    102889: 06/05/22: Ben Jackson: Re: Possible output drive strength when using Micron DDR and Stratix II DDR Controller
        102913: 06/05/23: KJ: Re: Possible output drive strength when using Micron DDR and Stratix II DDR Controller
102887: 06/05/22: Andrew: ModelSim Designer
102895: 06/05/22: Nigel: Re: CPLD (CoolRunner failures)
102896: 06/05/22: Nigel: Re: CPLD (CoolRunner failures)
102897: 06/05/22: Nigel: Re: CPLD (CoolRunner failures)
102899: 06/05/23: Bob: Xilinx -- please help with Virtex-4 datasheet
    102928: 06/05/23: Austin Lesea: Re: Xilinx -- please help with Virtex-4 datasheet
102901: 06/05/22: Nigel: Re: CPLD (CoolRunner failures)
102907: 06/05/23: Antti: ISE 8.1SP4 PN doesnt start
    102916: 06/05/23: Antti: Re: ISE 8.1SP4 PN doesnt start
        102937: 06/05/24: Jim Granville: Re: ISE 8.1SP4 PN doesnt start
            102981: 06/05/24: Ben Jones: Re: ISE 8.1SP4 PN doesnt start
                103001: 06/05/24: Tim: Re: ISE 8.1SP4 PN doesnt start
                103038: 06/05/25: Jim Granville: Re: ISE 8.1SP4 PN doesnt start
    102925: 06/05/23: johnp: Re: ISE 8.1SP4 PN doesnt start
    102926: 06/05/23: Antti: Re: ISE 8.1SP4 PN doesnt start
    102927: 06/05/23: <tgschwind@tiscalinet.ch>: Re: ISE 8.1SP4 PN doesnt start
    102973: 06/05/24: Antti: Re: ISE 8.1SP4 PN doesnt start
    102983: 06/05/24: Brian Davis: Re: ISE 8.1SP4 PN doesnt start
    102985: 06/05/24: Antti: Re: ISE 8.1SP4 PN doesnt start
102909: 06/05/23: Raymond: OPB Timer MicroBlaze
    102912: 06/05/23: Ben Jones: Re: OPB Timer MicroBlaze
    102918: 06/05/23: Raymond: Re: OPB Timer MicroBlaze
102914: 06/05/23: ivo: someone used FIFO along with the OPB-bus in FPGA ?
    102970: 06/05/24: Guru: Re: someone used FIFO along with the OPB-bus in FPGA ?
102917: 06/05/23: amko: FPGA delay generator
    102938: 06/05/23: John_H: Re: FPGA delay generator
    102969: 06/05/24: John Adair: Re: FPGA delay generator
    102979: 06/05/24: Kolja Sulimma: Re: FPGA delay generator
        102987: 06/05/24: John Adair: Re: FPGA delay generator
            103014: 06/05/24: Kolja Sulimma: Re: FPGA delay generator
                103084: 06/05/25: John Larkin: Re: FPGA delay generator
            103029: 06/05/24: John_H: Re: FPGA delay generator
            103059: 06/05/25: John Adair: Re: FPGA delay generator
    102982: 06/05/24: amko: Re: FPGA delay generator
    102984: 06/05/24: amko: Re: FPGA delay generator
    102999: 06/05/24: amko: Re: FPGA delay generator
    103050: 06/05/25: amko: Re: FPGA delay generator
102924: 06/05/23: dp: Re: CPLD (CoolRunner failures)
102930: 06/05/23: <fpgabuilder-groups@yahoo.com>: PCI 64/66 fpga eval boards
    102931: 06/05/23: <mljohnson00@yahoo.com>: Re: PCI 64/66 fpga eval boards
        103015: 06/05/24: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: PCI 64/66 fpga eval boards
            103020: 06/05/24: John Aderseen: Re: PCI 64/66 fpga eval boards
                103023: 06/05/24: Keith: Re: PCI 64/66 fpga eval boards
                    103027: 06/05/24: Joel Kolstad: Re: PCI 64/66 fpga eval boards
                        103042: 06/05/24: krw: Re: PCI 64/66 fpga eval boards
                            103054: 06/05/25: John Aderseen: Re: PCI 64/66 fpga eval boards
                                103087: 06/05/25: Joel Kolstad: Re: PCI 64/66 fpga eval boards
                                103166: 06/05/26: krw: Re: PCI 64/66 fpga eval boards
                            103086: 06/05/25: Joel Kolstad: Re: PCI 64/66 fpga eval boards
                            103089: 06/05/25: Keith: Re: PCI 64/66 fpga eval boards
    102932: 06/05/23: John Aderseen: Re: PCI 64/66 fpga eval boards
    102933: 06/05/23: John Aderseen: Re: PCI 64/66 fpga eval boards
        102974: 06/05/24: Dave: Re: PCI 64/66 fpga eval boards
        103109: 06/05/25: John Aderseen: Re: PCI 64/66 fpga eval boards
    102967: 06/05/24: fpgabuilder: Re: PCI 64/66 fpga eval boards
    103026: 06/05/24: qrk: Re: PCI 64/66 fpga eval boards
    103052: 06/05/25: fpgabuilder: Re: PCI 64/66 fpga eval boards
    103055: 06/05/25: fpgabuilder: Re: PCI 64/66 fpga eval boards
    103095: 06/05/25: fpgabuilder: Re: PCI 64/66 fpga eval boards
    103111: 06/05/25: fpgabuilder: Re: PCI 64/66 fpga eval boards
102935: 06/05/23: Anonymous: .hex or .svf file from Mediatronix picoBlaze IDE
102940: 06/05/23: Brad Smallridge: I2C on Xilinx V4
    102947: 06/05/24: Falk Brunner: Re: I2C on Xilinx V4
    102975: 06/05/24: Antti: Re: I2C on Xilinx V4
    102997: 06/05/24: Felix Bertram: Re: I2C on Xilinx V4
        103009: 06/05/24: Ray Andraka: Re: I2C on Xilinx V4
        103032: 06/05/24: Brad Smallridge: Re: I2C on Xilinx V4
            103143: 06/05/26: Felix Bertram: Re: I2C on Xilinx V4
    103011: 06/05/24: Antti: Re: I2C on Xilinx V4
        103012: 06/05/24: c d saunter: Re: I2C on Xilinx V4
102943: 06/05/23: Kishore: Verilog vs VHDL
    102944: 06/05/23: Jon Beniston: Re: Verilog vs VHDL
        102945: 06/05/23: mk: Re: Verilog vs VHDL
            102953: 06/05/23: Dave: Re: Verilog vs VHDL
    102946: 06/05/23: Jon Beniston: Re: Verilog vs VHDL
    102949: 06/05/23: Ed McGettigan: Re: Verilog vs VHDL
    102950: 06/05/23: Mike Treseler: Re: Verilog vs VHDL
    102955: 06/05/23: JJ: Re: Verilog vs VHDL
    102964: 06/05/23: <ghelbig@lycos.com>: Re: Verilog vs VHDL
    102966: 06/05/24: Thomas Stanka: Re: Verilog vs VHDL
    102978: 06/05/24: Tim: Re: Verilog vs VHDL
    103013: 06/05/24: Phil Tomson: Re: Verilog vs VHDL
        103046: 06/05/25: Phil Tomson: Re: Verilog vs VHDL
        103225: 06/05/29: Ron: Re: Verilog vs VHDL
            103564: 06/06/06: Martin Thompson: Re: Verilog vs VHDL
            103611: 06/06/06: Austin Lesea: Who's dying?
                103612: 06/06/06: c d saunter: Re: Who's dying?
                103613: 06/06/07: Jim Granville: Re: Who's dying?
                    103614: 06/06/06: Austin Lesea: Re: Who's dying?
                        103617: 06/06/07: Jim Granville: Re: Who's dying?
                            103647: 06/06/07: Austin Lesea: Re: Who's dying?
                                103661: 06/06/08: Jim Granville: Re: Who's dying?
                                    103663: 06/06/07: Austin Lesea: Re: Who's dying?
                                        103670: 06/06/08: Jim Granville: Re: STOP IT :)
                                        103671: 06/06/07: Austin Lesea: Re: STOP IT :)
    103031: 06/05/24: JJ: Re: Verilog vs VHDL
    103608: 06/06/06: <burn.sir@gmail.com>: Re: Verilog vs VHDL
    103667: 06/06/07: <burn.sir@gmail.com>: STOP IT :)
    103673: 06/06/07: Peter Alfke: Re: STOP IT :)
102956: 06/05/23: Eka From Indonesia: Reading from and Writing to J3 Intel StrataFlash NOR FlashPROM on Spartan3E SK
    103175: 06/05/26: Eka From Indonesia: Re: Reading from and Writing to J3 Intel StrataFlash NOR FlashPROM on Spartan3E SK
102958: 06/05/23: bijoy: FPGA : P&R problem - Help !
    102980: 06/05/24: Symon: Re: FPGA : P&R problem - Help !
    103004: 06/05/24: Andy Ray: Re: FPGA : P&R problem - Help !
        103010: 06/05/24: Symon: Re: FPGA : P&R problem - Help !
102959: 06/05/23: bijoy: FPGA : Constraint for BRAM placements
    102965: 06/05/24: Andreas Ehliar: Re: FPGA : Constraint for BRAM placements
102961: 06/05/23: <thomas.b36@gmail.com>: Config XCF04S using iMPACT
102971: 06/05/24: Antti: Most expensive 8051 in DIP40? here on my desk, labelled Virtex-4 V4LX25 :)
    102972: 06/05/24: Antti: Re: Most expensive 8051 in DIP40? here on my desk, labelled Virtex-4 V4LX25 :)
    102976: 06/05/24: Hans: Re: Most expensive 8051 in DIP40? here on my desk, labelled Virtex-4 V4LX25 :)
    102977: 06/05/24: Antti: Re: Most expensive 8051 in DIP40? here on my desk, labelled Virtex-4 V4LX25 :)
    103028: 06/05/25: Jim Granville: Re: Most expensive 8051 in DIP40? here on my desk, labelled Virtex-4
102988: 06/05/24: Kamtsa: WebPack ISE 8 - how to avoide 'non supported language' warnings?
    103049: 06/05/24: Kamtsa: Re: WebPack ISE 8 - how to avoide 'non supported language' warnings?
102990: 06/05/24: Marco: fpga debug
    102992: 06/05/24: Falk Brunner: Re: fpga debug
        102995: 06/05/24: Falk Brunner: Re: fpga debug
        103003: 06/05/24: Vivian Bessler: Re: fpga debug
            103047: 06/05/24: Ron: Re: fpga debug
                103142: 06/05/26: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Re: fpga debug
        103297: 06/05/30: dalai lamah: Re: fpga debug
            103299: 06/05/30: Falk Brunner: Re: fpga debug
    102993: 06/05/24: Marco: Re: fpga debug
    102996: 06/05/24: Marco: Re: fpga debug
    103005: 06/05/24: Nial Stewart: Re: fpga debug
103000: 06/05/24: Kishore: System Generator Eval version for Malab R2006a
103006: 06/05/24: Nial Stewart: Stopping Quartus using multipliers?
    103007: 06/05/24: Mike Treseler: Re: Stopping Quartus using multipliers?
        103019: 06/05/24: Nial Stewart: Re: Stopping Quartus using multipliers?
    103016: 06/05/24: Slurp: Re: Stopping Quartus using multipliers?
        103018: 06/05/24: Nial Stewart: Re: Stopping Quartus using multipliers?
    103021: 06/05/24: Henry Wong: Re: Stopping Quartus using multipliers?
        103024: 06/05/24: Nial Stewart: Re: Stopping Quartus using multipliers?
    103025: 06/05/24: KJ: Re: Stopping Quartus using multipliers?
103008: 06/05/24: Matt Blanton: setting max fanout with xps flow
    103078: 06/05/25: Matt Blanton: Re: setting max fanout with xps flow
    103080: 06/05/25: Peter Alfke: Re: setting max fanout with xps flow
        103081: 06/05/25: Matt Blanton: Re: setting max fanout with xps flow
            103100: 06/05/25: Matt Blanton: Re: setting max fanout with xps flow
                103102: 06/05/25: Joseph Samson: Re: setting max fanout with xps flow
                    103103: 06/05/25: Matt Blanton: Re: setting max fanout with xps flow
    103098: 06/05/25: Peter Alfke: Re: setting max fanout with xps flow
    103106: 06/05/25: Matt Blanton: Re: setting max fanout with xps flow
        103146: 06/05/26: Martin Thompson: Re: setting max fanout with xps flow
103017: 06/05/24: <raarce@gmail.com>: Report for routing resource usage?
    103045: 06/05/24: Ron: Re: Report for routing resource usage?
        103203: 06/05/28: Kolja Sulimma: Re: Report for routing resource usage?
    103205: 06/05/28: Paul Leventis: Re: Report for routing resource usage?
103022: 06/05/24: <joel.weddick@lmco.com>: XdmHelpers:662
103036: 06/05/24: <42hammer@gmail.com>: Embedded Programming of Altera EPCS device
103043: 06/05/24: <harbinxiaoting@hit.edu.cn>: how to readback a frame
    103065: 06/05/25: Vivian Bessler: Re: how to readback a frame
    103620: 06/06/06: <harbinxiaoting@hit.edu.cn>: Re: how to readback a frame
    103621: 06/06/06: Nicky: Re: how to readback a frame
    103803: 06/06/12: Vivian Bessler: Re: how to readback a frame
        103886: 06/06/14: Vivian Bessler: Re: how to readback a frame
    103884: 06/06/14: Nicky: Re: how to readback a frame
103048: 06/05/24: <roiavidan@gmail.com>: problem programming Altera Cyclone device
    103057: 06/05/25: <MikeShepherd564@btinternet.com>: Re: problem programming Altera Cyclone device
    103058: 06/05/25: Nial Stewart: Re: problem programming Altera Cyclone device
        103066: 06/05/25: Nial Stewart: Re: problem programming Altera Cyclone device
            103153: 06/05/26: Nial Stewart: Re: problem programming Altera Cyclone device
                103155: 06/05/26: Hans: Re: problem programming Altera Cyclone device
    103064: 06/05/25: <roiavidan@gmail.com>: Re: problem programming Altera Cyclone device
    103105: 06/05/25: Roi: Re: problem programming Altera Cyclone device
    103186: 06/05/27: Roi: Re: problem programming Altera Cyclone device
103051: 06/05/25: Jim: ISE sends sensitive information to Xilinx site!
    103056: 06/05/25: Ron: Re: ISE sends sensitive information to Xilinx site!
        103062: 06/05/25: Jan Panteltje: Re: ISE sends sensitive information to Xilinx site!
    103060: 06/05/25: <stenasc@yahoo.com>: Re: ISE sends sensitive information to Xilinx site!
    103061: 06/05/25: John Adair: Re: ISE sends sensitive information to Xilinx site!
        103063: 06/05/25: Jan Panteltje: Re: ISE sends sensitive information to Xilinx site!
            103067: 06/05/25: David R Brooks: Re: ISE sends sensitive information to Xilinx site!
                103068: 06/05/25: Jan Panteltje: Re: ISE sends sensitive information to Xilinx site!
                    103071: 06/05/25: <MikeShepherd564@btinternet.com>: Re: ISE sends sensitive information to Xilinx site!
                        103072: 06/05/25: Jan Panteltje: Re: ISE sends sensitive information to Xilinx site!
                            103079: 06/05/25: Ben Jones: Remote Application delivery for EDA
                                103088: 06/05/25: Ben Jones: Re: Remote Application delivery for EDA
                                    103231: 06/05/29: Ron: Re: Remote Application delivery for EDA
                                        103252: 06/05/29: Phil Hays: Re: Remote Application delivery for EDA
                                        103258: 06/05/29: Tim: Re: Remote Application delivery for EDA
                                103120: 06/05/26: Jim Granville: Re: Remote Application delivery for EDA
                            103090: 06/05/25: <MikeShepherd564@btinternet.com>: Re: ISE sends sensitive information to Xilinx site!
                                103094: 06/05/25: Jan Panteltje: Re: ISE sends sensitive information to Xilinx site!
                            103108: 06/05/25: Tim: Re: ISE sends sensitive information to Xilinx site!
                                103144: 06/05/26: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Re: ISE sends sensitive information to Xilinx site!
                        103244: 06/05/29: Jan Panteltje: Re: ISE sends sensitive information to Xilinx site!
            103119: 06/05/26: Jim Granville: Re: ISE sends sensitive information to Xilinx site!
                103149: 06/05/26: Jan Panteltje: Re: ISE sends sensitive information to Xilinx site!
        103118: 06/05/26: Jim Granville: Re: ISE sends sensitive information to Xilinx site!
            103128: 06/05/26: Jim Granville: Re: ISE sends sensitive information to Xilinx site!
            103154: 06/05/26: Austin Lesea: Re: ISE sends sensitive information to Xilinx site!------ Only if
                103161: 06/05/26: Austin Lesea: Re: ISE sends sensitive information to Xilinx site!------ Only if
                    103169: 06/05/26: Thomas Entner: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
                    103172: 06/05/27: John_H: Re: ISE sends sensitive information to Xilinx site!------ Only if
                        103178: 06/05/27: Jim Granville: Re: ISE sends sensitive information to Xilinx site!------ Only if
                    103185: 06/05/27: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
                        103195: 06/05/27: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
                    103190: 06/05/27: Austin Lesea: Re: ISE sends sensitive information to Xilinx site!------ Only if
                        103204: 06/05/28: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
    103075: 06/05/25: dp: Re: ISE sends sensitive information to Xilinx site!
    103085: 06/05/25: dp: Re: Remote Application delivery for EDA
    103092: 06/05/25: Erik Widding: Re: ISE sends sensitive information to Xilinx site!
    103096: 06/05/25: Robin Bruce: Re: Remote Application delivery for EDA
    103097: 06/05/25: dp: Re: Remote Application delivery for EDA
    103127: 06/05/25: dp: Re: ISE sends sensitive information to Xilinx site!
    103165: 06/05/26: <fpga_toys@yahoo.com>: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
    103176: 06/05/26: Marc Randolph: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
    103187: 06/05/27: dp: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
    103189: 06/05/27: radarman: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
    103241: 06/05/29: <wv9557@yahoo.com>: Re: ISE sends sensitive information to Xilinx site!
103053: 06/05/25: <antti.tyrvainen@luukku.com>: Quartus and Cygwin X-server
    103093: 06/05/25: Mike Treseler: Re: Quartus and Cygwin X-server
    103138: 06/05/26: int19h: Re: Quartus and Cygwin X-server
    103210: 06/05/28: <antti.tyrvainen@luukku.com>: Re: Quartus and Cygwin X-server
103073: 06/05/25: Vivian Bessler: ChipScope and the FPGA Editor ILA command
    103082: 06/05/25: Tim Verstraete: Re: ChipScope and the FPGA Editor ILA command
103074: 06/05/25: Tomasz Dziecielewski: Metastability question (newbie)
    103076: 06/05/25: Phil Hays: Re: Metastability question (newbie)
    103077: 06/05/25: Peter Alfke: Re: Metastability question (newbie)
103083: 06/05/25: Marco: ISE .ant file
103099: 06/05/25: Antti: using Altium DXP2004 with Virtex4, also soft processors
103101: 06/05/25: Eshwar: Xilinx ML321 (v2pro rocket io): Adding PCIe functionality
    103104: 06/05/25: Antti: Re: Xilinx ML321 (v2pro rocket io): Adding PCIe functionality
        103296: 06/05/30: Eshwar: Re: Xilinx ML321 (v2pro rocket io): Adding PCIe functionality
103107: 06/05/25: walterwwongjr@gmail.com: Startup in Dynamic Reconfigurable Computing needs a FPGA Designer
103110: 06/05/25: <jaxato@gmail.com>: DSP48E, What are the internal implementations used?
    103112: 06/05/25: Peter Alfke: Re: DSP48E, What are the internal implementations used?
        103116: 06/05/25: Austin Lesea: Re: DSP48E, What are the internal implementations used?
    103113: 06/05/25: Austin Lesea: Re: DSP48E, What are the internal implementations used?
    103115: 06/05/25: <jaxato@gmail.com>: Re: DSP48E, What are the internal implementations used?
    103117: 06/05/25: mk: Re: DSP48E, What are the internal implementations used?
    103121: 06/05/25: Peter Alfke: Re: DSP48E, What are the internal implementations used?
    103122: 06/05/25: <jaxato@gmail.com>: Re: DSP48E, What are the internal implementations used?
    103129: 06/05/25: Ray Andraka: Re: DSP48E, What are the internal implementations used?
        103130: 06/05/26: mk: Re: DSP48E, What are the internal implementations used?
            103133: 06/05/25: Ray Andraka: Re: DSP48E, What are the internal implementations used?
103123: 06/05/26: Roland: Synthesizing VHDL delays [noob]
    103124: 06/05/25: Antti: Re: Synthesizing VHDL delays [noob]
        103126: 06/05/26: Roland: Re: Synthesizing VHDL delays [noob]
103125: 06/05/25: radarman: Altium Livedesign eval boards - can you add a configuration prom?
    103140: 06/05/25: Antti: Re: Altium Livedesign eval boards - can you add a configuration prom?
    103194: 06/05/28: Kolja Waschk: Re: Altium Livedesign eval boards - can you add a configuration prom?
    103487: 06/06/04: Alex Gibson: Re: Altium Livedesign eval boards - can you add a configuration prom?
        103785: 06/06/11: Daniel O'Connor: Re: Altium Livedesign eval boards - can you add a configuration prom?
103139: 06/05/25: bijoy: FPGA : FFT
    103162: 06/05/26: Tim Verstraete: Re: FPGA : FFT
103141: 06/05/25: <vladimir@baykov.de>: Re: Cordic-based Sine Computer in MyHDL
103145: 06/05/26: marta: ADV7321 interlaced mode
    103198: 06/05/28: Derek Simmons: Re: ADV7321 interlaced mode
        103234: 06/05/29: marta: Re: ADV7321 interlaced mode
103147: 06/05/26: <goldenorfe@gmail.com>: Agility - user experiences? (newbie)
103148: 06/05/26: srini: DCM lock - require clarification
    103150: 06/05/26: Austin Lesea: Re: DCM lock - require clarification
103157: 06/05/26: Joseph: Xilinx IP wizard help
    103158: 06/05/26: Guru: Re: Xilinx IP wizard help
    103159: 06/05/26: Paulo Dutra: Re: Xilinx IP wizard help
    103160: 06/05/26: Joseph: Re: Xilinx IP wizard help
    103227: 06/05/29: Guru: Re: Xilinx IP wizard help
103163: 06/05/26: Jeff Brower: initial block processing in XST 8.1, part 2
103168: 06/05/26: <sgfallows@gmail.com>: Xilinx EDK library size issue
103170: 06/05/26: branek: tft and uClinux
    103174: 06/05/27: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: tft and uClinux
        103180: 06/05/27: Alex Freed: Re: tft and uClinux
        103184: 06/05/27: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: tft and uClinux
    103177: 06/05/26: branek: Re: tft and uClinux
    103182: 06/05/27: Antti: Re: tft and uClinux
        103281: 06/05/30: Tushar Dongre: Re: tft and uClinux
    103196: 06/05/28: branek: Re: tft and uClinux
    103199: 06/05/28: Antti: Re: tft and uClinux
    103284: 06/05/30: Antti: Re: tft and uClinux
103171: 06/05/27: Jim Granville: Potential of the CELL Processor for Scientific Computing
    103183: 06/05/27: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Potential of the CELL Processor for Scientific Computing
103179: 06/05/27: Marco T.: DVI connected to Virtex-4
    103181: 06/05/27: Antti: Re: DVI connected to Virtex-4
103192: 06/05/27: savs: Peripheral connected to multiple OPB buses
    103193: 06/05/27: Antti: Re: Peripheral connected to multiple OPB buses
    103197: 06/05/28: savs: Re: Peripheral connected to multiple OPB buses
    103201: 06/05/28: beeraka@gmail.com: Re: Peripheral connected to multiple OPB buses
    103208: 06/05/29: Zara: Re: Peripheral connected to multiple OPB buses
        103265: 06/05/30: Zara: Re: Peripheral connected to multiple OPB buses
    103228: 06/05/29: Guru: Re: Peripheral connected to multiple OPB buses
    103253: 06/05/29: savs: Re: Peripheral connected to multiple OPB buses
103200: 06/05/28: Weddick: COREGEN: DCM
    103266: 06/05/30: srini: Re: COREGEN: DCM
103202: 06/05/28: purple_stars: fpga uclinux, good starter board ?
    103218: 06/05/29: xsteve: Re: fpga uclinux, good starter board ?
    103221: 06/05/29: Antti: Re: fpga uclinux, good starter board ?
    103235: 06/05/29: John Adair: Re: fpga uclinux, good starter board ?
        103291: 06/05/30: John Adair: Re: fpga uclinux, good starter board ?
    103237: 06/05/29: Antti: Re: fpga uclinux, good starter board ?
    103243: 06/05/29: xsteve: Re: fpga uclinux, good starter board ?
    103246: 06/05/29: Antti: Re: fpga uclinux, good starter board ?
    103292: 06/05/30: Antti: Re: fpga uclinux, good starter board ?
103211: 06/05/28: Jim: Specifying a non connected port
103212: 06/05/28: Marco: ISE 8.1 with 7.1
    103214: 06/05/28: Antti: Re: ISE 8.1 with 7.1
    103216: 06/05/29: Marco: Re: ISE 8.1 with 7.1
    103217: 06/05/29: Antti: Re: ISE 8.1 with 7.1
    103220: 06/05/29: Marco: Re: ISE 8.1 with 7.1
    103223: 06/05/29: John McGrath: Re: ISE 8.1 with 7.1
        103248: 06/05/29: leevv: Re: ISE 8.1 with 7.1
    103230: 06/05/29: Marco: Re: ISE 8.1 with 7.1
103213: 06/05/28: jpvarkey@gmail.com: PCI related documents
    103215: 06/05/29: water7: Re: PCI related documents
103222: 06/05/29: <shabana_rizvi@yahoo.com>: XC9572 Readback
    103226: 06/05/29: Falk Brunner: Re: XC9572 Readback
103229: 06/05/29: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: ngdbuild:604 - storing netlists in other directories than the project
    103232: 06/05/29: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Re: ngdbuild:604 - storing netlists in other directories than the
    103239: 06/05/29: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Re: ngdbuild:604 - storing netlists in other directories than the
    103240: 06/05/29: Petter Gustad: Re: ngdbuild:604 - storing netlists in other directories than the project dir
103233: 06/05/29: jpvarkey@gmail.com: PCI related doubts !!!!!!
103236: 06/05/29: <r-m-w@web.de>: JTAG in-system programming of PROM devices
    103238: 06/05/29: Antti: Re: JTAG in-system programming of PROM devices
103242: 06/05/29: <already5chosen@yahoo.com>: Fast Serial I/O on Virtex-5
    103247: 06/05/29: Antti: Re: Fast Serial I/O on Virtex-5
        103255: 06/05/29: Antti Lukats: Re: Fast Serial I/O on Virtex-5
            103256: 06/05/30: Jim Granville: Re: Fast Serial I/O on Virtex-5
    103254: 06/05/29: Peter Alfke: Re: Fast Serial I/O on Virtex-5
    103257: 06/05/29: Antti: Re: Fast Serial I/O on Virtex-5
103245: 06/05/29: metry: How to add a peripheral IP generated by Coregen to EDK?
    103249: 06/05/29: Andi: Re: How to add a peripheral IP generated by Coregen to EDK?
103250: 06/05/29: bjzhangwn: hard disk drivers problem
    103251: 06/05/29: dp: Re: hard disk drivers problem
    103282: 06/05/30: =?ISO-8859-1?Q?Michael_Sch=F6berl?=: Re: hard disk drivers problem
103259: 06/05/29: Kishore: System Generator cc1 error
    104635: 06/07/03: David: Re: System Generator cc1 error
103260: 06/05/29: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: IOB IO Standards in Spartan 3
    103261: 06/05/29: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: IOB IO Standards in Spartan 3
    103263: 06/05/30: Antti Lukats: Re: IOB IO Standards in Spartan 3
    103264: 06/05/29: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: IOB IO Standards in Spartan 3
    103304: 06/05/30: Antti: Re: IOB IO Standards in Spartan 3
103262: 06/05/29: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Personalization of Xilinx ISE
    103270: 06/05/30: Aurelian Lazarut: Re: Personalization of Xilinx ISE
        103287: 06/05/30: Aurelian Lazarut: Re: Personalization of Xilinx ISE
            103289: 06/05/30: c d saunter: Re: Personalization of Xilinx ISE
    103286: 06/05/30: Gabor: Re: Personalization of Xilinx ISE
    103340: 06/05/31: Gabor: Re: Personalization of Xilinx ISE
103267: 06/05/30: jpvarkey@gmail.com: PCI Header types !!!
    103269: 06/05/30: Antti: Re: PCI Header types !!!
        103274: 06/05/30: Alan Myler: Re: PCI Header types !!!
    103271: 06/05/30: jpvarkey@gmail.com: Re: PCI Header types !!!
    103272: 06/05/30: Antti: Re: PCI Header types !!!
    103279: 06/05/30: colin: Re: PCI Header types !!!
    103294: 06/05/30: Brannon: Re: PCI Header types !!!
103268: 06/05/30: jpvarkey@gmail.com: Power Up delay in FPGA !!!!!
    103275: 06/05/30: Rene Tschaggelar: Re: Power Up delay in FPGA !!!!!
        103276: 06/05/30: KJ: Re: Power Up delay in FPGA !!!!!
103273: 06/05/30: <m_oylulan@hotmail.com>: Mains pick-up on I/O pins
    103280: 06/05/30: Leon: Re: Mains pick-up on I/O pins
    103285: 06/05/30: Gabor: Re: Mains pick-up on I/O pins
    103306: 06/05/30: Ben Jackson: Re: Mains pick-up on I/O pins
    103396: 06/06/01: <m_oylulan@hotmail.com>: Re: Mains pick-up on I/O pins
103277: 06/05/30: Srikanth BJ: generating IP cores
103278: 06/05/30: Srikanth BJ: generating IP cores
    103283: 06/05/30: Antti: Re: generating IP cores
        103305: 06/05/30: Ben Jackson: Re: generating IP cores
        103381: 06/05/31: Colin Hankins: Re: generating IP cores
    103288: 06/05/30: Srikanth BJ: Re: generating IP cores
    103300: 06/05/30: Antti: Re: generating IP cores
103293: 06/05/30: Ed: reverse from jedec to abel
103295: 06/05/30: John Adair: OVERCOAT - FPGA Development Arrays
103298: 06/05/30: billu: Aurora sample design: Testing/Eye Diagrams
    103302: 06/05/30: Ed McGettigan: Re: Aurora sample design: Testing/Eye Diagrams
    103423: 06/06/01: billu: Re: Aurora sample design: Testing/Eye Diagrams
103301: 06/05/30: Josh Rosen: Running Xilinx and Altera Tools on Fedora Core 5
    103303: 06/05/30: Josh Rosen: Re: Running Xilinx and Altera Tools on Fedora Core 5
    103313: 06/05/31: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Running Xilinx and Altera Tools on Fedora Core 5
103308: 06/05/30: water7: PCI Design
    103391: 06/06/01: Nial Stewart: Re: PCI Design
    103486: 06/06/04: water7: Re: PCI Design
    103490: 06/06/04: <fpga_toys@yahoo.com>: Re: PCI Design
103311: 06/05/30: mike_la_jolla: Need help reattaching top to FPGA
    103317: 06/05/30: Austin Lesea: Re: Need help reattaching top to FPGA
    103320: 06/05/31: Bob: Re: Need help reattaching top to FPGA
    103336: 06/05/31: Brian Davis: Re: Need help reattaching top to FPGA
103312: 06/05/30: Joseph: PLB transfers: PPC to IP
    103329: 06/05/31: Ben Jones: Re: PLB transfers: PPC to IP
103314: 06/05/31: Mr. Ken: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103316: 06/05/30: Peter Alfke: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
        103321: 06/05/31: Mr. Ken: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103318: 06/05/31: John_H: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
        103322: 06/05/31: Mr. Ken: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
            103341: 06/05/31: John_H: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
                103375: 06/06/01: Mr. Ken: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103319: 06/05/30: John_H: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103323: 06/05/31: Jim Granville: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103324: 06/05/31: Zara: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
        103328: 06/05/31: Mr. Ken: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
            103330: 06/05/31: Falk Brunner: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
                103362: 06/05/31: John_H: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103342: 06/05/31: John_H: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103347: 06/05/31: Stephen Craven: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103358: 06/05/31: Stephen Craven: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103360: 06/05/31: Kolja Sulimma: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103361: 06/05/31: Kolja Sulimma: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
        103376: 06/06/01: Mr. Ken: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
            103382: 06/06/01: Kolja Sulimma: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
                103383: 06/06/01: Mr. Ken: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103369: 06/05/31: Peter Alfke: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103380: 06/06/01: Herman Dullink: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    104006: 06/06/16: John_H: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
        104011: 06/06/16: Ray Andraka: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
            104028: 06/06/16: John_H: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    104007: 06/06/16: John_H: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103325: 06/05/30: jpvarkey@gmail.com: Cardbus Power On Reset !!!!!!!!
    103326: 06/05/31: Antti: Re: Cardbus Power On Reset !!!!!!!!
        103332: 06/05/31: Nial Stewart: Re: Cardbus Power On Reset !!!!!!!!
    103327: 06/05/31: jpvarkey@gmail.com: Re: Cardbus Power On Reset !!!!!!!!
    103333: 06/05/31: Antti: Re: Cardbus Power On Reset !!!!!!!!
    103334: 06/05/31: jpvarkey@gmail.com: Re: Cardbus Power On Reset !!!!!!!!
    103335: 06/05/31: Antti: Re: Cardbus Power On Reset !!!!!!!!
    103482: 06/06/03: stijena: Re: Cardbus Power On Reset !!!!!!!!
    103510: 06/06/04: jpvarkey@gmail.com: Re: Cardbus Power On Reset !!!!!!!!
103331: 06/05/31: Michael Dales: Problems simulation plb_gemac core for Virtex-II Pro
103337: 06/05/31: Roger: RocketIO signal polarity swap
    103413: 06/06/01: Ed McGettigan: Re: RocketIO signal polarity swap
        103455: 06/06/02: Roger: Re: RocketIO signal polarity swap
103338: 06/05/31: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Price history?
103339: 06/05/31: rickman: Configuring Spartan 3
    103344: 06/05/31: Aurelian Lazarut: Re: Configuring Spartan 3
        103351: 06/05/31: Aurelian Lazarut: Re: Configuring Spartan 3
    103345: 06/05/31: rickman: Re: Configuring Spartan 3
    103359: 06/05/31: Greg Neff: Re: Configuring Spartan 3
        103411: 06/06/01: Aurelian Lazarut: Re: Configuring Spartan 3
    103395: 06/06/01: rickman: Re: Configuring Spartan 3
    103415: 06/06/01: rickman: Re: Configuring Spartan 3
103343: 06/05/31: CMOS: combining state machines.
    103346: 06/05/31: Zara: Re: combining state machines.
    103365: 06/05/31: Ron: Re: combining state machines.
    103399: 06/06/01: Andy: Re: combining state machines.
103349: 06/05/31: <henryk.mueller@gmx.de>: Virtex-4FX12MM: Any hardware MAC address accessable?
    103350: 06/05/31: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
        103354: 06/05/31: Tim: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
            103363: 06/05/31: Antti Lukats: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
                103364: 06/05/31: Tim: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
    103352: 06/05/31: <henryk.mueller@gmx.de>: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
    103353: 06/05/31: Antti: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
    103355: 06/05/31: <henryk.mueller@gmx.de>: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
    103368: 06/05/31: Antti: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
    103386: 06/06/01: <henryk.mueller@gmx.de>: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
103356: 06/05/31: Jim: Using part of CPLD to Invert Own Clock
    103357: 06/05/31: Austin Lesea: Re: Using part of CPLD to Invert Own Clock
        103434: 06/06/01: Jim: Re: Using part of CPLD to Invert Own Clock
103367: 06/05/31: <junk.dontsend@gmail.com>: How many of the old reference sites are still around?
103371: 06/05/31: <ed.agunos@gmail.com>: controlling synthesis and implemention with tcl/tk scripts
103372: 06/05/31: Luke: SystemVeriling Synthesis for Xilinx FPGAs
    103373: 06/05/31: Luke: Re: SystemVeriling Synthesis for Xilinx FPGAs
    103453: 06/06/02: Hans: Re: SystemVeriling Synthesis for Xilinx FPGAs
103374: 06/05/31: Adam Megacz: clockless arbiters on fpgas?
    103377: 06/05/31: Peter Alfke: Re: clockless arbiters on fpgas?
        103387: 06/06/01: Falk Brunner: Re: clockless arbiters on fpgas?
            103427: 06/06/02: Jim Granville: Re: clockless arbiters on fpgas?
    103421: 06/06/01: Mike Treseler: Re: clockless arbiters on fpgas?
        103953: 06/06/15: Adam Megacz: Re: clockless arbiters on fpgas?
            103968: 06/06/16: Sylvain Munaut: Re: clockless arbiters on fpgas?
            103975: 06/06/16: mk: Re: clockless arbiters on fpgas? [here's how it's done in ASICs]
        103962: 06/06/15: Adam Megacz: Re: clockless arbiters on fpgas?
        103964: 06/06/15: Adam Megacz: Re: clockless arbiters on fpgas? [here's how it's done in ASICs]
        103966: 06/06/15: Adam Megacz: Re: clockless arbiters on fpgas? [here's how it's done in ASICs]
        103997: 06/06/16: Adam Megacz: Re: clockless arbiters on fpgas?
        103999: 06/06/16: Adam Megacz: Re: clockless arbiters on fpgas? [here's how it's done in ASICs]
        104000: 06/06/16: Adam Megacz: Re: clockless arbiters on fpgas?
    103428: 06/06/01: Tim: Re: clockless arbiters on fpgas?
        103952: 06/06/15: Adam Megacz: Re: clockless arbiters on fpgas?
    103430: 06/06/01: Peter Alfke: Re: clockless arbiters on fpgas?
        103431: 06/06/01: Jon Elson: Re: clockless arbiters on fpgas?
    103432: 06/06/01: dalai lamah: Re: clockless arbiters on fpgas?
    103433: 06/06/01: Peter Alfke: Re: clockless arbiters on fpgas?
    103459: 06/06/02: Marc Guardiani: Re: clockless arbiters on fpgas?
    103460: 06/06/02: Peter Alfke: Re: clockless arbiters on fpgas?


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search