Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMar2019

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 102400

Article: 102400
Subject: Re: getting good deals on small qty?
From: "Antti" <Antti.Lukats@xilant.com>
Date: 15 May 2006 14:39:41 -0700
Links: << >>  << T >>  << A >>
different price-break levels.

A 100 pcs is peanuts, no discount
B 1000 pcs is peanuts, no discount
C 10000 pcs order buys some discount
D 500,000 order placed 14 months advance buys real nice price.

price difference C vs D is still huge.

as you are talking 10-100-1000 prices there is nothing much the disti
could do.
its still not much profit for them.
I was surprised when SiLabs said they have flat pricing for 1 to 1000
well that is damn good price, seems that the are selling qty 1 for the
price
that you would expect for qty 1000,

9USD for S3e is already notsobad,
if you are lucky you get some cents off that price for qty 1000
but dont expect large difference.

for 100qty almost no discount. some penny maybe.

Antti


Article: 102401
Subject: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
From: Austin Lesea <austin@xilinx.com>
Date: Mon, 15 May 2006 14:48:26 -0700
Links: << >>  << T >>  << A >>
Jon,

The 4VFX40 and FX140 were taped out, with first samples available 4th Q 
2006.

I would suggest using the FX60 for development for a FX40 design.

Check with your FAE for status.  But now that we have fixed things, 
these should go smoothly.

Sadly, the fixes to the MGTs did affect the timeliness of the rollout 
(an understatement if I have ever made one).  Let us be honest;  IT MADE 
US LATE!  YES, L A T E.

And we are very sorry, and we promise not to ever make those mistakes again.

All the other parts (FX12, 20, 60, 100) are available as 'CES4'.

If anyone wants to berate us for their FX experience on V4, please do 
(we deserve it).  All I can say is that we have finally fixed things, 
and are shipping, and will go to production now that we have that over 
and done with.

 From the lash marks on the senior execs, I'd say our customers were 
very expressive with their displeasure, and a lot of processes and 
procedures got changed when it comes to announcing anything.  Especially 
anything with analog content.  We also have learned a lot about making 
gigabit transceivers that will work flawlessly, work identically, and 
yield well.

Austin



Jon Beniston wrote:

> Austin Lesea wrote:
> 
>>lb,
>>
>>V4 FX is not skipped.  It is most definitely being shipped right now.
>>In fact the backlog was just cleared.
>>
> 
> 
> Are any FX40 parts at the fab yet?
> 
> Cheers,
> Jon
> 

Article: 102402
Subject: Re: Virtex 5 announced and sampling
From: Austin Lesea <austin@xilinx.com>
Date: Mon, 15 May 2006 15:16:41 -0700
Links: << >>  << T >>  << A >>
Antti,

So do we.

Austin

Antti Lukats wrote:

> "Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag 
> news:4468f4b4@clear.net.nz...
> 
>>Peter Alfke wrote:
>>
>>
>>>Antti, remember how a LUT is really constructed.
>>>It contains 64 latches plus a 6-level 64-to-1 multiplexer, like a
>>>christmas tree.
>>>The data sheet just (for tutorial purposes) shows the final stage of
>>>this big multiplexer separately.
>>>If that bothers you, ignore it. But just do not believe that it costs
>>>more than the extra delay of any multiplexer level.
>>>There are 6 levels of multiplexing, nothing we can do about it.
>>
>>ISTR that Altera define differing delay times, for their LUT inputs.
>>Will Xilinx define to that level of detail now, as well ?
>>
>>-jg
>>
> 
> yes Altera uses different LUT delays for different inputs to achive better 
> timing
> 
> Antti 
> 
> 

Article: 102403
Subject: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
From: Josh Rosen <bjrosen@polybusPleaseDontSPAMme.com>
Date: Mon, 15 May 2006 18:26:54 -0400
Links: << >>  << T >>  << A >>
On Mon, 15 May 2006 14:48:26 -0700, Austin Lesea wrote:

> Jon,
> 
> The 4VFX40 and FX140 were taped out, with first samples available 4th Q
> 2006.
> 
> I would suggest using the FX60 for development for a FX40 design.
> 
> Check with your FAE for status.  But now that we have fixed things, these
> should go smoothly.
> 
> Sadly, the fixes to the MGTs did affect the timeliness of the rollout (an
> understatement if I have ever made one).  Let us be honest;  IT MADE US
> LATE!  YES, L A T E.
> 
> And we are very sorry, and we promise not to ever make those mistakes
> again.
> 
> All the other parts (FX12, 20, 60, 100) are available as 'CES4'.
> 
> If anyone wants to berate us for their FX experience on V4, please do (we
> deserve it).  All I can say is that we have finally fixed things, and are
> shipping, and will go to production now that we have that over and done
> with.
> 
>  From the lash marks on the senior execs, I'd say our customers were
> very expressive with their displeasure, and a lot of processes and
> procedures got changed when it comes to announcing anything.  Especially
> anything with analog content.  We also have learned a lot about making
> gigabit transceivers that will work flawlessly, work identically, and
> yield well.
> 
> Austin

Originally the V4FX series was supposed to support quad date rate (10GHz),
is that ever going to happen or has Xilinx given up on that? In the
InfiniBand world QDR is going to start happening in the 2007 time frame so
it would be nice if QDR RocketIO were to become available next year in
either the V4FX or V5FX.

Also do you plan to add hardware CRC16s to the V5FX? The V4FX had hardware
CRC32s but not CRC16s, having both would be a big help. 

One final thing which is a tools issue and has nothing to do with the
hardware. Please provide separate models for the CRC32s, tying them to the
RocketIO models is a major pain. The CRC32 may be physically located in
the same tile as the SerDes but logically it's independent. It makes as
little sense to combine the CRC32 model with the SerDes model as it would
to tie the Block RAM and Multiplier together. Those components are also
next to each other but you provide separate models. One final thing,
please provide Verilog behavioral models for the RocketIO instead of those
awful SMART models. SMART models slow down the simulation and their lack
of transparency complicates the debug process.

 

Article: 102404
Subject: Re: Virtex 5 announced and sampling ... and real!
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 16 May 2006 10:38:55 +1200
Links: << >>  << T >>  << A >>
Austin Lesea wrote:

> Jim,
> 
> Basically, equivalent in this sense is "equal."
> 
> So if the static power was 1 watt before, it is still one watt (or less).
> 
> At 65nm, there is gate leakage.
> 
> Gate leakage does not vary with temperature.
> 
> So there is a component of the static power that remains the same at 
> -40C, or at 25C, or even at 100C.
> 
> That factor is a significant part of the static leakage.  Basically, the 
> cost of using 65nm.
> 
> What you will find is that the typical static current for Vccint 
> (Iccint) for V5 is at first, larger than what you would expect. However, 
> it will be on par, or below what the 100C number was for the V4.  If the 
> worst case for V4 at 100C was X watts, then a similar sized V5 will be X 
> watts or less over the entire tempeature range, without a huge 
> difference from 25C to 100C (which was what folks are used to seeing 
> before gate leakage became a dominant factor in 65nm).
> 
> Does this answer the question?

Yes, thanks.
  I'll admit I took the 'Lower' in your sentence

" Lower dynamic power, and equivalent static power, today."

  as applying to all clauses.

  I do see the curves and infos, are rather sparse on revealing the 
_actual_ Static Icc numbers - as dynamic Icc keeps improving, the static
Icc is going to become a larger % of the power budget....

-jg






Article: 102405
Subject: USB2 camera to Xilinx ML40x boards
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Mon, 15 May 2006 16:12:30 -0700
Links: << >>  << T >>  << A >>
Does any one have any software (or experience) to share (or sell) concerning 
bringing a USB2 camera image into a XILINX ML401, ML402, or ML403 board.

Many thanks,

Brad Smallridge
Ai Vision
 



Article: 102406
Subject: Re: Virtex 5 announced and sampling ... and real!
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 15 May 2006 23:48:07 GMT
Links: << >>  << T >>  << A >>
http://www.google.com/search?hl=en&lr=&q=%22triple+oxide%22+semiconductor+-xilinx

"Austin Lesea" <austin@xilinx.com> wrote in message 
news:e4arf0$avv12@xco-news.xilinx.com...
> Uwe,
>
> Easy for you to say now.  But there was a time where the competition was 
> selling against triple oxide as being too new, too risky, and too 
> expensive (with no benefit).
>
> So, humor me, name the chips that use a triple oxide process.
>
> Austin
>
> Uwe Bonnes wrote:
>
>> Austin Lesea <austin@xilinx.com> wrote:
>> ...
>>
>>>Imitation is the sincerest form of flattery, as STM now also has a triple 
>>>oxide 90nm process.  I am sure they will also offer it at 65nm, as they 
>>>also realized how useful it was to their customers.
>>
>>
>> If using triple oxide is imitation and "Imitation is the sincerest form 
>> of
>> flattery" then the whole semiconductor industry is using this
>> "flattery". Did Xilinx invent the MOS transistor, self aligning gates, 
>> wire
>> bonding, etc. and all those other things they use to produce an IC? 
>> Well,
>> as Newton said: "If I have seen a little further it is by standing on the
>> shoulders of Giants."
>>
>> Is using a third oxid thickness really that great genuine invention 
>> nobody
>> thought of before. Didn't the engineers at Xilinx need to bang their head
>> fighting for this feature against many (d|m)amages seeing only the added
>> cost? Perhaps other engineers in other companies wheren't that succesfull 
>> on
>> the first try. Now perhaps their (d|m)amages see the light.
>>
>> Otherwise congratulation to the new "baby".
>>
>> And hopefully a faster release story to general availability then for 
>> XC3SE and ... and ...
>>
>> Cheers 



Article: 102407
Subject: Re: Virtex 5 announced and sampling
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 15 May 2006 23:53:26 GMT
Links: << >>  << T >>  << A >>
"Peter Alfke" <peter@xilinx.com> wrote in message 
news:1147725970.779784.92570@u72g2000cwu.googlegroups.com...
> Antti, remember how a LUT is really constructed.
> It contains 64 latches plus a 6-level 64-to-1 multiplexer, like a
> christmas tree.
> The data sheet just (for tutorial purposes) shows the final stage of
> this big multiplexer separately.
> If that bothers you, ignore it. But just do not believe that it costs
> more than the extra delay of any multiplexer level.
> There are 6 levels of multiplexing, nothing we can do about it.
> Peter Alfke

So the luts are actually full multiplexers, not a memory array style of 
addressing?  I would have thought LUTs would work much better than general 
multiplexors by using a nand/nand style of structure to drive one active 
line in a 64-wide CMOS tree.  Muxes? 



Article: 102408
Subject: Actel Fusion FPGAs
From: "rickman" <spamgoeshere4@yahoo.com>
Date: 15 May 2006 16:59:21 -0700
Links: << >>  << T >>  << A >>
I read a couple of threads on the Actel Fusion FPGAs from early this
year saying they were delayed and not to expect them for up to 6
months.  It is now 3 months later and I was wondering if anyone had
heard anything more from Actel on these parts.

I was looking at the web site for their combination Fusion and ARM core
they call the M7Fusion.  It is shown in two parts, the M7AFS600 with
7000 tiles free of 14,000 or the M7AFS1500 with 32,000 tiles free of
about 38,000.  I am not so familar with the Actel tiles.  Are they
roughly comparable to a 4 LUT with a FF?  Or are they more limited?

I don't suppose anyone would have an idea of the price of the M7AFS600
and M7AFS1500 devices?  I guess if they are not shipping samples yet,
they don't really have a handle on pricing.

I am still waiting for the data sheet to download.  Are these parts 5
volt tolerant?  I see the analog section is good for +-12 volts, I
would expect the digital section could do 5 volts!


Article: 102409
Subject: Re: Virtex 5 announced and sampling
From: "Peter Alfke" <peter@xilinx.com>
Date: 15 May 2006 17:02:15 -0700
Links: << >>  << T >>  << A >>
Jim, the short answer is yes, and even for Virtex-4.
There is a limit to the numbers given in the data sheet, but Xilinx
software has, for several years, documented (and has taken advantage
of)  the differences in LUT through delay from the various inputs.  In
the battle of picoseconds, these small delay differences become
important

To Antti: The reason for only 32 bits in the SRL32, even though the
LUT6 has 64 latches, is different:
In previous generations with SRL16 in a LUT4, we used a circuit trick
(capacitive storage) to avoid using a master latch plus a slave latch,
which is the conventional way to build flip-flops or registers, even
shift registers. For ever smaller transistor geometries, such
"old-fashioned tricks" do not scale well, and we went back to a
conventional register implementation, with two latches per flip-flop,
thus only 32 shift register bits in a LUT6.

Thanks for the interest in Virtex-5. We are all very excited about our
new and very healthy baby... 
Peter Alfke,


Article: 102410
Subject: Re: Virtex 5 announced and sampling
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 16 May 2006 12:41:33 +1200
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> Jim, the short answer is yes, and even for Virtex-4.
> There is a limit to the numbers given in the data sheet, but Xilinx
> software has, for several years, documented (and has taken advantage
> of)  the differences in LUT through delay from the various inputs.  In
> the battle of picoseconds, these small delay differences become
> important
> 
> To Antti: The reason for only 32 bits in the SRL32, even though the
> LUT6 has 64 latches, is different:
> In previous generations with SRL16 in a LUT4, we used a circuit trick
> (capacitive storage) to avoid using a master latch plus a slave latch,
> which is the conventional way to build flip-flops or registers, even
> shift registers. For ever smaller transistor geometries, such
> "old-fashioned tricks" do not scale well, and we went back to a
> conventional register implementation, with two latches per flip-flop,
> thus only 32 shift register bits in a LUT6.
> 
> Thanks for the interest in Virtex-5. We are all very excited about our
> new and very healthy baby... 
> Peter Alfke,

  When will this topology be available in Spartan families ?

-jg


Article: 102411
Subject: Re: Virtex 5 announced and sampling ... and real!
From: Austin Lesea <austin@xilinx.com>
Date: Mon, 15 May 2006 18:17:28 -0700
Links: << >>  << T >>  << A >>
I can use google, too.

None of these links are actually referring to a real product, and most 
are referring to Xilinx (without naming us, like the Altera quote).

Austin

> http://www.google.com/search?hl=en&lr=&q=%22triple+oxide%22+semiconductor+-xilinx

Article: 102412
Subject: Re: reverse engineering ?
From: "dp" <dp@tgi-sci.com>
Date: 15 May 2006 18:38:08 -0700
Links: << >>  << T >>  << A >>
> I think your ideas are too abstract.

Basically you are right, I meant my comments in a broader
sense. Of course none of us is interested in aiding
evolution by giving property away...

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------


MikeShepherd564@btinternet.com wrote:
> >The only way is to keep on deveoping new things faster than the
> >old ones get copied. Witholding knowledge seems to be a "no-no"
> >in evolutionary sense, this is how we are designed. The smarter
> >a society, the more rewards it offers for knowledge creation.
> > This is not to say I am all open, of course. The above strategy
> >is probably optimized at an (inter?) species level, and I also am only
> >an individual... This is part (not a predominant one, though) of
> >the reason why I maintain a complete in-house tooling/development
> >capability, once you do a design on a wintel machine it is
> >anything but proprietary (can become public on a click
> >beyond the control of the design owner).
>
> I think your ideas are too abstract.  If I meet a lion, I need quick
> thinking to stay alive.  I could stop to consider whether evolution
> has equipped the lion better to deal with this meeting and whether, in
> the long run, the chances of surviving an encounter with a lion make
> it worthwhile or not to take evasive action.  I could prepare to
> lecture the lion on the moral and practical advantages of a vegetarian
> life, but I'd do better to defer these worthy pursuits until I'm out
> of harm's way.
>
> Substitute "lion" with "Chinese techno-pirate" and the same rules
> apply.  Some designs will be copied, but this doesn't mean we should
> abandon all protection.


Article: 102413
Subject: Re: Actel Fusion FPGAs
From: "rickman" <spamgoeshere4@yahoo.com>
Date: 15 May 2006 19:30:22 -0700
Links: << >>  << T >>  << A >>
rickman wrote:
> I am still waiting for the data sheet to download.  Are these parts 5
> volt tolerant?  I see the analog section is good for +-12 volts, I
> would expect the digital section could do 5 volts!

I got the datasheet and it is not 5 volt tolerant on the digital I/Os.
Very odd.  They use a process that can build a 12 volt tolerant analog
section and can't make the digital section 5 volt tolerant.  :^(


Article: 102414
Subject: Re: filter design
From: "light" <linhaidu840329@163.com>
Date: 15 May 2006 20:32:13 -0700
Links: << >>  << T >>  << A >>
Thank you for your comments, MikeShepherd.  I just want to write it in
a more convenient way! But if it hurt anybody, I'm very sorry,
I will try to resolve the problem myselt!
Thank you again for your help! I'll learn from it!


Article: 102415
Subject: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
From: ghelbig@lycos.com
Date: 15 May 2006 21:41:46 -0700
Links: << >>  << T >>  << A >>
I too had the same thought.  For a while.

A platform USB cable from the Xilinx store costs $150.  Given the time
to reverse engineer the protocol and design a board, and ...

And let's not forget that Xilinx owns the USB Vendor ID for the device,
so one can't re-use it without their permission.

You can't make one that's iMPACT compatable; might as well buy one of
the Digilent $38 versions.


Article: 102416
Subject: Re: USB2 camera to Xilinx ML40x boards
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Mon, 15 May 2006 22:50:08 -0600
Links: << >>  << T >>  << A >>
Brad Smallridge wrote:
> Does any one have any software (or experience) to share (or sell) concerning 
> bringing a USB2 camera image into a XILINX ML401, ML402, or ML403 board.
> 
> Many thanks,
> 
> Brad Smallridge
> Ai Vision
>  
> 
> 
I looked into trying to get a USB camera working on the ML402.  The 
problem is that the ML40x boards are really designed to be USB 
peripherals and not masters.  The webcams all seem to have proprietary 
interfaces (above the USB layer) and the only real way to use them is 
with a Windows driver.  No webcam manufacturers publish the specs on 
talking to the camera.  You might have better luck connecting to one of 
the cameras with a standard interface.  These are much more expensive 
though.  -Kevin

Article: 102417
Subject: Re: Actel Fusion FPGAs
From: "Andrew FPGA" <andrew.newsgroup@gmail.com>
Date: 15 May 2006 21:54:40 -0700
Links: << >>  << T >>  << A >>
I don't know about the Fusion tile but the Actel Proasic 2 family tile
seemed a lot more limited than when compared to a xilinx spartan 3
logic cell say.

>From what I recall, the Proasic logic element could be a flop OR a
lut(i think only 3 input from memory) not both at the same time like
the spartan 3. Also no carry chain or XOR/AND arithmetic bits and
pieces that  the spartan 3 has extra.

Regards
Andrew

rickman wrote:
> I read a couple of threads on the Actel Fusion FPGAs from early this
> year saying they were delayed and not to expect them for up to 6
> months.  It is now 3 months later and I was wondering if anyone had
> heard anything more from Actel on these parts.
>
> I was looking at the web site for their combination Fusion and ARM core
> they call the M7Fusion.  It is shown in two parts, the M7AFS600 with
> 7000 tiles free of 14,000 or the M7AFS1500 with 32,000 tiles free of
> about 38,000.  I am not so familar with the Actel tiles.  Are they
> roughly comparable to a 4 LUT with a FF?  Or are they more limited?
>
> I don't suppose anyone would have an idea of the price of the M7AFS600
> and M7AFS1500 devices?  I guess if they are not shipping samples yet,
> they don't really have a handle on pricing.
>
> I am still waiting for the data sheet to download.  Are these parts 5
> volt tolerant?  I see the analog section is good for +-12 volts, I
> would expect the digital section could do 5 volts!


Article: 102418
Subject: Re: Floating point reality check
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Mon, 15 May 2006 23:01:07 -0600
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> Andreas Ehliar wrote:
> 
>> H have recently been working on a floating point unit for a Virtex 4
>> SX 35. I have a floating point adder and a floating point multiplier.
>> The adder has 6 pipeline stages and the multiplier has 3 stages.
>>
>> The idea behind this project is to find out the kind of floating
>> point performance that is possible in a modern FPGA.
>>
>> Our floating point format uses up to 15 bits of mantissa (with an
>> implicit one) and up to 10 bits of exponent. We have managed to get
>> a complex butterfly running at up to 250 MHz. So my question now is
>> if these numbers are reasonable or if anyone knows of a reference to
>> a faster fpu.
>>
>>
>> We have already used some tricks to improve performance, for example
>> by manually instantiating LUTs so that we can build an adder with a
>> 2 to 1 MUX on one of the operands using only one LUT per bit.
>>
>> We have also tried to build up the design using RLOC:ed modules. This
>> did not lead to improved performance as compared to a non RLOC:ed design.
>> This could change once we start to fill up the device though. At the
>> moment we are only utilizing about 20% of the FPGA.
>>
>> /Andreas
> 
> 
> I've got a floating point 4/8/16 point kernel for Virtex4 that meets 
> timing at 400 MHz in the -10 speed grade part (limited by the speed of 
> the DSP48 and BRAM blocks).  It has 24 bit mantissas and 8 bit exponents 
> (IEEE single precision floating point).  Instances of that kernel are 
> combined obtain three parallel 400 MS/sec single precision 64 to 2048 
> point floating point FFTs for an aggregate continuous complex data 
> stream of up to 1.2GS/sec.  The 3 parallel 64-2k pt FFTs fit into a 
> single V4SX55-10 device, along with QDR-II RAM interfaces.
> 
> You need to use the adders in the DSP48's in order to reach 400MHz clock 
> rates, the LUT carry chains are too slow.  Reaching the 400 MHz 
> performance with the density needed requires considerable 
> hand-optimization as well as a number of algorithmic tricks.  You also 
> won't get the density if you start with floating point math operations 
> as your basic building blocks.

That's pretty impressive.  How did you implement the carry-kill chain, 
or whatever they call the ciruit that finds the location of the leading 
'1'?  This can be made with a carry chain, but I don't know if it would 
work with a 2.5ns period. -Kevin

Article: 102419
Subject: Synplify Pro warning - cudnt understand
From: "srini" <g.shrinivasan@gmail.com>
Date: 15 May 2006 22:52:17 -0700
Links: << >>  << T >>  << A >>
Hi,
In my TOP level verilog module, I have a data going from the ROM in one
of the blocks to the input of the Multiplier block. After synthesis, I
am getting the following warning message: " Removing sequential
instance of <instance name>.<signal name[]> in view.UNILIB.FPCPE(PRIM)
bcoz there are no reference to its outputs ".
Can anyone help me with some explanation for this warning message?

Thanks & regards,
Srini.


Article: 102420
Subject: Re: Actel Fusion FPGAs
From: "Antti" <Antti.Lukats@xilant.com>
Date: 15 May 2006 23:04:02 -0700
Links: << >>  << T >>  << A >>
well, take PA3 price, multiply by 2 and then add 120 USD for ARM
license (in small qty)
its the best estimate for today.

so qty 1 price over 200 USD

Antti


Article: 102421
Subject: Re: Make a signal free for glitches?
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Tue, 16 May 2006 08:19:25 +0200
Links: << >>  << T >>  << A >>
Thanks for this solution! :) I still miss an explanation why the muxcy 
solution may fail, counting out the possible glitches at the point of 
switching, wich I intend to take care of using synchronous resets.

"Peter Alfke" <peter@xilinx.com> wrote in message 
news:1147718359.906533.179030@y43g2000cwc.googlegroups.com...
> There is a guaranteed glitch-free clock multiplexer design in "six easy
> pieces", #6
> Find it under TechXclusives on the Xilinx website, or click on:
>
> http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1211408&iLanguageID=1&multPartNum=1
> &sTechX_ID=pa_six_easy&languageID=1
>
> Sorry for the ridiculously long URL.
> Peter Alfke, Xilinx



Article: 102422
Subject: Re: Make a signal free for glitches?
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Tue, 16 May 2006 08:24:51 +0200
Links: << >>  << T >>  << A >>
On second thought.... Are you sure this is safe? What if the three right 
gates are implemented in a lookup table (they probably will, won't they)? 
Having 2 different clocks into a lookuptable sounds very risky for the 
output.

"Peter Alfke" <peter@xilinx.com> wrote in message 
news:1147718359.906533.179030@y43g2000cwc.googlegroups.com...
> There is a guaranteed glitch-free clock multiplexer design in "six easy
> pieces", #6
> Find it under TechXclusives on the Xilinx website, or click on:
>
> http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1211408&iLanguageID=1&multPartNum=1
> &sTechX_ID=pa_six_easy&languageID=1
>
> Sorry for the ridiculously long URL.
> Peter Alfke, Xilinx
> ===============



Article: 102423
Subject: requirements to select FPGA using LVDS
From: "praveen.sethuram@gmail.com" <praveen.sethuram@gmail.com>
Date: 15 May 2006 23:53:54 -0700
Links: << >>  << T >>  << A >>
hi all,
wat all the basic requirements needed to be analysed before selecting a
FPGA chip for using high speed LVDS.
thanks in advance
praveen


Article: 102424
Subject: Re: Actel Fusion FPGAs
From: Thomas Reinemann <Thomas.Reinemann@masch-bau.uni-magdeburg.de>
Date: Tue, 16 May 2006 08:57:21 +0200
Links: << >>  << T >>  << A >>
rickman schrieb:
> I am not so familar with the Actel tiles.  Are they
> roughly comparable to a 4 LUT with a FF?  

No, a tile can be a 3 LUT _or_ a FF. I compared an Actel ProASIC and a
Spartan3 for my applications (controller in mechatronics) and estimated
a ratio of 6.5 tiles to one Slice.This is simple to comprehend then you
need two tiles to implement a 4 LUT and one for the FF, and this fits
roughly the ratio.
Furthermore you should know, Fuisons are ProASICs extend by some analog
circuitry.

Bye Tom.



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMar2019

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search