Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015Jan2015

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Authors (L)

L Horvath:
    18625: 99/11/04: How to connect a Xilinx Virtex FPGA to a TI DSP ?
L nguyen:
    56456: 03/06/05: ATA-6 controller
l nguyen:
    57986: 03/07/11: DCM CLKFX simulation
    58075: 03/07/14: Re: DCM CLKFX simulation
l'landre:
    22736: 00/05/21: Help for a novice of Xilinx Foundation
L-C:
    129056: 08/02/13: Is a FPGA the solution ?
L. Heijnen:
    33868: 01/08/07: 200MHz, 28 bit counter in Spartan ii
L. Kumpa:
    6961: 97/07/16: Re: Selection Criteria for CPLD's/FPGA's
    6985: 97/07/19: Re: free FPGA software from actel
L. Nguyen:
    53915: 03/03/27: SCSI LVDS and VirtexE
L. Schreiber:
    119189: 07/05/15: bus macros for partial reconfiguration of virtex2pro?
    119245: 07/05/15: ise project navigator can't dereference edk pcores from XilinxProcessorIPLib
    119546: 07/05/22: Re: How to include pcores librarys from XilinxProcessorIPLib (EDK)
    119547: 07/05/22: "black_box"-ing of components in toplevel
    119560: 07/05/22: Re: "black_box"-ing of components in toplevel
    119608: 07/05/23: Re: How to include pcores librarys from XilinxProcessorIPLib (EDK)
    120232: 07/06/04: any experiences concerning xup and digilent inc.?
    123759: 07/09/04: ERROR:NgdBuild:604 with user ipcore
    123761: 07/09/04: Re: ERROR:NgdBuild:604 with user ipcore
    123805: 07/09/05: Re: ERROR:NgdBuild:604 with user ipcore
    126569: 07/11/28: area group constraint problem
    126651: 07/11/29: Re: area group constraint problem (more detailed)
    126913: 07/12/06: Re: reconfigurable, modular design and clock signals - Question
    127040: 07/12/10: Re: reconfigurable, modular design and clock signals - Question
L.Brodbeck KS/EF2C 58/2/15 #7334:
    7982: 97/11/05: ANNOUNCEMENT: VHDL/FPGA Development Boards 200.000 Gates
    8148: 97/11/21: Re: Dr watson & M1
    8149: 97/11/21: Announcement: VHDL/FPGA Development Boards 200.000 Gates
L.C.:
    29156: 01/02/08: Altera, NON JTAG devices.
    29169: 01/02/08: Altera non JTAG devices. Prog specs?
L.L. Frederiks:
    2552: 96/01/02: Re: Gate-level description of 8051 to become available
L.O.S.:
    14927: 99/02/25: Where To FIND Info on Basic CPU Components
l.s.rockfan@web.de:
    126760: 07/12/01: Re: area group constraint problem (more detailed) - solved
    126909: 07/12/05: reconfigurable, modular design and clock signals - Question
laars kumar:
    38710: 02/01/22: Access to http://ripem.msu.edu
label:
    15269: 99/03/17: help!
    16071: 99/04/30: FPGA fitting
Labo.EKO:
    100693: 06/04/16: Petition about the xilinx online store ?
    100708: 06/04/16: Re: Where is the xilinx online store gone?
    100709: 06/04/16: Re: Where is the xilinx online store gone?
<LABORDEM@alpha.montclair.edu>:
    7518: 97/09/18: Computer Architecture
Lachlan J Follett:
    35528: 01/10/09: Re: Help reading from SmartMedia cards
    35529: 01/10/09: Re: Help reading from SmartMedia cards
LaesQ:
    77712: 05/01/15: Cheap source for GAL's
<lagerstrom@gmail.com>:
    118936: 07/05/07: Re: My Dear Spartan-3A, Please Please WAKE UP!
Lagudu Sateesh:
    64284: 03/12/24: Emulation on PRODESIGN Platinum Edition
    64476: 04/01/05: DCM Synthesis - Certify Planner Error
Laguna_b1:
    83375: 05/04/28: Xilinx FPU for Virtex-4 over FPU
lakshmi3489:
    145196: 10/02/01: Connecting ADC chip to sparta 3 a dsp
    145613: 10/02/15: Differential Signaling Buffer
    145616: 10/02/16: Re: Differential Signaling Buffer
    145822: 10/02/25: EDK spi ip core
    147296: 10/04/22: Custom IP with external ports
<lalitm@my-dejanews.com>:
    16503: 99/05/26: Reconfiguarble chips.
lalop:
    144343: 09/11/28: vga in virtex 4
lamiastella:
    150948: 11/02/24: Having two PLB Bus in XUPV2P
Lamont Cranston:
    152661: 11/09/24: Minimalist Spartan6-LX150 Board for $250
Lan Nguyen:
    58582: 03/07/27: Re: "ML300 Embedded" Mapping Help
    58854: 03/08/02: Re: "ML300 Embedded" Mapping Help
    59093: 03/08/07: Re: "ML300 Embedded" Mapping Help
Lana:
    51096: 02/12/31: shift register implementation
Lanarcam:
    95019: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95054: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95265: 06/01/21: Re: OT:Shooting Ourselves in the Foot
-Lance:
    78224: 05/01/26: Re: Xinx, FPGA Simulink Freeware/shareware ?
Lance Dannan Bresee:
    21941: 00/04/07: Re: Any free design of 8051 in the net?
    23074: 00/06/13: Re: Altera vs Xilinx
Lance Gin:
    2681: 96/01/23: In Search of Graphical VHDL Code Generators for FPGA Design
    2768: 96/02/05: Xilinx FPGA's with Mentor Tools?
    2830: 96/02/13: Re: Xilinx FPGA's with Mentor Tools?
    2835: 96/02/14: Re: Xilinx FPGA's with Mentor Tools?
    2869: 96/02/21: Re: Xilinx FPGA's with Mentor Tools?
    2879: 96/02/22: Re[2]: Xilinx FPGA's with Mentor Tools?
    2900: 96/02/27: Re: Xilinx FPGA's with Mentor Tools?
    3020: 96/03/14: Re: Xact6.o too slow
    3551: 96/06/19: Re: Xilinx CLB allocation question
    3564: 96/06/24: Re: Xilinx CLB allocation question
    3622: 96/07/03: Re: FSM encoding in VHDL with MAX+plusII
    3727: 96/07/22: Re: Xilinx library for autologic
    4103: 96/09/10: Re: Which FPGA design tools do you use ??
    4372: 96/10/21: Re: VHDL for Xilinx designs?
    4373: 96/10/21: Re: VHDL for Xilinx designs?
    4393: 96/10/23: Mentor B.2 and XACT 5.2.1 ?
    4496: 96/11/05: Re: What is the fastest fpga for ...
    4537: 96/11/10: Re: Xilinx and cost of tools
    4692: 96/11/30: In Search of Xilinx Routing Statistics
    5041: 97/01/15: Market Share Stats for Synthesis Vendors?
    5232: 97/01/31: Re: Synthesizing fast counter (carry look ahead adder)
    5277: 97/02/03: Re: Steven K. Knapp - no such article
    5335: 97/02/07: Re: Q is Xilinx Foundation BASE worth buying?
    5404: 97/02/13: Re: Gate level Simulation with Mentors Quicksim from Galileo
    5459: 97/02/17: Re: MG Autologic, Xilinx FPGAs and X-Blox
    5483: 97/02/19: Q: Search Engines for Electronic Parts?
    5565: 97/02/24: Re: Xilinx or Altera?
    5576: 97/02/25: Re: Q: Xilinx PPR Strategy Tips?
    5599: 97/02/27: SUMMARY - Electronic Component Search Engines
    5658: 97/03/04: Re: Instatiation of Xilinx Primitives in VHDL?
lance.work@gmail.com:
    73237: 04/09/16: Problem with I/O state while power on
lancepickens@gmail.com:
    111423: 06/11/02: Scientific Computing on FPGA
    111485: 06/11/03: Re: Scientific Computing on FPGA
Lancer:
    114787: 07/01/24: uClinux on Spartan 3
    114849: 07/01/25: Re: uClinux on Spartan 3
    115007: 07/01/29: Re: uClinux on Spartan 3
    115058: 07/01/30: Re: uClinux on Spartan 3
    116180: 07/03/03: Boot uClinux from RAM without flash
    119665: 07/05/24: Use BRAM as ROM (Xilinx)
lancos:
    109260: 06/09/22: Xilinx OPB BFM simulation error with m_ABus signal
LAnder7735:
    10725: 98/06/12: Re: Fastest and biggest FPGA fast and big enough?
landmarktrvl:
    3415: 96/05/28: EXOTIC DESTINATION
Landon Dyer:
    10379: 98/05/15: Re: Minimal ALU instruction set.
langjr15@uwgb.edu:
    112143: 06/11/16: xsa-200 building a Mp3 player
Langmann:
    51567: 03/01/16: Support for older Virtex
    51635: 03/01/17: Re: Support for older Virtex
    53174: 03/03/05: Re: EP310
langwadt@fonz.dk:
    134757: 08/08/28: crazy patent
    135350: 08/09/27: Re: 50 Ohm Analog Output of FPGA
    135862: 08/10/18: Re: configuring xc3s1500 from common parallel flash?
    141489: 09/06/25: Re: 720 Mhz IF Processing
    142426: 09/08/10: Re: delta-signa DAC with FPGA
    142689: 09/08/26: Re: Reading from ADC and writing to DAC at same time
    144119: 09/11/11: Re: 1.8V LVDS on spartan3A DSP
    144161: 09/11/15: Re: Interconnecting 3v3 LVDS transmitter to 2V5 Receiver
    148098: 10/06/21: Re: Newer Model Instrumentation Amp
    148186: 10/06/25: Re: fooling the compiler
    148882: 10/09/06: Re: We need an administrator for the group to fight spam
    150568: 11/01/26: Re: Xilinx news
    150569: 11/01/26: Re: Interfacing with a 5v micro controller
    151216: 11/03/15: Re: Regfile access
    151864: 11/05/25: Re: PCI Express Cable
    152467: 11/08/27: Re: cheating Arria FPGA i/o count
    152849: 11/10/27: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
    152865: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
    152890: 11/10/30: Re: Altera FPGA weirdness
    152893: 11/10/30: Re: Altera FPGA weirdness
    152907: 11/10/31: Re: Altera FPGA weirdness
    152928: 11/11/01: Re: Altera FPGA weirdness
    152930: 11/11/01: Re: Altera FPGA weirdness
    153033: 11/11/18: Re: Production Programming of Flash for FPGAs and MCUs
    153734: 12/05/02: Re: Smallest GPL UART
    153874: 12/06/18: Re: Virtex 4 Cameralink DCM Limitation
    153878: 12/06/19: Re: Virtex 4 Cameralink DCM Limitation
    153883: 12/06/20: Re: Virtex 4 Cameralink DCM Limitation
    153973: 12/07/05: Re: accumulator (again)
    154315: 12/09/26: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
    154328: 12/09/28: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
    154382: 12/10/18: Re: Serial LVDS ADC to spartan6
    154409: 12/10/27: Re: Altera delivery
    154435: 12/10/29: Re: Using LVDS Input for Delta Sigma ADC
    154470: 12/11/07: Re: pci express reference clock step down
    154697: 12/12/19: Re: FPGA DSP basics: clock enable / new clock
    154915: 13/02/13: platform cable usb II and efuses on spartan-6
<langwadt@fonz.dk>:
    134042: 08/07/22: Re: Help to SImulate Uart TX
    134083: 08/07/24: Re: Help to SImulate Uart TX
    134253: 08/08/01: Re: ISE new file wizard
    155604: 13/07/29: Re: serial protocol specs and verification
    155628: 13/07/30: Re: seperate high speed rules for HDL?
    155629: 13/07/30: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155644: 13/07/31: Re: seperate high speed rules for HDL?
    155645: 13/07/31: Re: serial protocol specs and verification
    155647: 13/07/31: Re: seperate high speed rules for HDL?
    155652: 13/07/31: Re: serial protocol specs and verification
    155663: 13/08/01: Re: seperate high speed rules for HDL?
    156298: 14/02/11: Re: How to synchronize register bank used in the IP Core
    156331: 14/03/10: Re: license server
    156338: 14/03/11: Re: license server
    156339: 14/03/11: Re: Ball-park price of Xilinx Virtex 7 FPGA?
    156342: 14/03/11: Re: Ball-park price of Xilinx Virtex 7 FPGA?
    156382: 14/03/22: Re: Xilinx ISERDESE2 deserializer primitive behaviour
    156463: 14/04/08: Re: on-chip bypass caps
    156600: 14/05/08: Re: The USB FPGA?
    156862: 14/07/11: Re: Using FPGA as dual ported ram
    156883: 14/07/15: Re: Using FPGA as dual ported ram
    156991: 14/08/13: Re: LVDS problem - Black magic anyone?
    157017: 14/08/28: wrong waveforms in vivado waveform viewer
    157066: 14/09/20: Re: NetCPU or DotNetCPU DB200 anyone?
    157071: 14/09/22: Re: NetCPU or DotNetCPU DB200 anyone?
    157073: 14/09/22: Re: NetCPU or DotNetCPU DB200 anyone?
    157177: 14/10/27: Re: XILINX PCIe read of slow device
    157181: 14/10/28: Re: XILINX PCIe read of slow device
    157598: 14/12/24: Re: How to automatically allocate multiple bit fields into constant
<langwadt@ieee.org>:
    88828: 05/08/29: Re: Array of slope A/Ds in FPGA?
    89063: 05/09/04: Re: High baud rate chips for RS232 protocol
    90649: 05/10/18: Re: clock timing
    90734: 05/10/19: Re: MAC Architectures
    90778: 05/10/20: Re: MAC Architectures
    91123: 05/10/30: Re: Sigma-Delta A/D
    91172: 05/10/31: Re: Sigma-Delta A/D
    91226: 05/11/01: Re: Sigma-Delta A/D
    91556: 05/11/08: Re: Why Spartan-3e is the best
    92069: 05/11/21: Re: Oh no! Resets Again? Yes, but it could be important.
    92263: 05/11/24: Re: FPGA ARM IP Core
    93368: 05/12/20: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
    94114: 06/01/05: Re: Do you name your FPGA?
    94846: 06/01/18: data2bram and coregen
    95482: 06/01/23: Re: Quadrature Encoder ::
    96452: 06/02/03: Re: FPGA growth vs. ASIC growth
    97554: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
    97725: 06/02/26: Re: fpga to 5v ttl logic
    98634: 06/03/13: Re: Why does Xilinx hate version control?
    98648: 06/03/14: Re: How do I handle this memory related issue?
    99236: 06/03/21: Re: How to get eps file from XST RTL viewer for LATEX
    99262: 06/03/22: Re: How to get eps file from XST RTL viewer for LATEX
    99296: 06/03/22: Re: Going from CLK1X to CLK2X.. really safe?
    101178: 06/04/26: Re: The use of analog switches as level translators
    103605: 06/06/06: Re: FPGA board for USB experiments?
    103607: 06/06/06: ise8.1 picking local instead of global clk routing?
    103662: 06/06/07: Re: FPGA board for USB experiments?
    103825: 06/06/12: Re: How do I use the DDS core in a verilog flow?
    103869: 06/06/13: Re: How do I use the DDS core in a verilog flow?
    103872: 06/06/13: Re: How do I use the DDS core in a verilog flow?
    111676: 06/11/07: Re: Need just a few 5V Spartan
    112615: 06/11/26: Re: vccaux and vccint
    113935: 06/12/29: Re: SPI slave problem
    116336: 07/03/07: Re: Query regarding Project.Plz help very urgent
    118106: 07/04/17: Re: 80000 Bit Shift Register
    129273: 08/02/19: Re: FPGA Programming solution
    129276: 08/02/19: Re: FPGA Programming solution
    129320: 08/02/20: Re: FPGA Programming solution
laoshan.zb@gmail.com:
    89572: 05/09/19: xilinx ML310 board PCI DMA problem
Lapides:
    8935: 98/02/07: Re: Asic to FPGA
Lara Simsic:
    47664: 02/10/01: Re: Nios interrupt latency?
    54682: 03/04/15: Re: nios-build under Solaris?
    54905: 03/04/21: Re: nios-build under Solaris?
Lardino@ibm.net:
    10476: 98/05/20: Re: FPGA-based CPUs (was Re: Minimal ALU instruction set)
<larell@airmail.net>:
    21709: 00/03/29: Re: clock
Larice Robert:
    6424: 97/05/23: Re: Q: Leonardo, any pros/cons using this ?
    9688: 98/03/31: XC4000XL/XLT clamp diodes
Larrie Carr:
    157: 94/09/02: Re: PLDshell/Intel ftp site
    285: 94/10/12: Re: Any documentation for Xilinx XNF file format?
    344: 94/10/25: Re: High Bus Drive (24mA) FPGAs/CPLDs?
Larry:
    96291: 06/02/01: Re: Maximum system frequency on FPGA/CPLD
    101278: 06/04/28: Re: Xilinix SPI programming with USB Platform Cable
    141516: 09/06/26: SPARTAN-3AN open-drain at vccio1.8V
larry:
    52895: 03/02/25: Re: Delay element in Virtex2
Larry Cameron:
    2545: 95/12/30: Re: Gate-level description of 8051 to become available
Larry Chen:
    4385: 96/10/23: Motorola 68HC16 background debugger
    4793: 96/12/16: Motorola 68HC16 background debugger
    4792: 96/12/16: Motorola 68HC16 background debugger
    4886: 96/12/25: Motorola 68HC16 background debugger
    4890: 96/12/25: HC16 background debugger
    4891: 96/12/25: Motorola 68HC16 background debugger
    4892: 96/12/25: Motorola 68HC16 background debugger
    4957: 97/01/04: 68HC16 background debugger
    4958: 97/01/04: 68HC16 background debugger
    4976: 97/01/08: Motorola 68HC16 background debugger
    5008: 97/01/12: Motorola 68HC16 background debugger
    5638: 97/03/04: Motorola 68HC16 background debugger
Larry Doolittle:
    21: 94/07/29: FPGA software
    376: 94/11/01: Re: about ALTERA
    9525: 98/03/21: Re: Strange Xilinx question?
    14951: 99/02/26: Virtex multiplication
    18504: 99/10/28: Re: Announcing Free VHDL Simulator for Windows
    20057: 00/01/25: Re: Xilinx programming from a Linux PC
    20154: 00/01/28: Spartan II availability and pricing
    20255: 00/02/02: Re: Spartan II availability and pricing
    20392: 00/02/08: Re: Spartan II availability and pricing
    20398: 00/02/08: Re: Spartan II availability and pricing
    20399: 00/02/09: Re: Spartan II availability and pricing
    21272: 00/03/14: Re: Atmel censors web access
    21379: 00/03/21: Re: JTAG by parallel port
    21454: 00/03/22: Re: FPGA openness
    21601: 00/03/26: Re: No- FPGA openness
    21619: 00/03/26: Re: FPGA openness
    22684: 00/05/17: Spartan II availability and pricing
    22771: 00/05/23: Re: Xilinx Logic Cell counts and carry chains
    22826: 00/05/25: Re: 8087 in FPGA?
    22968: 00/06/06: Re: Spartan II availability and pricing
    33099: 01/07/17: Drive strength of Xilinx DONE pin
    46797: 02/09/09: Re: Can FPGA implements ADC?
    46877: 02/09/10: Re: XCR3384XL availability
    46881: 02/09/10: Re: XCR3384XL availability
    46882: 02/09/10: Re: XCR3384XL availability
    46890: 02/09/10: Re: XCR3384XL availability
    46978: 02/09/13: Re: exploiting metastability
    46995: 02/09/13: Re: exploiting metastability
    47068: 02/09/16: Re: Question about Virtex-II DCM's jitter
    47069: 02/09/16: Re: Virtex II packaging, why no QFP?
    47085: 02/09/17: Re: Question about Virtex-II DCM's jitter
    47132: 02/09/18: Re: linear-log converter required
    48084: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48122: 02/10/11: Re: Intel ARM 'XScale' cores as IP blocks that can be synthesized into an FPGA/ASIC?
    48343: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48506: 02/10/18: Re: Size of configuration bitstream for xcv50 (xilinx)
    49548: 02/11/14: Re: Programming a Spartan2 via JTAG
    49569: 02/11/15: Re: Microblaze
    49614: 02/11/18: Re: Virtex is the 4th Xilinx Fpga generation
    49646: 02/11/18: Re: Virtex is the 4th Xilinx Fpga generation
    49753: 02/11/20: Re: Webpack and Virtex Pro?
    49992: 02/11/27: Re: question about PCB traces for FPGA board... ?
    50154: 02/12/03: Re: free software for XC4000
    50428: 02/12/10: Re: Clocking in a Spartan IIE
    51393: 03/01/12: Re: Open FPGA please!
    51865: 03/01/24: Re: VHDL or Verilog?
    51891: 03/01/24: Re: VHDL or Verilog?
    52067: 03/01/30: Re: GNU C for custom processor
    53235: 03/03/07: Re: JTAG
    53517: 03/03/14: Xilinx WebPACK on WINE -- getting close
    53524: 03/03/15: Re: Xilinx WebPACK on WINE -- getting close
    54217: 03/04/05: Re: Xilinx announces 90nm sampling today!
    54222: 03/04/05: Re: Xilinx announces 90nm sampling today!
    54226: 03/04/05: Re: Xilinx announces 90nm sampling today!
    54303: 03/04/07: Re: Spartan-3 in docsan Webpack release notes... a joke???
    54337: 03/04/08: Re: price of fpga chips
    54442: 03/04/10: Re: Balanced Presentation
    55182: 03/04/29: Re: Low pin count SOC
    55424: 03/05/07: Re: PLL chips
    56554: 03/06/09: Xilinx Parallel Cable IV and non-captive software
    56852: 03/06/17: Re: Downloading bit-stream with a microprocessor.
    58267: 03/07/18: Re: processing `ifdef in Xilinx ISE 5.2i
    59322: 03/08/14: Re: Old Xilinx FPGAs
    60616: 03/09/17: Re: Xilinx
    62887: 03/11/10: Re: 0.13u device with 5V I/O
    63314: 03/11/19: Re: Anyone use HDL as design tool for PCBs?
    63353: 03/11/20: Re: 400 Mb/s ADC
    63589: 03/11/26: Re: Soft-core processor construction
    63720: 03/12/02: Re: Exact Timing Constraints vs. Over-Constraining
    63738: 03/12/02: Re: Exact Timing Constraints vs. Over-Constraining
    63747: 03/12/03: Re: Exact Timing Constraints vs. Over-Constraining
    64029: 03/12/12: MAX104 vs. XC2VP
    64341: 03/12/29: Re: Parallel Cable 4 & Linux
    64512: 04/01/06: Re: Questions about guard bits in CORDIC algorithm
    64726: 04/01/12: Re: fpga database?
    65753: 04/02/05: Re: Do Xilinx Fix Their Prices?
    67425: 04/03/11: Re: licence for Xilinx 2.1i
    67815: 04/03/19: Re: Why It Is not Recommended to Infer latches in VLSI Design...
    68129: 04/03/27: Re: study verilog or vhdl?
    68172: 04/03/29: Re: study verilog or vhdl?
    68417: 04/04/03: Re: The Logic Behind License Renewal
    68454: 04/04/05: Re: Logic required for multiplication
    70624: 04/06/22: Re: Linux.
    88886: 05/08/30: Re: Array of slope A/Ds in FPGA?
    92394: 05/11/29: Re: Cypress FX2 bandwidth problem
    94709: 06/01/16: Re: best evm for virtex-4 and linux
    95708: 06/01/25: Re: open source fpga programmer programs
    95856: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source interface?
    95987: 06/01/27: Re: So Xilinx, is XDL and related libraries an available open source interface?
    96040: 06/01/28: Re: So Xilinx, is XDL and related libraries an available open source interface?
    96137: 06/01/30: Re: Xilinx Legal
Larry Edington:
    19508: 99/12/28: VGA controller in FPGA
    19563: 99/12/31: Design security
    19570: 00/01/01: Re: Design security
    19577: 00/01/01: Re: Design security
    19579: 00/01/01: Re: Design security
    19584: 00/01/02: Re: Design security
    23221: 00/06/17: Re: Hand soldering a PQ208 - It looks tough to do.
Larry Eisner:
    20218: 00/02/01: PCI core in public domain
Larry Elmore:
    19796: 00/01/12: Re: HW resources increased
Larry Getzin:
    3772: 96/07/29: 35K gates into 1 device...doable?
Larry Kilgallen:
    5312: 97/02/06: Re: DES Challenge
    5358: 97/02/10: Re: DES Challenge
Larry Li:
    13549: 98/12/09: *** FPGA/DSP Engineer Wanted ***
    15175: 99/03/11: *** HOU-TX Electrical Engineer FPGA ***
Larry M. Weissman, X3722:
    3: 94/07/27: Re: This (new) froup
Larry Martin:
    2660: 96/01/21: Re: PLD JDEC Files
Larry McKeogh:
    18107: 99/09/30: Re: Problems with Xilinx Webpack 2.1
    40759: 02/03/14: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
    48521: 02/10/18: Re: Webpack4.2
    49228: 02/11/05: Re: WebPACK 5.1 SP2
    66970: 04/03/02: Re: embedded powerpc in VirtexII-pro
Larry Phillips:
    18059: 99/09/27: Re: Looking for substitute for XC17*** Xilinx Prom
Larry Ryan:
    2453: 95/12/07: VHDL Editor for Windows PC, Suggestions?
Larry Watts:
    5150: 97/01/27: Job: HW Project Leaders/Managers - FPGA/ASIC/PCI/VME
<larry@metraplex.com>:
    5229: 97/01/31: Actel Designer 3.1 Problem
Lars:
    8315: 97/12/08: Re: PCI cores and PCI bus HDL models
    8316: 97/12/08: SDRAM & SSTL
    8376: 97/12/11: Re: gates
    8533: 98/01/06: SDRAM model
    8903: 98/02/06: Asic to FPGA
    10721: 98/06/12: Fastest and biggest FPGA fast and big enough?
    23030: 00/06/09: Virtex-EM and F2.1
    23290: 00/06/21: Re: Wanted: Xilinx VirtexE
    23291: 00/06/21: Distributed RAM and VHDL
    23466: 00/06/26: Dual Port BlockRAM Timing (Write-Read)
    23613: 00/07/02: Re: MPEG audio questions...
    26307: 00/10/11: LUT to CLB assignment
    26369: 00/10/13: const coeff multiplier w/ LUTs
    79381: 05/02/18: Re: FPGA Hardware/Cell Diagnostics
    92277: 05/11/25: Configuration PROM XC18V02 bit error
    92280: 05/11/25: Re: Configuration PROM XC18V02 bit error
    93733: 05/12/29: System Monitor in Virtex-4
    93736: 05/12/29: Re: System Monitor in Virtex-4
    93745: 05/12/29: Re: System Monitor in Virtex-4: alive? or dead? or just forgotten?
    93975: 06/01/04: Remapping from Virtex-II to Virtex-4
    93982: 06/01/04: Re: Remapping from Virtex-II to Virtex-4
    94060: 06/01/05: Re: Remapping from Virtex-II to Virtex-4
    100846: 06/04/19: Re: MaxPlus2 and the Byteblaster MV
    114130: 07/01/05: Re: measure setup and hold time
    114131: 07/01/05: Spartan3E minimum clock-to-output (hold time)
    114132: 07/01/05: Re: Spartan3E minimum clock-to-output (hold time)
    114137: 07/01/05: Re: ISE 8.2sp3 clobbering source file timestamps?
    114143: 07/01/05: Re: Spartan3E minimum clock-to-output (hold time)
    114256: 07/01/09: Re: measure setup and hold time
    128768: 08/02/06: 1-Wire and Dallas DS1WM in Spartan
    131113: 08/04/11: Xilinx tech Xclusive
    131118: 08/04/11: Re: Xilinx tech Xclusive
    131120: 08/04/11: Re: Xilinx tech Xclusive
    131165: 08/04/13: Re: Xilinx tech Xclusive
    131396: 08/04/21: Re: synchronous reset problems on FPGA
    134561: 08/08/18: Spartan-3AN JTAG problem
    134611: 08/08/21: Re: Spartan-3AN JTAG problem
    138944: 09/03/16: Re: Send data from FPGA to PC via USB
    140026: 09/04/24: Re: FPGA board with ARM9
    148216: 10/06/30: Re: MicroBlaze - how to instantiate/connect more BRAM to the LMB
    152527: 11/09/05: POST_CRC in Spartan-6
    152537: 11/09/08: Re: POST_CRC in Spartan-6
    153295: 12/01/27: Re: XLNX efuse anyone?
Lars Erik Svendsen:
    31887: 01/06/07: Re: PCI to compactPCI adapter
Lars Fomsgaard:
    14584: 99/02/05: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
    14548: 99/02/04: VHDL problem (Xilinx-problem)
    14583: 99/02/05: Re: VHDL problem (Xilinx-problem)
    16096: 99/05/03: Xilinx netlister - Workaround needed
Lars FREUND:
    17027: 99/06/26: Altera: Simulation results differ...
Lars Freund:
    13567: 98/12/10: Documention AHDL?
    14576: 99/02/05: can I trust Altera Simulator?
    14593: 99/02/05: Re: can I trust Altera Simulator?
Lars Helgeson:
    76032: 04/11/22: Help! What is this card?
Lars Henrik Mathiesen:
    28291: 01/01/05: Re: Nondeterministic FSMs in hardware?
Lars Lotzenburger:
    23136: 00/06/15: CoreGenerator and VHDL
    24258: 00/08/01: Virtex-EM development board
Lars Rzymianowicz:
    16143: 99/05/06: Re: One Sheep Farmer's Impressions of SNUG'99
    23288: 00/06/21: Anyone tried the Virtex dev. board from Avnet?
    23890: 00/07/14: Re: Anyone tried the Virtex dev. board from Avnet?
    23798: 00/07/10: Re: Xilinx Design Flow
    24963: 00/08/23: Re: Mealy vs Moore FSM model
    24965: 00/08/23: Re: Mealy vs Moore FSM model
    24918: 00/08/22: Re: Mealy vs Moore FSM model
    25607: 00/09/15: Re: PCI-Tip? (for Xilinx Virtex/-E)
    25925: 00/09/26: Synopsys FPGA Compiler II on Solaris
    26169: 00/10/06: Re: Synopsys FPGA Compiler II on Solaris
    26335: 00/10/12: Re: Category : Subject:Floorplanning
    26559: 00/10/20: Re: Synopsys FPGA Compiler II on Solaris
    28646: 01/01/19: problem with Xilinx CORE Generator
    28710: 01/01/22: Inferring Virtex selectRAM with FC2?
    31673: 01/06/02: Re: pci pads
    34188: 01/08/16: Re: Development boards
    40370: 02/03/06: Re: exceeding 2GB limits in xilinx
Lars Theodorsson:
    72739: 04/08/31: Re: Xilinx DCM Spread Spectrum feature
    75693: 04/11/12: Re: constraints coverage
Lars Unger:
    51980: 03/01/28: 1024bit Adder
    52029: 03/01/29: Re: 1024bit Adder
    52030: 03/01/29: Re: 1024bit Adder
    52031: 03/01/29: Re: 1024bit Adder
    52361: 03/02/07: Carry Save Adder
    52408: 03/02/08: Re: Carry Save Adder
    52549: 03/02/13: Re: Causing Modelsim to break using VHDL code
    52622: 03/02/17: Re: pos-map and post-PAR mismatch
    52680: 03/02/19: XCV800 Configuration PROM
    52728: 03/02/20: Re: XCV800 Configuration PROM
    52872: 03/02/25: Re: Xilinx FPGA on PCI board
    53653: 03/03/19: Re: unsupported switches of PAR
    66333: 04/02/17: Re: GSR in Spartan3 ?
Lars Wanhammar:
    46555: 02/09/03: Re: Bit serial arithmetic Vs Digit serial Arithmetic
Lars0909:
<larstore@gmail.com>:
    126878: 07/12/05: Need help with Altera .pof format!
larwe:
    91749: 05/11/11: Re: Factory Mutual Approvable Sealed Lead Acid Battery
    94972: 06/01/19: Re: OT:Shooting Ourselves in the Foot
    95005: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95239: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    106826: 06/08/20: Re: Hardware book like "Code Complete"?
    109196: 06/09/21: Re: Dell Laptop for Embedded Work
    109197: 06/09/21: Re: Dell Laptop for Embedded Work
    109284: 06/09/22: Re: OT: Google display of this thread
    116103: 07/03/01: Re: suggestions for good MPEG encoder dev kit, embedded hard disk dev kit
    116110: 07/03/01: Re: suggestions for good MPEG encoder dev kit, embedded hard disk dev kit
    116124: 07/03/01: Re: suggestions for good MPEG encoder dev kit, embedded hard disk dev kit
    117699: 07/04/07: Re: A new way to define systems of systems?
    117702: 07/04/07: Re: A new way to define systems of systems?
    120945: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
<larwe@larwe.com>:
    81995: 05/04/05: Re: ISA vs. patent/trademark
    82002: 05/04/05: Re: ISA vs. patent/trademark
    83323: 05/04/27: Re: x on ml300?
    83340: 05/04/27: Re: x on ml300?
laser:
    109581: 06/09/29: Little help needed with FT2232L USB demo board
laserbeak43:
    134274: 08/08/04: Schematic Capture tutorials/books?
    134286: 08/08/04: Re: Schematic Capture tutorials/books?
    134310: 08/08/06: Re: Schematic Capture tutorials/books?
    134311: 08/08/06: Re: Schematic Capture tutorials/books?
    134312: 08/08/06: Re: Schematic Capture tutorials/books?
    134345: 08/08/06: Re: Schematic Capture tutorials/books?
    134346: 08/08/06: ISE 8.1i sp3: map is not recognized as an internal or external
    134376: 08/08/07: Re: ISE 8.1i sp3: map is not recognized as an internal or external
    134382: 08/08/08: Re: Schematic Capture tutorials/books?
    134383: 08/08/08: Re: ISE 8.1i sp3: map is not recognized as an internal or external
    134393: 08/08/08: Re: Development board with SD card.
    134394: 08/08/08: Re: Development board with SD card.
    134406: 08/08/09: Re: ISE 8.1i sp3: map is not recognized as an internal or external
    134521: 08/08/16: Verilog modules and stimulus in same file
    134522: 08/08/16: Verilog modules and stimulus in same file: oh and one more thing...
    134536: 08/08/16: Re: Verilog modules and stimulus in same file: oh and one more
    134537: 08/08/16: Re: Verilog modules and stimulus in same file
    134538: 08/08/16: Re: Verilog modules and stimulus in same file
    134657: 08/08/25: [solved] Re: ISE 8.1i sp3: map is not recognized as an internal or
    134957: 08/09/08: Vista 64: USB drivers still don't install
    135999: 08/10/26: S3E starter kit: LCD interface questions
    136430: 08/11/16: Digilent Spartan3e starter kit, Not working.
    136432: 08/11/16: Re: Digilent Spartan3e starter kit, Not working.
    136527: 08/11/20: Re: [SOLVED]Digilent Spartan3e starter kit, Not working.
    136921: 08/12/13: Re: Online C-to-FPGA tool
    144506: 09/12/11: Re: Xilinx's version of Quartus' Signaltap?
    144536: 09/12/13: Re: Xilinx's version of Quartus' Signaltap?
Laserbeak43:
    133803: 08/07/15: Re: prob regarding Bitgen failed while gen prog file xilinx ise 7.1i
    133820: 08/07/16: Re: prob regarding Bitgen failed while gen prog file xilinx ise 7.1i
    136009: 08/10/27: Re: S3E starter kit: LCD interface questions
    142391: 09/08/08: Spartan3e Starter kit and Ethernet tutorials
Laslo Chaki:
    12411: 98/10/11: ASIC-FPGA-TELCOM job in N.California
lass:
    48085: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48524: 02/10/18: Re: Floorplanner RPM. How to use it?
    49460: 02/11/12: Re: EDIF generation from XST of ISE 5.1i
    49766: 02/11/20: Re: Webpack and Virtex Pro?
Lasse:
    113508: 06/12/14: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
Lasse Eriksson:
    120852: 07/06/18: Re: No serial output while booting a Xilinx ML403 board
Lasse Langwadt Christensen:
    12513: 98/10/14: Re: VHDL Editor
    13252: 98/11/21: Re: CPUs: Big Endianness vs Small Endianness
    13278: 98/11/23: Re: Big-Endian vs Little-Endian
    13298: 98/11/24: Re: Integer divide algorithms
    13756: 98/12/22: Re: exporting synario schematics?
    14139: 99/01/15: Re: HEX file format
    14295: 99/01/23: Re: Array Usage in VHDL Question
    14461: 99/01/30: Re: Off topic DRAM/SIMM question....
    14462: 99/01/30: Re: Off topic DRAM/SIMM question....
    14515: 99/02/02: Re: Off topic DRAM/SIMM question....
    14543: 99/02/04: Re: Off topic DRAM/SIMM question....
    14550: 99/02/04: Re: VHDL problem (Xilinx-problem)
    14570: 99/02/04: Re: VHDL problem (Xilinx-problem)
    14635: 99/02/07: Re: Xilinx de-compiler
    14824: 99/02/18: Re: four signals into array?
    15041: 99/03/04: Re: Clock divider: 100MHz->40MHz
    15046: 99/03/04: Re: Selt-Timed circuit
    15244: 99/03/16: Re: How can I improve an adder?
    15321: 99/03/18: Re: How can I improve an adder?
    15542: 99/03/30: Re: Info about FPGA/PLD
    16717: 99/06/04: Re: Xinx M1.5 under WinNT how to `nice' par
    16754: 99/06/07: Re: Xinx M1.5 under WinNT how to `nice' par
    16797: 99/06/09: Re: LINE DELAYS USING RAMS
    17108: 99/06/30: Re: uLaw and ALaw conversion in an FPGA
    17120: 99/07/01: Re: uLaw and ALaw conversion in an FPGA
    17212: 99/07/09: Re: how to get money surfing the net...
    17490: 99/07/31: Re: Semi-deterministic behaviour in FPGA's
    20822: 00/02/23: Re: Bit Serial Arithmetic De-mystified
    22627: 00/05/15: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
    22660: 00/05/17: Re: Where can I find resource for USB?
    22661: 00/05/17: Re: HELP - what to choose?
    22726: 00/05/19: Re: SpartanXL driving 5V CMOS input
    23046: 00/06/10: Re: Microprocessors in FPGA
    25089: 00/08/25: Re: fpga programmed by microcontroller
    25436: 00/09/11: Re: xilinx web site access
    25552: 00/09/14: Re: Is this practical?
    25863: 00/09/23: Re: Bluetooth core??
    28760: 01/01/23: Re: Virtex-II officially launched
    30470: 01/04/09: Re: Handel-C
    31144: 01/05/13: Re: Implementation Of LUT in Vertex-E
    31562: 01/05/30: Re: Xilinx Installation and Java Errors on Pentium 4
    31791: 01/06/05: Re: one state machine
    31952: 01/06/09: Re: Flash programming via FPGA's JTAG ????
    31988: 01/06/10: Re: Flash programming via FPGA's JTAG ????
    31989: 01/06/10: Re: Flash programming via FPGA's JTAG ????
    31990: 01/06/10: Re: Async FIFO in maxplus2
    32195: 01/06/18: Re: Flexlm license and windows 2000
    32291: 01/06/22: Re: Verilog or VHDL?
    32559: 01/06/29: Re: Is the Grass Greener for an Engineer in the USA?
    33196: 01/07/19: Re: Working Design - Anyone
    33197: 01/07/18: Re: Xilinx WebPACK - ROM
    33810: 01/08/06: Re: May I connect two pins to the same net?
    34538: 01/08/29: Re: download bitstream to FPGA
    34800: 01/09/08: Re: Special counter for scheduling
    34801: 01/09/08: Re: Missing bits
    35250: 01/09/27: Re: Gated clocks and shortage of clock buffers
    35251: 01/09/27: Re: Gated clocks and shortage of clock buffers
    36719: 01/11/17: Re: Xilinx and Multirate clock ??
    36729: 01/11/17: Re: Q: XILINX binary .bit file header - ?
    36884: 01/11/23: Re: Xilinx and Multirate clock ??
    39105: 02/01/31: skew between gated clks in Virtex2?
    39293: 02/02/05: Re: skew between gated clks in Virtex2?
    39753: 02/02/18: Re: Pseudorandom Bitstream
    41654: 02/04/04: Re: powerpc in virtex2pro
    42049: 02/04/13: virtex2 bufgce or not bufgce
    42067: 02/04/15: Re: virtex2 bufgce or not bufgce
    42469: 02/04/24: configuration mystery
    42508: 02/04/25: Re: configuration mystery, solved
    44133: 02/06/12: constrains for external memory
    45296: 02/07/18: trick to using bufgce?
    45421: 02/07/23: Re: Clock-gating in Virtex-E parts
    45484: 02/07/24: Re: Clock-gating in Virtex-E parts
    45651: 02/07/30: anyone with a few xc2v3000-fg676-5 ??
    45705: 02/08/02: Re: Xilinx ISE 4.2: UCF file name
    45707: 02/08/02: Re: Safe design speed
    49552: 02/11/15: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
    52466: 03/02/10: Re: Xilinx ISE 4.2i killing Windows 2000?
    52704: 03/02/19: Re: Quick FPGA PCI I/O in Spartan-IIE for single peripheral
    57045: 03/06/22: Re: Reducing synthesize time for state machines
    57604: 03/07/03: Re: ARM C/C++ compiler independent of OS
    57605: 03/07/03: Re: Looking for DIMM format FPGA board
    57808: 03/07/07: Re: Difficulty with OPB bus and user IP
    58361: 03/07/22: Re: Use ICAp iwth a soft IP core to decompress!!!!
    60567: 03/09/16: Re: USB transceiver for FPGA
    60583: 03/09/17: Re: USB transceiver for FPGA
    63094: 03/11/14: Re: Color STN LCD controller
    64205: 03/12/20: Re: CRC-32 in spatan-3
    65637: 04/02/04: Re: JTAG pin states
    66054: 04/02/12: Re: Xilinx Platform Flash Prom
    66107: 04/02/12: Re: getting back Xilinx ISE commands
    66394: 04/02/18: Re: Can FPGA bootstrap itself?
    67612: 04/03/16: Re: copy protection on FPGA using embedded serial number
    67953: 04/03/23: Re: XCV2000E survived 3.3V core voltage!
    70914: 04/07/01: Re: *RANT* Ridiculous EDA software "user license agreements"?
    71853: 04/08/02: Re: 1GHz FPGA counters
    71864: 04/08/03: Re: 1GHz FPGA counters
    75629: 04/11/11: Re: Xilinx Tshirts in football package.....
    75717: 04/11/12: Re: digital analog conversion
    75998: 04/11/22: Re: Xilinx S3 IO during programming latches Cypress FX2 Reset
    76038: 04/11/23: Re: Help! What is this card?
    76071: 04/11/23: Re: Beginers Question ModelSim Signals
    76177: 04/11/27: Re: dual-write port BRAM with XST/Webpack
    82560: 05/04/14: Re: Reverse engineering masked ROMs, PLAs
    84480: 05/05/19: Re: Xilinx : Clock Swallowing
Lasse Natvig:
    7223: 97/08/15: Post.doc position in HW/SW Codesign
lastminutepanic:
    148619: 10/08/07: VHDL newbie- stuck just weeks before project submission :(..please
Laszlo Joo:
    1358: 95/06/06: FPGA conversion options
LATAWIEC Regis:
    3753: 96/07/25: VME Hardware Interface using CPLD
Lathe_Biosas:
    89019: 05/09/02: gal16v8 CUPL problems
<Lathi.Tan@gmail.com>:
    109373: 06/09/25: state machine dead problem
    109378: 06/09/25: Re: state machine dead problem
    109384: 06/09/25: Re: state machine dead problem
Lau, James:
    42846: 02/05/04: FPGA SOPC solution with MobileUne
laura:
    131491: 08/04/22: the order in which some switches are turned on
Laura Faus:
    52604: 03/02/15: Virtex-E 600--2'sC/Straight Binary?
<laura_pretty05@yahoo.com.hk>:
    98240: 06/03/07: Re: Questions about counter in VHDL
    98241: 06/03/07: Re: Questions about counter in VHDL
    98242: 06/03/07: Re: Questions about counter in VHDL
    98286: 06/03/08: Re: Questions about counter in VHDL
    98306: 06/03/08: Re: Questions about counter in VHDL
    98312: 06/03/08: VHDL
    98342: 06/03/08: Re: VHDL
    98652: 06/03/14: About Altera FPGA Board
    98680: 06/03/14: Re: About Altera FPGA Board
    98773: 06/03/16: Re: About Altera FPGA Board
    98851: 06/03/17: Re: About Altera FPGA Board
    98982: 06/03/18: Re: About Altera FPGA Board
Laurence McCotter:
    30302: 01/04/02: pinout in text format for Virtex-E XCV200E
Laurens Drost:
    16337: 99/05/17: Re: Synopsys DC & Modelsim
laurent:
    23096: 00/06/14: for my students
    23097: 00/06/14: for my students + my E-mail
Laurent Gauch:
    8060: 97/11/13: XC: bitfile to ASCII file
    8821: 98/01/29: Progamm spec. eeprom Atmel
    8822: 98/01/29: Progamm spec. eeprom Atmel
    9220: 98/03/03: Spartan config. Mode
    12216: 98/10/05: Spartan: strange problem
    12217: 98/10/05: Re: Spartan: strange problem
    21841: 00/04/03: FPGA controlling S-7600A TCP/IP ...
    22039: 00/04/14: Re: Demo - board
    22054: 00/04/16: Re: FPGA/PLD design tools?
    22471: 00/05/09: Re: Xilinx fpga board schematics?
    22538: 00/05/11: Re: FPGA emulators?
    22539: 00/05/11: Re: Shifting with STD_LOGIC_VECTOR???
    22781: 00/05/24: Re: ISA interface on FPGA or CPLD
    22266: 00/05/03: Re: Bidirectional bus
    23373: 00/06/23: Re: What tools do people use for Xilinx FPGAs?
    24204: 00/07/29: Spartan-II / Virtex-E / DC linear regulators
    24515: 00/08/11: Re: Interview Questions
    24533: 00/08/12: Re: Xilinx, XVC300, 18V02
    24534: 00/08/12: XC2S200 / Master Serial / PCI system
    24555: 00/08/13: WS PIN - MULTILINX
    24756: 00/08/17: Re: Xilinx design flow with Mentor
    26432: 00/10/16: Re: Low power cpld?
    28969: 01/01/31: vector / edif format / LeonardoSpectrum
    29270: 01/02/12: Re: Virtex XCV2000E-6 BG560C - Orcad capture symbol
    29351: 01/02/15: Re: Bubble tristate
    29414: 01/02/20: Re: UCF problem "- Could not find NET "
    29459: 01/02/22: Re: How to get Xilinx FPGA demo board?
    29499: 01/02/23: Re: Searching for FPGA designer (PCI interface,DES, IDE)
    29838: 01/03/13: Any advice about Visual IP
    32055: 01/06/12: USB for a new FPGA based product, which transciever ?
    32089: 01/06/13: Re: From EDF to VHDL?
    32252: 01/06/21: Searching any 144 pin SO-DIMM module
    33317: 01/07/23: 3.3i service pack 8
    35183: 01/09/25: Re: FPGA with embedded Memory
    42530: 02/04/26: webpack : how to generate a .sdf and .vhd for simulation
    42653: 02/04/30: EDIF parser (perl)
    42951: 02/05/08: Re: JTAG 5V tollerance...?
    43166: 02/05/15: Re: Processor interface to memory mapped FPGA
    43241: 02/05/17: Re: Spartan2 on a Compact Flash card
    43487: 02/05/22: Re: Xilinx Serial IO Data rates
    43488: 02/05/22: Re: i need help getting started with fpgas
    43569: 02/05/24: Re: SDRAM controler for Virtex-II
    43571: 02/05/24: Re: SOPC for machine vision
    43578: 02/05/24: Re: SDRAM controler for Virtex-II
    43581: 02/05/24: Re: JTAG ICE or programmer
    43631: 02/05/28: Re: XC95288 Programming
    43837: 02/06/04: Re: Looking for FPGA board with USB interface
    43923: 02/06/06: PowerPC Architecture
    43926: 02/06/06: Re: PowerPC Architecture
    44015: 02/06/10: synplicity/synopsys users: synthesis for A7 TRISCEND
    44492: 02/06/21: Re: xilinx, jtag vs. serial parallel mode
    44781: 02/07/01: Re: How can I preserve FFs in LeonardoSpectrum?
    44908: 02/07/05: Triscend: SDK CD-ROM : where ?
    44909: 02/07/05: Re: How to improve this VHDL code ?
    44954: 02/07/08: Camera Link to Virtex-II ?
    45025: 02/07/10: Re: Bi-Directional Bus problem in Xilinx FPGA
    45031: 02/07/10: Re: Bi-Directional Bus problem in Xilinx FPGA
    45100: 02/07/12: Re: LogiCore and PLX
    45208: 02/07/16: uCLinux on microblaze
    45241: 02/07/17: Re: I would like to know how to develop a MCU.
    45396: 02/07/22: Re: Delays in Leonardo
    45638: 02/07/30: VIRTEX-II pro -> LVTTL 3.3
    46102: 02/08/19: Re: rising_edge detector?
    46157: 02/08/20: Re: PS/2 Keyboard Interface in a Virtex-E
    46600: 02/09/04: Re: choice of fpga
    46934: 02/09/12: Re: differences between CoolRunner XPLA3 and CoolRunner-II?
    47115: 02/09/18: Re: Can I run a 3.3V CPLD off of 3V?
    47121: 02/09/18: GCLK pin used like an standard input
    47126: 02/09/18: Re: Simple parallelport IP for Spartan2
    47162: 02/09/19: Re: GCLK pin used like an standard input
    49540: 02/11/14: Re: EPP slave interface
    49572: 02/11/15: Re: EPP slave interface
    49929: 02/11/26: Re: Anybody know of vendors of PCI boards with FPGAs?
    50043: 02/11/29: Re: System Generator and 18x18 multipliers
    50134: 02/12/03: Re: ISA bus VGA
    50214: 02/12/05: Re: Simple parallelport IP for Spartan2
    50469: 02/12/11: Re: Some boards for designers...
    73792: 04/09/29: Re: High speed counters on Xilinx CoolRunner-II
    73276: 04/09/17: Re: How can i interface Spartan-3 with PC/104.
    73439: 04/09/22: VHDL gate level from Xilinx XST
    73118: 04/09/14: Re: Spartan 2E gets hot after configuration
    73170: 04/09/15: Xilinx Core Gen Question
    73222: 04/09/16: Re: Xilinx Core Gen Question
    75334: 04/11/02: Re: XST - Memory Problems
    74120: 04/10/04: Re: Asynchronous reset timing problem
    74835: 04/10/20: Question for XST expert
    75856: 04/11/17: Re: Suggestion for Xilinx parallel port cable replacement.
    75893: 04/11/18: Re: Spartan-3 configuring problem
    78815: 05/02/08: Re: SimmStick FPGA module
    78821: 05/02/08: Re: SimmStick FPGA module
    80149: 05/03/02: Spartan3E
    80624: 05/03/09: Re: Basic cheap fpga configuration
    80625: 05/03/09: Re: [ANN] jjtag - Java JTAG interface
    80912: 05/03/14: Re: XCF01's in the UK
    81017: 05/03/16: Re: Sensitivity list
    81896: 05/04/04: Re: XC95108 problem
    82486: 05/04/13: Re: LUT in fpga
    82949: 05/04/20: Re: Ambigous operator '&'
    83558: 05/05/03: Re: JTAG communication Problems in Quartus using Signal Tap
    83873: 05/05/09: Max7000ae and GCLRn
    83879: 05/05/09: Quartus II - multicyle option
    83880: 05/05/09: Re: Quartus II - multicyle option
    84015: 05/05/11: Re: Configuring an XC3S400 Spartan 3 with JTAG
    85357: 05/06/08: Re: faster Spartan III adder
    85364: 05/06/08: searching spartan-3
    86433: 05/06/28: Re: Good FPGA for an encryptor
    86989: 05/07/12: FPGA to ASIC + JTAG chain insertion
    87239: 05/07/20: Re: General-purpose STAPL Composer?
Laurent Gauch, Amontec:
    50310: 02/12/08: Re: How to assign pins in VHDL?
    50329: 02/12/09: Re: FPGA/PCI on low budget
    51966: 03/01/27: Re: conversion from Xilinx schematics to Mentor Graphics?
    53456: 03/03/13: Re: [Xilinx] Looking for Parallel Cable III ...
    53457: 03/03/13: Re: Homemade Xilinx Parallel JTAG Download Cable
    53709: 03/03/20: Re: PCI target design
    53863: 03/03/25: Re: Programming fpga
    54011: 03/03/31: Re: ModelSIM XE wave files
    54012: 03/03/31: Re: Help reg Target device & synthesis
    54318: 03/04/08: Re: Coolrunner 2 's 16 pins output effect
    54352: 03/04/08: Re: Dead cpld?
    54415: 03/04/10: Re: ieee1284
    54478: 03/04/11: Re: ieee1284
    54880: 03/04/21: ANN : Online VHDL Memo
    55336: 03/05/04: Re: cable length on homemade Parallel Cable III
    55428: 03/05/07: Re: Problem erasing Coolrunner
    56039: 03/05/28: Re: JTAG madness
    56085: 03/05/28: Re: New Xilinx PROMs
    56491: 03/06/06: Re: using USB
Laurent HAAS:
    14995: 99/03/02: Problem with Xchecker connection
Laurent Hugueville:
    10836: 98/06/24: transfert a BINARY file from a PC to a XC3030 (Xilinx)
Laurent LE BOURHIS:
    2604: 96/01/10: IIR FILTER
Laurent Lemarchand:
    2615: 96/01/11: place/route for LUT-based FPGA
    7585: 97/09/24: EDIF spec for Xilinx XC6200
    13755: 98/12/22: SIS & CAD tools
Laurent Moll:
    4428: 96/10/28: Free NT device driver (with sources)
    5832: 97/03/19: Re: Development board with multiple FPGAs
Laurent Pinchart:
    80041: 05/03/01: FPGA interface to an asynchronous microcontroller memory bus
    80047: 05/03/01: Re: FPGA interface to an asynchronous microcontroller memory bus
    80048: 05/03/01: Re: FPGA interface to an asynchronous microcontroller memory bus
    80116: 05/03/02: Re: FPGA interface to an asynchronous microcontroller memory bus
    80118: 05/03/02: Re: FPGA interface to an asynchronous microcontroller memory bus
    80119: 05/03/02: Re: FPGA interface to an asynchronous microcontroller memory bus
    80120: 05/03/02: Re: FPGA interface to an asynchronous microcontroller memory bus
    102383: 06/05/15: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102425: 06/05/16: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102428: 06/05/16: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102455: 06/05/16: Re: USB2 camera to Xilinx ML40x boards
    102461: 06/05/16: Re: USB2 camera to Xilinx ML40x boards
    102488: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102490: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102508: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102509: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    102601: 06/05/18: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    103041: 06/05/25: Re: windrvr for Linux broken in 2.6.16
    111371: 06/11/02: Xilinx ISE Webpack - Any usable simulator for the Linux platform ?
    120823: 07/06/18: Enumerated type simulation issue (ISE simulator, 9.1.03i)
    121513: 07/07/06: Re: Xilinx ISE, EDK and some ground roules in software development
    121549: 07/07/07: Re: Xilinx ISE, EDK and some ground roules in software development
Laurent SANDRIN:
    37227: 01/12/04: altera max++ baseline and jedec file
Lauri Ehrenpreis:
    100108: 06/04/03: Xilinx XST incremental synthesis tooo slow
Lauri Kuru:
    38: 94/08/02: Re: How pricey is FPGA development?
    1344: 95/06/03: Re: Latch up in Xilinx 3000 Series FPGA's. Part smokes & smells bad.
    2245: 95/11/09: Re: X-Blox...The good, bad and ugly
Laust Brock-Nannestad:
    153180: 12/01/04: Re: slimming down ISE install
<lavazza2009@gmail.com>:
    138290: 09/02/12: Re: PLDShell Plus V5.1
Lawrence Butcher:
    3763: 96/07/26: Re: ATT serial EEPROMs
    4035: 96/09/05: synopsys vs. xilinx floor-planning
    4559: 96/11/13: Re: AAL5 SAR Design?
Lawrence Chai:
    18282: 99/10/12: Wanted: HOTWORKS board
Lawrence Chai MJ:
    16061: 99/04/30: WTB: XC6200
Lawrence D. Lopez:
    71997: 04/08/05: What is the price of the micro-blaze, ... ?
Lawrence Hau:
    11079: 98/07/17: FPAG -> Memory & CRC
Lawrence Kiss:
    75986: 04/11/21: Spartan 3 output voltage level
    75993: 04/11/22: Re: Spartan 3 output voltage level
    76015: 04/11/22: Re: Spartan 3 output voltage level
lawrence Lopez:
    71998: 04/08/05: Re: New WinFilter Digital Filter design freeware tool release available.
Lawrence Nospam:
    70206: 04/06/09: Question about Xilinx packages and CLB ordering
Lawrence Peregrim:
    25636: 00/09/15: Virtex clock fanout
    27074: 00/11/09: ChipScope
    28451: 01/01/12: Virtex counter speed
Lawrence Wilkinson:
    82721: 05/04/17: Re: Xilinx tools on Linux
    82756: 05/04/17: Re: Xilinx tools on Linux
    82757: 05/04/17: Re: Xilinx tools from the commandline
    83187: 05/04/25: Re: New FPGA Development Board
<lb.edc@telenet.be>:
    98175: 06/03/06: Re: why use an FPGA when a CPLD will do ??
    99348: 06/03/23: Re: Lattice FPGA
    99469: 06/03/24: Re: Lattice FPGA
    99473: 06/03/24: Re: Lattice FPGA
    102355: 06/05/15: Re: Virtex 5 announced
    102482: 06/05/16: Re: Xilinx or Altera...
    102506: 06/05/17: Re: Xilinx or Altera...
    102649: 06/05/18: Re: ADC implementation on FPGA ?
    102823: 06/05/21: Re: ispLEVER Starter 6.0 FPGA Design Software Available
    102824: 06/05/21: Re: ispLEVER Starter 6.0 FPGA Design Software Available
    102850: 06/05/22: Re: ispLEVER Starter 6.0 FPGA Design Software Available
    104430: 06/06/27: Re: need help plz.
    106724: 06/08/17: Re: FFT on an FPGA
    107178: 06/08/25: Re: fastest FPGA
    107572: 06/08/30: Re: Spartan-4 ?
    108462: 06/09/11: Re: Lattice eval board with PCIe and SATA
    108682: 06/09/15: Re: ispDesignExpert available for download anywhere ?
    108698: 06/09/15: Re: ispDesignExpert available for download anywhere ?
    108866: 06/09/18: Re: Lattice ECP2/M
    108883: 06/09/18: Re: Virtex4 Configuration ROM?
    109223: 06/09/22: Re: Lattice ispMACH4000 eval boards
    109292: 06/09/23: Re: PCI Express
    109308: 06/09/23: Re: PCI Express
    111212: 06/10/31: Re: FFT help
    111909: 06/11/13: Re: Stratix-III announced
    113077: 06/12/06: Re: Spartan-3A launched
    113089: 06/12/06: Re: Altera starter kits
    114966: 07/01/28: Re: Higher studies
    115983: 07/02/27: Re: Spartan-3AN
    115994: 07/02/27: Re: Spartan-3AN
    116061: 07/03/01: Re: Spartan-3AN
    116062: 07/03/01: Re: Virtex 4 FX Sonet Alignment
    117379: 07/03/29: Re: suggestion for choosing the right FPGA for gigabit transciever
    119870: 07/05/28: Rodney Smith, long term Altera CEO, dies in accident
    120254: 07/06/04: Re: Lattice XP2 finally announced
    120469: 07/06/07: Re: Lattce SC Purspeed I/O
    120526: 07/06/08: Re: Lattce SC Purspeed I/O
    122008: 07/07/17: Re: Xilinx XC9536 current draw ?
    122019: 07/07/17: Re: Xilinx XC9536 current draw ?
    122160: 07/07/21: Re: Xilinx fpgas...
    123057: 07/08/15: Re: Delaying a pulse train
    124819: 07/10/05: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    125741: 07/11/02: Re: Spartan-3 (XC3S400) DDR LVDS support?
    125896: 07/11/08: Re: Non-volatile FPGA in a small package
    126170: 07/11/16: Re: Lattice Semi
    126221: 07/11/17: Re: Low cost FPGA w/serdes
    126342: 07/11/20: Re: Low cost FPGA w/serdes
    129512: 08/02/26: Re: Xilinx self-termination
lbo_user:
    113463: 06/12/14: Re: NOR Flash Controller
    113469: 06/12/14: Re: NOR Flash Controller
    114852: 07/01/25: Any UK mirror for ISE 8.2i SP2?
<lbraeckm@gmail.com>:
    135562: 08/10/08: Re: How to synthesize a delay of around 10 ns in FPGA?
    135860: 08/10/18: Embedded Linux on V5 FXT
lbroto:
    68525: 04/04/07: Quartus for linux
LC:
    120274: 07/06/04: FFT and etc on a cycloneII or III help/sugestions.
    126808: 07/12/03: Re: Interfacing Cyclone III to 3.3v LVDS devices
    131002: 08/04/08: NoisII or else.
    131009: 08/04/08: Re: NoisII or else.
    131057: 08/04/09: Re: NoisII or else.
    131058: 08/04/09: Re: NoisII or else.
    131062: 08/04/09: Re: NoisII or else.
    131142: 08/04/12: Need help on UNISIM.Vcomponents.all
    131168: 08/04/14: Re: Need help on UNISIM.Vcomponents.all
    131169: 08/04/14: Re: Need help on UNISIM.Vcomponents.all
    131406: 08/04/21: not inferred RAM, on QII
    131415: 08/04/21: Re: not inferred RAM, on QII
    131457: 08/04/22: Re: not inferred RAM, on QII
    131459: 08/04/22: Re: not inferred RAM, on QII
    131518: 08/04/24: Re: not inferred RAM, on QII
    137449: 09/01/17: CycIII Intefacing these new serial ADC's
    143365: 09/10/06: Re: Altera logic programmer card (PLP6) problem
    144126: 09/11/12: Altera/EPCS16 issues
    147567: 10/05/04: Unecessary simulation paths
    147607: 10/05/06: Re: Unecessary simulation paths
    148016: 10/06/14: how fast is ... fast.
    148032: 10/06/15: Re: how fast is ... fast.
    148034: 10/06/15: Re: how fast is ... fast.
    148045: 10/06/16: Re: how fast is ... fast.
    148117: 10/06/22: Re: how fast is ... fast.
    149580: 10/11/08: Modelsim Altera - Strange issue.
lc:
    55508: 03/05/11: Altera Flex EPF81188A
    55524: 03/05/12: Re: Altera Flex EPF81188A
    55530: 03/05/12: Re: Altera Flex EPF81188A
    55689: 03/05/15: smallest embedded cpu.
    70517: 04/06/18: CPLD mistery. Help.
    70573: 04/06/21: Re: CPLD mistery. Help.... reHelp.
    70575: 04/06/21: Re: CPLD mistery. Help. The resulting equations.
    70621: 04/06/22: Re: CPLD mistery. Problem Found... and is an interesting one !
LC Geldenhuys:
    70017: 04/05/27: Propogation delays and setup times
    70051: 04/05/31: Re: Propogation delays and setup times
ldallara:
    1614: 95/07/31: Re: Dog Food Drive For Joe Costello
<ldoolitt@recycle>:
    17188: 99/07/07: Re: Floating point on fpga, Counters?
    17479: 99/07/30: Re: Semi-deterministic behaviour in FPGA's
    17586: 99/08/11: Re: Newbie - what are the limitations of the student edition
Le Mer Michel:
    28335: 01/01/08: APEX
    28437: 01/01/12: Re: APEX
    28480: 01/01/15: Re: APEX
    29151: 01/02/08: Re: Altera, NON JTAG devices.
    41044: 02/03/20: which is the fastest FPGA ?
    41286: 02/03/25: Re: which is the fastest FPGA ?
Le mer Michel:
    12428: 98/10/12: Re: Xilinx Foundation forgets the pin assignment. Bug?
    12534: 98/10/15: optimized fpga
    12606: 98/10/20: Re: gray code counter in a Xilinx fpga???
    12612: 98/10/20: output file format
    12755: 98/10/28: Re: State machines in VHDL/Verilog
    12943: 98/11/06: clock doubler
    12947: 98/11/06: Re: Clock Doubler
    13097: 98/11/16: Re: connecting 2 FPGA together
    13098: 98/11/16: Re: Example of clock circuit needed !
    13099: 98/11/16: Re: FPGAs evolution
    13100: 98/11/16: Re: Xilinx COREgen and Leonardo troubles...
    13203: 98/11/19: Re: XNF issue
    13333: 98/11/26: Re: Synchronous SRAM design wanted
    13796: 98/12/28: Re: 22V10 Metastability - help please
    13830: 98/12/29: Re: How to import EDIF file in Foundation Software?
    13869: 98/12/30: Re: about using Mentor and Foudation together
    13882: 98/12/31: Re: How to import EDIF file in Foundation Software?
    13940: 99/01/04: Re: How to import EDIF file in Foundation Software?
    15133: 99/03/09: Re: Pin constraints of Xilinx
    15136: 99/03/09: Re: keeping mapping information - VHDL based design
    15194: 99/03/12: Re: keeping mapping information - VHDL based design
    15217: 99/03/15: Re: SDF
    15249: 99/03/16: Re: Inferring IO's
    15270: 99/03/17: Re: Inferring IO's
    15271: 99/03/17: Re: Problems with foundation
    15272: 99/03/17: Re: help!
    15491: 99/03/26: Re: FPGA Express Synthesis Problem
    15543: 99/03/30: Re: Xilinx Download Serial Cable
    15600: 99/04/02: Re: virtex partial reconfiguration
    15999: 99/04/27: Re: How to use TDO pin of Xilinx4000 in Exemplar ?
    16014: 99/04/28: Re: High speed PLL inside FPGA
    16206: 99/05/10: Re: Spartan Metastability parameters
    16125: 99/05/05: Re: Configuring Xilinx FPGAs
    16164: 99/05/07: Re: PCI slave in FPGA?
    16205: 99/05/10: Re: Bitstream size
    16350: 99/05/18: Re: 4062XL problems and solutions
    16399: 99/05/20: Re: Foundation FPGA Express
    16616: 99/05/31: Re: Generating GSR From Within Chip
    16716: 99/06/04: Re: Using Virtex LUT and MULT_AND
    16886: 99/06/16: Re: Xilinx DP RAM SPO Output
    16885: 99/06/16: Re: 3 Questions with XILINX CPLD
    16887: 99/06/16: Re: FPGA board for ISA bus wanted
    17152: 99/07/05: Re: Using Block SelectRAM+ in Virtex
    17158: 99/07/06: Re: Virtex: Excessive PAR run-times without user-feedback?
    17198: 99/07/08: Re: Programming Xilinx without Foundation
    17224: 99/07/12: Re: how to choose only a set of pins
    17411: 99/07/26: Re: Using Xilinx Foundation & Mentor Graphics
    17412: 99/07/26: Re: Designing a Virtex board
Le.Wang:
    89361: 05/09/13: 24 Counters on one board
    89393: 05/09/14: Re: 24 Counters on one board
    89537: 05/09/18: Dll device for FPGA
leaf:
    99070: 06/03/19: Re: PCI Configuration access and Target State Machine...
    99121: 06/03/20: Re: PCI Configuration access and Target State Machine...
    99165: 06/03/20: Simulation tool
    99189: 06/03/21: Re: Simulation tool
    99489: 06/03/25: Re: PCI Configuration access and Target State Machine...
    99524: 06/03/25: Re: PCI Configuration access and Target State Machine...
Learner JCF:
    75211: 04/10/29: Re: dw_prefer_mc_inside command in DC
learnfpga:
    85210: 05/06/06: Re: ispLSI1016
    85358: 05/06/08: Re: FPGA/CPLD trend
    88754: 05/08/27: Problem with ModelSim XE
    88757: 05/08/27: Re: Problem with ModelSim XE
    88761: 05/08/27: Re: Problem with ModelSim XE
    88878: 05/08/30: Re: beginner [ query : resources and guidance for a newbie]
    91349: 05/11/03: Re: I have received a job offer
    112134: 06/11/16: Warnings in Xilinx 8.2i
    112176: 06/11/17: Re: Warnings in Xilinx 8.2i
learnfpga@gmail.com:
    85058: 05/06/03: Re: ispLSI1016
    85062: 05/06/03: Re: ispLSI1016
    85065: 05/06/03: Re: ispLSI1016
    85113: 05/06/04: Re: ispLSI1016
    85123: 05/06/05: ORCAD CIS 7.2
    85128: 05/06/05: Re: ispLSI1016
    85182: 05/06/06: FPGA/CPLD trend
<learnfpga@gmail.com>:
    85048: 05/06/03: ispLSI1016
<leaver.andrew@gmail.com>:
    134986: 08/09/09: Re: Altera library sim question
lecricri:
    7584: 97/09/24: logiblox and VHDL with viewlogic
lecroy:
    57416: 03/06/30: ise:Xilinx fires another shot
    57417: 03/06/30: Re: ise:Xilinx fires another shot
    57477: 03/07/01: Xilinx ISE drops support for more parts
    57548: 03/07/02: Re: Xilinx ISE drops support for more parts
    57549: 03/07/02: Re: Xilinx ISE drops support for more parts
    57550: 03/07/02: Re: Xilinx ISE drops support for more parts
    57655: 03/07/03: Re: Xilinx ISE drops support for more parts
    57656: 03/07/03: Re: Xilinx ISE drops support for more parts
    57809: 03/07/07: Re: Xilinx ISE drops support for more parts
    57839: 03/07/08: Re: Xilinx ISE drops support for more parts
    57862: 03/07/08: Re: Xilinx ISE drops support for more parts
    57903: 03/07/09: Re: Xilinx ISE drops support for more parts
    60218: 03/09/08: Xilinx S3 I/O robustness question
    60258: 03/09/09: Re: Xilinx S3 I/O robustness question
    60423: 03/09/12: Re: Xilinx S3 I/O robustness question
    60437: 03/09/12: Re: Xilinx S3 I/O robustness question
    60493: 03/09/15: Re: Xilinx S3 I/O robustness question
    60495: 03/09/15: Re: Xilinx S3 I/O robustness question
    60770: 03/09/22: Re: Xilinx S3 I/O robustness question
    61239: 03/09/30: Re: Xilinx S3 I/O robustness question
    61242: 03/09/30: Re: Xilinx S3 I/O robustness question
    61515: 03/10/06: Re: Xilinx S3 I/O robustness question
    61845: 03/10/14: Re: Xilinx S3 I/O robustness question
    62935: 03/11/11: Re: Xilinx S3 I/O robustness question
    63926: 03/12/09: Xilinx Spartan II pull-up, simple questions
    64719: 04/01/12: Why won't Xilinx document their code??
    72165: 04/08/10: Spartan III I/O robustness
    72461: 04/08/19: Re: Spartan III I/O robustness
    72463: 04/08/19: Quartus, building "Safe" FMSs
    72525: 04/08/23: Re: Quartus, building "Safe" FMSs
lecroy7200:
    81405: 05/03/23: Re: XC3000 non-recoverable lockup problem
    81406: 05/03/23: Re: XC3000 non-recoverable lockup problem
    81451: 05/03/24: Re: XC3000 non-recoverable lockup problem
    81458: 05/03/24: Re: XC3000 non-recoverable lockup problem
lecroy7200@chek.com:
    81424: 05/03/23: Re: Xilinx ISE 7.1 - Can this get any worse?
    81434: 05/03/23: Re: XC3000 non-recoverable lockup problem
    81436: 05/03/23: Re: XC3000 non-recoverable lockup problem
    81441: 05/03/23: Re: XC3000 non-recoverable lockup problem
    81475: 05/03/24: Re: Xilinx ISE 7.1 - Can this get any worse?
    81482: 05/03/24: Re: XC3000 non-recoverable lockup problem
    81486: 05/03/24: Re: XC3000 non-recoverable lockup problem
    81585: 05/03/28: Re: XC3000 non-recoverable lockup problem
    81592: 05/03/28: Re: XC3000 non-recoverable lockup problem
    81637: 05/03/29: Re: XC3000 non-recoverable lockup problem
    81643: 05/03/29: Re: XC3000 non-recoverable lockup problem
    81657: 05/03/29: Re: XC3000 non-recoverable lockup problem
    81673: 05/03/29: Re: XC3000 non-recoverable lockup problem
    81703: 05/03/30: Re: XC3000 non-recoverable lockup problem
    81769: 05/03/31: Re: XC3000 non-recoverable lockup problem
    81907: 05/04/04: Re: XC3000 non-recoverable lockup problem
    82098: 05/04/06: Re: XC3000 non-recoverable lockup problem
    82513: 05/04/13: Re: Reading old F2.1i schematics
    82894: 05/04/19: Re: XC3000 non-recoverable lockup problem
    82950: 05/04/20: Re: Charge-pumps in FPGAs? Not Since 1998
    82971: 05/04/20: Re: Charge-pumps in FPGAs? Not Since 1998
    83145: 05/04/24: Re: subjects should reflect the subject
    98666: 06/03/14: DSP Builder @ System Generator
    100157: 06/04/04: Altera Stratix II GX LVDS max speed
    100216: 06/04/05: Re: Altera Stratix II GX LVDS max speed
    100290: 06/04/06: Re: Altera Stratix II GX LVDS max speed
    100300: 06/04/06: Altera Talkback
    100566: 06/04/12: Re: Altera Stratix II GX LVDS max speed
    100624: 06/04/13: Did National cheat with the Virtex 4
    100723: 06/04/17: Re: Did National cheat with the Virtex 4
    100724: 06/04/17: Re: Did National cheat with the Virtex 4? Or are they just smart engineers?
    100733: 06/04/17: Re: Did National cheat with the Virtex 4
    100736: 06/04/17: Re: Did National cheat with the Virtex 4? Or are they just smart engineers?
    100743: 06/04/17: Re: Did National cheat with the Virtex 4? Doesn't look like it....
    100766: 06/04/17: Re: Did National cheat with the Virtex 4
    103932: 06/06/15: Bug in Altera Quartus
    104395: 06/06/26: Xilinx ML461 memory board, whats the real story?
    104484: 06/06/28: Re: Xilinx ML461 memory board, whats the real story?
    104797: 06/07/06: Re: Xilinx ML461 memory board, whats the real story?
    112311: 06/11/20: Simple questions on IDELAYCTRL
    112448: 06/11/22: Re: Simple questions on IDELAYCTRL
    112449: 06/11/22: Re: Simple questions on IDELAYCTRL
    112457: 06/11/22: Re: Simple questions on IDELAYCTRL
    113805: 06/12/22: Re: Simple questions on IDELAYCTRL vs DCM
    113828: 06/12/23: Re: Simple questions on IDELAYCTRL vs DCM
    117419: 07/03/30: Another simple DCM question
    118641: 07/05/01: ISE 8.2 Strange cache problem? Warning...
    118728: 07/05/02: Re: ISE 8.2 Strange cache problem? Warning...
    128097: 08/01/15: All things ahead, planahead
    135907: 08/10/21: Would like to try ISIM, simple question
    135951: 08/10/23: Re: Would like to try ISIM, simple question
    136178: 08/11/04: Re: Would like to try ISIM, simple question
    136179: 08/11/04: Re: Would like to try ISIM, simple question
    136193: 08/11/05: Re: Would like to try ISIM, simple question
    136372: 08/11/13: Re: Would like to try ISIM, simple question
    136498: 08/11/19: Re: Would like to try ISIM, simple question
    136846: 08/12/08: Re: ISE doesn't work after a crash
    136860: 08/12/09: Re: How to save added signals to waveform viewer
    136915: 08/12/12: Re: Doubt about the maximum speed of FPGA clock nets
    137802: 09/01/29: Aldec Active HDL 8.1 major problem with code coverage
    137905: 09/02/02: Re: Problems when I download and install Xilinx ISE 10.1. Help
    141821: 09/07/10: One more DCM question
<lecroy7200@chek.com>:
    80490: 05/03/07: Xilinx / Altera TCLK termination (Pull up or down)
    80533: 05/03/07: Re: Xilinx / Altera TCLK termination (Pull up or down)
    80789: 05/03/11: Re: Xilinx / Altera TCLK termination (Pull up or down)
    80800: 05/03/11: XC3000 non-recoverable lockup problem
    80908: 05/03/14: Re: XC3000 non-recoverable lockup problem
    80909: 05/03/14: Re: XC3000 non-recoverable lockup problem
    80916: 05/03/14: Re: XC3000 non-recoverable lockup problem
    80917: 05/03/14: Re: XC3000 non-recoverable lockup problem
    80932: 05/03/14: Re: XC3000 non-recoverable lockup problem
    80965: 05/03/15: Re: XC3000 non-recoverable lockup problem
    80985: 05/03/15: Re: XC3000 non-recoverable lockup problem
    80989: 05/03/15: Re: XC3000 non-recoverable lockup problem
    81012: 05/03/16: Re: XC3000 non-recoverable lockup problem
    81077: 05/03/17: Re: XC3000 non-recoverable lockup problem
    81172: 05/03/18: Re: XC3000 non-recoverable lockup problem
    81178: 05/03/18: Re: XC3000 non-recoverable lockup problem
    81322: 05/03/21: Re: XC3000 non-recoverable lockup problem
    81361: 05/03/22: Re: XC3000 non-recoverable lockup problem
    81367: 05/03/22: Re: XC3000 non-recoverable lockup problem
Lee:
    67849: 04/03/21: Help recognizing format
    67980: 04/03/23: Re: Help recognizing format
    68911: 04/04/21: Compiling library problem in Xilinx ISE4.0?
    68918: 04/04/21: How may I use TCL file downloaded from Xilinx to compile libraries for ModelSim?
    68948: 04/04/22: Re: Compiling library problem in Xilinx ISE4.0?
    68949: 04/04/22: Re: How may I use TCL file downloaded from Xilinx to compile libraries for ModelSim?
    72385: 04/08/17: Rocket IO Deserializer
    75266: 04/10/31: In ISE 6.2i, CoreGen doesn't show any component?
    86462: 05/06/28: Re: FPGA for video processing
lee:
    47735: 02/10/02: Re: DFT , Design For Test HELPPPPP
    61373: 03/10/02: Re: Good VHDL/Verilog editor?
Lee Cao:
    20124: 00/01/27: ADC to DSP... FIFO?
Lee Fadden:
    345: 94/10/25: Memory
    363: 94/10/28: fpga
    362: 94/10/28: FPGA
    605: 95/01/18: Ray Andraka's services
    830: 95/03/08: Inverse-Fourier waveform synthesis
Lee I.:
    30099: 01/03/22: Re: Senior I/O Designer - Canada
Lee Iovino:
    30047: 01/03/21: Re: Senior I/O Designer - Canada
    30048: 01/03/21: implementing complex datacom protocols
Lee Jae-Hyuck:
    6061: 97/04/09: About the usage of Altera maxplus2
    6063: 97/04/09: About the usage of maxplus2
Lee Khoon:
    44987: 02/07/08: Re: Inserting flops to help timing (in Virtex-II)
Lee Mitchell:
    6899: 97/07/07: Re: Smart Card Design and Interface. How?
lee news:
    70063: 04/06/01: Re: Is this a bug in ISE 6.1?
    70064: 04/06/01: Re: DLL - Change in input frequency (CLKIN)
Lee Webb:
    21128: 00/03/07: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86,
Lee Weston:
    22718: 00/05/19: Re: Help with macrocell , explain it to me
    25944: 00/09/27: Preserving nets using Maxplus2 (9.5)
    25962: 00/09/28: Re: Preserving nets using Maxplus2 (9.5)
    28264: 01/01/04: FPGA Compiler2 question
    28487: 01/01/15: Certify 2.2.1 question
    36683: 01/11/15: Re: Synopsys+Xilinx vs Synplicity
lee youngtae:
    6327: 97/05/15: What's FPGA?
    6328: 97/05/15: What's FPGA?
    6329: 97/05/15: What's FPGA defintion?
<leeaby@gmail.com>:
    110516: 06/10/17: Newbie : Please give me an idea about programming an FPGA
Leeinhyuk:
    85407: 05/06/09: Motion controller design with CPLD
    85849: 05/06/17: Need application note for Motion controller with Xilinx
    85992: 05/06/20: Need Application note for Motion Controller with Xilinx
Leeja:
    196: 94/09/19: Postings sent as mail ???--------------
<leejp@my-deja.com>:
    17869: 99/09/14: simple VHDL?
    17882: 99/09/15: Re: simple VHDL?
    17899: 99/09/16: Re: simple VHDL?
    17900: 99/09/16: Re: simple VHDL?
Leendert:
    145109: 10/01/27: Re: AWGN TESTING
leevv:
    82588: 05/04/14: Internal clk gen on IO PAD in Xilinx FPGA
    85469: 05/06/09: Re: anyone tried the Actel ProASIC3 Starter Kit?
    86198: 05/06/22: problems with Xilinx GSRD design for ML403
    92437: 05/11/29: re:Merging the ML403 refence design and the GSRD design
    93532: 05/12/23: re:Virtex-4FX and ethernet mac
    102760: 06/05/19: xilinx V4 obufds_25 and 3.3 V
    102785: 06/05/20: Re: xilinx V4 obufds_25 and 3.3 V
    103248: 06/05/29: Re: ISE 8.1 with 7.1
    107692: 06/08/31: Re: MPMC2 : npi issues
    110958: 06/10/25: Re: xilinx sync fifo with first word fall-through
    110978: 06/10/26: Re: xilinx sync fifo with first word fall-through
    112852: 06/11/29: Re: Xilinx FIFOs round 2 - BUG-BUG in MPMC2
    112883: 06/11/30: Re: Xilinx FIFOs round 2 - BUG-BUG in MPMC2
    114060: 07/01/03: Re: Mapper using wrong EMAC with PowerPC in V4FX60
    118455: 07/04/26: Re: Problem with PowerPC PIT interrupt
    118456: 07/04/26: Re: Is anyone has experience to share OPB for 2 PowerPC in MPMC2 core
    120767: 07/06/15: Re: booting a large V4 PPC program with a minimum of on chip
    120786: 07/06/16: Re: booting a large V4 PPC program with a minimum of on chip
    129416: 08/02/22: Re: Xilinx self-termination
    139303: 09/03/25: Re: USB PHY
    140244: 09/05/05: Xilinx XPS_INTC and XPS_UARTLITE interrupt issues
leexiaofat:
    82254: 05/04/09: where can i get xilinx ise 7.1 evalution ?
Left blanks:
    23052: 00/06/11: Re: 68k - core, a free core 1, and 2 worth money = time.
Legalex:
    153758: 12/05/15: Synthesis Problem
    153761: 12/05/16: Re: Synthesis Problem
    153762: 12/05/16: Re: Synthesis Problem
    153765: 12/05/16: Re: Synthesis Problem
Legendary Design:
legg:
    77798: 05/01/17: Re: How protection diodes 'wear out'.
    78079: 05/01/24: Re: Urgent help regarding voltage overstressing
    153212: 12/01/08: Re: voltage drop on STRATIX FPGA supply planes
Legista:
    19496: 99/12/27: Schematics for ISP
Lehner Franz:
    61651: 03/10/08: Jtag
<leibnizster@gmail.com>:
    99097: 06/03/20: SMTP
Leinonen Mika:
    22939: 00/06/05: PLA to ABEL converter?
Leisure:
    23451: 00/06/26: Re: F2.1i
Leland C. Scott:
    144902: 10/01/13: Which WebPack for old Spartan and Spartan-2?
    144915: 10/01/14: Which WebPack for old Spartan and Spartan-2?
    144916: 10/01/14: Which WebPack for old Spartan and Spartan-2?
    144917: 10/01/15: Which WebPack for old Spartan and Spartan-2?
    144938: 10/01/16: Which WebPack for old Spartan and Spartan-2?
    144946: 10/01/16: Which WebPack for old Spartan and Spartan-2?
    155171: 13/05/22: Development/Experimenter's kits
    155187: 13/05/23: Re: Development/Experimenter's kits
    155188: 13/05/23: Re: Development/Experimenter's kits
    155194: 13/05/26: Re: Development/Experimenter's kits
    155195: 13/05/26: Re: Development/Experimenter's kits
Lelik Bolik:
    57128: 03/06/24: How to get 27MHz from 10 MHz in FPGA???
<lellis@my-dejanews.com>:
    10591: 98/06/03: Re: Example of 8051 codes to configure Xilinx fpga
<lembke.stefan@googlemail.com>:
    123147: 07/08/17: Slice equation in bitstream
    123151: 07/08/17: Re: Slice equation in bitstream
    123153: 07/08/17: Re: Slice equation in bitstream
    123157: 07/08/17: Re: Slice equation in bitstream
    123159: 07/08/17: Re: Slice equation in bitstream
    123162: 07/08/17: Re: Slice equation in bitstream
    124302: 07/09/18: Re: Slice equation in bitstream
    124460: 07/09/22: CRC calculation of Virtex 4 bitstream
    124479: 07/09/24: Re: CRC calculation of Virtex 4 bitstream
<lemnaj55@bellsouth.net>:
    17757: 99/08/31: MONEY!
Len:
    82773: 05/04/17: Multi-page schematics (.bdf) in Quartus II?
    82797: 05/04/18: Re: Multi-page schematics (.bdf) in Quartus II?
    83036: 05/04/21: Re: FIFO as a Logic Analyzer; Clock synthesizer
    84278: 05/05/16: Is a gated oscillator using NAND okay within a Cyclone FPGA?
    84281: 05/05/16: Re: Is a gated oscillator using NAND okay within a Cyclone FPGA?
    84283: 05/05/16: Re: Is a gated oscillator using NAND okay within a Cyclone FPGA?
    88890: 05/08/30: Implementing PLL in Cyclone - Schematic entry
    88892: 05/08/30: Re: Implementing PLL in Cyclone - Schematic entry
    90956: 05/10/25: Re: a few questions
    90959: 05/10/25: Re: a few questions
    92593: 05/12/01: Re: Quick question, how do I supply +-5V?
    92871: 05/12/08: Re: 2 clocks switching
    94193: 06/01/06: Re: Schematic Entry, Xilinx or Altera?
Len Chisholm:
    42651: 02/04/30: Re: Xilinx XC9500XL family - disabling the bus-hold circuits
    43285: 02/05/18: Building a relaxation oscillator with a Xilinx 9536XL
    54565: 03/04/14: Re: Too early to throw away Parallel Cable III...
Len Harold:
    59: 94/08/05: An FPGA WWW Page
    779: 95/02/28: Re: Can I implement a digital PLL in an FPGA??
    1134: 95/05/03: Looking for a few good web sites.
    1181: 95/05/11: Re: Overheating (was Re: Compression algo's for FPGA's)
    4208: 96/09/26: Re: How to Begin with FPGA design?
    6492: 97/05/28: Re: Cheap way to develop for FPGAs?
    7913: 97/10/29: Re: design sites
    10398: 98/05/16: Re: Xilinx Foundation and Linux
    51440: 03/01/13: Re: Simulate Virtex Primitive using ModelSim
<len>:
    121234: 07/06/28: d-link router?
<LenAnderson@ieee.org>:
    97549: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
Lengyel Sandor:
    10238: 98/05/05: Re: Why Altera & Cypress Software Clashes (was: VHDL compiler differences?)
lenile84:
    104423: 06/06/27: need help plz.
lenman:
    49154: 02/11/03: 16-bit FGPA CPU core (commercial)
    49159: 02/11/03: Re: 16-bit FGPA CPU core (commercial)
lennart:
    34327: 01/08/21: Re: Need help: CLKDLLE.v does not work in simulation.
    34963: 01/09/16: Re: using BlockRAM
    35080: 01/09/20: Re: Clockin on rising AND falling edge
    37447: 01/12/11: HDL editor ISE 4.1 : auto-keyboard switching
LENNART KIRKEVIK:
    83463: 05/04/30: problems getting flex10k10 to work
Lenny:
    28991: 01/02/01: Virtex : Timing Problem
lenz:
    58573: 03/07/27: FPGA research
    58594: 03/07/28: Re: FPGA research
    59179: 03/08/11: Virtex "Virtual VCC"
    59207: 03/08/12: Re: Virtex "Virtual VCC"
    62921: 03/11/11: Logic implementation in SRAM/OTP FPGAs
    66344: 04/02/17: GZIP algorithm in FPGA
    66659: 04/02/24: Stratix 2 ALUT architecture patented ?
    70795: 04/06/28: FPGA jobs in Germany
<lenz19@gmx.de>:
    101922: 06/05/08: Re: Funky experiment on a Spartan II FPGA
    102021: 06/05/09: Re: Funky experiment on a Spartan II FPGA
    141346: 09/06/19: FDRSE Spartan 3A - Active high/low set/reset
    141355: 09/06/19: Re: FDRSE Spartan 3A - Active high/low set/reset
    141357: 09/06/19: Re: FDRSE Spartan 3A - Active high/low set/reset
    141370: 09/06/21: Re: FDRSE Spartan 3A - Active high/low set/reset
Leo:
    80477: 05/03/06: VoIP & FPGA
    80537: 05/03/07: Re: VoIP & FPGA
    155521: 13/07/14: Floorplanning Literature
    155546: 13/07/17: Re: Floorplanning Literature
    155547: 13/07/17: Re: Floorplanning Literature
    155550: 13/07/17: Re: Floorplanning Literature
    155579: 13/07/23: FF Replication with Xilinx ISE
    155584: 13/07/24: Re: FF Replication with Xilinx ISE
    155587: 13/07/24: Re: FF Replication with Xilinx ISE
    157662: 15/01/22: Send a pulse across clocks
    157666: 15/01/22: Re: Send a pulse across clocks
    157667: 15/01/22: Re: Send a pulse across clocks
Leo Breuss:
    35583: 01/10/11: Timing constraints for unrelated clocks?
    35645: 01/10/12: Re: Timing constraints for unrelated clocks?
    35723: 01/10/15: Re: Timing constraints for unrelated clocks?
Leo Havmøller:
    42147: 02/04/17: Re: FPGA Timing Problem
    42602: 02/04/29: Re: FlexLM
    43230: 02/05/17: Re: extend jtag downloadcable
Leo Shvarberg:
    7611: 97/09/26: Re: ISP Serial EEPROM for Altera FLEX10k
    8551: 98/01/07: Re: serial conf. PROMS
    9064: 98/02/17: Re: Atmel SPROMs for Xilinx
    9065: 98/02/17: Re: ACROBAT
leoeltipo:
    148320: 10/07/07: LXT972 pass-through packet
Leon:
    17635: 99/08/17: Re: fpga board : make it or buy it?
    34233: 01/08/17: Re: Help with ACEX1K100 device
    85753: 05/06/15: Xilinx seminar is free AND low cost!
    85836: 05/06/16: Re: Availability of Spartan3
    86053: 05/06/21: Re: : Parts Back on Xilinx Online Store (www.xilinx.com/store)
    90880: 05/10/24: Re: evaluation edk in Spartan-3 starter kit
    93188: 05/12/15: Re: Digilent SRAM Controller
    93504: 05/12/23: Re: Spartan3e and ChipScope
    93554: 05/12/24: Re: Spartan3e and ChipScope
    93840: 06/01/01: Re: Easy and fun: Worlds smallest FPGA module.
    93916: 06/01/03: Re: CPU86 (Intel 8086) VHDL now available (thanks to HT-LAB !)
    94339: 06/01/10: ISE 8.1i WebPack available
    94476: 06/01/12: Re: ISE 8.1i WebPack available
    94373: 06/01/10: Re: Downloading WebPack-8.1, server maxes out at 30 kB / second (= > 7 hours)?
    94478: 06/01/12: Re: DSP soft processors
    94477: 06/01/12: Re: Conflicts between ISE4.2 and win2000 SP4
    94758: 06/01/17: Re: xilinx free Sample Pack info now also on Xilinx own webpages
    94915: 06/01/19: Re: Spartan3 initialization with DSP
    94965: 06/01/19: Re: Spartan3 initialization with DSP
    94904: 06/01/18: Re: How much do you trust your CAD Program?
    95173: 06/01/21: Re: Hi :-) Someone build a parallel JTAG cable like the xilinx one ?
    96535: 06/02/06: Re: Tefzel or Kynar for PCB mods ?
    96629: 06/02/07: Re: latest XILINX WebPack is totally broken
    97628: 06/02/24: Re: The 95108 cpld is getting heated when connected by CRO
    97756: 06/02/27: Re: The 95108 cpld is getting heated when connected by CRO
    97830: 06/02/28: Re: The 95108 cpld is getting heated when connected by CRO
    98209: 06/03/07: Atmel using Xilinx FPGAs
    98544: 06/03/12: Re: LEON processor core
    99614: 06/03/27: Re: spartan FPGA with PLCC package
    101345: 06/04/29: Re: URGENT: Xilinx site
    101390: 06/04/30: Re: URGENT: Xilinx site
    101393: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
    102071: 06/05/10: Quartus II 6.0 available
    103280: 06/05/30: Re: Mains pick-up on I/O pins
    103780: 06/06/11: Re: R: xilinx cable 3 doesn't talk with pc,but test ok
    104010: 06/06/16: Re: Floppy to FPGA?
    104888: 06/07/08: Re: Fastest platform to run ISE?
    105464: 06/07/24: Re: ByteBlasterMV?
    107388: 06/08/27: Re: Spartan 3 and 5V input
    110656: 06/10/19: Re: Cheapest FPGA board to study VHDL on
    110754: 06/10/21: Re: Cheapest FPGA board to study VHDL on
    112129: 06/11/16: Re: Old Spartan-II, worth prototyping?
    112488: 06/11/23: Re: Altera configuration with microcontroller
    114975: 07/01/28: Re: Minimal design for xilinx?
    129905: 08/03/09: Re: XC3S50-4VQ100C fpga chip
    132719: 08/06/05: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
    132921: 08/06/10: Altera Quartus Web Edition 8.0 available
    133273: 08/06/23: =?windows-1252?Q?Re=3A_NVIDIA=92s_Tesla_T10P_Blurs_Some_Lines?=
    133417: 08/06/27: Re: Standard forms for Karnaugh maps?
    134271: 08/08/04: Why PCI9054 fails to assert pci interrupt when local interrupt input is pulled down? Any advice? Thanks
    135392: 08/09/30: $99 XMOS Dev kit
    135413: 08/10/01: Re: $99 XMOS Dev kit
    135420: 08/10/01: Re: $99 XMOS Dev kit
    135422: 08/10/01: Re: $99 XMOS Dev kit
    135452: 08/10/02: Re: $99 XMOS Dev kit
    135453: 08/10/02: Re: Gee Thanks Altera, I really enjoy having a break waiting on your
    135631: 08/10/10: XMOS XC-1 kits are shipping
    135639: 08/10/10: Re: XMOS XC-1 kits are shipping
    135640: 08/10/10: Re: XMOS XC-1 kits are shipping
    135653: 08/10/11: Re: XMOS XC-1 kits are shipping
    135656: 08/10/11: Re: XMOS XC-1 kits are shipping
    135658: 08/10/11: Re: XMOS XC-1 kits are shipping
    135661: 08/10/11: Re: XMOS XC-1 kits are shipping
    135664: 08/10/11: Re: XMOS XC-1 kits are shipping
    135667: 08/10/11: Re: XMOS XC-1 kits are shipping
    135668: 08/10/11: Re: XMOS XC-1 kits are shipping
    135670: 08/10/11: Re: XMOS XC-1 kits are shipping
    135687: 08/10/12: Re: XMOS XC-1 kits are shipping
    135697: 08/10/12: Re: XMOS XC-1 kits are shipping
    135704: 08/10/13: Re: XMOS XC-1 kits are shipping
    135742: 08/10/14: Re: XMOS XC-1 kits are shipping
    135765: 08/10/15: Re: XMOS XC-1 kits are shipping
    135766: 08/10/15: Re: $99 XMOS Dev kit
    135805: 08/10/16: Re: XMOS XC-1 kits are shipping
    135806: 08/10/16: Re: XMOS XC-1 kits are shipping
    135819: 08/10/16: Re: XMOS XC-1 kits are shipping
    136204: 08/11/05: Re: Xmos now shipping silicon
    136229: 08/11/07: Re: Tilera multicore replaces FPGA?
    136236: 08/11/07: Re: Tilera multicore replaces FPGA?
    136238: 08/11/07: Re: Tilera multicore replaces FPGA?
    136249: 08/11/07: Re: Tilera multicore replaces FPGA?
    136253: 08/11/07: Re: Tilera multicore replaces FPGA?
    136264: 08/11/07: Altera Quartus II 8.1
    136266: 08/11/07: Re: Altera Quartus II 8.1
    136298: 08/11/10: Re: Tilera multicore replaces FPGA?
    136670: 08/11/30: Re: make phone calls from fpga. is it possible?
    137914: 09/02/02: Re: Spartan-6
    137916: 09/02/02: Re: Spartan-6
    137917: 09/02/02: Re: byteblaster cloning
    137960: 09/02/03: Re: Terasic DE1 - expansion port power ratings
    146500: 10/03/20: Re: Xilinx only on Avnet now
    147521: 10/04/29: Re: Quartus II under Windows7?
    147837: 10/05/26: Using XMOS devices to replace FPGAs
    147843: 10/05/26: Re: Using XMOS devices to replace FPGAs
    148778: 10/08/20: Re: CE compliance testing
    149224: 10/10/09: Re: ANN: Multi-port register-file (memory) generator
    149225: 10/10/09: Re: Another Xilinx webpack download rant
    149354: 10/10/18: Re: Combined Microprocessor and FPGA
    150719: 11/02/06: Re: Looking for contractor for FPGA-based multiUART
    150782: 11/02/10: Re: Designing in Altium
    150809: 11/02/14: Re: Xilinx USB programming cable.
    150823: 11/02/15: Re: Xilinx USB programming cable.
    150824: 11/02/15: Re: Xilinx USB programming cable.
    150831: 11/02/15: Re: Xilinx USB programming cable.
    150867: 11/02/17: Re: Xilinx USB programming cable.
    150913: 11/02/21: Re: Xilinx USB programming cable.
    150914: 11/02/21: Re: Xilinx USB programming cable.
    151116: 11/03/08: Re: Does anyone have current contact details for Jerry D. Harthcock?
    152370: 11/08/12: Re: Help needed to emulate a microcontroller.
Leon de Boer:
    33825: 01/08/06: Re: RAM - VHDL - Altera,...
    39566: 02/02/13: Is Leonardo spectrum OEM version for Altera limited?
    39636: 02/02/15: Re: Is Leonardo spectrum OEM version for Altera limited?
    39639: 02/02/15: Re: Xilinx synthesis tools
    45672: 02/08/01: tone detection...
    48442: 02/10/18: ps/2 keyboard FSM code simplification....
    48652: 02/10/22: slow slew rate signal...
    48729: 02/10/24: Re: slow slew rate signal...
    48730: 02/10/24: Re: slow slew rate signal...
    48731: 02/10/24: Re: slow slew rate signal...
    48732: 02/10/24: Re: slow slew rate signal...
    48733: 02/10/24: Re: slow slew rate signal...
    48735: 02/10/24: Re: slow slew rate signal...
Leon Heller:
    1097: 95/04/27: Re: Altera new FLEX 10000 - a worlds first
    1229: 95/05/19: Re: Is anybody using FPGA's to do PCI interfaces?
    1411: 95/06/18: Re: MACH110 Uk distributer ?
    3774: 96/07/29: Re: Clearing security fuse on Lattice ispLSI2032?
    4633: 96/11/22: Re: Lattice ISP Question
    5065: 97/01/19: Re: Meta Assembler wanted
    5233: 97/01/31: Re: Steven K. Knapp - no such article
    6169: 97/04/21: Xilinx XC6216 availability?
    6298: 97/05/10: Anybody else using Trianus?
    6307: 97/05/13: Re: Cheap way to develop for FPGAs?
    6774: 97/06/26: Re: FPGA prototype board
    7227: 97/08/15: Re: ISP Stories
    7794: 97/10/16: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
    8484: 97/12/21: Re: Schmitt Trigger on ISP
    8690: 98/01/20: Re: bypass for 68 pin PLCC
    8885: 98/02/05: VHDL vs schematics, I vote for VHDL and this is why...
    9755: 98/04/03: Re: Smoking Crater in a Xilinx 3k FPGA
    10682: 98/06/10: Re: How about Lattice ispLSI?
    11263: 98/07/31: Re: How to use fpga do a programmable clock generator(50hz to 50k )
    15116: 99/03/08: Re: Looking for advice on CPLD's
    15438: 99/03/24: DIY Xilinx Download Cable
    15897: 99/04/20: Re: Question about Statechart
    16382: 99/05/19: Re: Is schmitt trigger possible with Xilinx 9536?
    16401: 99/05/20: Re: Is schmitt trigger possible with Xilinx 9536?
    16748: 99/06/06: Re: FPGA/ VHDL books: any stores in central London
    17655: 99/08/19: Re: map hang
    17857: 99/09/14: Re: Foundation Express Map abnormal error
    17972: 99/09/20: Re: xilinx software
    18007: 99/09/23: Re: Programming Spartan XL
    18116: 99/10/01: Re: Lattice ISP-cable
    18608: 99/11/03: Re: schematics ==> www
    19204: 99/12/06: Re: hobbyist friendly pld?
    19321: 99/12/14: Re: hobbyist friendly pld?
    19365: 99/12/16: Re: hobbyist friendly pld?
    20408: 00/02/09: Re: Can hobbyist buy altera in uk?
    20438: 00/02/10: Altera - pcpu symbol in mega_lpm library
    20470: 00/02/11: Re: Xilinx board
    20705: 00/02/18: Re: Suggested prototyping boards < $200
    21341: 00/03/17: Re: Is there a cheaper alternative to ByteblasterMV?
    21736: 00/03/30: Re: VGA interface and VHDL
    22013: 00/04/12: Re: Programator for xilinx
    22888: 00/05/30: Re: Search Spartan for small quantity
    23159: 00/06/16: Re: Xilinx config over parallel port ?
    23160: 00/06/16: Re: VHDL synthesis.
    23370: 00/06/23: Re: What tools do people use for Xilinx FPGAs?
    23819: 00/07/11: Re: JTAG headers
    23891: 00/07/14: Re: Altera's promises unfulfilled???
    23941: 00/07/17: Re: search free pcb programmer FPGA or CPLD
    23982: 00/07/19: Re: search free pcb programmer FPGA or CPLD
    23999: 00/07/20: DIY ByteBlaster equivalent
    24731: 00/08/17: Re: Distributor attitude !!
    25315: 00/09/06: Re: 3.3/2.5 voltage regulators
    26828: 00/10/31: Re: Spartan II ?
    27790: 00/12/08: Re: PLCC adapter
    28361: 01/01/10: Re: FPGA starter kit recommendations
    28540: 01/01/16: Re: Spartan programming error
    28736: 01/01/22: Re: UK parts
    28829: 01/01/25: Re: xilinx cpld
    29298: 01/02/13: Re: IEEE & Floating point
    32345: 01/06/24: Re: ALTERA CHIPS - ANYBODY WANT TO BUY A "FEW" ONLY?
    32586: 01/07/01: Xillinx WebPack PAR problem
    33323: 01/07/23: Flex 10K10 prototyping system
    33329: 01/07/23: Re: Maxplus II download sites
    33334: 01/07/23: Re: Altera ISP - JTAG
    33338: 01/07/23: Re: Flex 10K10 prototyping system
    33346: 01/07/23: Re: Flex 10K10 prototyping system
    33372: 01/07/24: Re: Flex 10K10 prototyping system
    33517: 01/07/29: Announcement: Flex 10K10 design kit
    33796: 01/08/05: Re: Where's SpartanXL in WebPack?
    34059: 01/08/13: Re: Digilab 10K10 resources / samples?
    34060: 01/08/13: Re: Xilinx webpack vs. Student edition software
    34282: 01/08/18: Re: connected "not connect" pins on Xilinx
    34322: 01/08/21: Re: connected "not connect" pins on Xilinx
    34480: 01/08/27: Re: System Requirements
    34951: 01/09/15: Altera 10K shortage
    35056: 01/09/19: Re: SquareRootRaisedCosine filter design
    35778: 01/10/17: Re: Recommended Newsgroup
    35985: 01/10/25: Re: CPLD with built-in oscillator?
    36100: 01/10/29: Re: Cloning someone else's IP core
    36257: 01/11/04: Altera download problem
    36336: 01/11/06: Re: Altera download problem
    36357: 01/11/07: Re: FPGA suppliers for hobbyists?
    36385: 01/11/08: Re: Xilinx machine readable package info
    36386: 01/11/08: Re: Xilinx machine readable package info
    36736: 01/11/18: Re: WebPACK 4.1 under Win95
    36787: 01/11/20: Re: Modelsim
    36788: 01/11/20: Re: Modelsim
    37302: 01/12/06: Re: where is designed FPGA for apple II computer...?
    38357: 02/01/12: Re: speech recognition - active noise cancellation
    38373: 02/01/13: Re: speech recognition - active noise cancellation
    38531: 02/01/16: Re: Audio time delay circuit
    38565: 02/01/17: Re: Audio time delay circuit
    39110: 02/01/31: Re: Altera support sites
    40841: 02/03/16: Re: High speed clock routing
    43740: 02/05/31: Re: Engineering Samples for free?
    44232: 02/06/14: Re: Can someone who is not a student use Xilinx Foundation 2.1i Student Edition?
    44266: 02/06/15: Re: TTL library in Xilinx?
    44268: 02/06/15: Re: TTL library in Xilinx?
    44379: 02/06/18: Re: Internal oscillator in CPLD?
    44407: 02/06/19: Xilinx Webpack Fatal Error (0031)
    44510: 02/06/21: Re: Xilinx's 4.1i's Lastest webpack
    44530: 02/06/22: Re: Xilinx's 4.1i's Lastest webpack
    44702: 02/06/27: Re: 32KHz oscilator in CPLD
    45580: 02/07/27: Re: can 555 be used as clock input to cplds
    45770: 02/08/05: Re: modelsim XE starter
    46017: 02/08/14: Re: transputers
    46038: 02/08/15: Re: Xilinx tools: which one? Esp. schematic
    46068: 02/08/16: Re: transputers
    46852: 02/09/10: Re: How to make Altera UPX board self bootable?
    46853: 02/09/10: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
    46861: 02/09/10: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
    47311: 02/09/23: Altera Cyclone 'FPGA'
    47450: 02/09/25: Re: FPGA programming via microcontroller
    48259: 02/10/15: DIY Xilinx Parallel Cable III
    48265: 02/10/15: Re: programming the FPGA by a microcontroller
    48334: 02/10/16: Re: DIY Xilinx Parallel Cable III
    48420: 02/10/17: Re: DIY Xilinx Parallel Cable III
    48422: 02/10/17: Re: Hobbyist FPGA
    48580: 02/10/21: Re: Webpack download problem
    48605: 02/10/21: Re: Buy Small quantities
    49218: 02/11/05: Re: WebPACK 5.1 SP2
    49283: 02/11/07: Re: Instruction sets to implement instruction sets
    49641: 02/11/18: Re: programming Altera EPC1
    49795: 02/11/21: Re: XCS-05-3PC84 and XCS10-3PC84 Question
    49853: 02/11/22: Re: XCS-05-3PC84 and XCS10-3PC84 Question
    50014: 02/11/28: Re: Leon Softcore and Altera
    50636: 02/12/15: Re: Quartus does not start on Windows ME
    50686: 02/12/17: Re: neural networks
    50725: 02/12/18: Errors in Xilinx pinout spreadsheet
    50892: 02/12/22: Re: CPLD ISP cables (newbie question)
    55414: 03/05/07: Re: looking for I/Q mixers/modulators for TX and RX
    55547: 03/05/12: Re: Xilinx : Tools
    55801: 03/05/20: Re: smallest embedded cpu.
    55868: 03/05/22: Re: Programming Altera EPC1 and EPC1441
    55960: 03/05/25: Re: Newbie CPLD question
    55975: 03/05/25: Re: Newbie CPLD question
    56010: 03/05/27: Re: Newbie CPLD question
    56018: 03/05/27: Re: Xilinx Spartan download with Parallel III cable
    56069: 03/05/28: ANN: Getting started with programmable logic
    56261: 03/06/02: Re: Xilinx and programind mode !
    56586: 03/06/10: Re: how to get into xilinx ftp?
    56786: 03/06/16: Re: xilinx webpack programming
    56960: 03/06/19: Re: Altera FPGA
    57132: 03/06/24: Re: MIPS instruction set?
    57133: 03/06/24: Re: Xilinx ISE Webpack on Linux?
    57573: 03/07/02: Re: Looking for DIMM format FPGA board
    57601: 03/07/02: Re: Looking for DIMM format FPGA board
    57904: 03/07/09: Re: Rant mode ON
    58120: 03/07/15: Re: JTAG standard connector
    58253: 03/07/18: Re: External crystal oscillator for Spartan IIE
    59342: 03/08/15: Re: Free VHDL Simulator
    59731: 03/08/27: WebPack ISE and Norton Anti-virus
    60157: 03/09/05: Re: Original (5V) Xilinx Spartan ?
    60210: 03/09/08: Re: PIC Programming Help
    60593: 03/09/17: Re: Xilinx source dragonsources
    62669: 03/11/04: Re: Vendor supplied symbol/part models?
    62697: 03/11/05: Re: FPGA Prototyping Board
    62726: 03/11/05: Re: FPGA Prototyping Board
    64159: 03/12/18: Spartan3 availability
    64160: 03/12/18: Re: www.fpga-faq.com
    64176: 03/12/19: Re: Spartan3 availability
    64198: 03/12/19: Re: Spartan3 availability
    64204: 03/12/19: Re: Soldering of FPGAs
    64289: 03/12/25: Re: a question about flex10 configure
    64570: 04/01/08: Re: Wierd problem with Xilinx XC9572 ID code
    64888: 04/01/15: Re: yo, Mr. FPGA Engineer
    65378: 04/01/27: Re: isp Cable for Lattice CPLD
    65602: 04/02/03: Re: ByteBlaster fails on Windows 98
    65659: 04/02/04: Re: Spartan 3 Availability again
    65661: 04/02/04: Re: Spartan 3 Availability again
    65707: 04/02/05: Re: ByteBlaster fails on Windows 98
    65725: 04/02/05: Re: ByteBlaster fails on Windows 98
    66034: 04/02/11: Spartan-3 shipping, or perhaps not!
    66083: 04/02/12: Re: How many PCB layers ?
    66637: 04/02/24: Re: Spartan 2 XC2S400E and XC2S600E availabillity
    67420: 04/03/11: Re: what exactly means fanout ?
    67477: 04/03/12: ANN: new Pulsonix version 3 PCB software released
    67485: 04/03/12: Re: ANN: new Pulsonix version 3 PCB software released
    67523: 04/03/13: Re: ANN: new Pulsonix version 3 PCB software released
    67532: 04/03/13: Re: ANN: new Pulsonix version 3 PCB software released
    67536: 04/03/13: Re: ANN: new Pulsonix version 3 PCB software released
    67545: 04/03/14: Re: ANN: new Pulsonix version 3 PCB software released
    67610: 04/03/15: Re: low power Oscillator for Xilinx CoolrunnerII
    67939: 04/03/23: Re: Apparent Altera Cyclone JTAG problem
    68445: 04/04/05: Re: ATMEL support / Are they serious ?
    68509: 04/04/07: Cyclone and ByteBlasterMV?
    68533: 04/04/07: Re: Cyclone and ByteBlasterMV?
    68543: 04/04/07: Re: Cyclone and ByteBlasterMV?
    68551: 04/04/07: Re: Cyclone and ByteBlasterMV?
    68565: 04/04/08: Re: Cyclone and ByteBlasterMV?
    68705: 04/04/14: Re: Cyclone and ByteBlasterMV?
    68751: 04/04/16: Re: Altera flex 10k library component doubt
    68770: 04/04/17: Protel 2004 for FPGA design?
    68775: 04/04/17: Re: dumb question CPLD or FPGA
    68785: 04/04/18: Re: Altera flex 10k library component doubt
    68909: 04/04/21: Re: cpld in plcc84 package
    69019: 04/04/25: Altera ByteBlaster II schematic
    69036: 04/04/26: Re: Altera ByteBlaster II schematic
    69043: 04/04/26: Re: Altera ByteBlaster II schematic
    69139: 04/04/28: Re: Altera ByteBlaster II schematic
    69448: 04/05/11: Re: Effects of moisture on CPLD
    69461: 04/05/11: Re: Effects of moisture on CPLD
    69879: 04/05/23: Re: Altium FPGA board
    69961: 04/05/25: Re: CPLD Board design newbie questions
    70731: 04/06/25: Re: DPLL in CPLD
    70855: 04/06/30: Xilinx $99 Spartan-3 kit
    70895: 04/07/01: Re: Compact FPGA Board?
    71284: 04/07/13: Re: new Lattice FPGAs vs Cyclone and SpartanIII
    71403: 04/07/17: Re: Compact FPGA Board?
    71506: 04/07/20: Re: Altera FPGA's
    71546: 04/07/21: Re: Cheap FPGA's
    71566: 04/07/22: Re: Resources on FPGA wanted...
    71616: 04/07/25: Re: Image export from Quartus?
    71629: 04/07/26: Re: 1GHz FPGA counters
    71663: 04/07/27: Re: New WinFilter Digital Filter design freeware tool release available.
    71687: 04/07/27: Re: On-Chip Oscillator
    71707: 04/07/28: Re: FPGA vs CPLD
    71827: 04/08/01: Re: SPARTANII pinout table mysteries ???
    72083: 04/08/08: Re: ABEL support for legacy chips
    72208: 04/08/11: Re: FPGA/CPLD from logic diagram?
    72493: 04/08/20: Re: GAL,PAL,PLD, CPLD,FPGA
    72654: 04/08/27: Re: How to Figure out EPLD can be socketed or not!
    74010: 04/10/02: Re: How to generate a signal on Xilinx Spartan II
    72851: 04/09/05: Re: PCI Noise
    72854: 04/09/05: Re: PCI Noise
    72909: 04/09/08: Re: Quartus2 V4.1 SP1
    72910: 04/09/08: Re: Quartus2 4.1 SP1 Hangs
    72919: 04/09/08: Re: Quartus2 V4.1 SP1
    73202: 04/09/15: Re: problem with ALtera CPLD
    73344: 04/09/20: Re: Where are the Cyclones2
    74959: 04/10/22: Altera Cubic Cyclonium
    75307: 04/11/02: Re: "frying" FPGAs
    74691: 04/10/16: Re: ModelSim
    74850: 04/10/20: Re: Anyone routing signals between balls in FBGA?
    75607: 04/11/11: Re: Xilinx Tshirts in football package.....
    75882: 04/11/18: Re: Newbie FPGA Qs
    75958: 04/11/20: Re: FPGA development board
    75974: 04/11/21: Re: Altera chip identification
    76114: 04/11/25: Re: Hierarchical PCB design.
    76504: 04/12/04: Re: PLCC84
    77072: 04/12/21: Re: low cost Altera MAX II development kit with more I/O pins?
    77078: 04/12/21: Re: low cost Altera MAX II development kit with more I/O pins?
    77091: 04/12/22: Re: low cost Altera MAX II development kit with more I/O pins?
    77098: 04/12/22: Re: low cost Altera MAX II development kit with more I/O pins?
    77100: 04/12/22: Re: low cost Altera MAX II development kit with more I/O pins?
    77250: 05/01/01: Re: Getting started with Xilinx CPLD
    78323: 05/01/29: Re: Altera subscriptions deleted?
    78327: 05/01/29: Re: Altera subscriptions deleted?
    78645: 05/02/04: Re: Spartan-3 Starter Kit supplier in the UK?
    78809: 05/02/08: Re: SimmStick FPGA module
    79150: 05/02/15: Re: Cyclone clock
    79169: 05/02/15: Re: Cyclone clock
    80181: 05/03/02: Re: Xilinx ISE history?
    80196: 05/03/02: Re: PLL code
    80514: 05/03/07: Re: Asynchronous processor !?!
    81281: 05/03/21: Re: TPS75003 for FPGAs
    82148: 05/04/07: Interesting article about Xilinx FPGAs in the new Cray
    83818: 05/05/07: Re: how can i add my math library libm.a in my project
    84794: 05/05/27: Xilinx Parallel Cable III flying lead repair
    84922: 05/06/01: Spartan 3 kit FPGA configuration problem
    84924: 05/06/01: Re: Spartan 3 kit FPGA configuration problem
    84992: 05/06/02: Re: Basics FPGA
    85137: 05/06/06: Re: Xilinx + ModelSim XE Linux
    85159: 05/06/06: Spartan 3 Starter kit group formed
    85164: 05/06/06: Re: Spartan 3 Starter kit group formed
    85165: 05/06/06: Re: Spartan 3 Starter kit group formed
    85249: 05/06/07: Re: Pissed off with Xilinx - Spartan 3
    85274: 05/06/07: Re: Pissed off with Xilinx - Spartan 3
leon qin:
    52929: 03/02/26: Re: New release of Xilinx ISE tools (5.2)
    53536: 03/03/15: Re: Cypress Users Anyone?
    54087: 03/04/02: altera device config problem
    54568: 03/04/14: Xilinx has released SpartanIII
    55902: 03/05/23: New version,Low Speed
    56006: 03/05/27: Can I implement a NIOS cpu in EP1C6
    56059: 03/05/28: Cyclone doesn't non-clock rom?
    56061: 03/05/28: Re: Can I implement a NIOS cpu in EP1C6
    56332: 03/06/03: Stapl Player vs. SVF Player
    57175: 03/06/25: Re: Quartus II for Linux
    57695: 03/07/04: Re: Quartus II 3.0 Release & Web Edition Download Links
    58214: 03/07/17: Re: Xilinx ECS Schematic Entry
    59286: 03/08/14: Re: Limitations of Quartus II V3.0 Web
    60243: 03/09/09: Re: Programming Xilinx CPLD under linux
    60249: 03/09/09: Re: Programming Xilinx CPLD under linux
    60256: 03/09/09: Re: Programming Xilinx CPLD under linux
Leon Qin:
    32194: 01/06/18: Re: Pin locking in Maxplus2
    32202: 01/06/19: Re: Pin locking in Maxplus2
    34715: 01/09/04: LPM_FIFO_DC
    34731: 01/09/05: Re: LPM_FIFO_DC
    39804: 02/02/19: Re: Faster designs
    39805: 02/02/20: Re: FPGA choices and questions
    40266: 02/03/04: Is there a ver 7.1 of Sunplify?
    40642: 02/03/12: Where can I get a Ebbok <Writting Testbench>>
    40860: 02/03/16: Looking for EBook?
    40876: 02/03/17: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
    41252: 02/03/23: QuartusII 2.0!!!!!
    41253: 02/03/23: Re: Looking for EBook?
    41557: 02/04/01: [HELP] Can't Install Altera QuartusII 2.0 SP1
    41591: 02/04/02: Re: [HELP] Can't Install Altera QuartusII 2.0 SP1
    41605: 02/04/03: Re: [HELP] Can't Install Altera QuartusII 2.0 SP1
    42586: 02/04/28: Where can I get basic knowledge for LFSR and Module-2 theory
    45550: 02/07/25: Can Synplify7.1 run well on RedHat 7.2?
    46174: 02/08/21: What's wrong with clearLogic?
    47091: 02/09/17: Has ISE 5.1i shipped?
    47266: 02/09/21: Xilinx will not provid free ISE Allanice 5.1i?
    47386: 02/09/24: Can I implement a PCI Master in a ACEX EP1k30-3 FPGA?
Leon Stok:
    7777: 97/10/14: Int Workshop on Logic Synthesis 1998
Leon Vicente Miravet Segarra:
    8191: 97/11/26: problems with xc4000
Leon Viveros:
    76296: 04/11/29: VIRTEX II PRO FPGA - PC URGENT
Leon Willett:
    32375: 01/06/25: 2500ad 68HC05 assembler
    32407: 01/06/26: 2500AD 68HC05 assembler
Leonard Dieguez:
    68137: 04/03/27: Re: RocketIO 8/10b bypass
leonardopsantos:
    83924: 05/05/09: Impact Kernel 2.6
    84419: 05/05/18: re:Xilinx tools on Linux
<leong@sapura.po.my>:
    10030: 98/04/22: Re: Ask for / Discuss which FPGA & ASIC tools best buy
Leonid Shvarzberg:
    16738: 99/06/04: Re: Altera EPC1 PROM + Data IO ChipWriter
    26421: 00/10/16: Re: Altera Internal Error
    30515: 01/04/12: Re: Modlesim5.5
leonqin:
    81272: 05/03/20: Re: Spartan 3E vs. Cyclone2
    81890: 05/04/03: Re: PLX-9656 Controller interface
Leopold Faschalek:
    28260: 01/01/04: Re: Jedec to tms/tdi wiggles
Leow Yuan Yeow:
    96647: 06/02/08: DK: Interfacing Handel C and VHDL
    96694: 06/02/08: vhdl to edif
    96706: 06/02/09: Re: vhdl to edif
    96734: 06/02/09: Re: vhdl to edif
    98856: 06/03/17: Instantiating addsub, comparators in Xilinx
    98972: 06/03/18: Re: Instantiating addsub, comparators in Xilinx
    98975: 06/03/18: Re: Instantiating addsub, comparators in Xilinx
    99175: 06/03/21: Re: Instantiating addsub, comparators in Xilinx
    99183: 06/03/21: Re: Instantiating addsub, comparators in Xilinx
Leprechaun:
    12019: 98/09/24: strange problem of 4028XL
    12144: 98/10/01: Re: strange problem of 4028XL
    12786: 98/10/29: Question on setting M0, M1, M2 for XC4028XL
    13012: 98/11/11: connecting 2 FPGA together
    13093: 98/11/16: programming EPROM
    13284: 98/11/24: Re: connecting 2 FPGA together
    14866: 99/02/21: connecting 2 FPGA
<lerbacattivanonmuoremai@gmail.com>:
    111121: 06/10/29: image processing
Leroy Davis:
    22731: 00/05/20: Re: Printed magazines
Leroy Tanner:
    73465: 04/09/22: How To Synchronize FPGAs
    73576: 04/09/24: Re: How To Synchronize FPGAs
    75618: 04/11/11: multiplexer / serdes
Les Bartel:
    2312: 95/11/19: Re: [q][Reverse Engineering Protection]
Les Cargill:
    150477: 11/01/24: Re: Xilinx news
    152880: 11/10/29: Re: FPGA development
    154148: 12/08/21: Re: recruit FPGA design engineer in Scotland
    154158: 12/08/22: Re: recruit FPGA design engineer in Scotland
    154159: 12/08/22: Re: recruit FPGA design engineer in Scotland
    154160: 12/08/22: Re: recruit FPGA design engineer in Scotland
    154173: 12/08/27: Re: recruit FPGA design engineer in Scotland
    154174: 12/08/27: Re: recruit FPGA design engineer in Scotland
    154478: 12/11/11: Re: What the advantages and disadvantages between distributed arithmetic
    154480: 12/11/12: Re: What the advantages and disadvantages between distributed arithmetic
    154657: 12/12/12: Re: Where to move for an embedded software engineer.
    155336: 13/06/23: Re: New soft processor core paper publisher?
    155347: 13/06/24: Re: New soft processor core paper publisher?
    155349: 13/06/24: Re: New soft processor core paper publisher?
    155448: 13/06/28: Re: New soft processor core paper publisher?
    155449: 13/06/28: Re: New soft processor core paper publisher?
    155452: 13/06/28: Re: New soft processor core paper publisher?
    155462: 13/06/29: Re: New soft processor core paper publisher?
    155463: 13/06/29: Re: New soft processor core paper publisher?
    155464: 13/06/29: Re: New soft processor core paper publisher?
    155465: 13/06/29: Re: New soft processor core paper publisher?
    155472: 13/06/30: Re: New soft processor core paper publisher?
    155473: 13/06/30: Re: New soft processor core paper publisher?
    155483: 13/07/01: Re: New soft processor core paper publisher?
    155484: 13/07/01: Re: New soft processor core paper publisher?
    155493: 13/07/01: Re: New soft processor core paper publisher?
    155517: 13/07/14: Re: New soft processor core paper publisher?
    155519: 13/07/14: Re: New soft processor core paper publisher?
    155531: 13/07/15: Re: New soft processor core paper publisher?
    155533: 13/07/15: Re: New soft processor core paper publisher?
    156309: 14/02/13: Re: Monostable multivibrator
    156544: 14/04/18: Cheap spec an using an RTL-SDR
    157079: 14/09/23: Re: Some newbe questions.
    157286: 14/11/17: Re: disadvantages of inferring latches
    157297: 14/11/17: Re: disadvantages of inferring latches
    157310: 14/11/18: Re: disadvantages of inferring latches
Les Donaldson:
    15633: 99/04/04: Application Consulting Engineer (ACE)
    15634: 99/04/04: Application Consulting Engineer (ACE)
Les Hughes:
    2785: 96/02/07: Re: Xilinx FPGA's with Mentor Tools?
    2825: 96/02/13: Re: PIC16C71 CORE for XC4000 ?
    2902: 96/02/27: Re: Xilinx FPGA's with Mentor Tools?
Les S Brodie:
    30710: 01/04/25: Re: SPARTAN vs VERTEX
    31325: 01/05/18: Re: Xilinx Service Pack 8 Now Available
Lesec Patrice:
    11849: 98/09/14: PLEASE HELP :ALTERA & VHDL & LPM
Leslie Yip (/ Loui):
    16856: 99/06/15: Re: Digital filters in VHDL/FPGA
    16857: 99/06/15: delay line in FPGA / ASIC with VHDL
    16858: 99/06/15: Re: delay line in FPGA / ASIC with VHDL
    18153: 99/10/04: APEX device
    18308: 99/10/14: APEX
    18709: 99/11/09: Problems in Viewlogic's Workview office
<leslie.yip@asmpt.com>:
    10009: 98/04/22: Ask for / Discuss which FPGA & ASIC tools best buy
    10010: 98/04/22: Ask for / Discuss which FPGA & ASIC tools best buy
    10029: 98/04/22: Re: Ask for / Discuss which FPGA & ASIC tools best buy
    10048: 98/04/24: Re: Ask for / Discuss which FPGA & ASIC tools best buy
    10051: 98/04/24: Re: Ask for / Discuss which FPGA & ASIC tools best buy
    10368: 98/05/15: Motion Controller design for DC motor wanted
    10399: 98/05/16: Design/document/reference of motion encoder interface wanted
    10715: 98/06/12: Re: TESTBENCH
    10774: 98/06/18: Re: VHDL testbench in Maxplus2
    10992: 98/07/09: Re: Where to find gate-count information on some implementations?
    11113: 98/07/20: How to write a VHDL counter of up & down
    11137: 98/07/21: Any VHDL counter with up & down functions
    11165: 98/07/22: Re:Add info-How to write a VHDL counter of up & down
    11166: 98/07/22: Re:Add info-How to write a VHDL counter of up & down
    11256: 98/07/31: Re: TRISTATE in FPGA
    11355: 98/08/06: Re: [Q] motor control onto an FPGA
    11297: 98/08/03: How to write a VHDL counter for motion encoder
    12556: 98/10/16: What's wrong at this Address decoder?
    12592: 98/10/19: More: What's wrong at this Address decoder?
    12603: 98/10/20: Re: More: What's wrong at this Address decoder?
    12864: 98/11/03: Re: USB Joypad vhdl source code
    13046: 98/11/13: Re: VHDL project
    13186: 98/11/19: Re: Looking for a good documentation on FPGA
    13209: 98/11/20: Re: Example of clock circuit needed !
    13210: 98/11/20: Re: Synthesizeablel fifo
    14189: 99/01/19: Re: Hard porting to FPGA Express
    15155: 99/03/10: VLSI Design on random number genrator
<lesnleung@gmail.com>:
    91923: 05/11/16: UART CORE FOR NIOS
Lessard:
    26420: 00/10/15: business opportunity
Leszek:
    66155: 04/02/13: APEX fit problem
    67465: 04/03/12: Re: APEX fit problem
LET:
LEULATsM:
    28211: 00/12/30: <!-- To use a different cobrand, make sure you have a template for it in /parts/cobrand/ -->
Leumann Robert:
    24056: 00/07/25: Spartan II Pin
    24125: 00/07/27: Spartan-II power consumption
<leumig78@hotmail.com>:
    132658: 08/06/04: EAPR and EDK 9.1.02i
Lev Razamat:
    9712: 98/04/01: Re: Digital PLL's or Manual Synching?
    9727: 98/04/02: Re: Altera Bitblaster or Byteblaster
    10049: 98/04/24: Re: Altera 10K20 Configuration problem
    10125: 98/04/28: Re: FPGA input data rate limitations?
    10124: 98/04/28: Re: FPGA input data rate limitations?
    10538: 98/05/28: Re: Altera FLEX8k configuration problem
    10570: 98/06/01: Re: Altera FLEX8k configuration problem
    10835: 98/06/24: Re: How to Double Clk Freq in the FPGA design
    11030: 98/07/13: Reed-Solomon encoding
    14663: 99/02/09: Re: AHDL & VHDL
    14664: 99/02/09: Re: Need Help! clock multiplier!
    15422: 99/03/23: Re: ALTERA Byteblaster configuration for DOS and LINUX
    58667: 03/07/30: ALTERA Byte BlasterII
Leveridge & Friedman INC:
    9906: 98/04/12: ASIC or FPGA designers needed in Phoenix.
Levy Lazarre:
    7852: 97/10/23: Upgrade to Alliance 3.0 CAD VLSI software
Lewin A.R.W. Edwards:
    24083: 00/07/26: Re: tutorial on configurable system-on-chip design is available
    32326: 01/06/22: Re: SmartMedia controller available as CPLD/FPGA core?
    32330: 01/06/23: Re: SmartMedia controller available as CPLD/FPGA core?
    50470: 02/12/11: Re: Some boards for designers...
    66174: 04/02/13: Re: RFC: ARM+FPGA tiny board
    73628: 04/09/27: Re: embedded linux on FPGA?
Lewin A.R.W. Edwards (Despammed):
    40223: 02/03/02: Re: share two months salary with you if you have job information
Lewis:
    32176: 01/06/18: FPGA Boards
    32206: 01/06/19: Re: FPGA Boards
    34357: 01/08/22: Re: FPGA MP3 decoder
    39337: 02/02/06: Re: Preliminary timing simulation (Leonardo SDF => ModelSim)
lewis chen:
    16973: 99/06/22: Re: Altera EPC1 replacement?
    17154: 99/07/05: Re: Altera 10K prices
Lewis, Mike:
    17335: 99/07/21: Re: Synplify - Optimizing Out A Bus
    17478: 99/07/30: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
lexluthor:
    123935: 07/09/07: Re: ?Nios II?How Can I Find Out These Functions ?
    123937: 07/09/07: [Nios II] How does the PIO Core generate a interrupt?
    123962: 07/09/07: Re: How does the PIO Core generate a interrupt?
    123963: 07/09/07: Nios II -- Why does this error occur ?
    124103: 07/09/12: [Nios II] How fast the cpu in Nios II can reach in the Cycone ?
lexuancong:
    152932: 11/11/02: draw lines, circles, squares on FPGA by mouse and display on VGA (
Leyton Collins:
    12380: 98/10/10: Xilinix Foundation Install?
LFB3:
    4847: 96/12/20: $$$$$$$$$ HONEST, LEGAL, EASY CASH $$$$$$$
<lfcoug@sssdfdf.org>:
lfforth at free dot fr:
    68157: 04/03/28: Re: Strange FPGA design - part working with divided clock frequency
lgh:
    81347: 05/03/22: changing DDR2 pin LOC on UCF generated by MIG for virtex4
    81416: 05/03/23: re:changing DDR2 pin LOC on UCF generated by MIG for virtex4
lgs23:
    120153: 07/06/01: xilinx parallel cable troubles
    120264: 07/06/04: Re: xilinx parallel cable troubles
    120336: 07/06/05: Re: xilinx parallel cable troubles
Li GenZhu:
    65586: 04/02/02: A problem about GAL26V12
    65640: 04/02/03: Re: A problem about GAL26V12
Liam Maguire:
    1477: 95/06/27: help contact Metalithic Systems Inc
liandongzhang:
    42323: 02/04/20: Some Questions about Pci configuration.
Liang Yang:
    57875: 03/07/08: Re: std_logic_vector type port doesn't work after synthesis.
Liang-Kai Wang:
    53333: 03/03/11: question to generate three clock
Liao Jirong:
    51099: 03/01/01: Any Xilinx Design Language(.xdl) document?
    51107: 03/01/02: Any Xilinx Design Language(.xdl) document?
    53279: 03/03/10: Time constraint of bit-stream file
<liaobojie@gmail.com>:
    91231: 05/11/01: Spartan IIE VHDL inout port bidirectional bus problem.
license_rant_master:
    70885: 04/07/01: *RANT* Ridiculous EDA software "user license agreements"?
Liceo Herrera-Quick3:
    10220: 98/05/05: STUDENT RESIDENCE IN MADRID
<lichaoji@gmail.com>:
    135879: 08/10/20: Looking for a FPGA board for starter
lichau:
    60386: 03/09/11: Re: CMOS camera w/ USB2 -- crazy?
life.is.best:
    127312: 07/12/17: Xilinx Evaluation boad ISE sample project
    128119: 08/01/15: Virtex-4 Embedded Tri-Mode Ethernet MAC Wrapper v4.4. 10base-T
    130049: 08/03/14: ICMP checksum
    146792: 10/03/28: desgin suspended
Ligeti:
    119496: 07/05/21: Re: weird PACE Error, not one google result
light:
    102282: 06/05/13: filter design
    102414: 06/05/15: Re: filter design
<light@house.com>:
    8053: 97/11/11: - The Lighthouse of Your Guardian Angel on the Wishing Tower. -
<liguosu@gmail.com>:
    140445: 09/05/13: how to choose the FPGA/DSP coprocessor system architecture
    140447: 09/05/13: Re: how to choose the FPGA/DSP coprocessor system architecture
<lijia21cn@gmail.com>:
    138301: 09/02/13: ERROR:Map:11 - serdes_4b_1to7_wrapper symbol "rx0" - more than one
    138408: 09/02/20: Re: ERROR:Map:11 - serdes_4b_1to7_wrapper symbol "rx0" - more than
Lijo:
    52441: 03/02/10: Synthesis Scripts
    53875: 03/03/26: How to avoid this Latch
LIJO:
    53280: 03/03/10: Timing Simulation Glitches
    53370: 03/03/12: RESET --- Synchronous Vs Asynchronous
    53371: 03/03/12: DRC/ LVS
    54143: 03/04/03: Gatecount in which basic gate
    54372: 03/04/09: prelayout and post layout frequencies
    55307: 03/05/03: Cadence NCSIm Vs NCSim Desktop Vs Modelsim Vs VCS
    55658: 03/05/15: Moore Vs Mealy machine ..
    55802: 03/05/20: what are DCMs in FPGA
    58562: 03/07/26: Multi Cycle path and False paths
lijun2611:
    16319: 99/05/15: How can I get a ISA/PCI BUS model?
lik:
    87761: 05/07/31: some virtexII clock pads are useless??
Like Learn:
    153521: 12/03/23: Re: Virtex6HXT PCIe 8X Gen2 timing closure problem
LilacSkin:
    117914: 07/04/13: PLB Master to communicate with the BRAM
    117999: 07/04/16: PLB Master
    118004: 07/04/16: Re: PLB Master
    118007: 07/04/16: Re: PLB Master
    118017: 07/04/16: Re: PLB Master
    118055: 07/04/17: Re: PLB Master
    118059: 07/04/17: Re: PLB Master
    118074: 07/04/17: Re: PLB Master
    118752: 07/05/03: PLB master with burst mode
    118756: 07/05/03: Re: PLB master with burst mode
    119493: 07/05/21: SelectIO banking rules
    119524: 07/05/21: Re: SelectIO banking rules
    121309: 07/07/02: 32bit multiplication in a PowerPC405 of a VirtexIIPro
    121733: 07/07/12: ASM within C code in a PPC405 of VIRTEX II Pro
    121806: 07/07/13: Re: ASM within C code in a PPC405 of VIRTEX II Pro
    121835: 07/07/13: Re: ASM within C code in a PPC405 of VIRTEX II Pro
    121948: 07/07/16: Re: ASM within C code in a PPC405 of VIRTEX II Pro
    123209: 07/08/20: MCS -> BIT
    123211: 07/08/20: Re: MCS -> BIT
    123212: 07/08/20: Re: MCS -> BIT
    123758: 07/09/04: Import Xilinx SDK Project in Wind River Workbench
    128645: 08/02/01: Xilinx timming analysis
    128689: 08/02/04: OFFSET In and hold time
    128716: 08/02/05: A way to limit the data path delay
    128731: 08/02/05: Re: A way to limit the data path delay
    128938: 08/02/11: Unsigned to signed vector.
    128944: 08/02/11: Re: Unsigned to signed vector.
    128946: 08/02/11: Re: Unsigned to signed vector.
    128948: 08/02/11: Re: Unsigned to signed vector.
    129979: 08/03/12: VME 2 Ghz clock generator
    129984: 08/03/12: Re: VME 2 Ghz clock generator
lilaisgr8:
    152536: 11/09/08: facing problem in creating ..BMM file with RAMB18X2
Liliana Dinoia:
    5351: 97/02/10: FREE CREDIT CARD NUMBER
Lillian Chow:
    10007: 98/04/21: Cyberromance survey
LIM JAE-HWAN:
    23000: 00/06/08: I don't know "simulator mode"
Lim Sung-taek:
    14455: 99/01/30: Q:Installing Xilinx F1.4 license server
limours:
    79300: 05/02/17: Re: ProAsic3 (PA3)
Lin Feng Ming:
    1473: 95/06/27: Re: The "InOut" Port mode in the Xilinx FPGA
Lin MuIin:
    81241: 05/03/20: DATA2MEM, how do I get the ELF file?
    81252: 05/03/20: Re: DATA2MEM, how do I get the ELF file?
    81288: 05/03/21: Parallel port to Virtex 2 level converter chip, anyone?
    81289: 05/03/21: Re: Parallel port to Virtex 2 level converter chip, anyone?
lina:
    83874: 05/05/09: how to add library
    84919: 05/06/01: How to speed up float computing
    84925: 05/06/01: Re: How to speed up float computing
    84965: 05/06/01: How to speed up float computing--continued
    84986: 05/06/02: some mistakes with EDK7.1i
    89475: 05/09/15: flash on P160 Module
Lina:
    55452: 03/05/08: Re: SystemC and Virtex-E
    84018: 05/05/11: how to use libm.a and libc.a
    84067: 05/05/11: How to use XMD debugger
    84250: 05/05/16: why is it wrong with "sin"?
    85026: 05/06/02: Re: some mistakes with EDK7.1i
    85127: 05/06/05: how to use FPU with EDK7.1i
    89165: 05/09/06: to use flash on the fpga board
    89213: 05/09/07: Re: to use flash on the fpga board
    92688: 05/12/04: programming flash memeory
    92700: 05/12/05: Re: programming flash memeory
Linas Petras:
    79996: 05/02/28: Update EDK 6.1 to EDK 6.3
    80065: 05/03/01: Re: virtex4 virtex-4 FX eval board
    94470: 06/01/12: Re: Samples
    94469: 06/01/12: Re: Webpack 8.1 device support
    120119: 07/06/01: CoreGen Issues ??
<lincoln@mailinator.com>:
    75249: 04/10/30: Re: Xilinx Platform Studio- I don't get C source code error messages.
Linda Boyd:
    4118: 96/09/13: COURSES: High Level Design Using VHDL, Beaverton, Oregon
    4117: 96/09/13: COURSES: High Level Design Using Verilog, Beaverton, Oregon
    4317: 96/10/14: COURSES: High Level Design Using Verilog, Beaverton, Oregon
    4316: 96/10/14: COURSES: High Level Design Using VHDL, Beaverton, Oregon
    5474: 97/02/19: COURSE: High Level Design Using Verilog, Beaverton, Oregon
    5473: 97/02/19: COURSE: High Level Design Using VHDL, Beaverton, Oregon
    5538: 97/02/23: COURSE: High Level Design Using VHDL, Beaverton, Oregon
    5539: 97/02/23: COURSE: High Level Design Using Verilog, Beaverton, Oregon
    5737: 97/03/11: COURSE: High Level Design Using VHDL, March 31 - April 4
    6366: 97/05/19: Qualis Public Verilog training course schedule: Fall '97
    6367: 97/05/19: Qualis Public VHDL training course schedule: Fall '97
    6608: 97/06/05: Qualis Verilog Training
    6609: 97/06/05: Qualis VHDL Training
    6743: 97/06/23: Qualis Verilog Training
    6744: 97/06/23: Qualis VHDL Training
    7039: 97/07/25: Qualis Verilog Training
    7038: 97/07/25: Qualis VHDL Training
    7112: 97/08/01: Verilog Training from Qualis
    7113: 97/08/01: VHDL Training at Qualis
Linda Dawson:
    2910: 96/02/28: ANNOUNCE: VHDL Tips and Models on NEW Web Site
Lindo St Angel:
    4568: 96/11/15: The best timing diagram editor/simulator?
<lingamaneni.naveen@gmail.com>:
    111729: 06/11/08: abel to vhdl converter
    113474: 06/12/14: Re: abel to vhdl converter
    113512: 06/12/15: Re: abel to vhdl converter
    116665: 07/03/14: .bit file to VHDL/verilog source code
lingbo:
    34496: 01/08/27: Re: Help needed: simulation OK, synthesis OK, but doesnt work :-<
<lingleq@my-deja.com>:
    17159: 99/07/06: Xilink FPGA
lingwitt:
    116505: 07/03/11: Xilinx: Case Statements
    116510: 07/03/11: Re: Xilinx: Case Statements
    116512: 07/03/11: Re: Xilinx: Case Statements
    116524: 07/03/12: Re: Xilinx: Case Statements
linical:
    71678: 04/07/27: ramdon noise generation
    71749: 04/07/29: Re: ramdon noise generation
    71767: 04/07/29: Re: ramdon noise generation
linnix:
    107511: 06/08/29: Re: September training?
    107525: 06/08/29: Re: September training?
    107545: 06/08/29: Re: September training?
    111879: 06/11/12: Xilinx XC9500 Jtag instructions?
    111889: 06/11/12: Re: Xilinx XC9500 Jtag instructions?
    111903: 06/11/12: Re: Xilinx XC9500 Jtag instructions?
    120132: 07/06/01: Re: Cyclone 3 Starter Board Question
    120143: 07/06/01: Re: Cyclone 3 Starter Board Question
    128172: 08/01/17: Re: effect of xray on fpga electronic circuits
    134744: 08/08/28: Re: Mass storage device on ML403 board
Linnix:
    71721: 04/07/28: Re: FPGA vs CPLD
    75011: 04/10/24: Re: Looking for FPGA design services in India or similar
lino:
    21222: 00/03/10: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
Lino de Martin:
    23959: 00/07/18: xilinx prom 17s05lvc Need programming specification
    23961: 00/07/18: Re: SerialProm programmer
linobi:
    152315: 11/08/08: Newbie PCB
    152322: 11/08/08: Re: Newbie PCB
<linq936@hotmail.com>:
    87043: 05/07/13: virtex 4 : how can I know the clock region coverage?
    93270: 05/12/17: How to use ISE FPGA Editor to compare timing path easily?
    93757: 05/12/29: Virtex 4 desing : ChipScope insertion impacts my timing problem debug
linux user:
    61980: 03/10/15: Running Quartus II on ReadHat Linux 9.0
    62020: 03/10/16: Re: Running Quartus II on ReadHat Linux 9.0
    62089: 03/10/18: Running Quartus II on ReadHat Linux 9.0
    62090: 03/10/18: Re: Running Quartus II on ReadHat Linux 9.0
    62255: 03/10/23: Re: Running Quartus II on ReadHat Linux 9.0
    62351: 03/10/27: Re: Running Quartus II on ReadHat Linux 9.0
    62962: 03/11/11: Re: Programmer's unpaid overtime. ==> I would suggest here some prudence
lioncat:
    140312: 09/05/08: Question on using ODDR
    140316: 09/05/08: Re: Question on using ODDR
    140365: 09/05/11: Re: Question on using ODDR
    140368: 09/05/11: Re: Question on using ODDR
Lionel Damez:
    90752: 05/10/20: EDK/ISE : unroutable design
    90799: 05/10/21: Re: EDK/ISE : unroutable design
    90907: 05/10/25: Re: EDK/ISE : unroutable design
Lionel DORIS:
    32831: 01/07/10: Pins state on Spartan XL before config.
    36891: 01/11/23: Using XC18Vxx ISP config proms with Spartan XL
lionheart70:
    124345: 07/09/18: Re: how to bidirectional signal in xilinx EDK tool ?
lior:
    15054: 99/03/04: Re: wanted: info about Fast Ethernet cores
Lior Dvir - Telrad LTD:
    17176: 99/07/07: Re: Altera EPC1 replacement?
lioupayphone@gmail.com:
    93583: 05/12/25: how to use ICAP on Virtex-II XC2V1000-FG456-4?
<lioupayphone@gmail.com>:
    93008: 05/12/11: who can help me? i want to know the bitsream format of Virtex-II
    93284: 05/12/19: where can i get a release copy of ISE 8i?
    93318: 05/12/19: help: how to use ICAP of Virtex-II ?
liqiyue@gmail.com:
    126646: 07/11/28: Interfacing Cyclone III to 3.3v LVDS devices
liran:
    46320: 02/08/26: writeing a synthesized vhdl code for "shifter "
Lis Hu:
    53092: 03/03/03: scripting leonardo spectrum
    54304: 03/04/07: precision RTL/Synplify/LeonardoSpectrum/Quartus
    54373: 03/04/09: Re: precision RTL/Synplify/LeonardoSpectrum/Quartus
    55679: 03/05/15: Large Fifos
    56699: 03/06/11: test vectors storage/generation
    59068: 03/08/07: Re: Error Generate Statement
    60378: 03/09/11: Re: Reading and processing input from graphics cards (DVI)?
Lisa Nangel:
    15233: 99/03/15: How can I improve an adder?
Lisa Warren:
    31287: 01/05/17: Re Xilinx 1553 Interface
<lisa_crawford@cmagroup.com>:
    14509: 99/02/02: Job: New York; Senior Engineer; FPGA, Imaging, Video
ListSoft:
Little Caesar:
    2236: 95/11/07: Re: I find large VHDL code(for my partition system)
Little_orange:
    107679: 06/08/31: FFT IP CORE: XFFTV2.0
little_orange:
    107383: 06/08/27: FFT : XK_INDEX
    107385: 06/08/27: FFT IP CORE: XK_INDEX???
LittleAlex:
    133677: 08/07/09: Re: How to download bitstream into Cyclone III starter board
    133681: 08/07/09: Re: logical net 'NET' has no load
    133692: 08/07/09: Re: logical net 'NET' has no load
    133725: 08/07/11: Re: VHDL code for DDFS
    134479: 08/08/12: Re: Using a Spartan 3 FPGA kit with a USB/DB9
    134482: 08/08/12: Re: altera cyclone3 484BGA package
    134483: 08/08/12: Re: Using a Spartan 3 FPGA kit with a USB/DB9
    134488: 08/08/12: Re: Altera question - MAX3000 vs MAX7000
    134913: 08/09/06: Re: Best way to buy Xilinx FPGAs?
    134914: 08/09/06: Re: Altera library sim question
    134915: 08/09/06: Re: Best way to buy Xilinx FPGAs?
    134916: 08/09/06: Some feedback on the Xilinx web site
    134918: 08/09/06: Re: uClinux / Microblaze -- Min. Requirements
    134961: 08/09/08: Re: Some feedback on the Xilinx web site
    135032: 08/09/11: Re: Altera library sim question
    135104: 08/09/16: Re: Xilinx build system
    135105: 08/09/16: Re: Two JTAG Parallel IV Cable in a single PC.
    135150: 08/09/17: Re: interview questions ........
    135271: 08/09/23: Re: Xilinx Mode Select Pins
    135430: 08/10/01: Re: Gee Thanks Altera, I really enjoy having a break waiting on your
    135889: 08/10/20: Re: Looking for a FPGA board for starter
    135918: 08/10/21: Re: Spartan 3 IO banking rules problem in ISE
    135935: 08/10/22: Re: Cyclone III, DP RAM, and Verilog
    136145: 08/11/03: Re: How to move project files from ISE 7.1 to ISE 10.1
    136197: 08/11/05: Re: RS-232 Bus controller design in VHDL
    136218: 08/11/06: Re: How to move project files from ISE 7.1 to ISE 10.1
    136235: 08/11/07: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
    136400: 08/11/14: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
    136412: 08/11/14: Re: rank beginner here, need to know where to start to get RS232
    136415: 08/11/14: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
    136796: 08/12/05: Re: is it a bug?(Xilinx Xapp859 reference design: DDR2 SDRAM
    136797: 08/12/05: Re: Equivalent ASIC Gate Estimate
    136877: 08/12/10: Re: Looking for FPGA engineer for HD camera project
    137339: 09/01/09: Re: fpga mac controller with tcp/ip/dhcp
    137690: 09/01/27: Re: now what is this? iMPACT:2356 - Platform Cable USB firmware must
    137691: 09/01/27: Re: What software do you use for PCB with FPGA ?
    137696: 09/01/27: Re: XST Makes Odd Choice
    137821: 09/01/30: Re: byteblaster cloning
    138412: 09/02/20: Re: Troubleshooting fpga design
    138484: 09/02/24: Re: Where can a cheap programmer for Xilinx Virtex II XC2V1500 be
    138506: 09/02/25: Re: Can Xilinx IST automatically detect non-compatible library?
    138562: 09/02/27: Re: why is the bottom 5 lsb all zero of ingress_start_addr/egress_start_addr[27:6]
    138634: 09/03/02: Re: PCIE with Avalon I/F
    138635: 09/03/02: Re: how to communicate with NiosII
    138636: 09/03/02: Re: xilinx-microblaze interrupt controller
    138850: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
    139224: 09/03/23: Re: Looking for a low-cost development kit
    139340: 09/03/26: Re: Looking for a low-cost development kit
    139462: 09/03/30: Re: initialize BRAM contents
    139978: 09/04/21: Re: ISE 10.1 installation troubles on windows Vista 32bit
    140034: 09/04/24: Re: FPGA evaluation board for SD/SDHC Host controller
    140153: 09/04/30: Re: prohibit global clock designation
    140175: 09/05/01: Re: ISE/EDK/SDK 11.1 licensing
    140178: 09/05/01: Re: ISE/EDK/SDK 11.1 licensing
    140259: 09/05/06: Re: Darnit! Broke MXE...
    140317: 09/05/08: Re: Quartus II negative bus dimensions in Schematic file
    140587: 09/05/19: Re: XILINX license model restricts longtime availability
    140712: 09/05/22: Re: Can we expect ISE Gui and makefile to produce identical bit
    141046: 09/06/03: Re: Micron SODIMM Type Variation
    141070: 09/06/04: Re: Has anyone tried to install a Xilinx floating license? The
    141140: 09/06/08: Re: Xilinx Block RAM Sim
    141194: 09/06/10: Re: USB3300 - Xilinx ML401 interface
    143001: 09/09/14: To Xilinx: Regarding the download manager
    143002: 09/09/14: Re: To Xilinx: Regarding the download manager
    143102: 09/09/20: Re: To Xilinx: Regarding the download manager
    143794: 09/10/26: Re: Picoblaze assembler not running Help!!!
    143907: 09/11/02: Re: Inter FPGA communication bus for Cypress Ez USB device
    144000: 09/11/06: Re: OK Xilinx users, it's time I was let in on the joke...
    144167: 09/11/16: Re: Old EDK versions
    144446: 09/12/08: Re: dual core microblaze
    144481: 09/12/09: Re: EDK problem
    144599: 09/12/19: Re: EDK problem
    146485: 10/03/19: Re: wishbone
    146486: 10/03/19: Re: Xilinx Spartan6 Virtex6 Rollout
littlebean:
    55075: 03/04/25: question about modelsim
Litv:
    110448: 06/10/16: Re: Low hierarchy not follow in ChipScope Pro
<litv@fromru.com>:
    81061: 05/03/16: Xilinx System Generator
Litvinov:
    37463: 01/12/11: Initialization of RAM
#LIU BO (G0194808w)#:
    54179: 03/04/04: None
LIU Xianhua:
    33381: 01/07/25: FSB bus
Liu Yin:
    8487: 97/12/22: FPGA Hardware Architectrue
Livia:
    130061: 08/03/14: I need help! Connecting my dual port RAM to a microblaze
Liviu:
    21846: 00/04/03: Library of Parameterized Modules
<lixia.rem@gmail.com>:
    133665: 08/07/09: Re: HWICAP initialization
    134049: 08/07/23: icap Xwicap_DeviceRead problems
    134889: 08/09/04: Re: icap Xwicap_DeviceRead problems
    134890: 08/09/04: Re: icap Xwicap_DeviceRead problems
liyiyiyam:
    142804: 09/09/02: ERROR:Pack:1564
Liyong Chen:
    4821: 96/12/18: Test
Lizard Blizzard:
    53436: 03/03/13: Re: footprints
Ljubisa Bajic:
    52765: 03/02/20: Re: Gate boosting
    52782: 03/02/21: Re: Gate boosting
    54170: 03/04/03: Re: Xilinx announces 90nm sampling today!
    54225: 03/04/04: Re: Xilinx announces 90nm sampling today!
    55033: 03/04/24: Re: DC requirement in FFT
    55383: 03/05/06: Re: Ibis for Cyclone?
    56347: 03/06/03: Re: Parallel_case Synthesis directive
    56691: 03/06/11: Re: DVI with a Virtex-II
    56721: 03/06/12: Re: DVI with a Virtex-II
    56760: 03/06/13: Re: DVI with a Virtex-II
    62102: 03/10/19: Re: Italy is out of FPGA world?
    62243: 03/10/22: Re: The Luddite Needs Reference Books...
    62569: 03/11/01: Video decoder and encoder IC's
    62804: 03/11/07: Re: ASIC speed
    72625: 04/08/26: Re: ring oscillator calibration
    79924: 05/02/25: Re: Engineer in Eastern Europe
    80292: 05/03/03: Re: Signal Integrity, ground bounce, crosstalk, SSOs, BGA pin-outs, parasitic inductance...
    80738: 05/03/10: Re: Iccint(max)
    81490: 05/03/24: Altera's power consumption net seminar
    81540: 05/03/26: Re: Altera's power consumption net seminar
    83335: 05/04/27: Re: Virtex 4 Power consumption
    83425: 05/04/29: Re: Virtex 4 Power consumption
<ljung@codetronix.com>:
    135298: 08/09/24: Re: Avalda's Parallel F# to RTL FPGA Compiler
    140759: 09/05/25: Re: Doubt about a Microblaze Based Multiprocessor SoC
    140782: 09/05/25: Re: Doubt about a Microblaze Based Multiprocessor SoC
LK Allen:
    69371: 04/05/08: Director of Applications/FPGA
<lkjrsy@gmail.com>:
    115853: 07/02/22: porting virtex2-pro into virtex4. Performance!!
    115991: 07/02/27: How can we know how many BRAM are used?
    116029: 07/02/28: How to implement pipeline in this case?
    116030: 07/02/28: How to implement pipeline in this case?
    122212: 07/07/24: Corgen Adder Vs DSP48 Adder in Virtex4
<lkostov@my-deja.com>:
    22805: 00/05/25: Re: Web page for FPGA design jobs???
    22806: 00/05/25: Help for Spartan XCS10
    22834: 00/05/26: Re: Help for Spartan XCS10
    22885: 00/05/30: Re: search PCB programmer VHDL
    27419: 00/11/21: Cores for EPP
    27437: 00/11/22: Re: Another simple Xilinx question
    28765: 01/01/23: Could I use IOPAD twince in the design?
lktan:
    43759: 02/05/31: communication between two RC100
    44911: 02/07/05: choosing RC100 over RC1000?
    45295: 02/07/18: Mapping error
llaa57:
    52364: 03/02/07: Divide clock frequency by 1.5: output duty cycle is not 50%
<llabakdas@gmail.com>:
    87586: 05/07/26: Asynchronous Priority comparator
    88247: 05/08/12: Re: Asynchronous Priority comparator
llandre:
    22931: 00/06/03: Re: to make few modifications on a design
    22932: 00/06/03: Free sources on the net
    26606: 00/10/22: SoC: Triscend vs Atmel FPSLIC
    29795: 01/03/10: Questions about Xilinx Web Pack ISE
    29796: 01/03/10: Re: Spartan-II Evaluation Board
    30549: 01/04/14: VHDL FFT core: where?
    34956: 01/09/16: Problems with Xilinx App Note 223 (UART with Internal 16-Byte Buffer)
    115583: 07/02/14: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
    115599: 07/02/14: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
    115660: 07/02/16: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
    124196: 07/09/14: Xilinx GSRD reference design and 3rd party synthesizer
Lllapides:
    2483: 95/12/15: Re: FPGA => ASIC (Summary)
    3734: 96/07/22: Re: What does the timing report from Synthesizer mean?
    3872: 96/08/13: Re: Quick question for Model Tech. experts:
    5581: 97/02/26: Re: Does anybody know how defaults work in a State Machine in AHDL ?
<llombard@gmail.com>:
    125439: 07/10/25: Re: HELP, how to time constraint part of a design?
    125659: 07/10/31: Re: HELP, how to time constraint part of a design?
llossak:
    38139: 02/01/06: WARNING
    38173: 02/01/07: Re: WARNING
    38374: 02/01/12: modelsim
Lloyd D. Songne, Jr.:
    4229: 96/10/02: Where can I find pSOS skilled professionals?
Lloyd Miller:
    4688: 96/11/29: Re: Addressbility.
LM:
    39987: 02/02/23: Implementing MD5 in hardware (Handel C, VHDL)
    129607: 08/02/28: What demokit and VHDL compiler pair to buy
    129609: 08/02/28: Re: What demokit and VHDL compiler pair to buy
    153086: 11/11/28: FPGA with a bus (serial,USB or ethernet)
    153350: 12/02/04: Re: A smallish starter Kit for led control
    153426: 12/02/22: What is a PLD/FPGA with serial or Ethernet port logic or block built in
    153431: 12/02/23: Re: What is a PLD/FPGA with serial or Ethernet port logic or block
    153437: 12/02/24: Re: What is a PLD/FPGA with serial or Ethernet port logic or block
    153442: 12/02/25: Re: What is a PLD/FPGA with serial or Ethernet port logic or block
    153450: 12/02/27: Re: What is a PLD/FPGA with serial or Ethernet port logic or block
    153844: 12/06/04: Questions about LCMXO2280-B-EVN and LCMXO2-1200ZE-B-EVN ev kits
    153847: 12/06/05: Re: Questions about LCMXO2280-B-EVN and LCMXO2-1200ZE-B-EVN ev kits
    153849: 12/06/05: Re: Questions about LCMXO2280-B-EVN and LCMXO2-1200ZE-B-EVN ev kits
    154032: 12/07/17: What is best/good way to create a small delay with LCMXO2-1200ZE ev kit
    154034: 12/07/17: Re: What is best/good way to create a small delay with LCMXO2-1200ZE
    154468: 12/11/07: Is it possible to use MachXO2 Demo board to program an external FPGA?
    156296: 14/02/11: How to find power supply pins in Lattice Diamond projects
    156299: 14/02/11: Re: How to find power supply pins in Lattice Diamond projects
    156300: 14/02/11: Re: How to find power supply pins in Lattice Diamond projects
    156302: 14/02/12: Re: How to find power supply pins in Lattice Diamond projects
    156314: 14/02/25: Re: How to find power supply pins in Lattice Diamond projects
    156315: 14/02/25: Re: How to find power supply pins in Lattice Diamond projects
lm317t:
    128057: 08/01/14: FPGA's as DSP's
    128073: 08/01/14: Re: FPGA's as DSP's
    129646: 08/03/01: Re: Software for FPGA-based PC scope
    129657: 08/03/02: Re: Software for FPGA-based PC scope
    129660: 08/03/02: Re: Software for FPGA-based PC scope
    129669: 08/03/02: Re: Software for FPGA-based PC scope
    129811: 08/03/05: Re: question about verilog language constructs
    129890: 08/03/08: Re: XC3S50-4VQ100C fpga chip
    130003: 08/03/12: Re: Matlab, RS-232, Ethernet
    130024: 08/03/13: Re: Matlab, RS-232, Ethernet
    131224: 08/04/15: Re: Which to learn: Verilog vs. VHDL?
    131225: 08/04/15: Re: Simulation tools for Xilinx ISE
    131229: 08/04/15: Re: Which to learn: Verilog vs. VHDL?
<lnarayan@hclt.com>:
    17019: 99/06/25: synopsys message "unable to resolve reference" with 4000xv
<lnds@hotmail.com>:
    117022: 07/03/21: Re: Need fair opinions on choosing either Altera or Xilinx as main FPGA source
lng:
    46113: 02/08/19: Re: CLOCK DLL IN SPARTAN2E Timing question
    46114: 02/08/19: Re: rising_edge detector?
    46116: 02/08/19: Re: BRAM simulation model error?
    46146: 02/08/20: Re: BRAM simulation model error?
    46436: 02/08/29: Re: Problem: Spartan 2 E CCLK
    46560: 02/09/03: Re: Question about IOB, BUFG, IBUF and IBUG.
    46625: 02/09/04: Re: why the need for HIGH speed design?
    46628: 02/09/04: Re: why the need for HIGH speed design?
    46810: 02/09/09: Re: why the need for HIGH speed design?
    47482: 02/09/26: Re: Looking for a dead Virtex
Lnguen:
    56463: 03/06/05: Re: Clk between multiple boards
lnguyen:
    63931: 03/12/09: Re: Too many signals [Xilinx Foundation 4.1i]
    63967: 03/12/10: spartan2 pin LOC strange error
<lnwolf@amaroq.com>:
    9918: 98/04/13: Xilinx Timing Constraints
    10113: 98/04/27: Re: Make a delay in Xilinx FPGAs (more Details)?
Loan Nguyen:
    50792: 02/12/19: Re: Two clocks for the same module
<locate@locate-now.com>:
    23206: 00/06/17: Internet and scripting
<lochen@noos.fr>:
    116727: 07/03/16: init of FPGA's Block-RAMs.
Lockie:
    62600: 03/11/03: Xilinx - Multi Volt Interfacing
    62658: 03/11/04: Re: Xilinx - Multi Volt Interfacing
    62688: 03/11/05: Re: Xilinx - Multi Volt Interfacing
Lode Nachtergaele:
    3266: 96/05/07: Re: SILAGE
Loek Frederiks:
    11264: 98/07/31: Re: leapfrog wavform
log:
    19018: 99/11/24: Obselete processor substitutes
Logan Shaw:
    104831: 06/07/07: Re: How much time does it need to sort 1 million random 64-bit/32-bit
    105922: 06/08/03: Re: Where are Huffman encoding applications?
Loganathan Lingappan:
    50766: 02/12/18: Xilinx 4000 FPGA : ERROR XNFO-11
Logaras Evangelos:
    111295: 06/11/01: DDR_controller_EDK
Logixa:
    156716: 14/06/07: Ethernet Switch on Configurable Logic now available
logjam:
    77933: 05/01/20: Copying/Reverse Engineering PAL
    77957: 05/01/20: Re: Copying/Reverse Engineering PAL
    77984: 05/01/21: Re: Copying/Reverse Engineering PAL
    77999: 05/01/22: Microscope examination of a PLD
    78013: 05/01/22: Re: Copying/Reverse Engineering PAL
    78015: 05/01/22: Re: Copying/Reverse Engineering PAL
    78019: 05/01/22: Re: Microscope examination of a PLD
    78024: 05/01/23: Re: Microscope examination of a PLD
    78046: 05/01/23: Re: Microscope examination of a PLD
    78103: 05/01/24: Re: Copying/Reverse Engineering PAL
    78112: 05/01/24: Re: Copying/Reverse Engineering PAL
    78115: 05/01/25: Re: Copying/Reverse Engineering PAL
    78154: 05/01/25: Re: Copying/Reverse Engineering PAL
    78155: 05/01/25: Re: Copying/Reverse Engineering PAL
    78162: 05/01/25: Re: Copying/Reverse Engineering PAL
    78181: 05/01/25: Re: Copying/Reverse Engineering PAL
    78192: 05/01/25: Re: Copying/Reverse Engineering PAL
    78194: 05/01/26: Re: Copying/Reverse Engineering PAL
    78225: 05/01/26: Re: Copying/Reverse Engineering PAL
    78265: 05/01/27: Re: Copying/Reverse Engineering PAL
    78289: 05/01/28: Re: Copying/Reverse Engineering PAL
    78301: 05/01/28: Re: Microscope examination of a PLD
    89168: 05/09/07: Help finding Signetics Datasheets
    89198: 05/09/07: Re: Help finding Signetics Datasheets
    89243: 05/09/08: Reading a PAL fusemap with a microscope
    89277: 05/09/09: Re: Reading a PAL fusemap with a microscope
    89293: 05/09/11: Re: Reading a PAL fusemap with a microscope
    89331: 05/09/12: Re: Reading a PAL fusemap with a microscope
    89440: 05/09/14: HAL fuse map organization issue
    89441: 05/09/14: Re: HAL fuse map organization issue
    89511: 05/09/16: Re: Reading a PAL fusemap with a microscope
    89522: 05/09/17: Re: Reading a PAL fusemap with a microscope
    89538: 05/09/18: Re: Reading a PAL fusemap with a microscope
    89539: 05/09/18: Re: Reading a PAL fusemap with a microscope
    93759: 05/12/29: Brute Force Examination of a PLD
    93801: 05/12/30: Re: Brute Force Examination of a PLD
    94571: 06/01/13: FPGA Altair Advice
    94635: 06/01/15: Re: FPGA Altair Advice
    94580: 06/01/13: Re: Attack of the clones
    97129: 06/02/16: VHDL simulation
    97134: 06/02/16: Re: VHDL simulation
    97480: 06/02/23: Combinatorial Division?
    97559: 06/02/23: Re: Combinatorial Division?
    97565: 06/02/23: Re: Combinatorial Division?
    97576: 06/02/23: Re: Combinatorial Division?
    97639: 06/02/24: Re: Combinatorial Division?
    97640: 06/02/24: Re: Combinatorial Division?
    97722: 06/02/26: Re: Combinatorial Division?
    97785: 06/02/27: Re: Combinatorial Division?
    106610: 06/08/16: Simple state machine in CUPAL
    106661: 06/08/16: Re: Simple state machine in CUPAL
    106671: 06/08/16: Re: Simple state machine in CUPAL
    106737: 06/08/17: Re: Simple state machine in CUPAL
    111962: 06/11/13: NTSC/VGA / Ethernet Advice for S3EBOARD from Digilent
    111993: 06/11/14: Re: NTSC/VGA / Ethernet Advice for S3EBOARD from Digilent
    112062: 06/11/15: 8080 FSGA model in an FPGA
    112082: 06/11/15: Re: 8080 FSGA model in an FPGA
    112083: 06/11/15: Re: 8080 FSGA model in an FPGA
Loi Tran:
    40555: 02/03/10: Re: Audio project with an FPGA?
    41027: 02/03/19: Re: FIFO general question
    41512: 02/04/01: Web pack (how to) ?
    41586: 02/04/02: Re: Web pack (how to)?
    42547: 02/04/26: Re: Using PAL/GAL/FPGA to replace CPU's (correct news group?)
    42887: 02/05/06: Re: Xilinx IOBUF?
    43186: 02/05/15: WEBPack 4.1 - vhdl modules in schematics?
    45121: 02/07/13: 5V input to CLOCK on Xilinx Spartan 2
    45124: 02/07/13: Re: 5V input to CLOCK on Xilinx Spartan 2
    45125: 02/07/13: Re: 5V input to CLOCK on Xilinx Spartan 2
    45830: 02/08/07: Lattice GAL22V10 and everything it entails . . . !
    46067: 02/08/16: Re: rising_edge detector?
    47786: 02/10/04: Re: Low power design
    52894: 03/02/25: Re: two-clock FSM?
    54826: 03/04/19: Webpack 5.2 Install problems?
    54832: 03/04/20: Webpack - calling libraries?
    54835: 03/04/20: Re: Webpack 5.2 Install problems?
    54899: 03/04/21: Re: Webpack 5.2 Install problems?
    59368: 03/08/17: Re: Old Xilinx FPGAs
    59458: 03/08/19: Re: Which software from Xilinx
    62361: 03/10/28: Trenz-electronics (spartan2 development board) help?
Loic Lagadec:
    13033: 98/11/12: FPGAs evolution
Lois:
    77486: 05/01/07: Master's Project
lokesh:
    117991: 07/04/15: combinatorial vs sequential
lolita grenoble:
    146376: 10/03/15: how to use the design results of the vhdl code for a program in C
<lolita.tangier@gmail.com>:
    140067: 09/04/27: ERROR: NgdBuild:604 - logical block
    140073: 09/04/27: Re: ERROR: NgdBuild:604 - logical block
    140123: 09/04/29: Re: ERROR: NgdBuild:604 - logical block
    140124: 09/04/29: Re: ERROR: NgdBuild:604 - logical block
    140388: 09/05/12: Re: ERROR: NgdBuild:604 - logical block
    140390: 09/05/12: how i can use the external SRAM of FPGA
    140565: 09/05/18: Re: how i can use the external SRAM of FPGA
    140831: 09/05/27: how i can to send a sequence of bytes to the FPGA ?
    140837: 09/05/27: Re: how i can to send a sequence of bytes to the FPGA ?
Lolotheguru:
    72827: 04/09/03: CPLD : Is there a way
lomtik:
    77473: 05/01/07: signals inside a process
    77481: 05/01/07: Re: signals inside a process
    77617: 05/01/12: Looking for low-cost protoboards.
<lomtikster@gmail.com>:
    135507: 08/10/05: Reading files from CF (microblaze 7 and plb)
    135509: 08/10/06: Connecting MPD I/O ports in xps_sysace
    135591: 08/10/09: Re: Reading files from CF (microblaze 7 and plb)
    135592: 08/10/09: Re: Connecting MPD I/O ports in xps_sysace
    136188: 08/11/05: Re: Reading files from CF (microblaze 7 and plb)
    136189: 08/11/05: Connecting TFT Controller's signals, Microblaze
    136190: 08/11/05: Re: RS-232 Bus controller design in VHDL
    136191: 08/11/05: Xilinx TFT controller
    136293: 08/11/10: Re: Reading files from CF (microblaze 7 and plb)
    136294: 08/11/10: Re: Xilinx TFT controller
    136295: 08/11/10: Register access over PLB2DCR bridge
    136325: 08/11/11: Re: Register access over PLB2DCR bridge
    136337: 08/11/11: Re: Register access over PLB2DCR bridge
    136339: 08/11/11: Re: Register access over PLB2DCR bridge
<lone_traveler@my-deja.com>:
    22936: 00/06/04: Altera FPGA/CPLD in-system-programmer
Long:
    22467: 00/05/09: EETools Topmax
Long Nguyen:
    61051: 03/09/26: Re: Graphics rendering
<longbrmb@gmail.com>:
    129306: 08/02/20: Post PAR simulation is successful but still fails on the board
    129386: 08/02/22: Re: Post PAR simulation is successful but still fails on the board
    138763: 09/03/09: Timing requirements for generating off-chip clock with DDR register
    138768: 09/03/09: Re: Timing requirements for generating off-chip clock with DDR
    138782: 09/03/10: Re: Timing requirements for generating off-chip clock with DDR
longjin:
    50123: 02/12/02: block and distributed RAM
    50159: 02/12/03: Re: block and distributed RAM
<longwayhome@my-deja.com>:
    27297: 00/11/17: Hardware suggestions for evolutionary experiments
    27376: 00/11/20: Re: Hardware suggestions for evolutionary experiments
    27531: 00/11/27: Xess - XS40-005XL question
    27579: 00/11/29: Re: Xess - XS40-005XL question
    28147: 00/12/23: Question about programming xcv100
    28163: 00/12/23: Re: Question about programming xcv100
    28171: 00/12/24: Re: Question about programming xcv100
    28185: 00/12/25: Re: Question about programming xcv100
longyin:
    71641: 04/07/26: nios-run: waiting for target.......?
lonny:
    144901: 10/01/13: Virtex-5 with DDR3 running @ 50Mhz
looking for Xilinx ppc consultant:
    83862: 05/05/08: Looking for Xilinx Power-PC consultant
    83967: 05/05/10: Re: Looking for Xilinx Power-PC consultant
lorabanks:
Lorant:
    18377: 99/10/20: Interleaver
Lorcan Mc Donagh:
    21358: 00/03/20: Question about Atmel AT40k FPGA: mode4 configuration download details ? ( not in the datasheets )
Lord Crc:
    54554: 03/04/14: Re: Hardware acceleration for raytracing purposes
lordsathish:
    134998: 08/09/09: Can Soft microprocessor replace DSP's
lordwolf:
    123302: 07/08/22: Burst Memory Transfer Request from PPC
<lordxiphias@altern.org>:
    18610: 99/11/03: LX.MP3z: NO PORN, NO POP-UPS, NO BROKEN LINKS (Just MP3z!!)
Loren Charnley:
    1036: 95/04/19: Re: $40 Million For NeoCAD & A New FPGA Synthesis Tool
Lorenz Kolb:
    133655: 08/07/08: Re: How to download bitstream into Cyclone III starter board
    133689: 08/07/10: Re: How to download bitstream into Cyclone III starter board
    133709: 08/07/10: Re: Chipscope data port limitation to 256 bits
    133717: 08/07/11: Re: Chipscope data port limitation to 256 bits
    133850: 08/07/17: Re: Xilinx/Altera gate equivalence
    133858: 08/07/17: Re: free of bugs
    133880: 08/07/18: Re: verilog code
    133881: 08/07/18: Re: Problem creating the ML403 project using Xilinx tool
    133882: 08/07/18: Re: Xilinx/Altera gate equivalence
    133887: 08/07/18: Re: verilog code
    133890: 08/07/18: Re: Problem creating the ML403 project using Xilinx tool
    133892: 08/07/18: Re: Problem creating the ML403 project using Xilinx tool
    133894: 08/07/18: Re: Problem creating the ML403 project using Xilinx tool
    133951: 08/07/20: Re: Change clock domain for FIFO ...
    133973: 08/07/21: Re: Change clock domain for FIFO ...
    133980: 08/07/21: Re: Change clock domain for FIFO ...
    133982: 08/07/21: Re: Change clock domain for FIFO ...
    133986: 08/07/21: Re: Change clock domain for FIFO ...
    133987: 08/07/21: Re: Change clock domain for FIFO ...
    134379: 08/08/08: Re: ML403, U-Boot+Linux and Ethernet?
    134416: 08/08/09: Re: ML403, U-Boot+Linux and Ethernet?
    135071: 08/09/13: Re: Can Soft microprocessor replace DSP's
    135123: 08/09/17: Re: Random Mask Generation on FPGAs
    135153: 08/09/18: Re: Random Mask Generation on FPGAs
    135840: 08/10/17: Re: Forcing Xilinx tools to treat two clocks as unrelated
    136487: 08/11/19: Re: how to implement an application with external memory in ISE?
    136565: 08/11/22: Re: Student FPGAs
    136974: 08/12/16: Re: Sign extension issue in Xilinx Multiplier CoreGen version10
    137035: 08/12/20: Re: PLL and clock in altera cyclone 2 fpga
    137038: 08/12/20: Re: Large BRAM synthesis
    137046: 08/12/20: Re: Large BRAM synthesis
    137056: 08/12/21: Re: FPGA for Contoll
    137101: 08/12/23: Re: Adding userports to a custom peripheral in XPS
    137104: 08/12/23: Re: DFFR using DFF (only, may be extra gates)
    137107: 08/12/23: Re: Adding userports to a custom peripheral in XPS
    137144: 08/12/28: Re: FPGA > ASIC
    137173: 08/12/30: Re: Xilinx QUIZ 2008
    137181: 08/12/30: Re: Xilinx QUIZ 2008
    138082: 09/02/05: Re: How to divide clock frequency......
    138116: 09/02/06: Re: Xilinx Powerpc issue with custom peripherals
    150095: 10/12/13: Re: xilinx spartan 6 deserialization
    150103: 10/12/13: Re: Interfacing DS92LV1021 with FPGA serdes
Lorenz Schelling:
    17986: 99/09/21: ORCA-Defaults for PCI-Configuration registers
Lorenzo:
    59843: 03/08/29: Re: Xilinx Foundation Series F2.1i + win2k
    59995: 03/09/03: Re: How to extend a pulse width without clock!
    60563: 03/09/16: Re: Xilinx ISE 6.1i
    60594: 03/09/17: Re: platform flash as storage?
    60607: 03/09/17: Re: platform flash as storage?
Lorenzo Dal Bello:
    58625: 03/07/29: Partial Reconfiguration on Xilinx FPGA
Lorenzo Di Gregorio:
    13296: 98/11/24: Re: Integer divide algorithms
    13316: 98/11/25: Re: Integer divide algorithms
Lorenzo Lutti:
    42347: 02/04/21: Re: XC9500XL problem
    42425: 02/04/23: Re: XC9500XL problem
    43294: 02/05/18: Re: xilinx foundation 2.1 RPC problem on win2000
    44083: 02/06/11: Re: Problems initialising an FPGA - SPARTAN II
    44124: 02/06/12: Re: Problems initialising an FPGA - SPARTAN II
    44739: 02/06/28: Re: 5V tolerance
    44740: 02/06/28: State machine and syncronous inputs
    44741: 02/06/28: Foundation and ISE
    44755: 02/06/29: Re: State machine and syncronous inputs
    45007: 02/07/09: Re: Getting started with FPGAs
    46945: 02/09/12: Re: FPGA comes with a DAC?
    47284: 02/09/22: Timing accuracy with Modelsim
    47322: 02/09/23: Re: Timing accuracy with Modelsim
    47368: 02/09/24: Re: Timing accuracy with Modelsim
    47480: 02/09/26: Re: My CPLD (XC9536) is overheated
    47545: 02/09/28: Re: My CPLD (XC9536) is overheated
    48676: 02/10/22: Re: Ms-DOS formatting in an CompactFlash card?
    48677: 02/10/22: Re: slow slew rate signal...
    49198: 02/11/04: Re: Excessive heating on Xilinx XC9500XL
    49236: 02/11/05: Re: Excessive heating on Xilinx XC9500XL
    49590: 02/11/16: Intelligent pin grouping in ISE
    49611: 02/11/17: Are block RAMs supported in simulation?
    49714: 02/11/19: Re: Are block RAMs supported in simulation?
    49763: 02/11/20: Re: Are block RAMs supported in simulation?
    49764: 02/11/20: Re: Foundation 2.1i with Windows 2000?
    50535: 02/12/12: Two clocks for the same module
    50547: 02/12/12: Re: Two clocks for the same module
    50591: 02/12/13: Re: Two clocks for the same module
    50594: 02/12/13: Re: Two clocks for the same module
    50722: 02/12/18: Re: A/D converter in FPGA
    50749: 02/12/18: Re: A/D converter in FPGA
    51467: 03/01/14: Re: SChematic design approach compared to VHDL entry approach
    53837: 03/03/25: xst removes useful signals
    53895: 03/03/26: Re: xst removes useful signals
    53932: 03/03/27: Re: DSP-FPGA interface
    54063: 03/04/01: Re: DSP-FPGA interface
    54099: 03/04/02: Re: DSP-FPGA interface
    55289: 03/05/02: Re: IP Core for CAN communication
    55425: 03/05/07: Xilinx configuration flash/proms
    55505: 03/05/10: Re: Xilinx configuration flash/proms
    56106: 03/05/28: Re: New Xilinx PROMs
    56210: 03/05/30: Re: FPGA's an Flash
    56226: 03/05/31: Re: FPGA's an Flash
    57276: 03/06/26: Re: why so many problems Xilinx ?
    58627: 03/07/29: Re: xilinx programing interface
    58628: 03/07/29: Re: VHDL Book Recommendations Please
    58876: 03/08/03: Re: Pricing question....
    59146: 03/08/10: Re: Offshore engineering
    59155: 03/08/10: Re: Offshore engineering
    60168: 03/09/06: Re: Disable Pull up
    60170: 03/09/06: Re: Cpu Generator rel.1.00 released
    60330: 03/09/10: Duty cycle constraints and internal pulse shaping
    60694: 03/09/19: Re: Xilinx Parallel Cable 4 (PC4) and Platform Flash JTAG
    60732: 03/09/20: Re: Configuration Options:
    60955: 03/09/25: Re: Configuration Options:
    60956: 03/09/25: Re: Italy is out of FPGA world?
    60957: 03/09/25: Re: Xilinx
    62082: 03/10/18: Re: Italy is out of FPGA world?
    62104: 03/10/19: Re: Italy is out of FPGA world?
    62183: 03/10/21: Re: Italy is out of FPGA world?
    62476: 03/10/30: Re: How to protect fpga based design against cloning?
    62557: 03/11/01: Re: How to protect fpga based design against cloning?
    62586: 03/11/02: Re: How to protect fpga based design against cloning?
<lorenzo.verardo@abodata.com>:
    118954: 07/05/08: ISE 8.1
lori:
    96165: 06/01/31: Re: Virtex4 : Audio Codec AC97 LM4550
Lori Ann Clark:
    81096: 05/03/17: [OT] Requesting Engineers to participate in short survey
Lori Lorenser:
    96088: 06/01/30: Virtex4 : Audio Codec AC97 LM4550
    96336: 06/02/02: AC97 Controller
Lorinc Antoni:
    34393: 01/08/23: XHWIF for XESS boards
Lorne Mower:
    113797: 06/12/22: Re: FSL feasibiliity
Lorne Wilkinson:
    15139: 99/03/09: Re: Selt-Timed circuit
Lost Temper:
    64308: 03/12/26: Anyone has the AMD flash AM29LV800B verilog model?
LostSignal:
    54819: 03/04/18: Re: Cyclone power up problem - Summery
Lothar Brodbeck:
    11405: 98/08/11: Announcement: Now available 200.000 Gates Development Boards
    12038: 98/09/25: Announcement: 200.000 Gates FPGA Prototyping Board
Lothar Brodbeck AS/EC1:
    9976: 98/04/20: Announcement VHDL/FPGA Prototyping Boards (200.000 Gates)
    10828: 98/06/24: Announcement: FPGA 200.000 Gates Prototyping Board
<lothar_brodbeck@my-deja.com>:
    18224: 99/10/08: Announcement: VHDL/FPGA Development Boards (up to 400.000 Gates)
    18260: 99/10/11: Re: Announcement: VHDL/FPGA Development Boards (up to 400.000 Gates) (Corrected Links, More Boards)
Lou:
    150528: 11/01/25: Re: tft lcd with xilinx fpga
    150545: 11/01/26: Re: tft lcd with xilinx fpga
    150549: 11/01/26: Re: tft lcd with xilinx fpga
    150566: 11/01/26: Re: tft lcd with xilinx fpga
    150603: 11/01/27: Re: tft lcd with xilinx fpga
    150622: 11/01/28: Re: tft lcd with xilinx fpga
Lou Ricci:
    36953: 01/11/27: Virtex Orcad Library
Loucas Louca:
    959: 95/04/04: Aptix (Field Programmable Interconnect) ??
    2886: 96/02/23: Re: Floating Point and Reconfigurable Architectures
    2887: 96/02/23: Re: Floating Point and Reconfigurable Architectures
    3120: 96/04/06: Re: VHDL books with demo software????
louis:
    49729: 02/11/20: Re: clock difference between DLL input and output?
    50118: 02/12/03: Re: clock difference between DLL input and output?
    53486: 03/03/14: Re: Using divided clock
    53573: 03/03/17: Re: Using divided clock
    54689: 03/04/16: Re: uP interface question
    55328: 03/05/04: Re: Schmitt Trigger an a Virtex
    130680: 08/03/30: After reset, the PC register of PPC is not back to 0Xfffffffc
    130740: 08/03/31: Re: After reset, the PC register of PPC is not back to 0Xfffffffc
    131941: 08/05/08: Dual rank DDR2 memory for Xilinx ML410 board
    132112: 08/05/14: About the user defined instruction in APU
Louis:
    127933: 08/01/10: Place-and-Route : Intel vs AMD
Louis Audoire:
    939: 95/03/31: Re: meta-systems, who are they ?
Louis Caron:
    21294: 00/03/15: Re: Pb with Coregen in F2.1i
Louis Dupont:
    97066: 06/02/15: Altera Stratix EP1S80 DSP Development Board Non-Volatile Configuration
    127019: 07/12/08: Net hierarchy with Xilinx 9.1
louis lin:
    58201: 03/07/17: Xilinx xappp348: SPI Master
    58251: 03/07/18: processing `ifdef in Xilinx ISE 5.2i
    58324: 03/07/21: Re: processing `ifdef in Xilinx ISE 5.2i
    58653: 03/07/30: Re: Reseting the whole thing
    58706: 03/07/31: Re: Reseting the whole thing
    58763: 03/08/01: Re: Reseting the whole thing
    59376: 03/08/18: Re: Skew on a clock tree on a virtex II : what is the good figure ?
    59467: 03/08/20: Re: Skew on a clock tree on a virtex II : what is the good figure ?
    59525: 03/08/21: Re: Skew on a clock tree on a virtex II : what is the good figure ?
    62369: 03/10/28: Re: Picoblaze development tool
    62379: 03/10/28: Re: Are clock and divided clock synchronous?
    62402: 03/10/29: Re: Picoblaze development tool
    62408: 03/10/29: MicroBlaze : can I assign Boot BRAM address other than 0x0?
    63499: 03/11/24: Re: Laptop without serial/parallel port
    106617: 06/08/16: Ultracontroller II: PROM solution in EDK 8.1
    106782: 06/08/19: Re: Ultracontroller II: PROM solution in EDK 8.1
Louis Piché:
    4632: 96/11/22: Re: ViewLogic PRO series under win95
Louis Przebienda:
    8554: 98/01/08: Re: Xilinx Configuration Problem
Louis Swart:
    2180: 95/10/26: http://www.super.org:8000/FPGA/comp-arch-fpga.info
Louis Zhang:
    5679: 97/03/06: Xilinx 4002 RAM Question
    5724: 97/03/11: Re: Xilinx 4002 RAM Question
    5853: 97/03/20: Re: Xilinx 4002 RAM Question
    10760: 98/06/17: VHDL testbench in Maxplus2
    10778: 98/06/18: Re: VHDL testbench in Maxplus2
    11128: 98/07/20: Hierachical signal/port trace in Maxplus2 simulation
    13331: 98/11/26: Re: Which parts are fastest for 3-state enables?
    13418: 98/12/02: Interfaces to an Asynchronous SRAM
    13429: 98/12/02: Re: Interfaces to an Asynchronous SRAM
    13435: 98/12/02: Re: Interfaces to an Asynchronous SRAM
    13439: 98/12/03: Re: Interfaces to an Asynchronous SRAM
    15743: 99/04/11: Programming a long daisy-chain Xilinx 4000
    15934: 99/04/22: A large EEPROM/Flash for a long Xilinx chain
louis-zhang:
    22101: 00/04/22: High Speed LVDS or HSTL
<louis.dupont@gmail.com>:
    100107: 06/04/03: DMA with EDK
<louis_reginaldjean@my-deja.com>:
    23463: 00/06/26: FPGA and ASIC
Lourens Geldenhuys:
    19287: 99/12/10: MAX7256A dies during ICP
    19326: 99/12/14: Re: MAX7256A dies during ICP
Love Singhal:
    84755: 05/05/26: Virtex 4 configuration frames
    84783: 05/05/27: Re: Virtex 4 configuration frames
    86599: 05/06/30: Re: synthesis problem
    87302: 05/07/21: Re: All of the design is being optimized away and logic removed
    88550: 05/08/22: Problem in using Hard Macros in Xilinx ISE 7.1
    97681: 06/02/26: Virtex 4 Multiplier RPM Constraints?
    97702: 06/02/26: Re: Virtex 4 Multiplier RPM Constraints?
    97945: 06/03/02: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    97950: 06/03/02: Re: Virtex 4 Multiplier RPM Constraints?
    98014: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    103307: 06/05/30: Re: Virtex 5 announced and sampling ... and real!
<love>:
    4599: 96/11/19: >>> ARE YOU READY FOR LOVE? <<<
Lovely Robot:
    101286: 06/04/28: please help me out
lovesinghal:
    85979: 05/06/19: FPGAs: Where will they go?
    86035: 05/06/20: Re: FPGAs: Where will they go?
lovesinghal@gmail.com:
    84654: 05/05/24: Xilinx Virtex 4 Configuration Frames
LowSNR:
    124190: 07/09/13: Open-Source VHDL Synthesis for FPSLIC?
<lpjwll@sssdfdf.org>:
    16611: 99/05/31: YOURE NOT GOING TO BELIEVE THIS! 7449
lpm:
    49314: 02/11/08: External memory or on-chip?
    49389: 02/11/11: Re: External memory or on-chip?
<lqicjhgv@search26.com>:
    76545: 04/12/06: Re: why systemc?
lrl:
    58181: 03/07/16: Digital Root circuit using tree of 4-bit CLA's with Cout fed into Cin
ls_user:
    39276: 02/02/05: FPGA vs GAL : Lattice
    39278: 02/02/05: Re: FPGA vs GAL : Lattice
    39284: 02/02/05: Re: FPGA vs GAL : Lattice
    39288: 02/02/05: Re: FPGA vs GAL : Lattice
    39292: 02/02/05: Re: FPGA vs GAL : Lattice
    39506: 02/02/12: Re: Altera's new family Stratix
<lschirrm@gmail.com>:
    116848: 07/03/19: Altera introduces Cyclone III devices, ships 65nm
    116862: 07/03/19: Re: Altera introduces Cyclone III devices, ships 65nm
lsmsc:
    140189: 09/05/02: SysACE and append File
LSRsearch:
    5172: 97/01/29: scientific and medical imaging, fibre channel
lsuser:
    40580: 02/03/11: Re: FPGA wich supports LVDS
    40588: 02/03/11: Re: FPGA wich supports LVDS
    40595: 02/03/11: Re: FPGA wich supports LVDS
    40602: 02/03/11: Re: FPGA wich supports LVDS
    40610: 02/03/11: Re: floating pins
<LT1Z07@yahoo.com>:
    115169: 07/02/01: Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?
    115171: 07/02/01: Re: Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?
    115194: 07/02/02: Re: Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?
Lu Hu:
    46940: 02/09/12: 2-D resistor array
Luanne:
    66769: 04/02/26: Re: Stratix 2 / MAX II
lubot77:
    112951: 06/12/02: Video Mux using FPGA
    112955: 06/12/02: Re: Video Mux using FPGA
Luc:
    71384: 04/07/16: FAE Job opening
    71563: 04/07/22: Re: FPGA Selection--
    71591: 04/07/23: Re: Altera Cyclone Web presentation
    72074: 04/08/07: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
    73268: 04/09/17: Re: PLL in CPLD
    73418: 04/09/21: Re: Altera Max II
    73419: 04/09/21: Re: Mr. Greenfield, spare us the propaganda !
    76070: 04/11/23: Spartan 3L - misleading info to potential customers
    76086: 04/11/24: Re: Spartan 3L - read the offering and see if it is what you want?
    77669: 05/01/13: Re: Lattice DDR Interface
    78025: 05/01/23: Re: Comparison of LEON2, Microblaze and Openrisc processors
    78285: 05/01/28: Re: ProASIC§ Released
    78975: 05/02/10: Re: Is Atmel producing Altera EPCS memories???
    80486: 05/03/07: Re: Cheap alternatives to Mach 210s
    80544: 05/03/08: Re: Cheap alternatives to Mach 210s
    80842: 05/03/12: Re: Lattice's XP (flash + sram) fpga
    80987: 05/03/15: Re: Lattice ispLEVER
    81165: 05/03/18: Spartan 3E vs. Cyclone2
    81181: 05/03/18: Re: Spartan 3E vs. Cyclone2
    81267: 05/03/20: Re: Spartan 3E vs. Cyclone2
    81357: 05/03/22: Re: PAL problems (again)
    82995: 05/04/21: Re: Bug in DDR template in Lattice FPGAs ?
    83713: 05/05/05: DVI implementation
    84175: 05/05/13: Re: "Mine is bigger than yours..."
    84536: 05/05/20: Re: FFT with FPGA
    84616: 05/05/23: Re: Looking for core that does a vector product
    85073: 05/06/03: Re: ispLSI1016
    86014: 05/06/20: Design tools comparison between Xilinx, Altera and Lattice for FPGA designs
    86016: 05/06/20: Re: Lattice LFEC
    87042: 05/07/13: Re: Implement a JTAG controller in an FPGA
    87198: 05/07/19: Re: Lattice MachXO is LAUNCHED NOW!
    87223: 05/07/19: Re: Lattice MachXO is LAUNCHED NOW!
    88072: 05/08/08: Re: warning for ODDR primitive?
    88876: 05/08/30: Re: Embedded Processors/Serdes
    97032: 06/02/15: Re: Altera RoHS Irony
    97186: 06/02/18: Re: opencores.org ?
    97655: 06/02/25: Re: FPGA Selection Question
    138483: 09/02/24: IEEE1588
    138679: 09/03/04: Re: Lattice announces ECP3
    138680: 09/03/04: Re: Lattice announces ECP3
luc:
    90760: 05/10/20: Re: which is Low power FPGA?
Luc Braeckman:
    55272: 03/05/02: Re: Low power, high temperature CPLD
    69321: 04/05/06: Re: Max7000s: how to use the enable of the dffe flip-flop?
    69920: 04/05/24: Re: The fastest interface between FPGA's
    70087: 04/06/02: Re: How can I get an output clock phased align with the input clock.
    70111: 04/06/03: Re: How can I get an output clock phased align with the input clock.
    70209: 04/06/09: Re: How can I get an output clock phased align with the input clock.
    70847: 04/06/30: Re: a question in the pci interface design
    70996: 04/07/05: Re: new Lattice FPGAs vs Cyclone and SpartanIII
    71026: 04/07/06: Re: new Lattice FPGAs vs Cyclone and SpartanIII
    71060: 04/07/07: Re: new Lattice FPGAs vs Cyclone and SpartanIII
    71273: 04/07/13: Re: FPGA to PCI Bus Interface
    71288: 04/07/13: Re: new Lattice FPGAs vs Cyclone and SpartanIII
    71349: 04/07/15: Re: new Lattice FPGAs vs Cyclone and SpartanIII
    138482: 09/02/24: Re: Cyclone2 4-phase clock generation
Luc Claustres:
    54582: 03/04/14: Re: Hardware acceleration for raytracing purposes
Luc Deriemaeker:
    759: 95/02/24: Lattice ispLSI starter kit
Luc Nantel:
    19283: 99/12/09: Re: EEPROM for spartan xl series FPGA?
    19491: 99/12/25: Is Actel antifuse FPGA realy secure ?
<luca.haab@ascom.ch>:
    28959: 01/01/31: XILINX FPGA programming through JTAG
<luca_grossi@hotmail.com>:
    109344: 06/09/24: Generating Core component
    110567: 06/10/17: 64 bit division compensate NCO
    110691: 06/10/19: Re: 64 bit division compensate NCO
    110700: 06/10/19: Re: 64 bit division compensate NCO
<lucaroccasalva@gmail.com>:
    116112: 07/03/01: Help with Partial Reconfiguration on Spartan3
    116421: 07/03/08: XILINX ISE PAR error: CLK0_BUFG_INST is not placed
Lucas:
    85644: 05/06/13: Xilinx LVDS and SCSI
Lucian Fogoros:
    9368: 98/03/07: Correlation-continued
Luciano Lavagno:
    3997: 96/08/31: Announcement: public release of embedded system design software
Lucien Murray-Pitts:
    35399: 01/10/02: Re: Spartan II use of GCK[0:3] pins as general inputs
LucienZ:
    143292: 09/09/30: Implement ARM cores on a FPGA chip?
    143334: 09/10/02: Re: Implement ARM cores on a FPGA chip?
    143335: 09/10/02: Re: Implement ARM cores on a FPGA chip?
    143336: 09/10/02: Re: Implement ARM cores on a FPGA chip?
    143347: 09/10/04: Re: Implement ARM cores on a FPGA chip?
    143348: 09/10/04: Re: Implement ARM cores on a FPGA chip?
    143351: 09/10/04: Re: Implement ARM cores on a FPGA chip?
    143376: 09/10/07: Re: Implement ARM cores on a FPGA chip?
    143384: 09/10/07: Re: Implement ARM cores on a FPGA chip?
    143398: 09/10/09: Re: Implement ARM cores on a FPGA chip?
    143399: 09/10/09: Re: Implement ARM cores on a FPGA chip?
    143408: 09/10/09: Re: Implement ARM cores on a FPGA chip?
    143414: 09/10/10: Re: Implement ARM cores on a FPGA chip?
    143834: 09/10/28: ML605 Evaluation Kit and FPGA Mezzanine Connectors (FMC) ?
    143838: 09/10/28: Re: ML605 Evaluation Kit and FPGA Mezzanine Connectors (FMC) ?
    144214: 09/11/20: Re: ML605 Evaluation Kit and FPGA Mezzanine Connectors (FMC) ?
luciorech:
    119534: 07/05/22: PLB behaviors strangely during burst transactions
    119540: 07/05/22: PLB behaviours strangely during burst transactions
    119567: 07/05/22: Re: PLB behaviours strangely during burst transactions
    119594: 07/05/23: Re: PLB behaviours strangely during burst transactions
1 Lucky Texan:
    152174: 11/07/15: Re: Very Slow Circuits (Was: Fast Circuits)
Ludger Schulte:
    3537: 96/06/17: XC4025
ludovic aubel:
    58259: 03/07/18: Re: How fast coregen FIR?
Ludovic Lemenuel:
    27929: 00/12/15: Semiconductor process engineers needed
    27928: 00/12/15: Semiconductor process engineers needed
Ludwig Lenz:
    94481: 06/01/12: Xilinx Vertex II Pro with tow VDEC videodevices
    97839: 06/02/28: XUP Vertex II J5 Expansionheader Voltage
    114869: 07/01/25: xilinx 8.2 xps debug problems
<Lue.Her@gmail.com>:
    122057: 07/07/18: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
Luhan:
    107638: 06/08/30: Re: Performance Appraisals
    107995: 06/09/03: Re: Please help me with (insert task here)
    108021: 06/09/04: Re: Please help me with (insert task here)
Luhan Monat:
    64387: 03/12/31: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
luigi:
    95416: 06/01/23: Configuration Spartan 3
    95468: 06/01/23: Re: Configuration Spartan 3
Luigi:
    19056: 99/11/25: Analog
    39263: 02/02/05: Adding internal JTAG chains on FPGA
    39366: 02/02/07: Re: Adding internal JTAG chains on FPGA
    39943: 02/02/22: Pin assignments in QUARTUS
    39991: 02/02/23: Re: Pin assignments in QUARTUS
    40177: 02/03/01: Re: Pin assignments in QUARTUS
    40977: 02/03/19: Signal driven by a "configuration done" event
    41049: 02/03/20: VHDL OPEN association element error in QUARTUS compiler
    55666: 03/05/15: Doubling data output without DRR banks and without double clock frequency
Luigi Funes:
    18567: 99/11/01: 16 bit counter in Abel
    18616: 99/11/03: Re: 16 bit counter in Abel
    19306: 99/12/12: Re: Lattice ispLSI Security
    19398: 99/12/19: Re: Speed grade
    21799: 00/04/01: Re: What's so good about antifuse???
    30517: 01/04/12: Re: help with ABEL-HDL and CPLDs
luigi funes:
    26594: 00/10/21: Re: Hay Ray -
    28323: 01/01/06: Altera free software
    29424: 01/02/21: Re: ALtera CPLD
    30039: 01/03/21: backup FLEX10K
    30243: 01/03/29: Re: Encryption Bitstrems
    30325: 01/04/02: Re: pseudo random numbers
    30388: 01/04/05: Re: RC4/ARC4 on an FPGA.
    30402: 01/04/06: Re: High Speed PLA/FPGA
    30588: 01/04/18: clocking on both edges
    30615: 01/04/19: Re: Wanted: ISA bus implementation for Xilinx
    31750: 01/06/05: Re: Xilinx Configuration Bitstream
    34147: 01/08/15: Re: Building a clock out of a PLD
    35479: 01/10/07: Altera LCELL and output pins
    35741: 01/10/16: Re: System Gates
    38471: 02/01/15: Re: remainder
    40929: 02/03/18: laser programmed FPGAs
    41064: 02/03/20: Re: MAX7000 bypass capasitances
    41876: 02/04/09: differences betw. EPF10K30E and EP1K30?
    41890: 02/04/10: Re: FPGA Partioning
    42927: 02/05/07: Re: OP-AMP in FPGA
    47516: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
    47663: 02/10/01: xilinx free logic analyzer?
    47669: 02/10/01: Re: xilinx free logic analyzer?
    47691: 02/10/02: Re: xilinx free logic analyzer?
    47798: 02/10/04: Clear Logic is definitively dead?
    49626: 02/11/18: programming Altera EPC1
    49627: 02/11/18: Re: max3000
    51004: 02/12/26: Re: Altera Quartus or MAX Plus?
    51017: 02/12/26: Re: Altera Quartus or MAX Plus?
Luigi Padovani:
    73584: 04/09/24: Nios Addressing
luigi raffo:
    62698: 03/11/05: parameter in top module in XILINX ISE 6.1.02
<luigi_funes@my-deja.com>:
    19332: 99/12/14: Re: Lattice ispLSI Security
luiguo:
    93836: 06/01/01: FPGA running diff with simulation
    93842: 06/01/01: Re: FPGA running diff with simulation
    105731: 06/07/31: Re: Verilog case statements
Luis Alberto Guanuco:
    155797: 13/09/06: Re: Xilinx Platform Cable USB protocol specifications and/or
Luis Cupido:
    43044: 02/05/10: altera 7000's
    43210: 02/05/16: Re: extend jtag downloadcable
    43673: 02/05/29: Re: Frequency synthesiser
    89139: 05/09/06: Cyclone conf flash - 25p10 !
    89141: 05/09/06: Re: Reprogramming one MAXII EPM1270 vs security bit set
    89179: 05/09/07: Re: Cyclone conf flash - 25p10 !
    89181: 05/09/07: Re: Cyclone conf flash - 25p10 !
    89190: 05/09/07: Re: Cyclone conf flash - 25p10 !
    89276: 05/09/10: Re: Cyclone conf flash - 25p10 !
    89382: 05/09/14: Re: Is a CPLD appropriate for this triple PWM application?
    89426: 05/09/15: Re: Is a CPLD appropriate for this triple PWM application?
    89471: 05/09/15: Re: Is a CPLD appropriate for this triple PWM application?
    154383: 12/10/19: tell QuartusII to use registers and not RAM
    154389: 12/10/20: Re: tell QuartusII to use registers and not RAM
Luis de Funes:
    13524: 98/12/07: The best PLD?
    13530: 98/12/08: ALTERA isp cable
    14733: 99/02/13: cpld internal oscillator
    15067: 99/03/04: Wath's "XOR adjacent path"?
    15166: 99/03/10: Re: Function generator in Xilinx
    15202: 99/03/12: Re: Infidels Invited, Heathens Highly Welcome !
    15323: 99/03/18: Re: Want to learn about FPGA.
Luis Sanchez Fernandez:
    3607: 96/07/03: CHDL '97
    4146: 96/09/18: CHDL '97
    5325: 97/02/07: CHDL '97 Advance Programme
Luis Vaccaro:
    71660: 04/07/27: Re: 1GHz FPGA counters
    88148: 05/08/10: Re: MPEG-2 links please
    91363: 05/11/04: Re: I have received a job offer
    91364: 05/11/04: Re: I have received a job offer
Luis Yanes:
    16044: 99/04/29: Re: Xilinx FPGA eval board
    17236: 99/07/13: Digital modulator? Synthesisable Sin(x) funct.
    17446: 99/07/28: Re: Digital modulator? Synthesisable Sin(x) funct.
    17447: 99/07/28: Re: Digital modulator? Synthesisable Sin(x) funct.
    17464: 99/07/29: Re: Digital modulator? Synthesisable Sin(x) funct.
    17494: 99/08/02: Re: Digital modulator? Synthesisable Sin(x) funct.
    17495: 99/08/02: Re: Digital modulator? Synthesisable Sin(x) funct.
    18871: 99/11/19: Re: How many bits in an FPGA bitstream?
    23571: 00/07/01: Re: Looking for 'FREE' FPGA software
    23618: 00/07/03: Re: Looking for 'FREE' FPGA software
    28653: 01/01/19: Re: FSM encoding
Luis_circuits:
LuisGomezMelis:
    20211: 00/02/01: RE: INTERNET CONSULTANT NEEDED
    20212: 00/02/01: RE:INTERNET CONSULTANT NEEDED
Luiz Andre' Barroso:
    86: 94/08/11: Re: Wanted: Literature on Reconfigurable Systems..
    321: 94/10/19: USC Multiprocessor Testbed on the WWW
Luiz Carlos:
    54744: 03/04/17: spartan-3 vs cyclone
    54920: 03/04/22: Re: spartan-3 vs cyclone
    55662: 03/05/15: Re: Spartan3 DLL?
    56272: 03/06/02: MicroBlaze and Spartan3
    56328: 03/06/03: Re: MicroBlaze and Spartan3
    56335: 03/06/03: Re: DES-encrypt, Spartan3, was Re: FPGA's an Flash
    57406: 03/06/30: Re: SPARTAN-3 vs. VIRTEX-II
    57407: 03/06/30: Re: MIPS instruction set?
    57436: 03/06/30: Re: SPARTAN-3 vs. VIRTEX-II
    57468: 03/07/01: Re: SPARTAN-3 vs. VIRTEX-II
    57475: 03/07/01: Re: MIPS instruction set?
    57505: 03/07/01: Re: SPARTAN-3 vs. VIRTEX-II
    57533: 03/07/02: Re: SPARTAN-3 vs. VIRTEX-II
    57535: 03/07/02: Re: SPARTAN-3 vs. VIRTEX-II
    59566: 03/08/21: Re: DCM vs state machine
    59587: 03/08/22: Re: DCM vs state machine
    59752: 03/08/27: Re: Thinking out loud about metastability
    59777: 03/08/28: Re: Thinking out loud about metastability
    59778: 03/08/28: Re: Thinking out loud about metastability
    59780: 03/08/28: Input comparator
    59802: 03/08/28: Re: Thinking out loud about metastability
    59812: 03/08/28: Re: Thinking out loud about metastability
    59851: 03/08/29: Re: Thinking out loud about metastability
    59918: 03/09/01: Re: Thinking out loud about metastability
    59550: 03/08/21: Re: DCM vs state machine
    59942: 03/09/02: Re: Input comparator
    59989: 03/09/03: Re: Thinking out loud about metastability
    59993: 03/09/03: Re: Input comparator
    59994: 03/09/03: Re: Input comparator
    60045: 03/09/04: Re: Input comparator
    60047: 03/09/04: More about metastability
    60049: 03/09/04: Re: Thinking out loud about metastability
    60081: 03/09/04: Re: More about metastability
    60266: 03/09/09: Re: Original (5V) Xilinx Spartan ?
    60268: 03/09/09: Re: Original (5V) Xilinx Spartan ?
    60302: 03/09/10: Re: Original (5V) Xilinx Spartan ?
    60304: 03/09/10: Re: Original (5V) Xilinx Spartan ?
    60306: 03/09/10: Re: opinions are OK
    61004: 03/09/26: Re: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
    62628: 03/11/03: Re: Shannon Entropy for Black Holes
    71991: 04/08/05: Re: New WinFilter Digital Filter design freeware tool release available.
    72480: 04/08/20: Re: Spartan III I/O robustness
    72546: 04/08/24: Altera MAX II
    72598: 04/08/26: Re: Altera MAX II
    73229: 04/09/16: Re: Need some help with some technical claims...
    74167: 04/10/05: Re: FPGA vs ASIC area
    74170: 04/10/05: Re: meaning of "field-programmable" in FPGA
    74286: 04/10/07: XILINX SHIPS ONE MILLION SPARTAN-3 FPGAS
    74318: 04/10/07: Re: XILINX SHIPS ONE MILLION SPARTAN-3 FPGAS
    74579: 04/10/14: Re: Where to buy cheap MAXII CPLD?
Luk Michel St.Onge:
    31460: 01/05/25: Re: FPGA
Lukas Louw:
    12108: 98/09/29: Simple programmable device suggestions please?
Lukasz Salwinski:
    55602: 03/05/13: Re: ISE WebPack under Linux (use of command line tools)
    56904: 03/06/18: Re: Spartan3 in WebPack
    56965: 03/06/19: Re: Spartan3 in WebPack
    70867: 04/06/30: Re: Xilinx $99 Spartan-3 kit
    72118: 04/08/09: nallatech ?
    72176: 04/08/10: Re: nallatech ?
    75070: 04/10/25: Re: Altium board again
    77106: 04/12/22: Re: Open source FPGA EDA Tools
    77623: 05/01/12: Re: Looking for low-cost protoboards.
    78023: 05/01/22: Xilinx: xst internal error
    79945: 05/02/26: Re: programming 2 pulses using VHDL
    80194: 05/03/02: Re: Xilinx ISE7.1
    81319: 05/03/21: Re: Xilinx ISE 7.1 - Can this get any worse?
    81568: 05/03/27: Re: Multi-FPGA PCB data aggregation?
    84183: 05/05/13: floorplanning
    84227: 05/05/15: Re: floorplanning
    85591: 05/06/11: Re: X-Fest devkit order leadtimes & software silliness....
    101665: 06/05/04: Re: Xilinx 3s8000?
    101692: 06/05/04: Re: Xilinx 3s8000?
    101747: 06/05/05: Re: Xilinx 3s8000?
Luke:
    35155: 01/09/24: Please help in Cossap and VHDL ..FPGA sintesys
    89578: 05/09/19: Re: Modelsim XE, what's the latest version?
    90616: 05/10/17: Re: FPGA timming
    102016: 06/05/09: Superscalar Out-of-Order Processor on an FPGA
    102025: 06/05/09: Re: Superscalar Out-of-Order Processor on an FPGA
    102027: 06/05/09: Re: Superscalar Out-of-Order Processor on an FPGA
    102035: 06/05/09: Re: Superscalar Out-of-Order Processor on an FPGA
    102039: 06/05/09: Re: Superscalar Out-of-Order Processor on an FPGA
    102072: 06/05/10: Re: Superscalar Out-of-Order Processor on an FPGA
    102097: 06/05/10: Re: Superscalar Out-of-Order Processor on an FPGA
    102201: 06/05/11: Multiple Write Port Register Files
    102258: 06/05/12: Re: Multiple Write Port Register Files
    103372: 06/05/31: SystemVeriling Synthesis for Xilinx FPGAs
    103373: 06/05/31: Re: SystemVeriling Synthesis for Xilinx FPGAs
Luke Darnell:
    84242: 05/05/16: Xilinx : Clock Swallowing
    84600: 05/05/22: Virtex4 Block Ram : ISE6.3 Problem
Luke Roth:
    21837: 00/04/03: Re: Xilinx student edition, version 1.5
    29633: 01/03/02: Re: What about speed-grade?
    30025: 01/03/20: BG575 socket recommendation?
    30833: 01/04/30: Re: Multiple state machines in altera AHDL
    31939: 01/06/08: Re: Cheap FPGA's
    34152: 01/08/15: Re: Reconfigurable Computational Accelerator
    34204: 01/08/16: Re: Reconfigurable Computational Accelerator
    36447: 01/11/08: Re: FPGA Wish list
Luke Scharf:
    26992: 00/11/06: Re: ISO C -> VHDL translator, prefer open source
<luke@kdine.com>:
    7952: 97/11/02: $1000/wk Donating Sperm
Lukose Ninan:
    17808: 99/09/06: Re: QuickLogic FPGAs
    17809: 99/09/06: TI C30 DSP core in FPGA?
    29372: 01/02/16: Re: Design of a divide by 6.5 counter ?
    30713: 01/04/25: Re: Any good sources for digital rf processing ?
Luong Do:
    9197: 98/03/01: Xilinx FPGA HOWTO or FAQ
Luong V. Do:
    10365: 98/05/14: HELP: Top Level Design with Schematic Editor using XNF from FPGA EXPRESS
Lupu Cristian:
    17838: 99/09/10: Help
lusch:
    146237: 10/03/09: Spartan3AN DDR2 - bad writing zeros
    146249: 10/03/09: Re: Spartan3AN DDR2 - bad writing zeros
    146282: 10/03/10: Re: Spartan3AN DDR2 - bad writing zeros
    147759: 10/05/22: Re: MIG v3.0 inputs signal
Luthfi Kisbiono Arif:
    10619: 98/06/06: Re: Example of 8051 codes to configure Xilinx fpga
Lutz Buettner:
    2481: 95/12/15: problem with statemachine
Lutz Kleberhoff:
    19432: 99/12/21: Re: AMD FLASH ?
    22699: 00/05/18: Re: PCI & Virtex
Lutz Lisseck:
    32264: 01/06/21: ispDesignExpert fitter question
luu:
    122406: 07/07/26: why my usb cable can established,but can't download??? xilinx
luu thanh trung:
    30276: 01/03/30: Re: Xilinx GSR in Verilog simulations
luudee:
    137982: 09/02/03: xilinx platform usb cable linux troubles
    138027: 09/02/04: Re: xilinx platform usb cable linux troubles
    138034: 09/02/04: Re: xilinx platform usb cable linux troubles
    138038: 09/02/04: REWARD $$$ Xilinx USB Platform Cable problems
    138043: 09/02/04: Re: REWARD $$$ Xilinx USB Platform Cable problems
    138069: 09/02/05: Re: dual processor PC for PPR - are they worth the extra cost?
    138070: 09/02/05: Re: dual processor PC for PPR - are they worth the extra cost?
    138090: 09/02/06: job offer: PLB v4.6 expert, freelance
    138135: 09/02/07: Re: Rotary Encoder - Microblaze and ML505
    138256: 09/02/10: Xilinx FAT FS library
    138266: 09/02/11: Re: Xilinx FAT FS library
    138309: 09/02/15: Microblaze (7.10d) Interrupt Handler problems
    138312: 09/02/15: Re: Microblaze (7.10d) Interrupt Handler problems
    138494: 09/02/24: mb-gcc producing incorrect code ???
    138499: 09/02/25: Re: mb-gcc producing incorrect code ???
    138500: 09/02/25: Re: mb-gcc producing incorrect code ???
    138542: 09/02/26: Re: mb-gcc producing incorrect code ???
    139983: 09/04/22: ISE 11.1 still no MP support :(
    140613: 09/05/20: Muli-Cycle Path Constrains in RTL
    140614: 09/05/20: Re: Online tool that generates parallel CRC and Scrambler
    140715: 09/05/22: Re: Muli-Cycle Path Constrains in RTL
    140783: 09/05/26: 11.1 & USB cable drivers
    140791: 09/05/26: Re: 11.1 & USB cable drivers
    141294: 09/06/16: BSB/XBD Problem
    141652: 09/07/02: XILINX: verilog is not supported as a language, using usenglish
    141703: 09/07/03: Re: XILINX: verilog is not supported as a language, using usenglish
    141704: 09/07/03: Re: 50 000 registered users at OpenCores.org
    141707: 09/07/04: Re: 50 000 registered users at OpenCores.org
    141934: 09/07/17: Re: Do you prefer paper or plastic... er, I mean paper or e-books?
    141973: 09/07/20: Re: Strange FPGA behavior
    142091: 09/07/24: Re: Xilinx ISE 11.x lossage
    142488: 09/08/12: Re: Peter Alfke
    142984: 09/09/12: Re: ANN: Coding style guidance for FPGA memory
    142985: 09/09/12: Re: Behavior of crystal oscillator?
    143017: 09/09/15: Re: ANN: Coding style guidance for FPGA memory
    143018: 09/09/15: Re: ANN: Coding style guidance for FPGA memory
    143682: 09/10/21: EDK/DDR Problem with HTG-V5-DDR3-PCIE Development Board
    143701: 09/10/21: Re: Teammates, interested?
    143790: 09/10/26: V5 GTX Receiver Detect
    143801: 09/10/26: Re: V5 GTX Receiver Detect
    143813: 09/10/27: Re: V5 GTX Receiver Detect
    143877: 09/10/31: Re: Chipscope with Verilog
    143908: 09/11/02: Re: V5 GTX Receiver Detect
    143988: 09/11/05: Re: OK Xilinx users, it's time I was let in on the joke...
    144015: 09/11/07: Re: OK Xilinx users, it's time I was let in on the joke...
    146400: 10/03/15: Re: Looking for a G.723.1 codec IP core for Xilinx FPGA
    146621: 10/03/24: Re: wishbone
    146622: 10/03/24: Re: Xilinx Spartan6 Virtex6 Rollout
    146790: 10/03/28: Re: USB 3.0 implementation on FPGA
    146888: 10/03/31: FMC Boards ?
    146901: 10/03/31: Re: FMC Boards ?
    146924: 10/04/01: Re: FMC Boards ?
    147053: 10/04/12: Re: FMC Boards ?
    147234: 10/04/19: Re: FMC Boards ?
    147383: 10/04/25: Re: voltage divider calcs
    147631: 10/05/10: Re: FMC Boards ?
    147932: 10/06/03: Re: Job experience? How?
    149893: 10/12/01: Re: What should I use for highspeed/low latency communication beteen
    150213: 11/01/01: USB Cables again
    151446: 11/04/09: Re: Fun with Xilinx Constraints
    151447: 11/04/09: Re: IP Core Delivery Format Info
    156420: 14/04/03: Digilent Drivers stuck with Fedora 20
LUUTHANHTRUNG:
    33633: 01/08/01: Xilinx Foundation 2.1i Update
    33676: 01/08/02: Core 2.1i
    33805: 01/08/05: Core Generation 2.1i
    33806: 01/08/05: Core Generation 2.1i
<lux.junip@gmail.com>:
    134732: 08/08/28: Re: Saving PAR Constraints
Luzerne:
    115977: 07/02/27: Re: Xilinx ISE webpack in Ubuntu?
    116140: 07/03/02: Re: Xilinx ISE webpack in Ubuntu?
    116770: 07/03/17: Re: Xilinx Platform cable USB and impact on linux without windrvr
    117103: 07/03/23: Re: Xilinx Platform cable USB and impact on linux without windrvr
    117179: 07/03/25: Re: Xilinx Platform cable USB and impact on linux without windrvr
    117305: 07/03/27: Re: Xilinx Platform cable USB and impact on linux without windrvr
<lwatts@world.std.com>:
<lwibov@yahoo.com>:
<lyfieryflame@gmail.com>:
    125438: 07/10/25: compile EDIF(generated by Celoxica DK4) using Quartus II
Lyle Kraft:
    1879: 95/09/14: Anyone using Altera 8820A ?
    1962: 95/09/25: Re: Anyone using Altera 8820A ?
lynch:
    59774: 03/08/28: We are debugging a pci board and met some difficulties.
Lyndon Amsdon:
    50987: 02/12/24: Altera Quartus or MAX Plus?
    50999: 02/12/25: Re: Altera Quartus or MAX Plus?
    51013: 02/12/26: Re: Altera Quartus or MAX Plus?
    51024: 02/12/26: Re: Altera Quartus or MAX Plus?
Lynn Ross:
    3811: 96/08/05: Job Opportunity-Hughes Research Laboratories
    3952: 96/08/23: Job Opportunity-Hughes Research Laboratories
Lynn West:
    1764: 95/08/28: Actel PCI App Note
lyo34:
    151514: 11/04/16: XST - timing constraints of the combinatorial logic
    151592: 11/04/22: Re: XST - timing constraints of the combinatorial logic
lyonscf@gmail.com:
    126885: 07/12/05: Re: Researching Reconfigurable Computing
<lyonscf@gmail.com>:
    126796: 07/12/02: Researching Reconfigurable Computing
<lyqin@cti.com.cn>:
    30151: 01/03/26: What's new in Synplify 6.20 than 6.13
lyra:
    120569: 07/06/11: Re: Altera FPGA programming problem.
lyttlec:
    116833: 07/03/19: alliance tooset on Linux
lzh:
    5931: 97/03/27: verilog to VHDL tools needed!
lzh08:
    109203: 06/09/21: please tell me how to learn testbench?
    109242: 06/09/22: who can give me source code about ISA BUS ?
    109376: 06/09/25: Re: who can give me source code about ISA BUS ?
    109379: 06/09/25: sytemverilog supported by quartus 6.0?
    118331: 07/04/24: I make a usb blaster for altera by myself!
    125055: 07/10/16: RTM ERROR:fail to get the remote thread list.
<lzh@bd748.pku.edu.cn>:
    8126: 97/11/19: what is metastability time of a flip_flop
    8499: 97/12/25: how to instantiate an LCELL in VHDL source file
<lzkelley@gmail.com>:
    124962: 07/10/12: NgdBuild:455 Multiple Drivers


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015Jan2015

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search