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Messages from 132100

Article: 132100
Subject: Re: Problem writing quadrature decoder
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 13 May 2008 14:15:18 -0700 (PDT)
Links: << >>  << T >>  << A >>
Here is my bird's eye conclusiont:
The least demanding shaft encoders use two sets of contacts to read
manual rotation. Usually there is a mechanical detent, which precludes
any resolution finer than the detent. Activation speed is max 10 or 20
Hz.
My original proposal serves that purpose just fine, and is very simple
and cheap (4 LUTs)

At the other extreme are high-speed optical quadrature encoders in
robotics, where they might control an arm that moves up to a few
meters per second with a resolution of 1 micrometer, which means a few
MHz. There is no detent, and highest resolution without hysteresis is
desirable. The computer can suppress counter changes due to mechanical
oscillations. John H. presented a synchronous circuit that covers that
application, and is also very simple.

It has been an interesting, albeit lengthy discussion.
Peter Alfke

Article: 132101
Subject: Re: 5 V oscillator output to GCLK
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 13 May 2008 14:21:20 -0800
Links: << >>  << T >>  << A >>
Kolja Sulimma wrote:

> On 9 Mai, 23:33, Jon Elson <el...@wustl.edu> wrote:

>> A long clock trace (bad idea, anyway) fed with a series
>> resistor is essentially a lumped-constant low-pass filter.

> No. It is a transmission line with an impedance matched driver. 
> You can get any frequency accross that setup that you like.

If matched with the characteristic impedance it works
like a transmission line, if not it looks like a capacitor
or inductor depending on the termination.

The phone system (US, anyway) seems to use 600 ohm termination
on about 100 ohm UTP cable.  The result is that the cable looks
like a capacitor and, for long lines, results in a high frequency
drop off.

http://en.wikipedia.org/wiki/Loading_coil

The telephone solution is loading coils that increase the
series inductance (on average) resulting in a flatter
response to the required 4kHz, and a sharp drop after that.

The effect also shows up in antenna design when the frequency
doesn't match the appropriate length for the antenna elements.

As previously stated, though, it is only necessary to match
one end.  If the sink impedance is matched the voltage will
be reduced appropriately by the series source resistor
and the cable impedance as a voltage divider.

-- glen


Article: 132102
Subject: power supply noise margin
From: kislo <kislo02@student.sdu.dk>
Date: Tue, 13 May 2008 15:23:03 -0700 (PDT)
Links: << >>  << T >>  << A >>
What noise margin should a power distribution network be able to
delivery on the 1.2V, 2.5V and 3.3V supply for a Spartan3 ? is +-5%
noise budget ok for these supplies ?

Article: 132103
Subject: Re: Problem writing quadrature decoder
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 13 May 2008 14:26:21 -0800
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
(snip of mechanical encoder)

> At the other extreme are high-speed optical quadrature encoders in
> robotics, where they might control an arm that moves up to a few
> meters per second with a resolution of 1 micrometer, which means a few
> MHz. 

Just another thought, what happens for slow moving systems
and an optical encoder where it might generate a voltage
in between '1' and '0'?

-- glen


Article: 132104
Subject: Re: Problem writing quadrature decoder
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Wed, 14 May 2008 10:39:39 +1200
Links: << >>  << T >>  << A >>
glen herrmannsfeldt wrote:
> Peter Alfke wrote:
> (snip of mechanical encoder)
> 
>> At the other extreme are high-speed optical quadrature encoders in
>> robotics, where they might control an arm that moves up to a few
>> meters per second with a resolution of 1 micrometer, which means a few
>> MHz. 
> 
> 
> Just another thought, what happens for slow moving systems
> and an optical encoder where it might generate a voltage
> in between '1' and '0'?

Normally hysteresis is employed to handle that.
-jg


Article: 132105
Subject: Re: Problem writing quadrature decoder
From: John_H <newsgroup@johnhandwork.com>
Date: Tue, 13 May 2008 17:03:36 -0700 (PDT)
Links: << >>  << T >>  << A >>
glen herrmannsfeldt wrote:
<snip>
>
> Just another thought, what happens for slow moving systems
> and an optical encoder where it might generate a voltage
> in between '1' and '0'?
>
> -- glen

With the asynchronous crossing, the registered quadrature encoder
signals in the synchronous domain will come to a conclusion as to what
that intermediate voltage should be: high or low.  This will often
result in chatter between two quadrants in much the same way as switch
bounce because the threshold voltage may be modulated by noise giving
a different full-scale registered result on various consecutive
cycles.

The techniques is still completely stable.  That's why quadrature
encoders are so great.

- John_H

Article: 132106
Subject: Re: Problem writing quadrature decoder
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Wed, 14 May 2008 12:57:28 +1200
Links: << >>  << T >>  << A >>
John_H wrote:
> glen herrmannsfeldt wrote:
> <snip>
> 
>>Just another thought, what happens for slow moving systems
>>and an optical encoder where it might generate a voltage
>>in between '1' and '0'?
>>
>>-- glen
> 
> 
> With the asynchronous crossing, the registered quadrature encoder
> signals in the synchronous domain will come to a conclusion as to what
> that intermediate voltage should be: high or low.  This will often
> result in chatter between two quadrants in much the same way as switch
> bounce because the threshold voltage may be modulated by noise giving
> a different full-scale registered result on various consecutive
> cycles.
> 
> The techniques is still completely stable.  That's why quadrature
> encoders are so great.

With the proviso that such slow edges should NOT be fed into a FPGA.
(they have tr/tf specs)

If you have a cpld with hysteresis pin option,
(Atmel ATF15xxBE, Xilinx XC2Cxx, Lattice 40xxZE ) then you
are ok.

-jg


Article: 132107
Subject: Re: power supply noise margin
From: austin <austin@xilinx.com>
Date: Tue, 13 May 2008 17:59:51 -0700
Links: << >>  << T >>  << A >>
kislo,

The recommended limits on voltages include noise, yes.

Austin

Article: 132108
Subject: Re: Problem writing quadrature decoder
From: Peter Alfke <alfke@sbcglobal.net>
Date: Tue, 13 May 2008 20:32:03 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 13, 5:57=A0pm, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> With the proviso that such slow edges should NOT be fed into a FPGA.
> (they have tr/tf specs)
>
> If you have a cpld with hysteresis pin option,
> (Atmel ATF15xxBE, Xilinx XC2Cxx, Lattice 40xxZE ) then you
> are ok.
>
> -jg

You can feed any FPGA with excessive transition-time signals, as long
as you understand the consequences:
The signal will pick up noise and thus create digital glitches as it
moves through the threshold, and there will be some cross-current
through the inverter, adding some power consumption, but never causing
any damage. A slow-transitioning clock is an invitation to disaster,
but a logic input usually causes no harm. And you can convert any 2
pins into a one-bit Schmitt input, just with 2 external resistors.
Peter Alfke


Article: 132109
Subject: Re: Problem writing quadrature decoder
From: Peter Alfke <alfke@sbcglobal.net>
Date: Tue, 13 May 2008 20:56:38 -0700 (PDT)
Links: << >>  << T >>  << A >>
Let me try a conclusion after more than 70 postings:

Rotary (or linear) quadrature shaft encoder.
After a lengthy exchange of ideas, we found that there are only two
winning circuits.
Both are equally simple and inexpensive, and both can be used from
zero speed to multi-MHz speed. And none has cumulative errors.

Circuit A was presented by Peter Alfke, and it guarantees the
suppression of all contact bounce and erratic contact behavior,
completely isolating the position-indicating counter from such
disturbances. The design pays for this with an angular or linear
hysteresis (a.k.a. electronic backlash), that limits its resolution.

Circuit B was presented by John_H, and it guarantees the best possible
resolution. This design pays for this with a possibly erratic foward/
backward oscillating content in the counter that indicates the shaft
position.

Either design does the best possible job, and thus represents a
perfect engineering compromise.

Peter Alfke




Article: 132110
Subject: Yay! We're done with the quadrature encoder!
From: John_H <newsgroup@johnhandwork.com>
Date: Tue, 13 May 2008 22:26:34 -0700
Links: << >>  << T >>  << A >>
Aren't we?  :-)

Article: 132111
Subject: Re: Problem writing quadrature decoder
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Wed, 14 May 2008 17:29:54 +1200
Links: << >>  << T >>  << A >>
Hi Peter,

Peter Alfke wrote:
> Let me try a conclusion after more than 70 postings:
> 
> Rotary (or linear) quadrature shaft encoder.
> After a lengthy exchange of ideas, we found that there are only two
> winning circuits.
> Both are equally simple and inexpensive,

Not if you count registers ;)
With Xilinx tools, targeting a Xilinx CPLD, this used 8 more registers 
than the possible minimum.

> and both can be used from
> zero speed to multi-MHz speed. And none has cumulative errors.

...when used with a clean Quadrature signal.

> 
> Circuit A was presented by Peter Alfke, and it guarantees the
> suppression of all contact bounce and erratic contact behavior,
> completely isolating the position-indicating counter from such
> disturbances. The design pays for this with an angular or linear
> hysteresis (a.k.a. electronic backlash), that limits its resolution.

This is actually a pre-filter, so it can be used with any 'standard'
quadrature encoder.
If you want Circuit A to not count on illegal states, use this line:
rotary_event <= (rotary_q1 xor delay_rotary_q1)
              xor (rotary_q2 xor delay_rotary_q2);
-and optionally- (for those who think errors need reporting )
rotary_error <=  (rotary_q1 xor delay_rotary_q1)
              and (rotary_q2 xor delay_rotary_q2);		
		

> Circuit B was presented by John_H, and it guarantees the best possible
> resolution. This design pays for this with a possibly erratic foward/
> backward oscillating content in the counter that indicates the shaft
> position.

This is a more classic version, but with one packing twist :
It uses the two counter LSBs as the follow-nodes, whilst
that section of Circuit A uses two more registers.
Circuit A also consumes registers for Event and Direction,
and has more latency.

(in a fpga the higher register cost of Circuit A might not
bother anyone)

There was another 'Circuit C', submitted by nospam,
a more common 4 register vesion, but with illegal states
properly handled. It is very easy to follow, as it
tabulated the 16 states (8 as comments).
[Cost is 2 more registers, than B.]

Below is a version of Circuit B, extended to
a) Catch illegal states (for those who think that matters )
b) Does not count on illegal states. Instead, waits one click on POR

You can, of course, optionally add the Sticky-state filter of Circuit A
to the front of B or C, if you want to reduce possible visual
flicker.

Which I think covers all the bases, for everyone... :)

-jg


module
   whatCouldGoWrong
   ( input            clk
   , input      [1:0] quad
   , output reg [7:0] count
   , output OutByTwoErr
   );

// used for an asynchronous boundary crossing
   reg [1:0] rQuad;
// change the quadrature input to binary
   wire [1:0] binQuad = {rQuad[1],^rQuad[1:0]};
//   +1 is 0, -1 is 1, 2 is init only
   wire dir = (binQuad - count[1:0]) >> 1;
// Sense if out by  Plus/Minus ONE - IF equal, or out by 2, ignore
   wire OutByOne = ( count[1:0]-binQuad == 2'b01 )
                 | ( binQuad-count[1:0] == 2'b01 );

// If out by 2 frequently, your CLK, and/or sensor need attention!
// Can feed into an Error counter ( see some CAN Bus controllers )
   assign OutByTwoErr = ( count[1:0]-binQuad == 2'b10 )
                      | ( binQuad-count[1:0] == 2'b10 );
   always @(posedge clk)
   begin
     rQuad <= quad;
     if ( OutByOne )
       count <= count + (dir ? -8'h1 : +8'h1);
   end
endmodule


Article: 132112
Subject: About the user defined instruction in APU
From: louis <yilu@ce.et.tudelft.nl>
Date: Wed, 14 May 2008 01:37:23 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi, all,


I am using ML410 board and EDK 8.2. I am trying to make a PPC system
with APU support. I set the UID_1 register according to the rule
described in charpter 4 of PowerPC 405 processor block reference
guide, and set the control configuration register to "0x0001". In the
software, I define the related user defined instruction 1 as
UDIFCM(a, b, c) { udi0fcm(a, b, c) } (the "udi0fcm" is predefined in
"xpseudo_asm_gcc.h")  and add the "mtmsr(XREG_MSR_APU_AVAILABLE)" in
the applicaiton. I simulated the system by using modelsim 6.1c. In the
simulation, everytime when the UDIFCM comes, the APU always gives a
pulse on the singnal "APUFCMFLUSH", however, the singnals
"APUFCMDECUDI, APUFCMDECODED..." which should be "1" when decoding the
UID keep "0". It looks like the APU can not recognize the UID. And
also the actual value of the instruction does not match the UID
register value I set. I tried to use the pre-defined load/store
instruction follow the xapp 717, they worked fine. Could anyone give
me some hints for the APU-UID? That will appreciated if someone can
share his experience!


Regards,

luyi

Article: 132113
Subject: Re: Yay! We're done with the quadrature encoder!
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Wed, 14 May 2008 20:48:51 +1200
Links: << >>  << T >>  << A >>
John_H wrote:
> Aren't we?  :-)

ssshhh!  ;)
[Peter needs to publish it yet...]
-jg


Article: 132114
Subject: xilinx beginner modelsim question
From: Zorjak <Zorjak@gmail.com>
Date: Wed, 14 May 2008 05:09:47 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi!!!

I started recently with the xilinx software and these days I am trying
to become more familiar with the modelsim and ise. I  wanted to test
some basic counter simulation in modelsim so I used this simple code

counter design file

library ieee ;
  use ieee.std_logic_1164.all;
   use ieee.std_logic_unsigned.all;

  entity counter is
   port(  clk:  in std_logic;
     reset:  in std_logic;
     enable:  in std_logic;
     count:  out std_logic_vector(3 downto 0)
  );
  end counter;

  architecture behav of counter is
    signal pre_count: std_logic_vector(3 downto 0);
    begin
      process(clk, enable, reset)
      begin
        if reset = '1' then
          pre_count <= "0000";
       elsif (clk='1' and clk'event) then
          if enable = '1' then
           pre_count <= pre_count + "1";
          end if;
        end if;
      end process;
      count <= pre_count;
  end behav;


testbench


  library ieee ;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_textio.all;
  use std.textio.all;

  entity counter_tb is
  end;

  architecture counter_tb of counter_tb is

 component counter
   port ( count : out std_logic_vector(3 downto 0);
          clk   : in std_logic;
          enable: in std_logic;
          reset : in std_logic);
 end component ;

 signal   clk    : std_logic := '0';
 signal   reset  : std_logic := '0';
 signal   enable : std_logic := '0';
 signal   count  : std_logic_vector(3 downto 0);

 begin

  dut : counter
 port map (
     count => count,
     clk   => clk,
    enable=> enable,
    reset => reset );


   clock : process
   begin
       clk<='0';
       wait for 5 ns;
       clk<='1';
       wait for 5 ns;
   end process clock;

   stimulus : process
   begin

     wait for 5 ns; reset  <= '1';
      wait for 4 ns; reset  <= '0';
      wait for 4 ns; enable <= '1';
    wait;
  end process stimulus;

but my simulation doesn't give right results. (I am getting U state on
all inputs). I am trying to find my mistake for more than 4 hours so
please if someone could help me please do it. I have defined new
project, I have compiled files and when I start simulation this
results repeat over and over again. I fell that this is stupid little
mistake but I can't find it no matter  what.

Thanks for any kind of help
Zoran

Article: 132115
Subject: demo board under 500usd
From: kclo4 <alexis.gabin@gmail.com>
Date: Wed, 14 May 2008 06:00:08 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi everyone,

I am considering to buy a fpga board for less than 500usd , I have
looked around and I found 2 board that look like nice :
the NIOS II development kit with a cycloneIII-25 that include a touch
screen LCD
and Spartan-3A DSP S3D1800A MicroBlaze Processor Edition

I would like to make some SDR project(i got a demo board of a adc
board 16bit/160mhz sampling freq) so i would like a fpga big enought
to make some dsp processing
I believe the Spartan 3 DSP 1800 is bigger than the cyclone 3 25 so i
think i will have more logic to make bigger design and also the xilinx
kit include a 1gbit connection that might be usefull to transfer data
to a pc

Does someone have any feedback on those boards?? which fpga is bigger?

thanks you

alexis

Article: 132116
Subject: problem in using ICAP
From: fmostafa <fatma.abouelella@ugent.be>
Date: Wed, 14 May 2008 07:30:53 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi ,
I'm trying to partially reconfigure my device (XC2VP30 on XUP board)
through ICAP. I have my ICAP attached to OPB which is attached to
PowerPC. In bitgen.ut file I have set the value of mode pins
(M2M1M0) to 1 (PULLUP). So it is not set on 101 which is JTAG mode. As
well the base address and high address of my HWICAP is 0x40200000 and
0x4200ffff as mentioned in the datasheet of HWICAP. Initially my OPB
clock frequency is 50 MHz . The
system contains a gpio,  a hwicap, a uartlite and an plb2opb
bridge all attached to the opb. . I'm also using EDK, ISE 9.1.

my problem that i tried to start with an exmaple to write to a
LUT and read form , this example is attached with the EDK
(xhwicap_lut.c)

i started with the example without major changes just i add
#define XHI_READ_DEVICEID_FROM_ICAP   XHI_XC2VP30
to define my part no
also in the UCF file i made a reservation for a LUT to be not in use
CONFIG PROHIBIT = SLICE_X0Y0 according to the guide lines in the
example

and it works until a XHwIcap_SetClbBits() and then nothing happen .

also i tried to follow the guide lines to Amir to use the
XHwIcap_CommandDesync()  but nothing change.
the status returned after the XHwIcap_Initialize() is XST_SUCCESS.
i don't know what is wrong , i guess that to start with an example is
an easy way to learn.

the following part of the code , the important command that i use


#define TEST_COL        0       /* Test Column for LUT */
#define TEST_ROW        0       /* Test Row for LUT    */


#define LUT_SIZE        16      /* The number of bits in a LUT */
#define NUM_READS       10      /* How many times to read back */

#define MAX_COUNT       0xFFFF  /* LUT hold 16-bit values */



static XHwIcap HwIcap;

Xuint8 LutWriteBuffer[LUT_SIZE];        /* Value written to the
LUT     */
Xuint8 LutReadBuffer[LUT_SIZE];         /* Value read back from the
LUT */


    XStatus Status;

    Xuint32 Count;           /* Current value to test */
    XStatus Status;          /* Return value          */
    Xuint32 Index;           /* Counter               */
    Xuint32 RowNum;          /* CLB Row location      */
    Xuint32 ColNum;          /* CLB Column location   */
    Xuint32 Slice;           /* CLB Slice location    */
#ifdef PAUSE
    Xuint8 Ch;               /* For reading from UART */
#endif /* PAUSE */


    /*
     * Initialize Hwicap device
     */

    Status = XHwIcap_Initialize(&HwIcap, DeviceId,
XHI_TARGET_DEVICEID);
    Print("just print status: %d\r\n", Status);
	 if (Status == XST_DEVICE_IS_STARTED)
    {
       Print("Device is already initialized.\r\n");
    }
    else if (Status != XST_SUCCESS)
    {
       Print("Failed to initialize: %d\r\n", Status);
       return XST_FAILURE;
    }




   /*Status= XHwIcap_CommandDesync(&HwIcap);
   Print("just print status for Desync: %d\r\n", Status);
    if(Status != XST_SUCCESS)
	 {
        print("\n Desynchronization was not successful!\n");

	 }*/

    /*
     * Identify the LUT to change: LUT in SLICE_X0Y0.
     */
    ColNum = XHwIcap_mSliceX2Col(TEST_COL);
    RowNum = XHwIcap_mSliceY2Row(&HwIcap, TEST_ROW);
    Slice  = XHwIcap_mSliceXY2Slice(TEST_COL, TEST_ROW);



    Count = 0;
    while (1)
    {
        Count = Count + 1;

        /*
         * Set the LUT array to be assigned
         */
        for (Index = 0; Index < LUT_SIZE; Index++)
        {
            LutWriteBuffer[Index] = (Count >> Index) & 0x01;

        }


        /*
         * Set LUT
         */
        Status = XHwIcap_SetClbBits(&HwIcap, RowNum, ColNum,
                 XHI_CLB_LUT.CONTENTS[Slice][XHI_CLB_LUT_F],
LutWriteBuffer,
                 LUT_SIZE);

        /*
         * Read back LUT value
         */
        Status = XHwIcap_GetClbBits(&HwIcap, RowNum, ColNum,
                                    XHI_CLB_LUT.CONTENTS[Slice]
[XHI_CLB_LUT_F],
                                    LutReadBuffer, LUT_SIZE);

        /*
         * Compare the written and read values
         */
        for (Index = 0; Index < LUT_SIZE; Index++)
        {
            if (LutWriteBuffer[Index] != LutReadBuffer[Index])
            {
                Print("Read %d failed at index %d\r\n", Count, Index);
                break;
            }
        }

        if ((Count % 100) == 0)
        {
            Print("Iteration Number:");
            Print(" %d of Writing/Reading the LUT is successful \r\n",
Count);
        }

    }


}






Article: 132117
Subject: Re: xilinx beginner modelsim question
From: Barry <barry374@gmail.com>
Date: Wed, 14 May 2008 08:30:46 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 14, 5:09=A0am, Zorjak <Zor...@gmail.com> wrote:
> Hi!!!
>
> I started recently with the xilinx software and these days I am trying
> to become more familiar with the modelsim and ise. I =A0wanted to test
> some basic counter simulation in modelsim so I used this simple code
>
> counter design file
>
> library ieee ;
> =A0 use ieee.std_logic_1164.all;
> =A0 =A0use ieee.std_logic_unsigned.all;
>
> =A0 entity counter is
> =A0 =A0port( =A0clk: =A0in std_logic;
> =A0 =A0 =A0reset: =A0in std_logic;
> =A0 =A0 =A0enable: =A0in std_logic;
> =A0 =A0 =A0count: =A0out std_logic_vector(3 downto 0)
> =A0 );
> =A0 end counter;
>
> =A0 architecture behav of counter is
> =A0 =A0 signal pre_count: std_logic_vector(3 downto 0);
> =A0 =A0 begin
> =A0 =A0 =A0 process(clk, enable, reset)
> =A0 =A0 =A0 begin
> =A0 =A0 =A0 =A0 if reset =3D '1' then
> =A0 =A0 =A0 =A0 =A0 pre_count <=3D "0000";
> =A0 =A0 =A0 =A0elsif (clk=3D'1' and clk'event) then
> =A0 =A0 =A0 =A0 =A0 if enable =3D '1' then
> =A0 =A0 =A0 =A0 =A0 =A0pre_count <=3D pre_count + "1";
> =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 end process;
> =A0 =A0 =A0 count <=3D pre_count;
> =A0 end behav;
>
> testbench
>
> =A0 library ieee ;
> =A0 use ieee.std_logic_1164.all;
> =A0 use ieee.std_logic_unsigned.all;
> =A0 use ieee.std_logic_textio.all;
> =A0 use std.textio.all;
>
> =A0 entity counter_tb is
> =A0 end;
>
> =A0 architecture counter_tb of counter_tb is
>
> =A0component counter
> =A0 =A0port ( count : out std_logic_vector(3 downto 0);
> =A0 =A0 =A0 =A0 =A0 clk =A0 : in std_logic;
> =A0 =A0 =A0 =A0 =A0 enable: in std_logic;
> =A0 =A0 =A0 =A0 =A0 reset : in std_logic);
> =A0end component ;
>
> =A0signal =A0 clk =A0 =A0: std_logic :=3D '0';
> =A0signal =A0 reset =A0: std_logic :=3D '0';
> =A0signal =A0 enable : std_logic :=3D '0';
> =A0signal =A0 count =A0: std_logic_vector(3 downto 0);
>
> =A0begin
>
> =A0 dut : counter
> =A0port map (
> =A0 =A0 =A0count =3D> count,
> =A0 =A0 =A0clk =A0 =3D> clk,
> =A0 =A0 enable=3D> enable,
> =A0 =A0 reset =3D> reset );
>
> =A0 =A0clock : process
> =A0 =A0begin
> =A0 =A0 =A0 =A0clk<=3D'0';
> =A0 =A0 =A0 =A0wait for 5 ns;
> =A0 =A0 =A0 =A0clk<=3D'1';
> =A0 =A0 =A0 =A0wait for 5 ns;
> =A0 =A0end process clock;
>
> =A0 =A0stimulus : process
> =A0 =A0begin
>
> =A0 =A0 =A0wait for 5 ns; reset =A0<=3D '1';
> =A0 =A0 =A0 wait for 4 ns; reset =A0<=3D '0';
> =A0 =A0 =A0 wait for 4 ns; enable <=3D '1';
> =A0 =A0 wait;
> =A0 end process stimulus;
>
> but my simulation doesn't give right results. (I am getting U state on
> all inputs). I am trying to find my mistake for more than 4 hours so
> please if someone could help me please do it. I have defined new
> project, I have compiled files and when I start simulation this
> results repeat over and over again. I fell that this is stupid little
> mistake but I can't find it no matter =A0what.
>
> Thanks for any kind of help
> Zoran

Zoran -

I compiled and simulated your files in Modelsim SE 6.2h and your
counter works fine.  Perhaps you should try some of the examples that
ship with Modelsim - find the examples folder in your install
directory.  Maybe something is wrong in your modelsim.ini file; I
really have no idea.

Barry

Article: 132118
Subject: Re: xilinx beginner modelsim question
From: Dave Pollum <vze24h5m@verizon.net>
Date: Wed, 14 May 2008 08:47:24 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 14, 7:09 am, Zorjak <Zor...@gmail.com> wrote:
> Hi!!!
>
> I started recently with the xilinx software and these days I am trying
> to become more familiar with the modelsim and ise. I  wanted to test
> some basic counter simulation in modelsim so I used this simple code
>
> counter design file
>
> library ieee ;
>   use ieee.std_logic_1164.all;
>    use ieee.std_logic_unsigned.all;
>
>   entity counter is
>    port(  clk:  in std_logic;
>      reset:  in std_logic;
>      enable:  in std_logic;
>      count:  out std_logic_vector(3 downto 0)
>   );
>   end counter;
>
>   architecture behav of counter is
>     signal pre_count: std_logic_vector(3 downto 0);
>     begin
>       process(clk, enable, reset)
>       begin
>         if reset = '1' then
>           pre_count <= "0000";
>        elsif (clk='1' and clk'event) then
>           if enable = '1' then
>            pre_count <= pre_count + "1";
>           end if;
>         end if;
>       end process;
>       count <= pre_count;
>   end behav;
>
> testbench
>
>   library ieee ;
>   use ieee.std_logic_1164.all;
>   use ieee.std_logic_unsigned.all;
>   use ieee.std_logic_textio.all;
>   use std.textio.all;
>
>   entity counter_tb is
>   end;
>
>   architecture counter_tb of counter_tb is
>
>  component counter
>    port ( count : out std_logic_vector(3 downto 0);
>           clk   : in std_logic;
>           enable: in std_logic;
>           reset : in std_logic);
>  end component ;
>
>  signal   clk    : std_logic := '0';
>  signal   reset  : std_logic := '0';
>  signal   enable : std_logic := '0';
>  signal   count  : std_logic_vector(3 downto 0);
>
>  begin
>
>   dut : counter
>  port map (
>      count => count,
>      clk   => clk,
>     enable=> enable,
>     reset => reset );
>
>    clock : process
>    begin
>        clk<='0';
>        wait for 5 ns;
>        clk<='1';
>        wait for 5 ns;
>    end process clock;
>
>    stimulus : process
>    begin
>
>      wait for 5 ns; reset  <= '1';
>       wait for 4 ns; reset  <= '0';
>       wait for 4 ns; enable <= '1';
>     wait;
>   end process stimulus;
>
> but my simulation doesn't give right results. (I am getting U state on
> all inputs). I am trying to find my mistake for more than 4 hours so
> please if someone could help me please do it. I have defined new
> project, I have compiled files and when I start simulation this
> results repeat over and over again. I fell that this is stupid little
> mistake but I can't find it no matter  what.
>
> Thanks for any kind of help
> Zoran

Your clock process will only produce -1- clock cycle.  You need the
clock to be in a loop:

   clock : process
   begin
     loop
       clk<='0';
       wait for 5 ns;
       clk<='1';
       wait for 5 ns;
     end loop;
   end process clock;

-Dave Pollum


Article: 132119
Subject: Re: xilinx beginner modelsim question
From: Dave <dhschetz@gmail.com>
Date: Wed, 14 May 2008 09:36:34 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 14, 11:47 am, Dave Pollum <vze24...@verizon.net> wrote:
> On May 14, 7:09 am, Zorjak <Zor...@gmail.com> wrote:
>
>
>
> > Hi!!!
>
> > I started recently with the xilinx software and these days I am trying
> > to become more familiar with the modelsim and ise. I  wanted to test
> > some basic counter simulation in modelsim so I used this simple code
>
> > counter design file
>
> > library ieee ;
> >   use ieee.std_logic_1164.all;
> >    use ieee.std_logic_unsigned.all;
>
> >   entity counter is
> >    port(  clk:  in std_logic;
> >      reset:  in std_logic;
> >      enable:  in std_logic;
> >      count:  out std_logic_vector(3 downto 0)
> >   );
> >   end counter;
>
> >   architecture behav of counter is
> >     signal pre_count: std_logic_vector(3 downto 0);
> >     begin
> >       process(clk, enable, reset)
> >       begin
> >         if reset = '1' then
> >           pre_count <= "0000";
> >        elsif (clk='1' and clk'event) then
> >           if enable = '1' then
> >            pre_count <= pre_count + "1";
> >           end if;
> >         end if;
> >       end process;
> >       count <= pre_count;
> >   end behav;
>
> > testbench
>
> >   library ieee ;
> >   use ieee.std_logic_1164.all;
> >   use ieee.std_logic_unsigned.all;
> >   use ieee.std_logic_textio.all;
> >   use std.textio.all;
>
> >   entity counter_tb is
> >   end;
>
> >   architecture counter_tb of counter_tb is
>
> >  component counter
> >    port ( count : out std_logic_vector(3 downto 0);
> >           clk   : in std_logic;
> >           enable: in std_logic;
> >           reset : in std_logic);
> >  end component ;
>
> >  signal   clk    : std_logic := '0';
> >  signal   reset  : std_logic := '0';
> >  signal   enable : std_logic := '0';
> >  signal   count  : std_logic_vector(3 downto 0);
>
> >  begin
>
> >   dut : counter
> >  port map (
> >      count => count,
> >      clk   => clk,
> >     enable=> enable,
> >     reset => reset );
>
> >    clock : process
> >    begin
> >        clk<='0';
> >        wait for 5 ns;
> >        clk<='1';
> >        wait for 5 ns;
> >    end process clock;
>
> >    stimulus : process
> >    begin
>
> >      wait for 5 ns; reset  <= '1';
> >       wait for 4 ns; reset  <= '0';
> >       wait for 4 ns; enable <= '1';
> >     wait;
> >   end process stimulus;
>
> > but my simulation doesn't give right results. (I am getting U state on
> > all inputs). I am trying to find my mistake for more than 4 hours so
> > please if someone could help me please do it. I have defined new
> > project, I have compiled files and when I start simulation this
> > results repeat over and over again. I fell that this is stupid little
> > mistake but I can't find it no matter  what.
>
> > Thanks for any kind of help
> > Zoran
>
> Your clock process will only produce -1- clock cycle.  You need the
> clock to be in a loop:
>
>    clock : process
>    begin
>      loop
>        clk<='0';
>        wait for 5 ns;
>        clk<='1';
>        wait for 5 ns;
>      end loop;
>    end process clock;
>
> -Dave Pollum

The clock process is Ok as is - there doesn't need to be a loop. Since
there's no 'wait' statement at the end of the process, execution will
go back to the top of the process on the next delta cycle.

This stimulus process could use some work, though. Try defining the
reset and enable signals from the beginning, like this:

   stimulus : process
   begin
      reset <= '0';
      enable <= '0';
      wait for 5 ns; reset  <= '1';
      wait for 4 ns; reset  <= '0';
      wait for 4 ns; enable <= '1';
    wait;
  end process stimulus;

Otherwise, the reset and enable signals are 'U" until you drive them
in the testbench. This could cause U's and X's to propagate through
your DUT, and the feedback in the counter could make them last
forever.

Hope this helps,

Dave



Article: 132120
Subject: Re: How to input an analog signal to FPGA board for processing?
From: Vagant <vladimir.v.korostelev@rambler.ru>
Date: Wed, 14 May 2008 09:59:08 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 13 =CD=C1=CA, 02:51, Andy Peters <goo...@latke.net> wrote:
> On May 11, 11:53 pm, Vagant <vladimir.v.koroste...@rambler.ru> wrote:
>
> > Hello,
> > I am a beginer and have a basic question.
> > My project implemented on FPGA board (which is Spartan3E-1600
> > Microblaze Development Kit) includes ADC and is supposed to do some
> > digital signal processing of an analog RF signal from 'outside
> > world'.
> > How I can input an analog signal to my FPGA?
>
> Do you have the manual for the board? Hint: it's Xilinx p/n UG257.
>
> The section "Analog Capture Circuit" starts on Page 75 of That Fine
> Document.
>
> Header J7, which is a bog standard 0.1"-center pin strip, is the input
> to the two ADCs.
>
> You'll probably have to make a cable or adapter so you can use those
> pins. If you are incapable of making such an adapter, you probably
> shouldn't be messing around with FPGAs.
>
> -a

Thank you very much, it's very helpful indeed.
By the way, it's a shame that I have not noticed section 'Analog
Capture Circuit' myself..

Article: 132121
Subject: Re: demo board under 500usd
From: ghelbig@lycos.com
Date: Wed, 14 May 2008 11:37:20 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 14, 6:00 am, kclo4 <alexis.ga...@gmail.com> wrote:
> Hi everyone,
>
> I am considering to buy a fpga board for less than 500usd , I have
> looked around and I found 2 board that look like nice :
> the NIOS II development kit with a cycloneIII-25 that include a touch
> screen LCD
> and Spartan-3A DSP S3D1800A MicroBlaze Processor Edition
>
> I would like to make some SDR project(i got a demo board of a adc
> board 16bit/160mhz sampling freq) so i would like a fpga big enought
> to make some dsp processing
> I believe the Spartan 3 DSP 1800 is bigger than the cyclone 3 25 so i
> think i will have more logic to make bigger design and also the xilinx
> kit include a 1gbit connection that might be usefull to transfer data
> to a pc
>
> Does someone have any feedback on those boards?? which fpga is bigger?
>
> thanks you
>
> alexis

If I were going to start playing with FPGA based SDR, I would get a
Quicksilver board.

G.

Article: 132122
Subject: Re: Yay! We're done with the quadrature encoder!
From: Jon Elson <elson@wustl.edu>
Date: Wed, 14 May 2008 13:48:11 -0500
Links: << >>  << T >>  << A >>


John_H wrote:
> Aren't we?  :-)

I did mine in 2001, been happy with it since.  But, it is proprietary,
and I don't intend to publish it.  (sorry)

Jon


Article: 132123
Subject: Re: Programming XCR3064xl - voltage at output stuck at 0
From: xcr3064xl <xc3064@gmail.com>
Date: Wed, 14 May 2008 13:58:03 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 12, 11:54 pm, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> xcr3064xl wrote:

> - What does the fitter report file say ?

I looked into the HTML fitter report.
After I commented out assignments to two pins, the
number of 'Pins Used' went down by two. That looks
sensible.

> - Does the fuse-file change with the two compile choices ?

Which one is the fuse file?

I ran a diff on two directories (VHDL in one directory had
two PINxx <= '0' assignments; in the other those assignments
have been commented out and nothing was driving the
pins).

Here are some differences:

1) No assignmnent
2) Driving '0'; P14 <= '0';
(I have omitted differences for the other pin)


file: *_pad.csv
1) P14,WPU,,I/O,,,,,,,,,,
2) P14,p14,O,I/O,OUTPUT,,,,,,,,,


file: *.pad
1) P14|WPU||I/O||||||||||
2) P14|p14|O|I/O|OUTPUT|||||||||


file: *.mfd
1)
2)
MACROCELL | 3 | 10 | p14_MC
ATTRIBUTES | 1074004738 | 0
INPUTS | 0
EQ | 1 |
   p14 = Gnd;   // (0 pt, 0 inp)

K.

Article: 132124
Subject: Re: Programming XCR3064xl - voltage at output stuck at 0
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Thu, 15 May 2008 09:44:59 +1200
Links: << >>  << T >>  << A >>
xcr3064xl wrote:
> Which one is the fuse file?

After 'generate programming file' run, you should have a DesignName.JED 
file.

If that does not change (and it is not in your list) then
it seems the tools are 'droppnig the ball'.

Does the fitter .RPT file change equations for the pin ?

-jg




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