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Threads Starting Apr 2001

30292: 01/04/01: Matt Billenstein: adding std_logic_vectors
    30304: 01/04/02: Ray Andraka: Re: adding std_logic_vectors
        30312: 01/04/02: Reto Zimmermann: Re: adding std_logic_vectors
30293: 01/04/01: Gonzalo Arana: IDE-PCI question
30294: 01/04/01: prashanth: Dist_ram :Memory instantiation
    30324: 01/04/03: Rick Filipkiewicz: Re: Dist_ram :Memory instantiation
        30494: 01/04/11: niki: Re: Dist_ram :Memory instantiation
30295: 01/04/02: <yorams@hywire.com>: xapp258 question
    30298: 01/04/02: Magnus Homann: Re: xapp258 question
    30313: 01/04/02: Peter Alfke: Re: xapp258 question
        30335: 01/04/03: Magnus Homann: Re: xapp258 question
            30341: 01/04/03: Peter Alfke: Re: xapp258 question
            32824: 01/07/10: Johan Petersson: Re: xapp258 question
30297: 01/04/02: <yorams@hywire.com>: xapp258 question
30299: 01/04/02: =?iso-8859-1?Q?J=F6rg?= Ritter: pseudo random numbers
    30303: 01/04/02: Ray Andraka: Re: pseudo random numbers
        30306: 01/04/02: =?iso-8859-1?Q?J=F6rg?= Ritter: Re: pseudo random numbers
        30308: 01/04/02: Nicolas Matringe: Re: pseudo random numbers
            30315: 01/04/02: Ray Andraka: Re: pseudo random numbers
                30330: 01/04/03: Hal Murray: Re: pseudo random numbers
                    30339: 01/04/03: Ray Andraka: Re: pseudo random numbers
                30345: 01/04/03: Kevin Neilson: Re: pseudo random numbers
        30346: 01/04/03: Austin Lesea: Re: pseudo random numbers
            30347: 01/04/03: Peter Alfke: Re: pseudo random numbers
            30348: 01/04/03: Ray Andraka: Re: pseudo random numbers
                30349: 01/04/03: Austin Lesea: Re: pseudo random numbers
                    30351: 01/04/04: Ray Andraka: Re: pseudo random numbers
                        30371: 01/04/04: Austin Lesea: Re: pseudo random numbers
            30365: 01/04/04: Nicolas Matringe: Re: pseudo random numbers
        30369: 01/04/04: =?iso-8859-1?Q?J=F6rg?= Ritter: Re: pseudo random numbers
            30372: 01/04/04: Ray Andraka: Re: pseudo random numbers
            30548: 01/04/13: Marc D Bumble: Re: pseudo random numbers
                30550: 01/04/15: Simon A. Young: Re: pseudo random numbers
    30307: 01/04/02: Eric Pearson: Re: pseudo random numbers
        30316: 01/04/02: Ray Andraka: Re: pseudo random numbers
            30320: 01/04/03: Jim Granville: Re: pseudo random numbers
            30328: 01/04/03: Allan Herriman: Re: pseudo random numbers
    30325: 01/04/02: luigi funes: Re: pseudo random numbers
        30327: 01/04/03: Ray Andraka: Re: pseudo random numbers
            30419: 01/04/07: Rick Collins: Re: pseudo random numbers
                30427: 01/04/07: Ray Andraka: Re: pseudo random numbers
30300: 01/04/02: sam: XCV1000BG560: onchip ram
    30301: 01/04/02: Keith R. Williams: Re: XCV1000BG560: onchip ram
    30423: 01/04/07: Richard Martineau: Re: XCV1000BG560: onchip ram
        30428: 01/04/07: Ray Andraka: Re: XCV1000BG560: onchip ram
            30564: 01/04/17: Martin: Re: XCV1000BG560: onchip ram
                30566: 01/04/17: Peter Alfke: Re: XCV1000BG560: onchip ram
                30567: 01/04/17: Keith R. Williams: Re: XCV1000BG560: onchip ram
30302: 01/04/02: Laurence McCotter: pinout in text format for Virtex-E XCV200E
    30310: 01/04/02: Brian Drummond: Re: pinout in text format for Virtex-E XCV200E
    30326: 01/04/03: Kent Orthner: Re: pinout in text format for Virtex-E XCV200E
30305: 01/04/02: hanshu: some info. on FPGA
    30333: 01/04/03: news.hinet.net: Re: some info. on FPGA
    30334: 01/04/03: Srinivasan Venkataramanan: Re: some info. on FPGA
    30377: 01/04/04: Brian Dipert: Re: some info. on FPGA
30309: 01/04/02: ChristopheGuelff: good knwoledge in fpga or vhdl
30318: 01/04/02: Christof Paar: accepted papers at CHES 2001
30329: 01/04/02: Qian: Timing Error
    30338: 01/04/03: Ray Andraka: Re: Timing Error
    30378: 01/04/04: Rick Filipkiewicz: Re: Timing Error
30332: 01/04/03: Manjunathan: to add macro in the design
30337: 01/04/03: Matt Hayes: RC4/ARC4 on an FPGA.
    30388: 01/04/05: luigi funes: Re: RC4/ARC4 on an FPGA.
    30393: 01/04/06: rws: Re: RC4/ARC4 on an FPGA.
    30535: 01/04/13: james.rowland1: Re: RC4/ARC4 on an FPGA.
30340: 01/04/03: Fredrik Theander: Analog programable devices
30342: 01/04/03: <salary_guide@hitechsalary.com>: salary info for FPGA/HardwareEng's
    30355: 01/04/04: Rick Collins: Re: salary info for FPGA/HardwareEng's
        30366: 01/04/04: Craig from FL: Re: salary info for FPGA/HardwareEng's
        30367: 01/04/04: Ray Andraka: Re: salary info for FPGA/HardwareEng's
30344: 01/04/03: Chris Eilbeck: Atmel FPSLIC devices
30350: 01/04/04: Domagoj: Combined Multiplier-Divider in Virtex-E
    30352: 01/04/04: Peter Alfke: Re: Combined Multiplier-Divider in Virtex-E
        30356: 01/04/04: Domagoj: Re: Combined Multiplier-Divider in Virtex-E
    30353: 01/04/04: Ray Andraka: Re: Combined Multiplier-Divider in Virtex-E
        30357: 01/04/04: Domagoj: Re: Combined Multiplier-Divider in Virtex-E
            30368: 01/04/04: Ray Andraka: Re: Combined Multiplier-Divider in Virtex-E
        30571: 01/04/17: Domagoj: Re: Combined Multiplier-Divider in Virtex-E
30354: 01/04/04: Mark Walter: Xilinx Foundation 2.1i License
    30359: 01/04/04: Chris Dunlap: Re: Xilinx Foundation 2.1i License
30358: 01/04/04: Rajesh Bawankule: Verilog FAQ: April 2001
30360: 01/04/04: Shigeyuki Takano: Information about configuraiton time
30361: 01/04/04: Kristian Rye Vennesland: DSP Volume-control in FPGA
    30363: 01/04/04: Ralph Weir: Re: DSP Volume-control in FPGA
    30384: 01/04/05: Mark Sterk: Re: DSP Volume-control in FPGA
30370: 01/04/04: Riccardo Zambon: High Speed PLA/FPGA
    30381: 01/04/05: Hal Murray: Re: High Speed PLA/FPGA
        30382: 01/04/05: Jim Granville: Re: High Speed PLA/FPGA
    30395: 01/04/06: Peter Alfke: Re: High Speed PLA/FPGA
        30399: 01/04/06: Meelis Kuris: Re: High Speed PLA/FPGA
            30401: 01/04/06: Meelis Kuris: Re: High Speed PLA/FPGA
        30402: 01/04/06: luigi funes: Re: High Speed PLA/FPGA
            30406: 01/04/06: Peter Alfke: Re: High Speed PLA/FPGA
                30465: 01/04/09: Erik Widding: Re: High Speed PLA/FPGA
                    30492: 01/04/11: Peter Alfke: Re: High Speed PLA/FPGA
30373: 01/04/04: Qian: Simulation result shows that
30375: 01/04/04: <>: PC software for 10$/cd
30376: 01/04/04: Edward: QPSK phase rotator implementation in FPGA ?
    30379: 01/04/05: Ray Andraka: Re: QPSK phase rotator implementation in FPGA ?
    30385: 01/04/05: Evan Lavelle: Re: QPSK phase rotator implementation in FPGA ?
30380: 01/04/05: <yuryws@banet.net>: How to specify Spartan2 GSR/GTS for Synthesis
    30390: 01/04/05: Ray Andraka: Re: How to specify Spartan2 GSR/GTS for Synthesis
        30486: 01/04/10: <yuryws@banet.net>: Re: How to specify Spartan2 GSR/GTS for Synthesis
            30495: 01/04/11: Kolja Sulimma: Re: How to specify Spartan2 GSR/GTS for Synthesis
                30503: 01/04/11: Ray Andraka: Re: How to specify Spartan2 GSR/GTS for Synthesis
                    30518: 01/04/12: Philip Freidin: Re: How to specify Spartan2 GSR/GTS for Synthesis
                        32827: 01/07/10: Johan Petersson: Re: How to specify Spartan2 GSR/GTS for Synthesis
30383: 01/04/05: Helen Long: How to combine bus in schematic
    30386: 01/04/05: Dave Vanden Bout: Re: How to combine bus in schematic
        30430: 01/04/07: Thomas Heidel: Re: How to combine bus in schematic
            30438: 01/04/08: Dave Vanden Bout: Re: How to combine bus in schematic
30387: 01/04/05: Fuzesi Arnold: URGENT: Using SpartanII DLL to multiply clock freq
    30391: 01/04/05: Ray Andraka: Re: URGENT: Using SpartanII DLL to multiply clock freq
30389: 01/04/05: Andrew Hosmer: Altera 20k programming
    30397: 01/04/06: Vitaliy Tkachenko: Re: Altera 20k programming
        30403: 01/04/06: Andrew Hosmer: Re: Altera 20k programming
    30408: 01/04/06: Andrew Hosmer: Re: Altera 20k programming
        30415: 01/04/07: Vitaliy Tkachenko: Re: Altera 20k programming
            30418: 01/04/07: Andrew Hosmer: Re: Altera 20k programming
30392: 01/04/06: Dean Armstrong: Spartan II Configuration
    30444: 01/04/08: Jan Kindt: Re: Spartan II Configuration
        30447: 01/04/09: Dean Armstrong: Re: Spartan II Configuration
30394: 01/04/05: W.Turk: Modlesim5.5
    30396: 01/04/06: Utku Ozcan: Re: Modlesim5.5
    30398: 01/04/06: Nicolas Matringe: Re: Modlesim5.5
        30409: 01/04/06: Rick Filipkiewicz: Re: Modlesim5.5
            30455: 01/04/09: Nicolas Matringe: Re: Modlesim5.5
                30466: 01/04/09: Rick Filipkiewicz: Re: Modlesim5.5
            30476: 01/04/10: Utku Ozcan: Re: Modlesim5.5
    30515: 01/04/12: Leonid Shvarzberg: Re: Modlesim5.5
        30532: 01/04/12: cyber_spook: Re: Modlesim5.5
        30543: 01/04/13: Filip Gielen: Re: Modlesim5.5
            30544: 01/04/13: Nicolas Matringe: Re: Modlesim5.5
                32826: 01/07/10: Johan Petersson: Re: Modlesim5.5
30400: 01/04/06: Neil Badenoch: x4000 series reset
    30407: 01/04/06: Peter Alfke: Re: x4000 series reset
30404: 01/04/06: Scott Thibault: Beta tester needed: VHDL Studio Solaris/Linux/Windows
30405: 01/04/06: Matti Ruusunen: Why FPGA/CPLDs draw a lot current?
    30410: 01/04/07: Speedy: Re: Why FPGA/CPLDs draw a lot current?
        30411: 01/04/07: Jim Granville: Re: Why FPGA/CPLDs draw a lot current?
            30425: 01/04/07: Matti Ruusunen: Re: Why FPGA/CPLDs draw a lot current?
                30429: 01/04/08: Jim Granville: Re: Why FPGA/CPLDs draw a lot current?
                30487: 01/04/10: Frank Wirtz: Re: Why FPGA/CPLDs draw a lot current?
                    30488: 01/04/10: Austin Lesea: Re: Why FPGA/CPLDs draw a lot current?
                    30491: 01/04/11: Jim Granville: Re: Why FPGA/CPLDs draw a lot current?
30412: 01/04/06: djley: Xilinx conflict with Win95 and CPLD BGA's
30413: 01/04/07: <kahhean@bigfoot.com>: DLL locking problem
    30497: 01/04/11: <kahhean@bigfoot.com>: Re: DLL locking problem
30416: 01/04/07: sb: FPGA configuration from processor
    30417: 01/04/07: Kolja Sulimma: Re: FPGA configuration from processor
        30446: 01/04/08: Hal Murray: Re: FPGA configuration from processor
30421: 01/04/07: Marc Battyani: Synchronous demodulation in FPGA
30422: 01/04/07: Richard Martineau: xilinx price lists
    30424: 01/04/07: S. Ramirez: Re: xilinx price lists
        30426: 01/04/07: Kolja Sulimma: Re: xilinx price lists
    30437: 01/04/08: Dave Vanden Bout: Re: xilinx price lists
        30459: 01/04/09: Victor Schutte: Re: xilinx price lists
30431: 01/04/07: Compilit: Handel-C
    30432: 01/04/07: Compilit: Re: Handel-C
    30433: 01/04/08: S. Ramirez: Re: Handel-C
        30435: 01/04/08: niki: Re: Handel-C
        30436: 01/04/08: Rick Filipkiewicz: Re: Handel-C
            30439: 01/04/08: Robert Carney: Re: Handel-C
                30440: 01/04/08: niki: Re: Handel-C
                    30441: 01/04/08: Robert Carney: Re: Handel-C
                    30448: 01/04/08: cyber_spook: Re: Handel-C
                        30451: 01/04/08: niki: Re: Handel-C
                            30467: 01/04/09: cyber_spook: Re: Handel-C
                30469: 01/04/09: A E Lawrence: Re: Handel-C
                30471: 01/04/10: S. Ramirez: Re: Handel-C
            30470: 01/04/09: Lasse Langwadt Christensen: Re: Handel-C
    30443: 01/04/08: Bob Perlman: Re: Handel-C
        30450: 01/04/08: Rick Filipkiewicz: Re: Handel-C
    30453: 01/04/09: Richard Erlacher: Re: Handel-C
        30468: 01/04/09: cyber_spook: Re: Handel-C
            30483: 01/04/10: cyber_spook: Re: Handel-C
            30511: 01/04/11: cyber_spook: Re: Handel-C
        30473: 01/04/10: rodger: Re: Handel-C
        30477: 01/04/10: Jamie Lokier: Re: Handel-C
            30490: 01/04/11: S. Ramirez: Re: Handel-C
    30481: 01/04/10: Fabrice MONTEIRO: Obj: Handel-C
        30493: 01/04/11: niki: Re: Handel-C
            30498: 01/04/11: Fabrice MONTEIRO: Re: Handel-C
    30520: 01/04/12: Brendan Lynskey: Re: Handel-C
        30533: 01/04/12: cyber_spook: Re: Handel-C
            30534: 01/04/12: niki: Re: Handel-C
        32828: 01/07/10: Johan Petersson: Re: Handel-C
            32854: 01/07/10: Andy Freeman: Re: Handel-C
                32856: 01/07/10: news_alias: Re: Handel-C
                    32886: 01/07/10: Andy Freeman: Re: Handel-C
                        32892: 01/07/11: Magnus Homann: Re: Handel-C
                            32907: 01/07/11: Andy Freeman: Re: Handel-C
                32887: 01/07/10: Andy Freeman: Re: Handel-C
    30554: 01/04/16: riley: Re: Handel-C
30445: 01/04/08: [Pedro Silva]: Alternative to Xilink Foundation schematic editor
    30452: 01/04/09: Richard Erlacher: Re: Alternative to Xilink Foundation schematic editor
30454: 01/04/09: William Lenihan: small, fast, w/ PECL?
    30457: 01/04/09: Kolja Sulimma: Re: small, fast, w/ PECL?
        30485: 01/04/10: Geoffrey G. Rochat: Re: small, fast, w/ PECL?
            30635: 01/04/20: William Lenihan: Re: small, fast, w/ PECL?
30456: 01/04/09: Hayden So: Spartan-II DLL question
    30462: 01/04/09: Peter Alfke: Re: Spartan-II DLL question
30458: 01/04/09: Damir Danijel Zagar: VHDL falling edge in Xilinx Foundation...
    30480: 01/04/10: Jan Kindt: Re: VHDL falling edge in Xilinx Foundation...
    30489: 01/04/10: Andy Peters: Re: VHDL falling edge in Xilinx Foundation...
30460: 01/04/09: Jan Gray: MicroBlaze
    30461: 01/04/09: Ray Andraka: Re: MicroBlaze
        30463: 01/04/09: Jan Gray: Re: MicroBlaze
30464: 01/04/09: Soren 'Disky' Reinke: free software
    30474: 01/04/10: Kristian Rye Vennesland: Re: free software
        30478: 01/04/10: Jamie Lokier: Re: free software
        30522: 01/04/12: Wolfgang Loewer: Re: free software
    30475: 01/04/10: Srinivasan Venkataramanan: Re: free software
    30484: 01/04/10: cyber_spook: Re: free software
30472: 01/04/09: Michael Morell: Hot - FPGA System Design Engineer
30479: 01/04/10: Mark Harrison: CONTRACTORS
    30602: 01/04/18: Nhoxford: Re: CONTRACTORS
30482: 01/04/10: Richard Knispel: help with ABEL-HDL and CPLDs
    30496: 01/04/11: Bertram Geiger: Re: help with ABEL-HDL and CPLDs
        30504: 01/04/11: Richard Knispel: Re: help with ABEL-HDL and CPLDs
            30517: 01/04/12: Luigi Funes: Re: help with ABEL-HDL and CPLDs
30499: 01/04/11: <kahhean@bigfoot.com>: FPGA Express 3.5 One hot state machine Synthesis problem
    31298: 01/05/17: Tom Kaminski: Re: FPGA Express 3.5 One hot state machine Synthesis problem
        31302: 01/05/18: Rick Filipkiewicz: Re: FPGA Express 3.5 One hot state machine Synthesis problem
            31315: 01/05/18: Tom Kaminski: Re: FPGA Express 3.5 One hot state machine Synthesis problem
                31317: 01/05/18: Duane Clark: Re: FPGA Express 3.5 One hot state machine Synthesis problem
            31323: 01/05/18: Erik Widding: Re: FPGA Express 3.5 One hot state machine Synthesis problem
        31347: 01/05/20: Rick Collins: Re: FPGA Express 3.5 One hot state machine Synthesis problem
30500: 01/04/11: Michael Boehnel: Exit F3.1 Simulator automatically?
30501: 01/04/11: winmaster Winmaster: ABEL, syntax for High impedance output
    30502: 01/04/11: Bertram Geiger: Re: ABEL, syntax for High impedance output
30505: 01/04/11: M Wirtzfeld: Introductory Question - LSB to MSB Conversion.
    30509: 01/04/11: Ray Andraka: Re: Introductory Question - LSB to MSB Conversion.
30506: 01/04/11: Paul Urbanus: Changing Xilinx ROM contents without recompiling
    30507: 01/04/11: Jamie Sanderson: Re: Changing Xilinx ROM contents without recompiling
        30513: 01/04/12: Kent Orthner: Re: Changing Xilinx ROM contents without recompiling
    30525: 01/04/12: Victor the Cleaner: Re: Changing Xilinx ROM contents without recompiling
30508: 01/04/11: Rick Filipkiewicz: Virtex readback
30510: 01/04/11: winmaster Winmaster: Re: Re: ABEL, syntax for High impedance output
30512: 01/04/11: Matt Billenstein: ngdbuild:432 primitives unexpanded in Foundation?
30514: 01/04/12: C.Schlehaus: Problems Software Build ALTERA Quartus II
    30516: 01/04/12: Victor Schutte: Re: Problems Software Build ALTERA Quartus II
    30521: 01/04/12: Wolfgang Loewer: Re: Problems Software Build ALTERA Quartus II
30519: 01/04/12: JianYong Niu: *help* how to count clock cycles in a design? how can i know its maximum clock frequency?
    30527: 01/04/12: Mike Treseler: Re: *help* how to count clock cycles in a design? how can i know its
30523: 01/04/12: hwi-sung jung: How to use clock generator in Vertex-e?
    30528: 01/04/12: Tim Jaynes: Re: How to use clock generator in Vertex-e?
30524: 01/04/12: Dave R.: Is this realistic?
    30529: 01/04/12: Tim Jaynes: Re: Is this realistic?
    30530: 01/04/12: Kolja Sulimma: Re: Is this realistic?
        30531: 01/04/12: Kolja Sulimma: Re: Is this realistic?
30536: 01/04/13: Jae-cheol Lee: Is there any free processor core for vertex series?
    30537: 01/04/12: Jan Gray: Re: Is there any free processor core for vertex series?
        30538: 01/04/13: Jae-cheol Lee: Thank you very much.
            30539: 01/04/12: Austin Lesea: Re: Thank you very much.
    30542: 01/04/13: Keith Jasinski, Jr.: Re: Is there any free processor core for vertex series?
        30552: 01/04/16: Kent Orthner: Re: Is there any free processor core for vertex series?
    30561: 01/04/17: Santiago de Pablo: Re: Is there any free processor core for vertex series?
30540: 01/04/13: Joe Wetstein: not IOB
    30541: 01/04/13: Nicolas Matringe: Re: not IOB
30545: 01/04/13: Richard Meester: ad: Spartan II Prototyping boards.
30547: 01/04/14: Patatralla: Xilinx LUT's and Synopsys DC
30549: 01/04/14: llandre: VHDL FFT core: where?
    32823: 01/07/10: Johan Petersson: Re: VHDL FFT core: where?
30551: 01/04/15: Joachim =?iso-8859-1?Q?Str=F6mbergson?=: Getting license for Modelsim in Xilinx webpack?
    30555: 01/04/16: Ron Proveniers: Re: Getting license for Modelsim in Xilinx webpack?
        30578: 01/04/17: Jean-Marie Bussat: Re: Getting license for Modelsim in Xilinx webpack?
            30580: 01/04/18: Rick Collins: Re: Getting license for Modelsim in Xilinx webpack?
                30590: 01/04/18: Nial Stewart: Re: Getting license for Modelsim in Xilinx webpack?
30553: 01/04/16: <developers@tizek.com>: Tizek.com is in dire need of a development team...
30556: 01/04/16: cheny: cheny_w@hotmail.com
30557: 01/04/16: Dan: PCMCIA implemented with Xilinx. Spec info needed.
    30558: 01/04/17: Kolja Sulimma: Re: PCMCIA implemented with Xilinx. Spec info needed.
    30689: 01/04/24: Andrew DeWeerd: Re: PCMCIA implemented with Xilinx. Spec info needed.
30562: 01/04/17: Helen Long: inout pin of DAC
    30572: 01/04/17: C.Schlehaus: Re: inout pin of DAC
30563: 01/04/17: Frode Vatvedt Fjeld: compression
    30565: 01/04/17: Kolja Sulimma: Re: compression
    30576: 01/04/18: Jim Granville: Re: compression
        30589: 01/04/18: Frode Vatvedt Fjeld: Re: compression
            30603: 01/04/19: Jim Granville: Re: compression
                30618: 01/04/19: Frode Vatvedt Fjeld: Re: compression
30568: 01/04/17: Greg Neff: XC9500XL Internal Noise Immunity
    30584: 01/04/18: Peter Alfke: Re: XC9500XL Internal Noise Immunity
        30599: 01/04/18: Greg Neff: Re: XC9500XL Internal Noise Immunity
30569: 01/04/17: Anthony Ellis: Using BGA's
30570: 01/04/17: Kolja Sulimma: Download Cable Mystery Solved
    30575: 01/04/17: Greg Neff: Re: Download Cable Mystery Solved
    30585: 01/04/18: Eric: Re: Download Cable Mystery Solved
30573: 01/04/17: VR: Clean Frequency Division
    30574: 01/04/17: Falk Brunner: Re: Clean Frequency Division
    30577: 01/04/17: Peter Alfke: Re: Clean Frequency Division
        30579: 01/04/18: V R: Re: Clean Frequency Division
            30582: 01/04/18: Peter Alfke: Re: Clean Frequency Division
30581: 01/04/18: Allan Herriman: PAR single pass vs multi-pass differences
    30592: 01/04/18: Utku Ozcan: Re: PAR single pass vs multi-pass differences
        30593: 01/04/18: Utku Ozcan: Re: PAR single pass vs multi-pass differences
            30601: 01/04/18: Rick Filipkiewicz: Re: PAR single pass vs multi-pass differences
            30661: 01/04/22: Hamish Moffatt VK3SB: Re: PAR single pass vs multi-pass differences
        30605: 01/04/19: Allan Herriman: Re: PAR single pass vs multi-pass differences
            30607: 01/04/19: Utku Ozcan: Re: PAR single pass vs multi-pass differences
                30614: 01/04/19: Allan Herriman: Re: PAR single pass vs multi-pass differences
                    30621: 01/04/19: Utku Ozcan: Re: PAR single pass vs multi-pass differences
                        30631: 01/04/19: Chris G. Schneider: Re: PAR single pass vs multi-pass differences
                        30639: 01/04/20: Allan Herriman: Re: PAR single pass vs multi-pass differences
                            30652: 01/04/21: Rick Filipkiewicz: Re: PAR single pass vs multi-pass differences
    30756: 01/04/27: Carl Stern: Re: PAR single pass vs multi-pass differences
30583: 01/04/18: Fredrik Theander: testing
30586: 01/04/18: V R: FPGAs & Combinatorial Chew
    30597: 01/04/18: Mike Treseler: Re: FPGAs & Combinatorial Chew
    30642: 01/04/20: Rick Collins: Re: FPGAs & Combinatorial Chew
30587: 01/04/18: Dan Connors: MICRO-34 Call for Papers
30588: 01/04/18: luigi funes: clocking on both edges
    30604: 01/04/19: Peter Alfke: Re: clocking on both edges
        30606: 01/04/19: Hal Murray: Re: clocking on both edges
            30623: 01/04/19: Peter Alfke: Re: clocking on both edges
            30627: 01/04/20: Jim Granville: Re: clocking on both edges
                30629: 01/04/19: Peter Alfke: Re: clocking on both edges
        30617: 01/04/19: Hans Summers: Re: clocking on both edges
            30624: 01/04/19: Peter Alfke: Re: clocking on both edges
            30646: 01/04/20: glen herrmannsfeldt: Re: clocking on both edges
30591: 01/04/18: almerima: Acces of JTAG port of the FPGA (XSV Board)
30594: 01/04/18: <xkkdkx@webnetsolutions.it>: gay 7019
30595: 01/04/18: =?ISO-8859-1?Q?L=E4hteenm=E4ki?= Jussi: ALTERA Nios software examples?
30596: 01/04/18: Paul Teagle: looking for comment on implementation
    30598: 01/04/18: Austin Lesea: Re: looking for comment on implementation
    30608: 01/04/19: Kevin Neilson: Re: looking for comment on implementation
        30616: 01/04/19: Paul Teagle: Re: looking for comment on implementation
            30625: 01/04/19: Peter Alfke: Re: looking for comment on implementation
            30673: 01/04/23: Ray Andraka: Re: looking for comment on implementation
            30674: 01/04/23: Ray Andraka: Re: looking for comment on implementation
        30672: 01/04/23: Ray Andraka: Re: looking for comment on implementation
            30682: 01/04/23: Kolja Sulimma: Re: looking for comment on implementation
    30671: 01/04/23: Ray Andraka: Re: looking for comment on implementation
30600: 01/04/18: Ernst Rattenhuber: Wanted: ISA bus implementation for Xilinx
    30610: 01/04/19: Nial Stewart: Re: Wanted: ISA bus implementation for Xilinx
        30645: 01/04/20: Ernst Rattenhuber: Re: Wanted: ISA bus implementation for Xilinx
            30654: 01/04/21: Chris G. Schneider: Re: Wanted: ISA bus implementation for Xilinx
        30972: 01/05/06: Ahmed: Re: Wanted: ISA bus implementation for Xilinx
    30615: 01/04/19: luigi funes: Re: Wanted: ISA bus implementation for Xilinx
        30636: 01/04/20: Victor Schutte: Re: Wanted: ISA bus implementation for Xilinx
    30650: 01/04/21: Ray Andraka: Re: Wanted: ISA bus implementation for Xilinx
    34767: 01/09/07: cnspy: Re: Wanted: ISA bus implementation for Xilinx
        34947: 01/09/14: Steen: Re: Wanted: ISA bus implementation for Xilinx
            34948: 01/09/14: Eric Crabill: Re: Wanted: ISA bus implementation for Xilinx
30609: 01/04/19: Alan Lee: Half-clock problem.
30611: 01/04/19: Steven Sanders: wanted: dig. board with FPGA and processor
    30634: 01/04/20: Rick Collins: Re: wanted: dig. board with FPGA and processor
    30637: 01/04/20: Dziadek: Re: wanted: dig. board with FPGA and processor
30612: 01/04/19: Steven Derrien: Voltage supply reduction for low power in FPGAs.
    30622: 01/04/19: Austin Lesea: Re: Voltage supply reduction for low power in FPGAs.
        30638: 01/04/20: Victor Schutte: Re: Voltage supply reduction for low power in FPGAs.
30613: 01/04/19: M.S.Gaur: Looking for digital video to VGA RGB conversion
30619: 01/04/19: PROCOM: Jobs@ ASIC / FPGA / VLSI designers needed - Canada
30620: 01/04/19: PROCOM: Senior ASIC Designers Needed - Canada
30626: 01/04/19: Kristen_G_Kosar: Digital Design Positions Available
30628: 01/04/19: Yu, Wenjiang [BVW:KCK2:EXCH]: some general questions about FPGA design
    30630: 01/04/19: Peter Alfke: Re: some general questions about FPGA design
        30632: 01/04/19: eteam: Re: some general questions about FPGA design
30633: 01/04/20: rk: Chief Technical Engineer Position, Maryland
30640: 01/04/20: Chaffey, Paul: Free timing diagram editor
30641: 01/04/20: jeung joon ee: FREE SDRAM-controller core
30643: 01/04/20: M.S.Gaur: XSV boards memory addressing
30644: 01/04/20: Jun: what does it mean in fe.log?
    30662: 01/04/22: Utku Ozcan: Re: what does it mean in fe.log?
        30702: 01/04/24: Helen Long: Re: what does it mean in fe.log?
            30704: 01/04/24: Chris Dunlap: Re: what does it mean in fe.log?
30647: 01/04/20: Dan: Who make Xilinx Proto PCBs ? Spartan II on PCI bus.
    30660: 01/04/22: Mark Harvey: Re: Who make Xilinx Proto PCBs ? Spartan II on PCI bus.
30648: 01/04/20: Dirk Munk: What is a FPGA ?
    30649: 01/04/20: Peter Alfke: Re: What is a FPGA ?
    30653: 01/04/21: Tony Burch: Re: What is a FPGA ?
30651: 01/04/20: k: Hobbiest + LINUX
    30658: 01/04/21: Eric Smith: Re: Hobbiest + LINUX
30655: 01/04/22: Russell Shaw: WinCUPL still alive?
    30656: 01/04/22: Jim Granville: Re: WinCUPL still alive?
        30659: 01/04/22: Russell Shaw: Re: WinCUPL still alive?
    30680: 01/04/23: Robert Myers: Re: WinCUPL still alive?
30657: 01/04/21: A1A Computer Professionals: Unlimited Jobs for Electronic Engineering jobs incl: ASIC,DSP,VHDL,FPGA,RF etc..
30663: 01/04/23: ÀåÁ¾¿ì: What is reconfigurable processor?
30664: 01/04/23: Paul Teagle: CIC interpolate by 3 & filter
    30676: 01/04/23: Ray Andraka: Re: CIC interpolate by 3 & filter
        30688: 01/04/23: Tony Kirke: Re: CIC interpolate by 3 & filter
            30695: 01/04/24: Ray Andraka: Re: CIC interpolate by 3 & filter
30665: 01/04/22: Helen: Frequency of FPGA
    30677: 01/04/23: Ray Andraka: Re: Frequency of FPGA
30666: 01/04/22: Helen: Something about the counter
    30667: 01/04/23: Peter Alfke: Re: Something about the counter
    30669: 01/04/22: eteam: Re: Something about the counter
    30684: 01/04/23: Helen: Re: Something about the counter
        30686: 01/04/24: Ray Andraka: Re: Something about the counter
    30700: 01/04/24: Richard D. Mohlere: Re: Something about the counter
        30703: 01/04/24: Helen Long: Re: Something about the counter
            30735: 01/04/26: Magnus Homann: Re: Something about the counter
            30919: 01/05/03: Bhupesh: Re: Something about the counter
30668: 01/04/23: Matt Billenstein: Virtex-E HDL -- Possible to clock register directly from ibuf?
    30714: 01/04/25: Carsten Nöding: Re: Virtex-E HDL -- Possible to clock register directly from ibuf?
    30757: 01/04/27: Alan Nishioka: Re: Virtex-E HDL -- Possible to clock register directly from ibuf?
    30917: 01/05/03: Bhupesh: Re: Virtex-E HDL -- Possible to clock register directly from ibuf?
    30957: 01/05/04: Magnus Homann: Re: Virtex-E HDL -- Possible to clock register directly from ibuf?
30670: 01/04/23: Kristian Rye Vennesland: Altera DSP Design Kit
30675: 01/04/23: Rick Filipkiewicz: Virtex-E & 5V tolerance
    30679: 01/04/23: Austin Lesea: Re: Virtex-E & 5V tolerance
        30715: 01/04/25: Rick Filipkiewicz: Re: Virtex-E & 5V tolerance
30678: 01/04/23: Shawki Areibi: FPGA Prototyping Kits (Platforms)
    30848: 01/05/01: Dave Feustel: Re: FPGA Prototyping Kits (Platforms)
        30853: 01/05/01: Dave Vanden Bout: Re: FPGA Prototyping Kits (Platforms)
30681: 01/04/23: Edward: Any good sources for digital rf processing ?
    30690: 01/04/23: Anonymous Idiot: Re: Any good sources for digital rf processing ?
        30698: 01/04/24: Austin Lesea: Re: Any good sources for digital rf processing ?
        30699: 01/04/24: Edward: Re: Any good sources for digital rf processing ?
            30713: 01/04/25: Lukose Ninan: Re: Any good sources for digital rf processing ?
30683: 01/04/23: Helen: CarryLogic
    30691: 01/04/23: ivar: Re: CarryLogic
        30694: 01/04/24: Keith R. Williams: Re: CarryLogic
30685: 01/04/23: Chuck Woodring: timing.dly file in Xilinx
30687: 01/04/24: Joseph Mak: System Spec
30692: 01/04/24: <martin.j.thompson@trw.com>: Altera Mercury comments
    30693: 01/04/24: Nial Stewart: Re: Altera Mercury comments
        30705: 01/04/25: Rick Collins: Re: Altera Mercury comments
30696: 01/04/24: <ts1@its.com.sg>: * mail server not work on NT through cable modem
30697: 01/04/24: Vivian: XHWIF and Virtex Strartup
    30729: 01/04/26: Vivian: Re: XHWIF and Virtex Strartup
30701: 01/04/24: Shawki Areibi: SPARTAN vs VERTEX
    30710: 01/04/25: Les S Brodie: Re: SPARTAN vs VERTEX
    30711: 01/04/25: Falk Brunner: Re: SPARTAN vs VERTEX
    30716: 01/04/25: Kolja Sulimma: Re: SPARTAN vs VERTEX
30706: 01/04/25: Ralf =?iso-8859-1?Q?Oberl=E4nder?=: Failed to configure Spartan2
    30707: 01/04/25: Wilhelm Heupke: Re: Failed to configure Spartan2
30708: 01/04/25: Carsten Nöding: Pin A1 on Spartan2 chips
    30712: 01/04/25: Falk Brunner: Re: Pin A1 on Spartan2 chips
30709: 01/04/25: <greg.polk@polkservices.net>: Accept credit cards online at only 9.1% service charge 8363
30717: 01/04/26: BriMDavis: Virtex-II LUT aspect ratio
30718: 01/04/25: Richard B. Katz: MAPLD Conference - Call for Papers and Registration Open
30719: 01/04/25: Jeff: What is wrong with Xilinx Foundation Simulator?
    30721: 01/04/25: Ivar: Re: What is wrong with Xilinx Foundation Simulator?
30720: 01/04/26: William Lenihan: Virtex power supplies.
    30731: 01/04/26: Henri: Re: Virtex power supplies.
30722: 01/04/26: mok: VHDL coding question.
    30882: 01/05/02: auliya: Re: VHDL coding question.
        30888: 01/05/02: Steve Rencontre: Re: VHDL coding question.
            30903: 01/05/02: Colin Marquardt: Re: VHDL coding question.
        30904: 01/05/02: Mike Treseler: Re: VHDL coding question.
30723: 01/04/26: Chaffey, Paul: TimingTool and Netscape
30724: 01/04/26: mike: Configuration via PCI JTAG
    30726: 01/04/26: Nicolas Matringe: Re: Configuration via PCI JTAG
    30739: 01/04/26: cyber_spook: Re: Configuration via PCI JTAG
        30741: 01/04/26: Austin Franklin: Re: Configuration via PCI JTAG
            30742: 01/04/27: Erik Widding: Re: Configuration via PCI JTAG
                30764: 01/04/27: cyber_spook: Re: Configuration via PCI JTAG
30725: 01/04/26: Scullen: it worked-site for salary information
30727: 01/04/26: Paul Teagle: manufacturer's of FIR chips
    30730: 01/04/26: Ray Andraka: Re: manufacturer's of FIR chips
        30796: 01/04/29: Pete Fraser: Re: manufacturer's of FIR chips
30728: 01/04/26: "elvira catherina": <no subject>
30732: 01/04/26: Falk Brunner: Re: bidirectional I/O
30733: 01/04/27: Ajack: Anyone use Altera PCI developement Kit ?
30734: 01/04/26: Jeff: Bidirection port simulation
    30747: 01/04/26: ivar: Re: Bidirection port simulation
30736: 01/04/26: Zhen Luo: bidirectional I/O
30737: 01/04/26: tiderh: clock to pad timing
    30738: 01/04/26: Austin Lesea: Re: clock to pad timing
30740: 01/04/26: vikram m n rao: XILINX Foundation UCF Problem
    30750: 01/04/27: Alan Fitch: Re: XILINX Foundation UCF Problem
    30752: 01/04/27: Vivian: Re: XILINX Foundation UCF Problem
30743: 01/04/26: Jeff: Bidirection Macro
30744: 01/04/27: Meelis Kuris: Modelsim license
30745: 01/04/27: Tomasz Brychcy: back annotation
    30753: 01/04/27: Atkins, Kate: Re: back annotation
30746: 01/04/27: Tomasz Brychcy: difference?
30748: 01/04/26: Jinhua Li: Virtex-II: Clock-to-PAD Issue
    30788: 01/04/29: Marko: Re: Virtex-II: Clock-to-PAD Issue
30749: 01/04/27: Tobias Stumber: VirtexE 5V PCI
30751: 01/04/27: vikram m n rao: Input Pins and Synthesis
    30754: 01/04/27: Alan Fitch: Re: Input Pins and Synthesis
        30755: 01/04/27: Ivan GARCIA ALFONSO: XILINX ngd2vhdl tool
    30770: 01/04/27: Anonymous Idiot: Re: Input Pins and Synthesis
30758: 01/04/27: Aki M Suihkonen: Comparison of FPGA and DSP
    30762: 01/04/27: Steven Derrien: Re: Comparison of FPGA and DSP
        30767: 01/04/28: Kevin Neilson: Re: Comparison of FPGA and DSP
            30775: 01/04/28: Kolja Sulimma: Re: Comparison of FPGA and DSP
            30792: 01/04/29: Steven Derrien: Re: Comparison of FPGA and DSP
    30765: 01/04/27: Ray Andraka: Re: Comparison of FPGA and DSP
    30784: 01/04/28: Steve Bradshaw: Re: Comparison of FPGA and DSP
        30863: 01/05/02: David Abbott: Re: Comparison of FPGA and DSP
        30921: 01/05/03: Ray Andraka: Re: Comparison of FPGA and DSP
            30932: 01/05/03: Kevin Neilson: Re: Comparison of FPGA and DSP
    30864: 01/05/02: David Abbott: Re: Comparison of FPGA and DSP
        30869: 01/05/02: Adrian Hey: Re: Comparison of FPGA and DSP
30759: 01/04/27: vikram m n rao: Setting Pins High
    30761: 01/04/27: Alan Nishioka: Re: Setting Pins High
        30830: 01/04/30: vikram m n rao: MORE Problems Setting Pins High!
            30832: 01/04/30: Dave Vanden Bout: Re: MORE Problems Setting Pins High!
    30763: 01/04/27: Jan Gray: Re: Setting Pins High
        30766: 01/04/28: Kolja Sulimma: Re: Setting Pins High
30760: 01/04/27: vikram m n rao: Setting Pins High (cont'd)
30768: 01/04/28: Kevin Neilson: C++ To Gates
    30771: 01/04/27: Anonymous Idiot: Re: C++ To Gates
    30773: 01/04/28: Richard Meester: Re: C++ To Gates
        30776: 01/04/28: Rick Filipkiewicz: Re: C++ To Gates
            30777: 01/04/28: Richard Meester: Re: C++ To Gates
                30779: 01/04/28: Magnus Homann: Re: C++ To Gates
                    30780: 01/04/28: Austin Franklin: Re: C++ To Gates
                        30793: 01/04/29: Magnus Homann: Re: C++ To Gates
                            30799: 01/04/29: Austin Franklin: Re: C++ To Gates
                                30818: 01/04/30: Kevin Neilson: Re: C++ To Gates
                                30857: 01/05/01: cyber_spook: Re: C++ To Gates
                                    30865: 01/05/01: Austin Franklin: Re: C++ To Gates
                        30959: 01/05/04: Peter: Re: C++ To Gates
                    30806: 01/04/30: Richard Meester: Re: C++ To Gates
                        30814: 01/04/30: Brian Drummond: Re: C++ To Gates
                            30820: 01/04/30: Magnus Homann: Re: C++ To Gates
                        30821: 01/04/30: Magnus Homann: Re: C++ To Gates
                            30834: 01/05/01: Richard Meester: Re: C++ To Gates
                                30836: 01/05/01: Magnus Homann: Re: C++ To Gates
                                    30837: 01/05/01: Richard Meester: Re: C++ To Gates
                                        30841: 01/05/01: Kolja Sulimma: Re: C++ To Gates
                                            30847: 01/05/01: Richard Meester: Re: C++ To Gates
            30782: 01/04/28: Phil Hays: Re: C++ To Gates
                30783: 01/04/28: Kolja Sulimma: Re: C++ To Gates
                    30787: 01/04/28: Austin Franklin: Re: C++ To Gates
                        30790: 01/04/29: Kolja Sulimma: Re: C++ To Gates
                            30798: 01/04/29: Austin Franklin: Re: C++ To Gates
                                30804: 01/04/30: Kolja Sulimma: Re: C++ To Gates
                    30794: 01/04/29: Magnus Homann: Re: C++ To Gates
                        30797: 01/04/30: Rick Filipkiewicz: Re: C++ To Gates
                            30801: 01/04/29: Austin Franklin: Re: C++ To Gates
                            30803: 01/04/30: Kolja Sulimma: Re: C++ To Gates
                                30805: 01/04/30: Allan Herriman: Re: C++ To Gates
                                30822: 01/04/30: Magnus Homann: Re: C++ To Gates
                            30845: 01/05/01: Austin Franklin: Gates to Hardware...
                            31147: 01/05/13: Dave Feustel: Re: C++ To Gates
        30817: 01/04/30: Kevin Neilson: Re: C++ To Gates
            30827: 01/04/30: Rick Filipkiewicz: Re: C++ To Gates
30769: 01/04/28: Kevin Neilson: BlockRAM outputs and the Placer
    30772: 01/04/27: Anonymous Idiot: Re: BlockRAM outputs and the Placer
    30778: 01/04/28: Allan Herriman: Re: BlockRAM outputs and the Placer
        30815: 01/04/30: Kevin Neilson: Re: BlockRAM outputs and the Placer
    30781: 01/04/28: Phil Hays: Re: BlockRAM outputs and the Placer
30774: 01/04/28: Huang: Internal Error of routing in iSE3.3i
    30953: 01/05/04: Carl Stern: Re: Internal Error of routing in iSE3.3i
    30980: 01/05/07: Bret Wade: Re: Internal Error of routing in iSE3.3i
    30981: 01/05/07: Bret Wade: Re: Internal Error of routing in iSE3.3i
30785: 01/04/28: Buckin: CPLD
30786: 01/04/29: Russell Shaw: Multiple state machines in altera AHDL
    30800: 01/04/30: Russell Shaw: Re: Multiple state machines in altera AHDL
        30809: 01/04/30: Greg Deuerling: Re: Multiple state machines in altera AHDL
            30813: 01/05/01: Russell Shaw: Re: Multiple state machines in altera AHDL
                30816: 01/04/30: Nial Stewart: Re: Multiple state machines in altera AHDL
                    30831: 01/05/01: Russell Shaw: Re: Multiple state machines in altera AHDL
                        30835: 01/05/01: Nial Stewart: Re: Multiple state machines in altera AHDL
                        30839: 01/05/01: Magnus Homann: Re: Multiple state machines in altera AHDL
                    30842: 01/05/01: Greg Deuerling: Re: Multiple state machines in altera AHDL
                        30852: 01/05/01: Nial Stewart: Re: Multiple state machines in altera AHDL
                            30883: 01/05/02: Greg Deuerling: Re: Multiple state machines in altera AHDL
                    30850: 01/05/01: Erik Widding: Re: Multiple state machines in altera AHDL
                        30866: 01/05/02: Russell Shaw: Re: Multiple state machines in altera AHDL
        30833: 01/04/30: Luke Roth: Re: Multiple state machines in altera AHDL
        30838: 01/05/01: Russell Shaw: Re: Multiple state machines in altera AHDL
30789: 01/04/29: Thomas Wambera: Verilog + VHDL - and the other?
    30791: 01/04/29: Bertram Geiger: Re: Verilog + VHDL - and the other?
30795: 01/04/29: <Jhon12@hotmail.com>: Speedup games, programs and get more FREE RAM
30802: 01/04/30: A. I. Khan: Need info : Training on ASIC/FPGA
    30826: 01/04/30: Tom: Re: Need info : Training on ASIC/FPGA
        30900: 01/05/02: Jeff Cunningham: Re: Need info : Training on ASIC/FPGA
30807: 01/04/30: jawahar ali: FPGA-CPLD
    30808: 01/04/30: Falk Brunner: Re: FPGA-CPLD
    30812: 01/04/30: Kolja Sulimma: Re: FPGA-CPLD
30810: 01/04/30: Vivian: problems with rc1000pp and xhwif
30811: 01/04/30: <aa@mail.pt>: New sites 8994
30819: 01/04/30: Kevin Neilson: Shannon Capacity
    30823: 01/04/30: Austin Lesea: Re: Shannon Capacity
        30854: 01/05/01: Berni Joss: Re: Shannon Capacity
            30855: 01/05/01: Austin Lesea: Re: Shannon Capacity
                30889: 01/05/02: Steve Rencontre: Re: Shannon Capacity
                    30892: 01/05/02: Austin Lesea: Re: Shannon Capacity
                        30901: 01/05/02: Berni Joss: Re: Shannon Capacity
                            30902: 01/05/02: Austin Lesea: Re: Shannon Capacity
                            30908: 01/05/02: Philip Freidin: Re: Shannon Capacity
                            30982: 01/05/07: Vikram Pasham: Re: Shannon Capacity
                                30987: 01/05/08: Aki M Suihkonen: Re: Shannon Capacity
                                    30991: 01/05/08: Nemo: Re: Shannon Capacity
                                        31011: 01/05/09: Aki M Suihkonen: Re: Shannon Capacity
                                31049: 01/05/10: Muzaffer Kal: Re: Shannon Capacity
                                    31056: 01/05/10: Nemo: Re: Shannon Capacity
                30895: 01/05/02: Kolja Sulimma: Re: Shannon Capacity
                31128: 01/05/12: Rick Collins: Re: Shannon Capacity
            30874: 01/05/02: Klaus Falser: Re: Shannon Capacity
        30867: 01/05/01: rk: Re: Shannon Capacity
    30873: 01/05/02: Klaus Falser: Re: Shannon Capacity
        30893: 01/05/02: Austin Lesea: Re: Shannon Capacity
    30886: 01/05/02: Nemo: Re: Shannon Capacity
        30890: 01/05/02: Steve Rencontre: Re: Shannon Capacity
            30906: 01/05/02: Austin Lesea: Re: Shannon Capacity
                31131: 01/05/12: Rick Collins: Re: Shannon Capacity
            30977: 01/05/07: Jamie Lokier: Re: Shannon Capacity
        30894: 01/05/02: Austin Lesea: Re: Shannon Capacity
        30912: 01/05/03: Klaus Falser: Re: Shannon Capacity
            30920: 01/05/03: Nemo: Re: Shannon Capacity
                30929: 01/05/03: Kevin Neilson: Re: Shannon Capacity
                    30930: 01/05/03: Austin Lesea: Re: Shannon Capacity
                        30933: 01/05/03: Eric Smith: Re: Shannon Capacity
                            30934: 01/05/03: Eric Smith: Re: Shannon Capacity
                        30946: 01/05/04: Nemo: Re: Shannon Capacity
                    30947: 01/05/04: Nemo: Re: Shannon Capacity
                        30949: 01/05/04: Nemo: Re: Shannon Capacity
30824: 01/04/30: Stan Ramsden: FPGA : JTAG emulation in FPGA
30825: 01/04/30: Jonas Thor: High resolution time measurement?
    30828: 01/04/30: Austin Lesea: Re: High resolution time measurement?
        30829: 01/04/30: Kevin Neilson: Re: High resolution time measurement?
    30858: 01/05/01: Jonas Thor: Re: High resolution time measurement?
        30859: 01/05/01: Kolja Sulimma: Re: High resolution time measurement?
        30861: 01/05/01: Austin Lesea: Re: High resolution time measurement?
            30870: 01/05/02: Kolja Sulimma: Re: High resolution time measurement?
    30875: 01/05/02: Victor Schutte: Re: High resolution time measurement?
        30896: 01/05/02: Falk Brunner: Re: High resolution time measurement?
    30931: 01/05/03: Richard Dungan: Re: High resolution time measurement?
    30968: 01/05/05: John Larkin: Re: High resolution time measurement?
        30973: 01/05/06: Jonas Thor: Re: High resolution time measurement?
            30974: 01/05/06: John Larkin: Re: High resolution time measurement?
    31505: 01/05/28: Gonzalo Arana: Re: High resolution time measurement?


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