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Send me an email I'll send you a list Thank you software1for10@hotmail.comArticle: 30376
I have a QPSK receiver which has two sets of differential outputs, I & Q. I'll need to compensate for phase rotation before I can convert the I & Q signals into serial data. Where can I find imformation on how to do this ?Article: 30377
>Hello everyone > >I need some information on the basic introduction of FPGA.Please give me >some advise . > > I not-exactly-humbly suggest the resources at http://www.ednmag.com/ednmag/verticalmarkets/PLD.asp ;-) Brian Dipert Technical Editor: Memory, Multimedia and Programmable Logic EDN Magazine: http://www.ednmag.com Contributing Editor, CommVerge Magazine: http://www.commvergemag.com 1864 52nd Street Sacramento, CA 95819 (916) 454-5242 (voice), (916) 454-5101 (fax) ***REMOVE 'NOSPAM.' FROM EMAIL ADDRESS TO REPLY*** mailto:bdipert@NOSPAM.pacbell.net Visit me at http://members.aol.com/bdipertArticle: 30378
Qian wrote: > I tried to implement my VHDL program by Xilinx Foundation 3.li > however in my Place & Route step I got error information about timing constraint like > " > -------------------------------------------------------------------------------- > Constraint | Requested | Actual | Logic > | | | Levels > -------------------------------------------------------------------------------- > TS_N870 = PERIOD TIMEGRP "N870" 20 nS | | | > HIGH 10 nS | | | > -------------------------------------------------------------------------------- > * TS_CLK = PERIOD TIMEGRP "CLK" 20 nS HI | 20.000ns | 24.742ns | 18 > GH 10 nS | | | > -------------------------------------------------------------------------------- > TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO | 20.000ns | 11.374ns | 3 > TIMEGRP "PADS" 20 nS | | | > -------------------------------------------------------------------------------- > * TS_0 = MAXDELAY FROM TIMEGRP "N870" TO TI | 10.000ns | 27.188ns | 17 > MEGRP "PADS" 10 nS | | | > -------------------------------------------------------------------------------- > OFFSET = IN 20 nS BEFORE COMP "CLK" | 20.000ns | 17.622ns | 16 > -------------------------------------------------------------------------------- > * OFFSET = OUT 20 nS AFTER COMP "CLK" | 20.000ns | 24.097ns | 16 > -------------------------------------------------------------------------------- > > 3 constraints not met. > " > > Could anyone tell me how to solve that? > Thanks a lot! The timing of OFFSET contraints runs under the assumption that there is an external device running off the same clock that is using your output signals for its inputs. Basically what its saying is that the paths are so slow that even with 0 routing delay the path delays are longer than the clock period, and the and therefore synchronous operation is not possible. I've come across this before and although, strictly speaking, it should be a warning, I'm quite happy that it comes out as an error. I'm not generally in favour of tools that try to baby you in this way but in this case I/you are being told that continuing this layout is a waste of time. The ``PAR_ZEROFLOORS'' allows you to continue in the case that you need to analyse the paths to see why they are so sloooooow. In this case I don't think you'll need that since its clear that you will have to do some work to reduce the logic complexity - most likely you will have to do some pipelining. I have a rule-of-thumb for auto placed & routed designs coming from HDL synthesis. For a -6 VirtexE I mentally allow for 1.5-2 nsec per level and another 2 for the sum of the clock-to-out at the beginning of the path and the setup at the end. To do better than this you need, as Ray has said, to start getting into the floorplanner and/or use hard macros.Article: 30379
A simple way to do it is with differential detection. Basically multiplying your current complex sample by the complex conjugate of the previous sample will net you the sine and cosine of the phase difference between the samples, assuming the amplitude of the vector is more or less constant. There is a foil in my Modulation and Demodulation for FPGAs presentation (available on my website) showing a simple 1/4pi DQPSK receiver using this technique. The example was an IS-94 cell modem implemented in a Xilinx 4013. Edward wrote: > > I have a QPSK receiver which has two sets of differential outputs, > I & Q. I'll need to compensate for phase rotation before I can > convert the I & Q signals into serial data. Where can I find > imformation on how to do this ? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30380
Would like to implement Power-On-Reset. Use no external Reset pin. Asynchronous RST is used throughout the design on all flops/memories. What is the procedure for tying GSR to RST during synthesis (FPGA Express user)? Thnx.Article: 30381
>I have to map a clk phase generator, generating 8 clk phases >@155MHz. The distance between phases is 800ps and high >precision is required. >Does anybody knows about some programmable (very)fast >logic that can allow that? I don't know if there is some ECL >(or PECL) programmable stuff anywhere.... Interesting problem. PCB traces are pretty stable. 800 ns is ~5 inches. That probably isn't good enough for what you want. (But keep it in mind. You will have to correct for it anyway.) You could use coax instead and adjust as needed. Motorola makes a chip that's a digitally controlled delay. It's just a long chain of buffers with digital inputs selecting or bypassing clumps of buffers. You can adjust the delay in steps of ~20 ps up to ~2ns. E195/E196. Motorola (and probably others) make PECL PLLs. You could multiply your clock by 4. Now it's just "simple" logic to make the signals you want. Switch the differential pairs for the other 4 phases. -- These are my opinions, not necessarily my employeers. I hate spam.Article: 30382
Hal Murray wrote: > > >I have to map a clk phase generator, generating 8 clk phases > >@155MHz. The distance between phases is 800ps and high > >precision is required. > >Does anybody knows about some programmable (very)fast > >logic that can allow that? I don't know if there is some ECL > >(or PECL) programmable stuff anywhere.... > > Interesting problem. > > PCB traces are pretty stable. 800 ns is ~5 inches. That probably > isn't good enough for what you want. (But keep it in mind. You will > have to correct for it anyway.) You could use coax instead and > adjust as needed. > > Motorola makes a chip that's a digitally controlled delay. > It's just a long chain of buffers with digital inputs selecting or > bypassing clumps of buffers. You can adjust the delay in steps of > ~20 ps up to ~2ns. E195/E196. Has anyone tried a self-checking chain of the 40ps delays, in the newest FPGAs - you connect ~161 of them, and tap nominally every 20, then shuffle the groups Up/Dn under loop control to track the CLOCK. ( Peter A? ) Failing that, there is always a 1.24GHz source, and a PECL ring ctr, that will be high precision, and without phase jumps. On Semi's web site quotes 3GHz clocks for their QuadFF in PECL. -jgArticle: 30383
I just used DATAIN(23 downto 0) however in schematic we only have IPAD(16) & IPAD(8) I don't know how to combine them together Thanks a lot!Article: 30384
> But, I'm not quite sure how to implement a digital volume-control in the > FPGA. I am using > PCM-code and have been dabbling with the idea to just divide the > PCM-code with a user-defined number > to get a "weaker" signal, but that would change the frequency of the > signal somewhat. > Making the pulses less wide won't infect the frequency of the signal because the sampling frequency will/must be way beyond the maximal frequency of the audio signal so the harmonics you generate by shortening the PCM pulses will/must be filtered out in the last stage of your amplifier. Greetings, Mark Sterk If you want to mail me non-spam messages, don't send it into the void, send it to: mailto:strong@sjello.nlArticle: 30385
On Wed, 04 Apr 2001 20:48:53 GMT, edlee@gpetech.com (Edward) wrote: >I have a QPSK receiver which has two sets of differential outputs, >I & Q. I'll need to compensate for phase rotation before I can >convert the I & Q signals into serial data. Where can I find >imformation on how to do this ? The idea is simple - you have to derotate your I and Q. This is simply a complex conjugate multiply (think of vector rotation): (A+iB).(C-iD) = (AC+BD) + i(BC-AD) ie. 4 multiplies and 2 additions. The problem now is knowing what to multiply by (ie. the values of C and D). I don't know about IS94 (Ray's post), but on the 3G stuff I've worked on the phase reference changes so slowly (ie. C,D are effectively constant) that a DSP calculates the required derotation from a pilot channel and supplies the "constant" value to the hardware; you wouldn't bother to calculate sample-to-sample rotation in hardware. Depends on what system you're working on, and how clever your algorithms people are. BTW, you don't have to serialise *after* the derotation. It generally makes sense to serialise as early as possible; you can then optimise your multiplications and additions. EvanArticle: 30386
Helen Long wrote: > I just used DATAIN(23 downto 0) > however in schematic we only have IPAD(16) & IPAD(8) > I don't know how to combine them together > Thanks a lot! I don't know what schematic editor you are using, but here is how to do it with the editor in Xilinx Foundation: 1) Attach a bus to an instance of IPAD16 and name it DATAIN[15..0]. 2) Attach another bus to an instance of IPAD8 and name it DATAIN[7..0]. -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||Article: 30387
Hi, How Can I use Xilinx Spartan II DLL to 2x multiple? (~50% duty cycle needed) I've tried to implement the schematic on page 12 at http://www.xilinx.com/xapp/xapp174.pdf But it doesn't work! I've tried to modify CLKFB connect to CLK2X, but the result is similar. Any idea? Arnold Ps: Please mail me the answares too: mailto:arno@freemail.huArticle: 30388
Matt Hayes ha scritto nel messaggio <3ac9ba09$1@news.star.co.uk>... >I'm aware that quite a number of people believe that the RC4 algorithm isn't >particularly suited to hardware but the idea interests me nonetheless. The question is interesting and I hope to hear some guys more expert than me! It seems me RC4 is easy to implement in a PLD or FPGA with good performances. It requires only three additions and a swap for each byte to encrypt and I think it can be done with less than hundred cells and a 256 x 8 ram. Perhaps it has the best performance to cost ratio of all the well-known encryption algorithms! > >I have performed a few websearches but can't really find the answers I am >looking for. > >In particular, I would like to know: >a) what rates of data throughput have been achieved by RC4 implementations >on an FPGA? what is the fastest ever? I don't know the fastest implementation. I think it can be about 20-50 MBytes/s in a low cost PLD. The bottleneck is the RAM cycle time, and perhaps this prevent significant enhacements by pipelining. Luigi >b) if it is possible to purchase a fast RC4/ARC4 IP Core and what throughput >rates can be expected. > >Thanks, > > Matt. > >Article: 30389
I just started integration with my new boards and we're having trouble programming the FPGA's. This board is an IP format board on an Acromag carrier (PCI) on a PC running Windows 2k pro. It has 1 7k series and 2 20k200E's. The 7k is interface and control logic, etc. and is programmed via JTAG. The 2 20k's are programmed via Passive Serial w/ no device (just writing through the 7k). The 7k is fine, no problem, talks to the PC great. Programming the 20k's starts fine, the logic analyzer shows the proper waveform (per AN116), but CONF_DONE never goes high. I'm downloading .rbf files which are fixed size and big enough to generate the extra DCLK's necessary for INIT_DONE to go high also, but it doesn't. Hmmm... just to check things, I tried to program all 3 chips via JTAG chain (using .sof files for the 20k's). It sets up fine, downloads data, but no CONF_DONE so it fails at the end. Hmmmm, again...... pull-up resister ok, no short to ground, no short to another signal driving low, no noisy TCK, etc... I'm using MAX PLUS v10 for the 7k and latest Quartus for the 20k's. I've tried downloading the JTAG chain from both (skipping the 7k in Quartus). I've also tried using the chain, but programming each device individually. Questions: Should JTAG chain work? Since the 20k's were set up for passive serial, the CONF_DONE's are tied together. Since CONF_DONE powers up low, will chip2 keep chip1 from driving CONF_DONE hi after programming (and vice versa)? Any other ideas? Thanks much for all help and consideration, AndrewArticle: 30390
The power on reset happens whether you specify a global reset or not, and regardless of whether or not your logic has async resets on it or not. For synthesis, you needn't do a thing if you don't have a reset pin on your design. If you want to simulate it however, then use the ROC component in the unisim library. It gets connected to your Global reset net. You can leave it in there if you want. Synthesis will put the ROC in your design as a black box, and the xilinx software will ignore it. yuryws@banet.net wrote: > > Would like to implement Power-On-Reset. Use no external Reset pin. > Asynchronous RST is used throughout the design on all flops/memories. > > What is the procedure for tying GSR to RST during synthesis (FPGA > Express user)? > > Thnx. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30391
That schematic works fine. If you are not using the 1x clock, you can take the feedback from either the 1x or 2x outputs (in that case, I'd favor the 2x because it will take into account your circuit loading and won't use up the other BUFG. If you are using both the 1x and 2x clock, you must take the feedback off the 1x or you wind up with phase ambiguity on the generated 1x clock (and it usually seems to come up opposite what you wanted only when you aren't looking). If it is not owrking in simulation, the reason may be that your simulator resolution is too coarse. Set the simulator resolution to 100ps or finer. Fuzesi Arnold wrote: > > Hi, > > How Can I use Xilinx Spartan II DLL to 2x multiple? > (~50% duty cycle needed) > > I've tried to implement the schematic on page 12 at > http://www.xilinx.com/xapp/xapp174.pdf > > But it doesn't work! > > I've tried to modify CLKFB connect to CLK2X, but the result is similar. > > Any idea? > > Arnold > Ps: Please mail me the answares too: mailto:arno@freemail.hu -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30392
Hi All, I am having trouble configuring a Spartan II chip via the JTAG interface. The chip is an XC2S100-5CES in the PQ208 package. This is what I have done: I have a simple VHDL design, which I synthesise using Synplify Pro. I enable Readback and Reconfiguration in the Design Manager (To turn off the security flag). I then use the Xilinx Design Manager to generate a bitstream for this device. All appears to go well up to here. I enter the JTAG programmer. Connect to the cable and initialise the chain. The device is detected as being a Virtex XCV100. I assign the bitstream file I have created to the device. (which is targeted to an XC2S100_PQ208) I can get the ID number and the signature/usercode number from the device. Now when I try to program the device (without verify) this is the feedback I get. 'cpu_wrapper(Device1)': Checking boundary-scan chain integrity...done. 'cpu_wrapper(Device1)': Reading bit-stream file...done. 'cpu_wrapper(Device1)': Programming device.....done. 'cpu_wrapper(Device1)': If the security flag is turned on in the bitstream, programming status can not be confirmed; otherwise, programming terminated due to error. I have a suspicion that this is somehow due to the device being detected as a Virtex, and this is something to do with the fact that the chip is an Engineering Sample, but really I'm only guessing. Does anyone have any ideas about what is happening? Thanks very much. Dean ArmstrongArticle: 30393
Matt Hayes <matthewhayes9000@hotmail.com> wrote in message news:3ac9ba09$1@news.star.co.uk... > I'm aware that quite a number of people believe that the RC4 algorithm isn't > particularly suited to hardware but the idea interests me nonetheless. RC4 is not particularly compute intensive as encryption algorithms go, but being a symmetric algorithm, usually requires a key exchange mechanism such as Diffie-Hellman which is what really kills throughput. > I have performed a few websearches but can't really find the answers I am > looking for. > > In particular, I would like to know: > a) what rates of data throughput have been achieved by RC4 implementations > on an FPGA? what is the fastest ever? > b) if it is possible to purchase a fast RC4/ARC4 IP Core and what throughput > rates can be expected. I don't know about cores, but you might check rainbow.com and ncipher.com for encryption specific chipsets.Article: 30394
Hi Gang: Now ,i use Modelsim5.5.When i load or run a large design,it will always close automatic. Why?Article: 30395
The way I interprete your question, you need to divide a 155 MHz clock perid into eight parts. (Right??) The Virtex and Virtex-E devices give you four clock quadrants, which seems to meet half your requirements. Virtex-II goes further than that, it allows you to define the phase delay of any clock in increments of 1/256 of the clock period, implemented with stable delays of 50 ps increment. And there are 16 low-skew clock networks... So, Virtex-E gets you halfway to your goal, and Virtex-II easily meets all your requirements, even if it were *NOT* an even division of the clock period. And you get hundreds or thousands of flip-flops and LUTs plus a bunch of BlockRAMs and multipliers as a bonus. Should be hard to resist :-) Peter Alfke, Xilinx Applications Riccardo Zambon wrote: > Hi all, > I have to map a clk phase generator, generating 8 clk phases > @155MHz. The distance between phases is 800ps and high > precision is required. > Does anybody knows about some programmable (very)fast > logic that can allow that? I don't know if there is some ECL > (or PECL) programmable stuff anywhere.... > > Forgetting ECL, has anybody experienced VirtexII family at very high > system speed? > > Thanks for help, > Riccardo > > -- > Posted from david.siemens.it [192.109.0.136] > via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 30396
"W.Turk" wrote: > > Hi Gang: > Now ,i use Modelsim5.5.When i load or run a large design,it will > always close automatic. > Why? How much RAM do you have? UtkuArticle: 30397
If the 20ke's are set up for passive serial configuration, TRST pins should be tied to GND. To be able to configure the devices via the JTAG chain you need to connect the pins to I/O Vcc. VitaliyArticle: 30398
"W.Turk" wrote: > > Hi Gang: > Now ,i use Modelsim5.5.When i load or run a large design,it > will always close automatic. > Why? I have the same problem and I think, as Utku suggested, that it is RAM related. It usually happens when I restart the simulation. It works fine after freeing some RAM. -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 30399
I have a similar problem, I need 4 phases of 270MHz clock. But in Virtex-II, in low frequency mode I get only 210MHz from DCM, in high frequency mode clk90 output is not available. Will it work if I first create two 135MHz clocks with 45 degrees phase shift in low freq mode and then multiply both by 2 in high freq mode? The phase shift doesn't have to be very precise, -/+10 degrees would be ok I think. Mexx. "Peter Alfke" <palfke@earthlink.net> wrote in message news:3ACD5062.7425E890@earthlink.net... .. > Virtex-II goes further than that, it allows you to define the phase > delay of any clock in increments of 1/256 of the clock period, > implemented with stable delays of 50 ps increment. And there are 16 > low-skew clock networks... > > So, Virtex-E gets you halfway to your goal, and Virtex-II easily meets > all your requirements, even if it were *NOT* an even division of the > clock period. And you get hundreds or thousands of flip-flops and LUTs > plus a bunch of BlockRAMs and multipliers as a bonus. Should be hard to > resist :-) > > Peter Alfke, Xilinx Applications
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