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1994JulAugSepOctNovDec1994
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2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
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2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015Jan2015

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Authors (Q)

q:
    1401: 95/06/15: Understanding Lattice equations
    1583: 95/07/21: Xilinx XACT Ver 6.0
    1780: 95/08/31: Re: Actel PCI App Note
qamrul:
    143004: 09/09/14: 8 phase clock output
    143027: 09/09/15: Re: 8 phase clock output
    143029: 09/09/15: Re: 8 phase clock output
    143036: 09/09/15: Re: 8 phase clock output
    143152: 09/09/23: Re: 8 phase clock output
    143160: 09/09/23: Re: 8 phase clock output
    143171: 09/09/23: Re: 8 phase clock output
    143580: 09/10/16: Re: Tsamp for Spartan 3?
qaz:
    20391: 00/02/08: PC Card - generally 3.3V signaling on laptops?
    22110: 00/04/24: Quartus "clock skew excedes data delay" error
QBA:
    56512: 03/06/07: Logical analyzer via USB or printer port
qdsn:
    46334: 02/08/26: help me with analogue FPGAs or FPAA (and TRAC, PSOC, ispPAC etc.)
qfwfq:
    21069: 00/03/06: about multipliers
    27157: 00/11/13: applet for drawing sorting networks
<qhblhcjo@somethingfunny.net>:
    11950: 98/09/21: WOW!!! WHAT A STORY ONLINE!!!
Qi Sun:
    84213: 05/05/15: Re: Cant link with xil_malloc() function
    85835: 05/06/17: what's my problem with downloading?
Qian:
    29505: 01/02/23: UNISIM
    29955: 01/03/19: Cannot Export netlist from Synopsys
    30329: 01/04/02: Timing Error
    30373: 01/04/04: Simulation result shows that
Qian Zhang:
    1595: 95/07/24: Re: Help on Altera FLEX 8000 programming
    1601: 95/07/25: Re: FLEX8000 programming
    1911: 95/09/19: Re: Altera and Synopsys Interface
    26074: 00/10/02: Xilinx Demo Board
    26100: 00/10/03: Urgent How to generate BitFile
    26813: 00/10/30: Xilinix Foundation Question
    27025: 00/11/07: Re: help on a simple ALU
    27024: 00/11/07: 'event synthesis question
    27030: 00/11/07: Re: 'event synthesis question
    27056: 00/11/08: Re: 'event synthesis question
    27196: 00/11/14: Re: Clear AND Preset Pins
    27197: 00/11/14: Re: How to read schematic after synthesis
    27198: 00/11/14: Des warning matter?
    27221: 00/11/15: FPGA Pin Nunber
    27243: 00/11/16: Re: Need help locking pins for Spartan XL
    27859: 00/12/12: TWo CLOKS in VHDL synthesis
    27862: 00/12/12: Re: TWo CLOKS in VHDL synthesis
    27919: 00/12/14: Re: ERROR: The net has more than one driver?
    28130: 00/12/21: PIN NOT FOUND
    28131: 00/12/21: Implementation Fatal Error
qianeasy:
    70509: 04/06/18: Re: TCP/IP in Virtex II Pro
Qiang He:
    62768: 03/11/07: ispLSI-2064 -- how to decompile jedec file to ldf file?
<qianz@my-deja.com>:
    23529: 00/06/28: Xilinx Foundation Macro creation problem
    27165: 00/11/13: How to read schematic after synthesis
QiDaNei:
    66243: 04/02/15: confused DCM clkin_period vs true input clock
    66301: 04/02/16: how to priotize multiple conflicting constraints
    66434: 04/02/19: Is there an easy way to get a list of unused pin in ML300?
    66450: 04/02/19: why ISE par does not tell me all buffer usage?
Qingbo:
    134827: 08/09/03: what is the maximum number of DDR controllers
    134848: 08/09/03: Re: what is the maximum number of DDR controllers
qlyus:
    32277: 01/06/21: Re: Synplify register replication
    32284: 01/06/22: Re: Xilinx: Download times with Parallel/Multilinx cable
    32965: 01/07/13: Re: Problems: Xilinx 3.1i Service Pack 8
    34236: 01/08/16: Re: Internal clock skew when using DLL
    35759: 01/10/16: Is Xilinx AppNote#258 correctly documented ?
    47170: 02/09/19: Re: Has ISE 5.1i shipped?
    49256: 02/11/06: Xilinx, where is DesignManager in ISE 5.1 ?
    50558: 02/12/12: Re: Suggestions required for Handel-C code
    53541: 03/03/15: Quality of Xilinx Document
    57268: 03/06/26: why so many problems Xilinx ?
    57298: 03/06/26: Re: why so many problems Xilinx ?
    57300: 03/06/27: Re: why so many problems Xilinx ?
    61438: 03/10/03: Re: LVDS_25_DCI : Top Ten List
    61779: 03/10/10: Virtex-II Pro Core Voltage on ML300
    66593: 04/02/23: Why does Xilinx keep saying LVPECL_2.5 and _3.3V are identical?
    66610: 04/02/24: Re: Why does Xilinx keep saying LVPECL_2.5 and _3.3V are identical?
    67651: 04/03/16: ISE 6.2 (w/ SP#1) is 10+ times slower than 6.1
    67701: 04/03/17: Re: ISE 6.2 (w/ SP#1) is 10+ times slower than 6.1
    68587: 04/04/08: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
    68608: 04/04/09: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
    68617: 04/04/09: Does IBUFDS_DIFF_OUT with -DT option exist?
    68669: 04/04/13: New test of ISE 6.2 w/ SP#2
    70118: 04/06/03: Re: tri-state in altera
    70124: 04/06/03: Re: tri-state in altera and xilinx
    70125: 04/06/03: where is ISE 6.2 SP#3 ?
<qnnmoq@you.com>:
    31148: 01/05/13: Find your sole mate here!! Post your FREE personal ADs here!
<854272335@qq.com>:
    131873: 08/05/05: Silicon
<qqulbu@aerosmith.net>:
    18449: 99/10/25: WALK THIS WAY TALK THIS WAY
QRaheeL:
    88287: 05/08/14: XST (ISE 6.1i): Error: It's interesting and surprising
qrk:
    103026: 06/05/24: Re: PCI 64/66 fpga eval boards
    131269: 08/04/17: Re: Survey: FPGA PCB layout
    131310: 08/04/18: Re: Survey: FPGA PCB layout
    142011: 09/07/21: Re: Spartan 3 and DDR2
qtommy:
    94670: 06/01/16: problem with the SRAM
    94671: 06/01/16: Re: Displays an image in the XS Board RAM on a VGA monitor
quad:
    113995: 07/01/02: Bitstream programming
    114300: 07/01/10: EDIF generation from C
    114316: 07/01/11: Re: EDIF generation from C
    114423: 07/01/15: EDIF format
    114640: 07/01/21: Re: edif format
    115428: 07/02/10: NGDBuild error
Quadibloc:
    145772: 10/02/23: Re: using an FPGA to emulate a vintage computer
    146035: 10/03/04: Re: using an FPGA to emulate a vintage computer
    146095: 10/03/05: Re: using an FPGA to emulate a vintage computer
    146097: 10/03/05: Re: using an FPGA to emulate a vintage computer
    146099: 10/03/05: Re: using an FPGA to emulate a vintage computer
    146101: 10/03/05: Re: using an FPGA to emulate a vintage computer
    146122: 10/03/06: Re: using an FPGA to emulate a vintage computer
    146124: 10/03/06: Re: using an FPGA to emulate a vintage computer
    146125: 10/03/06: Re: using an FPGA to emulate a vintage computer
    146169: 10/03/07: Re: using an FPGA to emulate a vintage computer
    146180: 10/03/07: Re: using an FPGA to emulate a vintage computer
    146184: 10/03/07: Re: using an FPGA to emulate a vintage computer
    152124: 11/07/11: Re: HercuLeS high-level synthesis tool
    152131: 11/07/12: Re: HercuLeS high-level synthesis tool
    152134: 11/07/12: Re: HercuLeS high-level synthesis tool
    152561: 11/09/14: Re: The Manifest Destiny of Computer Architectures
    152583: 11/09/15: Re: The Manifest Destiny of Computer Architectures
Qualicum Consulting:
    16849: 99/06/14: FAE In Ottawa ASAP!!!!!!! l-
Quang Anh:
    118631: 07/05/01: Re: fast arbiters (was Re: How to design an abitration cicuit...)
    119091: 07/05/11: Re: fast arbiters (was Re: How to design an abitration cicuit...)
quantum:
    69837: 04/05/21: Old XCV50 FPGA and Ethernet
<quark.flavour@gmail.com>:
    127688: 08/01/05: Re: DDR SDRAM demo for Spartan-3E starter kit?
    127705: 08/01/06: Re: DDR SDRAM demo for Spartan-3E starter kit?
    127706: 08/01/06: Re: Spartan 3E Sarter Kit Ethernet
    127757: 08/01/07: Re: DDR SDRAM demo for Spartan-3E starter kit?
    127806: 08/01/08: Re: DDR SDRAM demo for Spartan-3E starter kit?
    127834: 08/01/08: Re: Using DDR SDRAM as single data rate ..?
quark01:
    96270: 06/02/01: Re: Parallel Cable IV does not work with parallel to usb cable
    105953: 06/08/03: Re: Chipscope
<quark01@gmail.com>:
    90101: 05/10/04: Re: How to make XST understand to pack mux(A,B,A+B) in a single level ?
<quarrie92@googlemail.com>:
    157023: 14/09/02: Re: Easy PC software tool - Bad experience
Quazar:
    101326: 06/04/29: PCI bridge
qudhs:
    68476: 04/04/06: Virtex2PV20 programming failed, DONE pin doesn't go HIGH
    68570: 04/04/08: Re: EDK 6.1: User Logic
    69938: 04/05/25: Virtex2P co-simulation problems using Modelsim and smartmodel
    74477: 04/10/12: xilinx VP20 and SDRAM
    77178: 04/12/28: failed to write to SDRAM
Quesito:
    112534: 06/11/24: Re: jtag loader for picoblaze
    112535: 06/11/24: Re: jtag loader for picoblaze
    112741: 06/11/28: verilog 2 VHDL translator
    112790: 06/11/29: Re: verilog 2 VHDL translator
    112973: 06/12/03: Picoblaze C compiler 1.8.4
    113015: 06/12/05: Re: Picoblaze C compiler 1.8.4
    113169: 06/12/07: Re: FPGA+Ethernet
    114525: 07/01/18: Re: PCI Card with FPGA
    115163: 07/02/01: Re: Webpack 9.1 problems with Impact on parallel cable
<quickwayne@gmail.com>:
    105781: 06/07/31: Re: Accessing one SDRAM from two MicroBlazes
    105785: 06/07/31: Re: Problems compiling with ISE Webpack 8.2.01i
    105813: 06/08/01: Re: Where are Huffman encoding applications?
    105836: 06/08/01: Re: Accessing one SDRAM from two MicroBlazes
    105858: 06/08/01: Re: Accessing one SDRAM from two MicroBlazes
    105907: 06/08/02: Re: MPD file option HDL
    105971: 06/08/03: Re: How can we fully utilize available BRAMs...
    105979: 06/08/04: Re: profiling my application in microblaze...
    106620: 06/08/16: Re: FPGA Memory Power
    106751: 06/08/18: Re: tcp/ip
    106752: 06/08/18: Re: EDK vs. ISE for image processing
    106860: 06/08/21: Re: CPU design
    108829: 06/09/17: A strange problem of Chipscope
    108843: 06/09/18: Re: A strange problem of Chipscope
    108847: 06/09/18: Re: A strange problem of Chipscope
    108913: 06/09/19: Re: A strange problem of Chipscope
Quiet Desperation:
    30970: 01/05/05: Re: VirtexE LVPECL I/O Ports? experience?
    34169: 01/08/15: Multilinx problem
    37763: 01/12/19: Virtex 2 & Trace
    37779: 01/12/20: Re: Virtex 2 & Trace
    45352: 02/07/19: FPGA Compiler II, Windows Version 3.7.1
    78278: 05/01/27: Rocket I/O + Optical Fiber
    78293: 05/01/28: Re: Rocket I/O + Optical Fiber
    78305: 05/01/28: Re: Rocket I/O + Optical Fiber
    79482: 05/02/19: Re: why to use FIFO on FPGA?
    79483: 05/02/19: Re: why to use FIFO on FPGA?
    79515: 05/02/20: Re: why are PCI-based FPGA cards so expensive ?
    81488: 05/03/24: LVPECL, Virtex II and the EP445
    81491: 05/03/24: Re: LVPECL, Virtex II and the EP445
    81500: 05/03/25: Re: LVPECL, Virtex II and the EP445
    81516: 05/03/25: Re: LVPECL, Virtex II and the EP445
    81519: 05/03/25: Re: LVPECL, Virtex II and the EP445
    82111: 05/04/06: Hey Xilinx
    82682: 05/04/15: Re: Hobby or job? (FPGA User's groups anyone?)
    83985: 05/05/10: 2.5/3.3 LVPECL in Virtex
Quigley:
    37269: 01/12/05: Newbie: FPGA or microcontroller for MPEG4 decoding?
QuikShot Computer Products:
    1384: 95/06/11: "Free" - E-Z Computer Assembly Guide
Quin:
    26800: 00/10/30: Undergraduate PLD Studies
Quinn:
    75309: 04/11/02: FPGA & DDR-SDRAM
    75311: 04/11/02: Re: FPGA & DDR-SDRAM
    75357: 04/11/03: Re: FPGA & DDR-SDRAM
    75502: 04/11/08: Re: Personality Module (Z-Dok) proto board for ML310
Quinn Johnson:
    75621: 04/11/11: Rocket IOs and Infiniband protocol
<quittj@my-deja.com>:
    27761: 00/12/06: Re: dual port ram for altera
Quy Dinh:
    4040: 96/09/05: PCI Bus Protocal & FPGA vendors
<qvhqlm@aerosmith.net>:
    18466: 99/10/26: WICKED WILD WILD WEST 8795
<qwerty@scottfamily.cc>:
    20413: 00/02/09: Re: odd behavior of Virtex RAM Block model
    24014: 00/07/21: Real time sims with NC-Verilog
    24326: 00/08/04: Re: Real time sims with NC-Verilog
    24327: 00/08/04: Large CPLD
    24633: 00/08/15: Lattice 8k family
<qykmel@nowhere.com>:
qysheng:
    41847: 02/04/08: virtexe pin problem
    103619: 06/06/06: IOBDELAY's delay value


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015Jan2015

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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