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Well good for you Brad. Sometimes the simulations can be tricky. In my testbenches, I typically generate a testbench clock tb_clk <= not tb_clk after CLOCK_PERIOD_CONST/2; I think Mike Tressler has a tic procedure that you can google for. In the testbench stimulus process: data <= (others => '0'); wait until rising_edge(tb_clk); -- change signals wait until rising_edge(tb_clk); -- etc Then I sometimes do a concurrent assignment uut_clk <= tb_clk after 5 ns; -- OK for non synthesizable code The above separates the data transitions from the clock transitions making the waveforms easier to view, and by tweaking the delay of the clock, one can effectively slide the data closer to the clock to crosscheck setup / hold input timing constraints for post place and route simulations. If the delay is more than 1/2 a clock cycle, it does not work because of some (I think) inertial pulse swallowing simulation property, but can be worked around by splitting the delay into two pieces. Good Luch Newman "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:111f8cseruh7t45@corp.supernews.com... > Thanks Newman, > > I think you are right. My problem is how I interpret the waveforms > not with the FIFO simulations themselves. There is something else > wrong with my design, but I now have both the behaviour and the > PAR sims working the same way. > > Brad > >Article: 79476
FIFOs, Are useful as a means to synchronize the passing of data between asynchronous clock domains. If you need to communicate both data, and when the data is ready, between two clock domains that are not the same in both frequency and/or phase, a FIFO is a universal means to allow the two clock domains to communicate without error. To synchonize events in one domain, to another domain requires the use of synchronizing circuits which are notorious in that engineers often get them wrong (they implement ones that do not work). At Intel, there are only a handful of senior engineers who are allowed to do synchronizer circuits. One of my first ever crisis cases at Xilinx was one where a cutomer had occasional errors in their application, which seemed to come and go at random. They blamed it on different lots of our silicon. Some lots they claimed, were worse, and some were not as bad. Well, it turned out that the bad lots were slightly slower (but well within specifications), and the good lots (which still had the problem, but not as often) were slightly faster. The speed difference made a poor FIFO design using CLBs have more (or less) frequent problems. In no case was their FIFO design good. It was always capable of failing, as they spun their own control, without regard to what an incredibly difficult problem it is. For example, what if the FIFO says it is ready with data to read, when it is not? That leads to a failure. What if it says it is ready to accept data on a write, when it is full? Also, a failure. Think about your gas gauge saying that you have gas, when you do not: not acceptable. But, there is a way to design a FIFO to be foolproof, even though in theory, that is impossible (without latency). So, if we do it for you (in hard logic), it saves you from making a very common mistake. By the way, the secret to low latency synchronization in FIFOs is that the gas gauge could say the tank was empty, when it was not, and then go back to being less than empty without causing any problems (thanks to Peter for this analogy). If you used our soft core FIFO (previous to V4), you would also be safe. But many looked at the FIFO IP, and said to themselves "I am smarter than that -- look at all the wasted logic to do such a simple job!" Sadly, it is not a simple job. Peter and I were in a 2 day class just last week on just this subject (asynchronous design, and communications between clock domains in large systems). Heck, Peter 'invented' the FIFO back at Fairchild! Even us "more experinced" engineers realize that we can (must) learn new things. Since the FIFO is built into the hardware, I imagine it is trivial to instantiate. Let us know if the HDL primitives are in Webpack. It would make no sense to Xilinx not to promote their use, as they prevent engineers from doing things the wrong way, and allow you to pack more into your design, and achieve higher performance. Austin bobrics@gmail.com wrote: > Hi, > Why do you need a FIFO? Is it similar to GBUF, IBUF for clocks to > buffer the signals for stability or more like temporary memory? > > If it's more like temporary memory, then why not just use intermediate > signals to store input signals and delay them (use shift register) a > specific number of clocks if needed? > > Also, is FIFO a Xilinx primitive component available with Webpack? > > Thanks >Article: 79477
I read the article and it is very interesting, but the code seems to be written in verilog, or pseudi verilog. Where I can find a brief verilog manual?Article: 79478
austin wrote: > FIFOs, > > Are useful as a means to synchronize the passing of data between > asynchronous clock domains. And even if you only have a single clock domain you use a FIFO in hardware for all applications that you use a FIFO in software, albeit in software the name Queue is more often used. bobrics@gmail.com wrote >If it's more like temporary memory, then why not just use intermediate >signals to store input signals and delay them (use shift register) a >specific number of clocks if needed? In a shift register you delay data for N cycles. In a FIFO you delay up to N data words as long as necessary. Kolja SulimmaArticle: 79479
Here are my 2 cents: I call a FIFO an ideal "Black Box", where you clock data in on one side, and pull it out with a different clock on the other side. And you need not worry about frequency or phase differences between the clock, and how much or how little data is in the FIFO (until you reach full or empty.) What makes a FIFO with independent clocks so attractive to the user (its simplicity), makes it really tough on the black box designer, for whom all problems stem from the unknown phase relationship between the two clocks. That's why there are Gray-coded counters and sneaky resynchronization circuits that are (almost) immune to metastable problems. Metastability is covered up by extra latency that releases empty a clock tick later than theoretically possible... Long answers to a short question. Each BlockRAM in Virtex-4 has a FIFO controller buried in the BlockRAM. Not very big since it is done in dedicated hard logic, but saves the user all the work and also all the thinking. And we tested it with 10e14 resynchronizing cycles at 500 MHz clock rate, with no failure. Peter Alfke, Xilinx Applications (from home on a rainy Saturdey)Article: 79480
austin wrote:
> If you used our soft core FIFO (previous to V4), you would also be safe.
> But many looked at the FIFO IP, and said to themselves "I am smarter
> than that -- look at all the wasted logic to do such a simple job!"
Well, sometimes it is the case. Have a look at Altera's NCO/DDC
megafunction and related examples. They explicitly generate a pair
of sine and cosine waves and then pass it to a mixer composed
of two rapid multipliers. This consumes many LEs, even on Stratix,
if the NCO uses the CORDIC approach. I have done a better and
smaller DDC/DUC without multipliers on Cyclone. Simply, the
algorithmic approach is a bit more sophisticated.
Best regards
Piotr Wyderski
Article: 79481Piotr, A comment on the soft cores (IP) of Altera, or Xilinx in general. Basically, soft IP (cores, or functions) need to be: * bullet-proof (fool-proof) * easy to use * versatile * configurable What these constrains lead to are cores that are generally not optimal for any specific function, but do the job. Any given core can probably be trimmed, modified, sped up, and improved. The FIFO core is one where that would be very dangerous, unless you were familiar with FIFO design, synchronizers, and asynchronous logic fundamentals. Many engineers are very smart, and can do a better job on any specific function (for their particular application). I would caution against it when dealing with synchronizing elements, like FIFOs. But, I would also caution that if you think you can do a better job, remember that verification is 90% of the work. Anything you modify, or improve makes you responsible for its verification. As I design for the next technology node, I look at what others did before me, and if I think I can improve upon it, I first ask: - why did they do it this way? - what may be other functions of this block that I am ignoring? - is there something I am not considering? - am I prepared to verify what I have changed? - do I have access to the test benches and simulations that were done by the prior owners? - what will I accomplish by my changes? - am I better off working on something else? - does it make business sense? Remember the classic engineering maxim: "If it ain't broke, don't fix it." Austin Piotr Wyderski wrote: > austin wrote: > > >>If you used our soft core FIFO (previous to V4), you would also be safe. >> But many looked at the FIFO IP, and said to themselves "I am smarter >>than that -- look at all the wasted logic to do such a simple job!" > > > Well, sometimes it is the case. Have a look at Altera's NCO/DDC > megafunction and related examples. They explicitly generate a pair > of sine and cosine waves and then pass it to a mixer composed > of two rapid multipliers. This consumes many LEs, even on Stratix, > if the NCO uses the CORDIC approach. I have done a better and > smaller DDC/DUC without multipliers on Cyclone. Simply, the > algorithmic approach is a bit more sophisticated. > > Best regards > Piotr Wyderski >Article: 79482
In addition to async clock domains as other have mentioned, I have a case where a data stream is split into MSBs and LSBs. The LSBs undergo some processing that takes several hunded clock cycles. The MSBs pass through, but need to be aligned with the output associated with the original LSBs with which they were paired. I *could* make 500 F/F long shift registers, but a block RAM based FIFO is must more efficient. I had another case where a PC would send commands to a FIFO, and the circuitry would fetch and process the commands in its own time, but gueess that's just another example of async clock. I have one case now where the clock is the same frequency on both sides of the FIFO, but the input clock is a fairly low quality (unavoidable... long story) while the output clock is a low phase noise uberclock divided from a faster clock. The clocks are coherent, but only through a large external loop involving a fractional-N PLL and other synthesis. Rather than trying to time up two clocks like this, it's far easier to just pass the data through a FIFO and not even worry about it. So it serves two functions: reclocking to a *cleaner* clock domain and avoiding a gnarly timing situation.Article: 79483
In article <1108855173.976052.110150@f14g2000cwb.googlegroups.com>, Peter Alfke <alfke@sbcglobal.net> wrote: > Here are my 2 cents: > I call a FIFO an ideal "Black Box", where you clock data in on one > side, and pull it out with a different clock on the other side. And you > need not worry about frequency or phase differences between the clock, > and how much or how little data is in the FIFO (until you reach full or > empty.) The real fun is if you have a situation like one of my designs where the data propagation delay through the FIFO of has to be identical from reset to reset within a certain spec. Synchronous reset of input and output pointers? Synchronous to which clock? Say you use the input clock. When that reset deasserts, the rising edge of the output clock can be anywhere within the period of the input clock (it's *asynchronous*) thus causing a prop delay uncertainty of one period on the input clock. Does not seem a big deal unitl I realize the clock period is 40 ns and my uncertainty spec is 5 ns. :( I did solve it, BTW, but as it might be patentable, I cannot speak of it. :)Article: 79484
Thanks KCL. I used a state machine to model that part of the design. Seems like its working.ITs only a piece of a bigger part. I am trying to have this display module be one of the modules for a VHDL vending machine. Do you know any materials in the internet that can help me design this vending machine. It has the following features: 1) 5 products price - 55/60/65/70/75c 2) 3 different coin inputs -25 c/10c/5c 3) Need to display the product price and price entered via the 3 coin inputs. 4) When the value of product selected is reached, it should be dispensed and any change displayed. 5) System should reset after this and also reset if done asynchronously.Article: 79485
A HW-designer's lament: I'm new to FPGA's, but not to HW design in general. Xilinx/Altera et al all characterize their FPGA's in terms of (very nice) HW features. Great, you buy an ev-kit, fire up the SW, only to discover that the SW, i.e, HDL, hides the HW from you. A design that could have been hand-wired in a matter of hours (using imaginary discrete chips having the function-blocks of the FPGA) now turns into an aggravated struggle against the SW (others have described it as pushing a rope, or searching for an incantation which will magically make the synthesis tool behave). Isn't there some way to do direct design instead of the tedious imposing of constraints upon an excruciatingly stupid piece of SW? Thoughts? Cheers, TomArticle: 79486
On Sat, 19 Feb 2005 18:01:21 -0800, Tom <tagerbaek@epo.org> wrote: >A HW-designer's lament: I'm new to FPGA's, but not to HW design in general. Xilinx/Altera et al all characterize their FPGA's in terms of (very nice) HW features. Great, you buy an ev-kit, fire up the SW, only to discover that the SW, i.e, HDL, hides the HW from you. A design that could have been hand-wired in a matter of hours (using imaginary discrete chips having the function-blocks of the FPGA) now turns into an aggravated struggle against the SW (others have described it as pushing a rope, or searching for an incantation which will magically make the synthesis tool behave). Isn't there some way to do direct design instead of the tedious imposing of constraints upon an excruciatingly stupid piece of SW? Thoughts? Cheers, Tom That's so hard to read all on one line without wrapping. When are Xilinx going to fix the software on www.xtra.xilinx.com ? Surely it's not hard; newsgroups have been around for a couple of decades now. (I know that some readers will wrap long lines, but not all of them do.) AllanArticle: 79487
Where is a good place to find info on building VHDL moore FSMs? I am trying to design a vending machine with the following features on a spartan 3 kit. It has the following features: 1) 5 products price - 55/60/65/70/75c 2) 3 different coin inputs -25 c/10c/5c 3) Need to display the product price and price entered via the 3 coin inputs.(first 2 digits display coin input values, last 2 digits display product price, use any digits to display change out) 4) When the value of product selected is reached, it should be dispensed and any change displayed. 5) System should reset after this and also reset if done asynchronously. The books I have talk about FSMs for 4-5 pages. Not good enough for me to start thinking about this the right way. thanksArticle: 79488
Hello, I have to use a Xilinx ML310 developement board in my final year project to test a VHDL design and to use Chipscope. My question is, is it necessary to use the parallel Cable IV in order to configure the Virtex 2Pr??? if so how can i use chipscope in order to read out my internal signals??? is it possible to use only the compact flash to do all these things?? Thanls a lotArticle: 79489
When I first got involved with embedded development I had a similar first reaction. With Altera's Quartus II software there is a graphic editor, MAX+plusII compatibility mode that and 74xx series library that once you learn how to use the tools would allow you to design, implement and test a system in a fraction of the time it would take to breadboard or wire wrap the same design. My suggestion to you is to down load Quartus II wepack and try the online tutorials. Especially the MAX+plusII tutorial. If you don't mind spending the money on a textbook or the time looking it up at a local technical university library, try "Digital Electronics with VHDL" by William Kleitz, ISBN 0-13-110080-7, TK7868.D5K555 2004. The author blends HDL design methods with skills like you have. DerekArticle: 79490
Hi, Thanks Bart for that answer. Yeah that's actually what I am working on right now, and stuck on one part, how do you know when it fail, and how do you know what the bit error rate is? In simulation I can see everything, but when I actually download the code to the FPGA, I don't know what's going on in there. I tried reading the result back via JTAG register, but it didn't work, BSCAN JTAG only allows me to read back register with very simple program. With a program this complicated, it didn't work. In addition to this bit error rate measurement, my boss wants a DNL and INL measurement; so as soon as I get done with this bit error rate measurement, I have to work on the DNL and INL part. Greatly appreciate if anyone can help! Thanks, AnnArticle: 79491
Hi Jason, But isn't that for simulation only? I want something to display after I download the program to the FPGA and ran it. Thanks, AnnArticle: 79492
I think you're confused about the capabilities of FPGAs. You can think of an FPGA as a bunch of logic with input wires and output wires. To display any kind of output message you will need some kind of output peripheral, such as an LCD. Or you can go even simpler than that and use a few 7-segment displays. You can then interface your display device with the FPGA and then write HDL code to drive the display and make it display what you want. Asking an FPGA to display a message directly is kind of like asking the power socket on the wall to play your DVD - the power socket can drive a DVD player, but it cannot directly play a DVD. Similarly, an FPGA can drive a display device but it cannot directly display a message. AL wrote: > Hi Jason, But isn't that for simulation only? I want something to display after I download the program to the FPGA and ran it. Thanks, AnnArticle: 79493
To print text on display I need to have font on a rom. Could you explain how to create a file to copy into rom?Article: 79494
I am trying to add USB IP core to PLB bus (not xilinx core), I have few basic doubts each time if I add any new IP core to exist hardware config do I need to build new Libraries and BSPs and integerate with kernel source and build new kernel?. Which part of kernel changes each time I add new IPcore ? because after adding new core I couldnot build new BSPs..Iam getting problems. One more doubt is I want to build my own base(hardware) system, but am getting messed up with memeory mapping...is any standard logic I should follow for memory mapping, can I get any tutorial which has example templete for memory mapping . I know above questions are simple so any of your suggestions can boost my confidence as beginner. thanksArticle: 79495
Hi, Some CS research papers propose the use of FPGA as PC co-processors for very specialized hard computing task (like searching DNA sequences). It's easy to find starter kits in the $100-200 range to experiment with FPGAs, but connecting them through the parallel port doesnt give a supercomputer :-; and the price of PCI based cards seem to be 2 orders of magnitude higher. Why is it so ? Is there no market niche for a cheap (say $200-500) general purpose co-processor card ? (Just wondering) Michel BillaudArticle: 79496
I have heared roumors that the PLL in Cyclone doesn't work below -20C if the output frequency is higher than the input. There is some fine print in the datasheet to that effect. Now I have no way of knowing if that is true or not - I live in California :)) "Alessandro Strazzero" <alessandro.strazzero@virgilio.it> wrote in message news:391fed46.0502180459.5ad267fb@posting.google.com... > Dear everybody, > > the goal of my post is to collect your opinions about the use of Altera Cyclone > devices in a rugged environment. I have to design a board which should control > a chopper based on GTOs. The environment is a railway vehicle and the following > are the conditions I have to consider: > > - extreme temperature range (-40°C to +85°C) > - strong mechanical vibrations > - long life duration (> 25 years) > - high degree of reliability > - very low frequency of maintenance > > From the point of view of the design I think Altera Cyclone is the best choise > for this kind of project beacuse its high flexibility. But I have some doubts > about its functionality in a rugged environment like above. > > Did you experience the use of Altera Cyclone in a rugged environment ? > What are your opinions about my choise ? > > Best Regards > > /Alessandro StrazzeroArticle: 79497
Well, there are some issues with this code example: 1) The reset is missing, this is a problem for the simulation 2) integer based counters tend to not wrap arount automatically, I do not know for sure what synthesis might result, but simulation will fail 3) While the general behavior is ok with the above points corrected, this is not a shift register. Sorry. See notes below. Try again! Chris KCL wrote: > probably something like > --------------------------------- > signal cpt : integer range 0 to 15; --i'm not sure for this declaration this is ok > usually i use only std_logic with convertion > signal temp : std_logic_vector( 15 downto 0); > > process(clk) > begin Missing reset here, initialize cpt here! > if rising_edge(clk) then > cpt <= cpt +1 ; This is a counter which does not wrap around, since it is of type integer! Take care! > if cpt = 0 then > temp <= in_parallel; > end if; Parallel loadable register. ok. > out_serie <= temp(cpt); Multiplexer, with output register. NOT a shift register!! Where is the shift?? > end if; > end process; > ---------------------------------------- > > > there is many others way to do it you just have to test different solution > to get the better and have imagination... > > alexis > > "bob" <kmart@nospam.com> a écrit dans le message de news: > jgpb11pishb8c3lqkt6s49lo7hhve16674@4ax.com... > >>Shift register example? >>Hi I am looking for a parallel in serial out latching shift register >>in VHDL. >>I want 16 bits but any example would be appreciated. >> >>Thanks >> > > >Article: 79498
Antti Lukats wrote: > Hi all > > I re-found once again my own "Rules of Life" what I first published 21 aug > 2001 > > 1 No Promises. > 2 Keep Promises. > 3 Give away what you do not need. > 4 Do what you want to do. > 5 Be Happy. > > In order to comply with Rules [5], [4] and specially [3] from the above > list, I am giving a promise (those braking rule #1) that I will make all > projects of my past live available as public domain. That includs all I can > publish (ie all that IP that belongs to me and is not covered by 3rd party > agreements), with the exception of maybe a few selected projects I am > actually working on at the moment. > > In order to comply with [2] first project is made public today at: > http://gforge.openchip.org > > there is OPB I2C IP-Core that uses the OpenCores I2C Core by implementing a > OPB 2 Wishbone adapter. Just noticed that in your VHDL code you don't use inout ports, resulting in 200% bloating of a normal inout port declaration. I presume this is because XST is too lazy to parse inouts so that we have to do some kind of backend annotation alongside HDL programming, resulting in a not very elegant code. This is probably the price to pay for such a cheap tool, so I should not really complain. Synplify will allow you to use inouts in sub modules, but it costs much more than XST. TonyFArticle: 79499
bob wrote: > So I guess I am asking if anybody has some VHDL code for a parallel in > SPI out latch, or a SPI output counter. In Project Navigator 6.3i chose from the menu: Edit -> Language Templates -> VHDL -> Synthesis Constructs -> Coding Examples -> Shift Registers -> Parallel In, Serial Out Kolja Sulimma
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