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Threads Starting Oct 2008

135411: 08/10/01: Alfreeeeed: Post-synthesis simulation
    135412: 08/10/01: Mike Treseler: Re: Post-synthesis simulation
    135415: 08/10/01: Kevin Neilson: Re: Post-synthesis simulation
135418: 08/10/01: Dave: Asynchronous delay report shows delays longer that clock period - ok?
    135419: 08/10/01: Ed McGettigan: Re: Asynchronous delay report shows delays longer that clock period
135421: 08/10/01: <cs_posting@hotmail.com>: Gee Thanks Altera, I really enjoy having a break waiting on your
    135430: 08/10/01: LittleAlex: Re: Gee Thanks Altera, I really enjoy having a break waiting on your
    135453: 08/10/02: Leon: Re: Gee Thanks Altera, I really enjoy having a break waiting on your
    135476: 08/10/03: <cs_posting@hotmail.com>: Re: Gee Thanks Altera, I really enjoy having a break waiting on your
135424: 08/10/01: FP: Xilinx device not listed
    135426: 08/10/01: Mike Treseler: Re: Xilinx device not listed
        135431: 08/10/01: Ed McGettigan: Re: Xilinx device not listed
    135427: 08/10/01: FP: Re: Xilinx device not listed
    135447: 08/10/02: Gabor: Re: Xilinx device not listed
    135495: 08/10/05: FP: Re: Xilinx device not listed
135428: 08/10/01: Gabor: Re: which FPGA chip to use for FFT?
135429: 08/10/01: glen herrmannsfeldt: Re: which FPGA chip to use for FFT?
135439: 08/10/02: jack.harvard@googlemail.com: floating point round off errors
    135441: 08/10/02: Göran Bilski: Re: floating point round off errors
    135443: 08/10/02: Andreas Ehliar: Re: floating point round off errors
    135449: 08/10/02: Brian Drummond: Re: floating point round off errors
        135459: 08/10/02: glen herrmannsfeldt: Re: floating point round off errors
            135464: 08/10/03: Brian Drummond: Re: floating point round off errors
                135466: 08/10/02: glen herrmannsfeldt: Re: floating point round off errors
                    135473: 08/10/03: Brian Drummond: Re: floating point round off errors
    135451: 08/10/02: jack.harvard@googlemail.com: Re: floating point round off errors
135444: 08/10/02: <news@rblack01.plus.com>: Standalone Altera production programmer
    135446: 08/10/02: Rob: Re: Standalone Altera production programmer
    135465: 08/10/03: Jim Granville: Re: Standalone Altera production programmer
135454: 08/10/02: commone: Two questions about Xilinx constraints setting
    135457: 08/10/02: commone: Re: Two questions about Xilinx constraints setting
        135460: 08/10/02: Mike Treseler: Re: Two questions about Xilinx constraints setting
            135462: 08/10/02: commone: Re: Two questions about Xilinx constraints setting
    135461: 08/10/02: commone: Re: Two questions about Xilinx constraints setting
135458: 08/10/02: beky4kr@gmail.com: WEBPACK for linux
    135463: 08/10/02: Jon Elson: Re: WEBPACK for linux
        135468: 08/10/02: thutt: Re: WEBPACK for linux
        135470: 08/10/03: Dave Farrance: Re: WEBPACK for linux
            135474: 08/10/03: Brian Drummond: Re: WEBPACK for linux
135471: 08/10/03: Rob: Virtex-5 DDR2 DCI termination
    135478: 08/10/03: Barry: Re: Virtex-5 DDR2 DCI termination
135475: 08/10/03: jack.harvard@googlemail.com: synopsys designware components on xilinx fpga
    135481: 08/10/03: mike_la_jolla: Re: synopsys designware components on xilinx fpga
135483: 08/10/04: Weng Tianxiang: Do two clock system blocks with one clock running half of other's
    135486: 08/10/04: kadhiem_ayob: Re: Do two clock system blocks with one clock running half of other's need asynchronous input/output buffers?
    135501: 08/10/05: Weng Tianxiang: Re: Do two clock system blocks with one clock running half of other's
    135503: 08/10/05: Peter Alfke: Re: Do two clock system blocks with one clock running half of other's
        135590: 08/10/09: Brian Drummond: Re: Do two clock system blocks with one clock running half of other's need asynchronous input/output buffers?
    135506: 08/10/05: Simon: Re: Do two clock system blocks with one clock running half of other's
    135552: 08/10/07: Weng Tianxiang: Re: Do two clock system blocks with one clock running half of other's
    135553: 08/10/07: Weng Tianxiang: Re: Do two clock system blocks with one clock running half of other's
    135571: 08/10/08: Andy: Re: Do two clock system blocks with one clock running half of other's
    135581: 08/10/08: Weng Tianxiang: Re: Do two clock system blocks with one clock running half of other's
135484: 08/10/04: bjzhangwn@gmail.com: Xilinx PCIE problem
135487: 08/10/04: Moti: Video processing in FPGA
    135488: 08/10/04: John_H: Re: Video processing in FPGA
    135513: 08/10/06: Martin Thompson: Re: Video processing in FPGA
135489: 08/10/04: dajjou: Bitstream configuration question (virtex 5).
135490: 08/10/04: bjzhangwn@gmail.com: Xilinx PCIE problem
    135492: 08/10/04: Pete Fraser: Re: Xilinx PCIE problem
    135537: 08/10/06: Ben Jackson: Re: Xilinx PCIE problem
135491: 08/10/04: bjzhangwn@gmail.com: Virtex-5 Integrated Endpoint Block for PCI Express Designs
135493: 08/10/05: Ali: OTU2 implementation with Virtex 4
    135516: 08/10/06: Allan Herriman: Re: OTU2 implementation with Virtex 4
        135674: 08/10/12: Allan Herriman: Re: OTU2 implementation with Virtex 4
    135646: 08/10/10: Ali: Re: OTU2 implementation with Virtex 4
135494: 08/10/05: FP: Xilinx cores with license
    135529: 08/10/06: Gabor: Re: Xilinx cores with license
        135536: 08/10/06: Pete Fraser: Re: Xilinx cores with license
135496: 08/10/05: Alex: A question about the use of FPGA
    135499: 08/10/05: Frank Buss: Re: A question about the use of FPGA
    135505: 08/10/05: Peter Alfke: Re: A question about the use of FPGA
        135518: 08/10/06: RCIngham: Re: A question about the use of FPGA
        135527: 08/10/06: John_H: Re: A question about the use of FPGA
        135535: 08/10/06: Frank Buss: Re: A question about the use of FPGA
    135508: 08/10/06: Alex: Re: A question about the use of FPGA
    135524: 08/10/06: Gabor: Re: A question about the use of FPGA
    135542: 08/10/06: Alex: Re: A question about the use of FPGA
135497: 08/10/05: Eric: ISE Question - FPGA Program.jpg (0/1)
    135530: 08/10/06: MM: Re: ISE Question - FPGA Program.jpg (0/1)
135498: 08/10/05: Nicolas Matringe: Spartan 3E overmapping problem
    135500: 08/10/05: Jonathan Bromley: Re: Spartan 3E overmapping problem
        135512: 08/10/06: Nicolas Matringe: Re: Spartan 3E overmapping problem
    135514: 08/10/06: Martin Thompson: Re: Spartan 3E overmapping problem
        135525: 08/10/06: Gabor: Re: Spartan 3E overmapping problem
            135534: 08/10/06: Nicolas Matringe: Re: Spartan 3E overmapping problem
135502: 08/10/05: girl_aj: Barrel Shifter: Newbie's Attempt
    135504: 08/10/05: girl_aj: Barrel Shifter: Newbie's Attempt
        135517: 08/10/06: RCIngham: Re: Barrel Shifter: Newbie's Attempt
    135519: 08/10/06: Brian Drummond: Re: Barrel Shifter: Newbie's Attempt
        135521: 08/10/06: girl_aj: Barrel Shifter: Newbie's Attempt
            135540: 08/10/07: Brian Drummond: Re: Barrel Shifter: Newbie's Attempt
    135526: 08/10/06: Mike Treseler: Re: Barrel Shifter: Newbie's Attempt
135507: 08/10/05: <lomtikster@gmail.com>: Reading files from CF (microblaze 7 and plb)
    135510: 08/10/06: Göran Bilski: Re: Reading files from CF (microblaze 7 and plb)
        135511: 08/10/06: Göran Bilski: Re: Reading files from CF (microblaze 7 and plb)
    135523: 08/10/06: <jason.hy.wu@gmail.com>: Re: Reading files from CF (microblaze 7 and plb)
    135591: 08/10/09: <lomtikster@gmail.com>: Re: Reading files from CF (microblaze 7 and plb)
    135597: 08/10/09: morphiend: Re: Reading files from CF (microblaze 7 and plb)
    136188: 08/11/05: <lomtikster@gmail.com>: Re: Reading files from CF (microblaze 7 and plb)
    136210: 08/11/05: <markmcmahon@hotmail.com>: Re: Reading files from CF (microblaze 7 and plb)
    136293: 08/11/10: <lomtikster@gmail.com>: Re: Reading files from CF (microblaze 7 and plb)
135509: 08/10/06: <lomtikster@gmail.com>: Connecting MPD I/O ports in xps_sysace
    135520: 08/10/06: Brian Drummond: Re: Connecting MPD I/O ports in xps_sysace
    135592: 08/10/09: <lomtikster@gmail.com>: Re: Connecting MPD I/O ports in xps_sysace
135528: 08/10/06: Gabor: Re: ISE Question - FPGA Program.jpg (1/1)
135532: 08/10/06: wallra: learning videos for xilinx edk tools
135541: 08/10/06: maverick: Looking for an FPGA board with large memory and high speed interfaces
    135544: 08/10/07: morphiend: Re: Looking for an FPGA board with large memory and high speed
    135545: 08/10/07: maverick: Re: Looking for an FPGA board with large memory and high speed
135543: 08/10/07: chenzcdyb: trigger problem with chipscope
    135546: 08/10/07: Gabor: Re: trigger problem with chipscope
135547: 08/10/07: Nial Stewart: Actel constraints?
    135554: 08/10/08: Nial Stewart: Another problem....
        135557: 08/10/08: Gabor: Re: Another problem....
            135570: 08/10/08: Nial Stewart: Re: Another problem....
        135586: 08/10/08: Thomas Stanka: Re: Another problem....
    135585: 08/10/08: Thomas Stanka: Re: Actel constraints?
        135589: 08/10/09: Nial Stewart: Re: Actel constraints?
135548: 08/10/07: <andrea.cortis@gmail.com>: Newbie question
    135550: 08/10/07: Mike Treseler: Re: Newbie question
        135615: 08/10/10: Frank Buss: Re: Newbie question
    135551: 08/10/07: <andrea.cortis@gmail.com>: Re: Newbie question
    135583: 08/10/08: Masca: Re: Newbie question
    135599: 08/10/09: <andrea.cortis@gmail.com>: Re: Newbie question
135555: 08/10/08: Bar Nash: Those FPGA boards
    135559: 08/10/08: Gabor: Re: Those FPGA boards
    135560: 08/10/08: Rich Webb: Re: Those FPGA boards
        135602: 08/10/09: Derek Simmons: Re: Those FPGA boards
    135614: 08/10/09: John Adair: Re: Those FPGA boards
135556: 08/10/08: Bar Nash: Input to FPGA boards
135558: 08/10/08: Fred: Packet sniffer help
    135587: 08/10/09: Fred: Re: Packet sniffer help
        135594: 08/10/09: Rich Webb: Re: Packet sniffer help
135561: 08/10/08: Pratap: How to synthesize a delay of around 10 ns in FPGA?
    135562: 08/10/08: <lbraeckm@gmail.com>: Re: How to synthesize a delay of around 10 ns in FPGA?
        135565: 08/10/08: Symon: Re: How to synthesize a delay of around 10 ns in FPGA?
    135564: 08/10/08: Gabor: Re: How to synthesize a delay of around 10 ns in FPGA?
    135566: 08/10/08: Peter Alfke: Re: How to synthesize a delay of around 10 ns in FPGA?
        135573: 08/10/08: Thomas Heller: Re: How to synthesize a delay of around 10 ns in FPGA?
        135626: 08/10/10: Thomas Heller: Re: How to synthesize a delay of around 10 ns in FPGA?
    135568: 08/10/08: KJ: Re: How to synthesize a delay of around 10 ns in FPGA?
    135575: 08/10/08: Peter Alfke: Re: How to synthesize a delay of around 10 ns in FPGA?
    135576: 08/10/08: Selensky: Re: How to synthesize a delay of around 10 ns in FPGA?
    135584: 08/10/08: Peter Alfke: Re: How to synthesize a delay of around 10 ns in FPGA?
    135613: 08/10/09: Peter Alfke: Re: How to synthesize a delay of around 10 ns in FPGA?
    135673: 08/10/11: Peter Alfke: Re: How to synthesize a delay of around 10 ns in FPGA?
    135712: 08/10/13: Kolja Sulimma: Re: How to synthesize a delay of around 10 ns in FPGA?
    135713: 08/10/13: General Schvantzkopf: Re: How to synthesize a delay of around 10 ns in FPGA?
        135984: 08/10/25: John_H: Re: How to synthesize a delay of around 10 ns in FPGA?
    135892: 08/10/20: Pratap: Re: How to synthesize a delay of around 10 ns in FPGA?
    135893: 08/10/20: Pratap: Re: How to synthesize a delay of around 10 ns in FPGA?
    135894: 08/10/20: Pratap: Re: How to synthesize a delay of around 10 ns in FPGA?
        135942: 08/10/22: Joseph H Allen: Re: How to synthesize a delay of around 10 ns in FPGA?
    135897: 08/10/20: General Schvantzkopf: Re: How to synthesize a delay of around 10 ns in FPGA?
    135899: 08/10/20: Peter Alfke: Re: How to synthesize a delay of around 10 ns in FPGA?
    135906: 08/10/21: Pratap: Re: How to synthesize a delay of around 10 ns in FPGA?
    135908: 08/10/21: John_H: Re: How to synthesize a delay of around 10 ns in FPGA?
    135956: 08/10/24: Kolja Sulimma: Re: How to synthesize a delay of around 10 ns in FPGA?
    135982: 08/10/25: Pratap: Re: How to synthesize a delay of around 10 ns in FPGA?
135563: 08/10/08: Matthew Hicks: MUX Inference
    135569: 08/10/08: Andy: Re: MUX Inference
        135572: 08/10/08: Matthew Hicks: Re: MUX Inference
        135574: 08/10/08: Peter Alfke: Re: MUX Inference
135567: 08/10/08: Teece: I need a good reference for VHDL
    135578: 08/10/08: Brad Smallridge: Re: I need a good reference for VHDL
    135616: 08/10/09: Stephen: Re: I need a good reference for VHDL
        136054: 08/10/29: RCIngham: Re: I need a good reference for VHDL
    136029: 08/10/28: Vivek Menon: Re: I need a good reference for VHDL
135577: 08/10/08: Brad Smallridge: Xilinx VHDL inferred RAMs
    135588: 08/10/09: Rob: Re: Xilinx VHDL inferred RAMs
        135596: 08/10/09: Gabor: Re: Xilinx VHDL inferred RAMs
        135598: 08/10/09: KJ: Re: Xilinx VHDL inferred RAMs
    135603: 08/10/09: Brad Smallridge: Re: Xilinx VHDL inferred RAMs
135579: 08/10/09: Owen Duffy: Update Altera MAXII UFM post production
    135832: 08/10/16: <vaughnbetz@gmail.com>: Re: Update Altera MAXII UFM post production
        135848: 08/10/17: Owen Duffy: Re: Update Altera MAXII UFM post production
            135909: 08/10/21: Owen Duffy: Re: Update Altera MAXII UFM post production
        135905: 08/10/21: <cs_posting@hotmail.com>: Re: Update Altera MAXII UFM post production
135580: 08/10/08: <james.e.steward@gmail.com>: ChipScope on Ubuntu 7.10 - blank screen
135593: 08/10/09: <richard.draelos@gmail.com>: how to share infered ROM memories in synplify?
    135595: 08/10/09: Gabor: Re: how to share infered ROM memories in synplify?
135600: 08/10/09: Nial Stewart: More Actel 'Funnies'
    135601: 08/10/09: Nathan Bialke: Re: More Actel 'Funnies'
    135604: 08/10/09: Nicolas Matringe: Re: More Actel 'Funnies'
        135621: 08/10/10: Nial Stewart: Re: More Actel 'Funnies'
            135678: 08/10/12: Nicolas Matringe: Re: More Actel 'Funnies'
                135702: 08/10/13: Nial Stewart: Re: More Actel 'Funnies'
                    135714: 08/10/13: Nial Stewart: Re: More Actel 'Funnies'
                    135716: 08/10/13: Nicolas Matringe: Re: More Actel 'Funnies'
        135708: 08/10/13: Gabor: Re: More Actel 'Funnies'
135605: 08/10/09: Saul Bernstein: Virtex-5 clocking
    135607: 08/10/09: Ed McGettigan: Re: Virtex-5 clocking
        135628: 08/10/10: Saul Bernstein: Re: Virtex-5 clocking
            135643: 08/10/10: Ed McGettigan: Re: Virtex-5 clocking
    135632: 08/10/10: Gabor: Re: Virtex-5 clocking
135606: 08/10/09: Uwe Bonnes: Mismatch between XST and trce delay estimation
    135618: 08/10/10: Andreas Ehliar: Re: Mismatch between XST and trce delay estimation
        135623: 08/10/10: Andreas Ehliar: Re: Mismatch between XST and trce delay estimation
        135624: 08/10/10: Uwe Bonnes: Re: Mismatch between XST and trce delay estimation
135608: 08/10/09: ertw: Virtex 5 DSP48E Instantiation.
135609: 08/10/09: shawn: Rebuilding harware for Petalogix Linux
135610: 08/10/09: FreeWheel: Lattice vs Altera (Mico32 / NIOS)....or?
    135611: 08/10/09: Frank Buss: Re: Lattice vs Altera (Mico32 / NIOS)....or?
        135612: 08/10/09: Frank Buss: Re: Lattice vs Altera (Mico32 / NIOS)....or?
        135622: 08/10/10: MK: Re: Lattice vs Altera (Mico32 / NIOS)....or?
    135619: 08/10/10: Goli: Re: Lattice vs Altera (Mico32 / NIOS)....or?
    135625: 08/10/10: MMJ: Re: Lattice vs Altera (Mico32 / NIOS)....or?
    135629: 08/10/10: =?ISO-8859-1?Q?Adam_G=F3rski?=: Re: Lattice vs Altera (Mico32 / NIOS)....or?
    135641: 08/10/11: Jim Granville: Re: Lattice vs Altera (Mico32 / NIOS)....or?
        135696: 08/10/13: MMJ: Re: Lattice vs Altera (Mico32 / NIOS)....or?
            135701: 08/10/13: Jim Granville: Re: Lattice vs Altera (Mico32 / NIOS)....or?
                135710: 08/10/13: MMJ: Re: Lattice vs Altera (Mico32 / NIOS)....or?
                    135711: 08/10/13: =?ISO-8859-2?Q?Adam_G=F3rski?=: Re: Lattice vs Altera (Mico32 / NIOS)....or?
                        135715: 08/10/13: =?ISO-8859-2?Q?Adam_G=F3rski?=: Re: Lattice vs Altera (Mico32 / NIOS)....or?
    135642: 08/10/10: Jon Beniston: Re: Lattice vs Altera (Mico32 / NIOS)....or?
        135706: 08/10/13: MMJ: Re: Lattice vs Altera (Mico32 / NIOS)....or?
            135707: 08/10/13: Frank Buss: Re: Lattice vs Altera (Mico32 / NIOS)....or?
    135751: 08/10/14: Jon Beniston: Re: Lattice vs Altera (Mico32 / NIOS)....or?
135617: 08/10/09: Gary Pace: VHDL Training Course
    135620: 08/10/10: HT-Lab: Re: VHDL Training Course
        135630: 08/10/10: Gary Pace: Re: VHDL Training Course
            135633: 08/10/10: HT-Lab: Re: VHDL Training Course
    135638: 08/10/10: Mike Treseler: Re: VHDL Training Course
    136040: 08/10/28: <trainingcity@gmail.com>: Re: VHDL Training Course
135627: 08/10/10: <saira.samar@gmail.com>: ddr2 sdram xilin mig controller, mig v1.72 issue
135631: 08/10/10: Leon: XMOS XC-1 kits are shipping
    135636: 08/10/10: <steveu@coppice.org>: Re: XMOS XC-1 kits are shipping
        135662: 08/10/11: Joerg: Re: XMOS XC-1 kits are shipping
            135665: 08/10/11: Joerg: Re: XMOS XC-1 kits are shipping
        135671: 08/10/12: Brian Drummond: Re: XMOS XC-1 kits are shipping
        135721: 08/10/13: Joerg: Re: XMOS XC-1 kits are shipping
            135729: 08/10/13: Joerg: Re: XMOS XC-1 kits are shipping
            135978: 08/10/24: Albert van der Horst: Re: XMOS XC-1 kits are shipping
    135637: 08/10/10: Benjamin Couillard: Re: XMOS XC-1 kits are shipping
    135639: 08/10/10: Leon: Re: XMOS XC-1 kits are shipping
    135640: 08/10/10: Leon: Re: XMOS XC-1 kits are shipping
    135650: 08/10/11: Benjamin Couillard: Re: XMOS XC-1 kits are shipping
    135651: 08/10/11: Benjamin Couillard: Re: XMOS XC-1 kits are shipping
    135652: 08/10/11: Simon: Re: XMOS XC-1 kits are shipping
        135654: 08/10/11: Hamish Shufflebotham: Re: XMOS XC-1 kits are shipping
            135657: 08/10/11: Hamish Shufflebotham: Re: XMOS XC-1 kits are shipping
                135659: 08/10/11: Hamish Shufflebotham: Re: XMOS XC-1 kits are shipping
                    135682: 08/10/12: Hamish Shufflebotham: Re: XMOS XC-1 kits are shipping
    135653: 08/10/11: Leon: Re: XMOS XC-1 kits are shipping
    135656: 08/10/11: Leon: Re: XMOS XC-1 kits are shipping
    135658: 08/10/11: Leon: Re: XMOS XC-1 kits are shipping
    135661: 08/10/11: Leon: Re: XMOS XC-1 kits are shipping
    135663: 08/10/11: HardySpicer: Re: XMOS XC-1 kits are shipping
    135664: 08/10/11: Leon: Re: XMOS XC-1 kits are shipping
    135666: 08/10/11: HardySpicer: Re: XMOS XC-1 kits are shipping
    135667: 08/10/11: Leon: Re: XMOS XC-1 kits are shipping
    135668: 08/10/11: Leon: Re: XMOS XC-1 kits are shipping
    135669: 08/10/11: Randy Yates: Re: XMOS XC-1 kits are shipping
    135670: 08/10/11: Leon: Re: XMOS XC-1 kits are shipping
    135687: 08/10/12: Leon: Re: XMOS XC-1 kits are shipping
    135690: 08/10/12: <steveu@coppice.org>: Re: XMOS XC-1 kits are shipping
    135697: 08/10/12: Leon: Re: XMOS XC-1 kits are shipping
    135703: 08/10/13: Bob: Re: XMOS XC-1 kits are shipping
        135722: 08/10/13: Eric Smith: Re: XMOS XC-1 kits are shipping
            135744: 08/10/14: Paul Carpenter: Re: XMOS XC-1 kits are shipping
            135745: 08/10/14: Paul Carpenter: Re: XMOS XC-1 kits are shipping
                135778: 08/10/15: Anton Erasmus: Re: XMOS XC-1 kits are shipping
            135750: 08/10/14: Joel Koltner: Re: XMOS XC-1 kits are shipping
            135754: 08/10/14: Eric Smith: Re: XMOS XC-1 kits are shipping
                135755: 08/10/14: Eric Smith: Re: XMOS XC-1 kits are shipping
    135704: 08/10/13: Leon: Re: XMOS XC-1 kits are shipping
    135727: 08/10/13: <steveu@coppice.org>: Re: XMOS XC-1 kits are shipping
    135742: 08/10/14: Leon: Re: XMOS XC-1 kits are shipping
    135765: 08/10/15: Leon: Re: XMOS XC-1 kits are shipping
    135769: 08/10/15: <info2@rayed.de>: Re: XMOS XC-1 kits are shipping
    135805: 08/10/16: Leon: Re: XMOS XC-1 kits are shipping
    135806: 08/10/16: Leon: Re: XMOS XC-1 kits are shipping
    135812: 08/10/16: Benjamin Couillard: Re: XMOS XC-1 kits are shipping
    135819: 08/10/16: Leon: Re: XMOS XC-1 kits are shipping
135634: 08/10/10: vssumesh: Can i ask some DFT questions
    135635: 08/10/10: Andy Botterill: Re: Can i ask some DFT questions
        135647: 08/10/11: Andy Botterill: Re: Can i ask some DFT questions
            135660: 08/10/11: Andy Botterill: Re: Can i ask some DFT questions
    135645: 08/10/10: vssumesh: Re: Can i ask some DFT questions
    135655: 08/10/11: vssumesh: Re: Can i ask some DFT questions
135644: 08/10/10: bzigon: Looking for a soft core 32 bit processor in VHDL
    135648: 08/10/11: Jon Beniston: Re: Looking for a soft core 32 bit processor in VHDL
    135649: 08/10/11: HT-Lab: Re: Looking for a soft core 32 bit processor in VHDL
    135718: 08/10/13: beky4kr@gmail.com: Re: Looking for a soft core 32 bit processor in VHDL
135672: 08/10/11: girl_aj: Newbie attempt with ALU
    135675: 08/10/12: Matthew Hicks: Re: Newbie attempt with ALU
135676: 08/10/12: FP: DDR FLOP?
    135677: 08/10/12: FP: Re: DDR FLOP?
        135680: 08/10/12: Hamish Shufflebotham: Re: DDR FLOP?
        135692: 08/10/12: Ed McGettigan: Re: DDR FLOP?
    135693: 08/10/12: John_H: Re: DDR FLOP?
    135705: 08/10/13: Gabor: Re: DDR FLOP?
    135709: 08/10/13: FP: Re: DDR FLOP?
135679: 08/10/12: <mstricker@embarqmail.com>: F.S. Xilinx Evaluation boards
135681: 08/10/12: Radha: Good reference for Static Timing Analysis
    135683: 08/10/12: Mike Treseler: Re: Good reference for Static Timing Analysis
135684: 08/10/12: mariosevr: Microblaze Network On Chip
135685: 08/10/12: Equinox: Complex Event Processing on FPGA
    135686: 08/10/12: Jonathan Bromley: Re: Complex Event Processing on FPGA
        135689: 08/10/13: Brian Drummond: Re: Complex Event Processing on FPGA
    135688: 08/10/13: Brian Drummond: Re: Complex Event Processing on FPGA
        135698: 08/10/13: David R Brooks: Re: Complex Event Processing on FPGA
    135694: 08/10/12: Equinox: Re: Complex Event Processing on FPGA
    135695: 08/10/12: Equinox: Re: Complex Event Processing on FPGA
    135700: 08/10/13: <spam@oxfordbromley.plus.com>: Re: Complex Event Processing on FPGA
    135746: 08/10/14: Benjamin Couillard: Re: Complex Event Processing on FPGA
    135781: 08/10/15: Equinox: Re: Complex Event Processing on FPGA
135691: 08/10/12: akineko: CPU Model for Co-simulation
    135757: 08/10/14: Tommy Thorn: Re: CPU Model for Co-simulation
    135809: 08/10/16: Jon Beniston: Re: CPU Model for Co-simulation
135717: 08/10/13: <pfrinec@yahoo.co.uk>: writing files to micro-SD with spartan 3e
    135719: 08/10/13: John McCaskill: Re: writing files to micro-SD with spartan 3e
    135723: 08/10/13: Eric Smith: Re: writing files to micro-SD with spartan 3e
        135728: 08/10/13: Eric Smith: Re: writing files to micro-SD with spartan 3e
    135724: 08/10/13: Antti: Re: writing files to micro-SD with spartan 3e
    135734: 08/10/14: colin: Re: writing files to micro-SD with spartan 3e
        135752: 08/10/14: Alex Freed: Re: writing files to micro-SD with spartan 3e
    135737: 08/10/14: <pfrinec@yahoo.co.uk>: Re: writing files to micro-SD with spartan 3e
    135768: 08/10/15: <pfrinec@yahoo.co.uk>: Re: writing files to micro-SD with spartan 3e
    135771: 08/10/15: Antti: Re: writing files to micro-SD with spartan 3e
    136373: 08/11/13: <pfrinec@yahoo.co.uk>: Re: writing files to micro-SD with spartan 3e
135720: 08/10/13: m m: Testing Analog-to-Digital Converter, Spartan-3A, LTC1407-A
135725: 08/10/13: KJ: converting MATLAB to VHDL
    135732: 08/10/14: Marty Ryba: Re: converting MATLAB to VHDL
135726: 08/10/13: <uraniumore238@gmail.com>: sensitive fpga
    135730: 08/10/13: Nathan Bialke: Re: sensitive fpga
    135731: 08/10/13: John_H: Re: sensitive fpga
        135779: 08/10/16: Jim Granville: Re: sensitive fpga
    135733: 08/10/13: <uraniumore238@gmail.com>: Re: sensitive fpga
    135738: 08/10/14: KJ: Re: sensitive fpga
    135770: 08/10/15: <cs_posting@hotmail.com>: Re: sensitive fpga
135735: 08/10/14: Markus: Microblaze and PowerPC405/440
    135740: 08/10/14: morphiend: Re: Microblaze and PowerPC405/440
135739: 08/10/14: FP: PRBS generator of Aurora core?
135741: 08/10/14: Fred: Literature on 100Base-TX request
    135767: 08/10/15: glen herrmannsfeldt: Re: Literature on 100Base-TX request
        135834: 08/10/17: Andreas Ehliar: Re: Literature on 100Base-TX request
            135859: 08/10/17: PatC: Re: Literature on 100Base-TX request
        135835: 08/10/16: Muzaffer Kal: Re: Literature on 100Base-TX request
            135853: 08/10/17: Muzaffer Kal: Re: Literature on 100Base-TX request
                135867: 08/10/18: Muzaffer Kal: Re: Literature on 100Base-TX request
                    135923: 08/10/21: Muzaffer Kal: Re: Literature on 100Base-TX request
                    135939: 08/10/22: glen herrmannsfeldt: Re: Literature on 100Base-TX request
            135940: 08/10/22: glen herrmannsfeldt: Re: Literature on 100Base-TX request
        135938: 08/10/22: Fred: Re: Literature on 100Base-TX request
    135818: 08/10/16: Fred: Re: Literature on 100Base-TX request
    135836: 08/10/17: Fred: Re: Literature on 100Base-TX request
    135842: 08/10/17: Fred: Re: Literature on 100Base-TX request
    135864: 08/10/18: Fred: Re: Literature on 100Base-TX request
    135914: 08/10/21: Fred: Re: Literature on 100Base-TX request
135743: 08/10/14: Roger: Simple Aurora Coregen queries
135747: 08/10/14: samliu: About the jitter of Xilinx Virtex-5's DCM output
    135749: 08/10/14: BobW: Re: About the jitter of Xilinx Virtex-5's DCM output
135748: 08/10/14: 500milesaway: Unexpected output in Post-translate Simulation: PLZ HELP
    135759: 08/10/15: Andreas Ehliar: Re: Unexpected output in Post-translate Simulation: PLZ HELP
135753: 08/10/14: James Harris: Re: $99 XMOS Dev kit
135756: 08/10/14: <niklas_molin@hotmail.com>: Virtex 5, DDR2 access
    135760: 08/10/14: PatC: Re: Virtex 5, DDR2 access
    135761: 08/10/15: Rob: Re: Virtex 5, DDR2 access
    135762: 08/10/15: Rob: Re: Virtex 5, DDR2 access
    135763: 08/10/15: Rob: Re: Virtex 5, DDR2 access
    135775: 08/10/15: <niklas_molin@hotmail.com>: Re: Virtex 5, DDR2 access
    135798: 08/10/16: <praveen@tarayinc.com>: Re: Virtex 5, DDR2 access
135764: 08/10/15: <chrisdekoh@gmail.com>: DDR2 timing questions
    135774: 08/10/15: Barry: Re: DDR2 timing questions
    135797: 08/10/16: <praveen@tarayinc.com>: Re: DDR2 timing questions
135766: 08/10/15: Leon: Re: $99 XMOS Dev kit
135772: 08/10/15: ALuPin@web.de: PLL in Altera PCI core ?
    135773: 08/10/15: ALuPin@web.de: Re: PLL in Altera PCI core ?
    135780: 08/10/15: Chris Finan: Re: PLL in Altera PCI core ?
135776: 08/10/15: James Harris: Re: $99 XMOS Dev kit
135777: 08/10/16: Jim Granville: Re: free cpu 8051 verilog code
    135783: 08/10/16: Nils: Re: free cpu 8051 verilog code
        135786: 08/10/16: Symon: Re: free cpu 8051 verilog code
        135795: 08/10/16: Meindert Sprang: Re: free cpu 8051 verilog code
135782: 08/10/16: Jan: Simulation
    135784: 08/10/16: Brian Drummond: Re: Simulation
    135785: 08/10/15: Mike Treseler: Re: Simulation
        135787: 08/10/15: Pete Fraser: Re: Simulation
        135808: 08/10/16: Brian Drummond: Re: Simulation
    135794: 08/10/16: backhus: Re: Simulation
        135830: 08/10/17: Jan: Re: Simulation
135788: 08/10/16: Jan: Distributed Dual-Port RAM
    135789: 08/10/16: Jan: Re: Distributed Dual-Port RAM
    135793: 08/10/15: John_H: Re: Distributed Dual-Port RAM
        135810: 08/10/16: Jan: Re: Distributed Dual-Port RAM
135790: 08/10/16: Andreas Ehliar: A couple of CPLD design challenges for the group
    135791: 08/10/16: Andreas Ehliar: Re: A couple of CPLD design challenges for the group
        135807: 08/10/16: Herbert Kleebauer: Re: A couple of CPLD design challenges for the group
    135792: 08/10/16: Andreas Ehliar: Re: A couple of CPLD design challenges for the group
    135799: 08/10/16: Andreas Ehliar: Re: A couple of CPLD design challenges for the group
        135820: 08/10/17: Jim Granville: Re: A couple of CPLD design challenges for the group
    135800: 08/10/16: Andreas Ehliar: Re: A couple of CPLD design challenges for the group
    135801: 08/10/16: Herbert Kleebauer: Re: A couple of CPLD design challenges for the group
    135802: 08/10/16: Frank Buss: Re: A couple of CPLD design challenges for the group
    135803: 08/10/16: Jim Granville: Re: A couple of CPLD design challenges for the group
        135941: 08/10/22: glen herrmannsfeldt: Re: A couple of CPLD design challenges for the group
    135804: 08/10/16: Jim Granville: Re: A couple of CPLD design challenges for the group
    135823: 08/10/17: Jim Granville: Re: A couple of CPLD design challenges for the group
    135826: 08/10/17: M.Randelzhofer: Re: A couple of CPLD design challenges for the group
        135843: 08/10/17: Andreas Ehliar: Re: A couple of CPLD design challenges for the group
            135866: 08/10/19: Jim Granville: Re: A couple of CPLD design challenges for the group
    135960: 08/10/24: Andreas Ehliar: Re: A couple of CPLD design challenges for the group
135796: 08/10/15: Pinhas: Re: free cpu 8051 verilog code
135811: 08/10/16: aleksa: Using GCK pin as both clock and signal (Spartan 2)
    135813: 08/10/16: Nathan Bialke: Re: Using GCK pin as both clock and signal (Spartan 2)
        135831: 08/10/17: Jim Granville: Re: Using GCK pin as both clock and signal (Spartan 2)
            135855: 08/10/18: Jim Granville: Re: Using GCK pin as both clock and signal (Spartan 2)
    135816: 08/10/16: aleksa: Re: Using GCK pin as both clock and signal (Spartan 2)
    135821: 08/10/16: Nathan Bialke: Re: Using GCK pin as both clock and signal (Spartan 2)
    135825: 08/10/16: aleksa: Re: Using GCK pin as both clock and signal (Spartan 2)
    135827: 08/10/16: Nathan Bialke: Re: Using GCK pin as both clock and signal (Spartan 2)
    135828: 08/10/16: aleksa: Re: Using GCK pin as both clock and signal (Spartan 2)
    135833: 08/10/16: Nathan Bialke: Re: Using GCK pin as both clock and signal (Spartan 2)
    135844: 08/10/17: aleksa: Re: Using GCK pin as both clock and signal (Spartan 2)
    135845: 08/10/17: aleksa: Re: Using GCK pin as both clock and signal (Spartan 2)
    135856: 08/10/17: Gabor: Re: Using GCK pin as both clock and signal (Spartan 2)
    135865: 08/10/18: aleksa: Re: Using GCK pin as both clock and signal (Spartan 2)
135814: 08/10/16: Roger: Xilinx SPI PROM programming via JTAG
    135815: 08/10/16: Rajkumar: Re: Xilinx SPI PROM programming via JTAG
        135817: 08/10/16: Roger: Re: Xilinx SPI PROM programming via JTAG
135822: 08/10/16: Philipp Falke: Comparing power consumption of two different processor designs
    135824: 08/10/16: Jon Beniston: Re: Comparing power consumption of two different processor designs
135829: 08/10/16: m: Linux on Microblaze
    135838: 08/10/17: Sebastien Bourdeauducq: Re: Linux on Microblaze
    136268: 08/11/07: guestuser1: Re: Linux on Microblaze
        136273: 08/11/08: David Brown: Re: Linux on Microblaze
            136285: 08/11/09: H. Peter Anvin: Re: Linux on Microblaze
                136289: 08/11/10: David Brown: Re: Linux on Microblaze
                    136341: 08/11/12: Andreas Ehliar: Re: Linux on Microblaze
                        136346: 08/11/12: David Brown: Re: Linux on Microblaze
                136336: 08/11/11: H. Peter Anvin: Re: Linux on Microblaze
        136334: 08/11/11: Eric Smith: Re: Linux on Microblaze
            136492: 08/11/19: Jan Bruns: Re: Linux on Microblaze
                136493: 08/11/19: David Brown: Re: Linux on Microblaze
                136513: 08/11/19: Eric Smith: Re: Linux on Microblaze
    136272: 08/11/08: <cs_posting@hotmail.com>: Re: Linux on Microblaze
    136302: 08/11/10: <cs_posting@hotmail.com>: Re: Linux on Microblaze
    136349: 08/11/12: Rich Walker: Re: Linux on Microblaze
135837: 08/10/17: Sebastien Bourdeauducq: Forcing Xilinx tools to treat two clocks as unrelated
    135839: 08/10/17: Rob: Re: Forcing Xilinx tools to treat two clocks as unrelated
    135840: 08/10/17: Lorenz Kolb: Re: Forcing Xilinx tools to treat two clocks as unrelated
    135846: 08/10/17: Sebastien Bourdeauducq: Re: Forcing Xilinx tools to treat two clocks as unrelated
    135847: 08/10/17: Sebastien Bourdeauducq: Re: Forcing Xilinx tools to treat two clocks as unrelated
    135869: 08/10/19: Sebastien Bourdeauducq: Re: Forcing Xilinx tools to treat two clocks as unrelated
    135875: 08/10/20: Rob: Re: Forcing Xilinx tools to treat two clocks as unrelated
135841: 08/10/17: <muthusnv@gmail.com>: Xilinx: FDR and FD inference in Synplify_pro
    135858: 08/10/17: John_H: Re: Xilinx: FDR and FD inference in Synplify_pro
135849: 08/10/17: Jan: Port mapping (combining components)
    135850: 08/10/17: =?ISO-8859-1?Q?Adam_G=F3rski?=: Re: Port mapping (combining components)
    135851: 08/10/17: Dave: Re: Port mapping (combining components)
        135852: 08/10/17: Jan: Re: Port mapping (combining components)
135854: 08/10/17: Roger: Aurora cores
135857: 08/10/18: blisca: configuring xc3s1500 from common parallel flash?
    135862: 08/10/18: langwadt@fonz.dk: Re: configuring xc3s1500 from common parallel flash?
        135870: 08/10/19: blisca: Re: configuring xc3s1500 from common parallel flash?
135860: 08/10/18: <lbraeckm@gmail.com>: Embedded Linux on V5 FXT
    135863: 08/10/18: Kolja Sulimma: Re: Embedded Linux on V5 FXT
135861: 08/10/18: cid: Entry Level FPGA Jobs and Outsourcing
    135868: 08/10/19: Nico Coesel: Re: Entry Level FPGA Jobs and Outsourcing
    135886: 08/10/20: Mike Treseler: Re: Entry Level FPGA Jobs and Outsourcing
        135896: 08/10/20: Mike Treseler: Re: Entry Level FPGA Jobs and Outsourcing
    135895: 08/10/20: cid: Re: Entry Level FPGA Jobs and Outsourcing
        135922: 08/10/22: Matthew Hicks: Re: Entry Level FPGA Jobs and Outsourcing
        135959: 08/10/24: Alan: Re: Entry Level FPGA Jobs and Outsourcing
    135903: 08/10/21: <cs_posting@hotmail.com>: Re: Entry Level FPGA Jobs and Outsourcing
135871: 08/10/19: Jan: Field update
    135873: 08/10/20: Jim Granville: Re: Field update
    135874: 08/10/19: Nico Coesel: Re: Field update
    135887: 08/10/20: Mike Treseler: Re: Field update
    135898: 08/10/20: Bryan: Re: Field update
135872: 08/10/19: Jukka Marin: Cyclone III, DP RAM, and Verilog
    135877: 08/10/20: KJ: Re: Cyclone III, DP RAM, and Verilog
        135883: 08/10/20: Jukka Marin: Re: Cyclone III, DP RAM, and Verilog
            135888: 08/10/20: Mike Treseler: Re: Cyclone III, DP RAM, and Verilog
    135935: 08/10/22: LittleAlex: Re: Cyclone III, DP RAM, and Verilog
    138905: 09/03/14: nntpman68: Re: Cyclone III, DP RAM, and Verilog
135876: 08/10/20: Michael Brown: Any more news on an Windows x64-compatible WebPack?
    135882: 08/10/20: Roger: Re: Any more news on an Windows x64-compatible WebPack?
    136001: 08/10/27: RedskullDC: Re: Any more news on an Windows x64-compatible WebPack?
135878: 08/10/20: ALuPin@web.de: WP335 - Examples
135879: 08/10/20: <lichaoji@gmail.com>: Looking for a FPGA board for starter
    135884: 08/10/20: John Adair: Re: Looking for a FPGA board for starter
    135889: 08/10/20: LittleAlex: Re: Looking for a FPGA board for starter
    135890: 08/10/20: James Harris: Re: Looking for a FPGA board for starter
    135991: 08/10/26: Tony Burch: Re: Looking for a FPGA board for starter
135880: 08/10/20: nfeske: Major update of the Genode FPGA graphics project
135881: 08/10/20: sebastian.schueppel@gmail.com: external differential clock inputs
    135885: 08/10/20: kadhiem_ayob: Re: external differential clock inputs
    135891: 08/10/20: Darol Klawetter: Re: external differential clock inputs
    135904: 08/10/21: Pratap: Re: external differential clock inputs
    136324: 08/11/11: sebastian.schueppel@gmail.com: Re: external differential clock inputs
135900: 08/10/21: Paul Boven: Question on timing constraints
    135901: 08/10/21: chestnut: Re: Question on timing constraints
    135902: 08/10/21: Darol Klawetter: Re: Question on timing constraints
    135911: 08/10/21: Symon: Re: Question on timing constraints
        135915: 08/10/22: Symon: Re: Question on timing constraints
        136010: 08/10/27: Paul Boven: Re: Question on timing constraints
            136018: 08/10/28: Martin Thompson: Re: Question on timing constraints
                136025: 08/10/28: Brian Drummond: Re: Question on timing constraints
                    136429: 08/11/16: hbenin: Re: Question on timing constraints
                        136738: 08/12/03: hbenin: Re: Question on timing constraints
    135912: 08/10/22: Brian Drummond: Re: Question on timing constraints
135907: 08/10/21: lecroy7200@chek.com: Would like to try ISIM, simple question
    135913: 08/10/22: Brian Drummond: Re: Would like to try ISIM, simple question
        135961: 08/10/24: Brian Drummond: Re: Would like to try ISIM, simple question
    135951: 08/10/23: lecroy7200@chek.com: Re: Would like to try ISIM, simple question
    135955: 08/10/23: Brian Davis: Re: Would like to try ISIM, simple question
    135981: 08/10/24: Brian Davis: Re: Would like to try ISIM, simple question
    136012: 08/10/27: Kevin Neilson: Re: Would like to try ISIM, simple question
        136206: 08/11/05: Brian Drummond: Re: Would like to try ISIM, simple question
            136376: 08/11/13: Mike Treseler: Re: Would like to try ISIM, simple question
            136425: 08/11/16: Brian Drummond: Re: Would like to try ISIM, simple question
        136498: 08/11/19: lecroy7200@chek.com: Re: Would like to try ISIM, simple question
    136178: 08/11/04: lecroy7200@chek.com: Re: Would like to try ISIM, simple question
    136179: 08/11/04: lecroy7200@chek.com: Re: Would like to try ISIM, simple question
    136193: 08/11/05: lecroy7200@chek.com: Re: Would like to try ISIM, simple question
    136372: 08/11/13: lecroy7200@chek.com: Re: Would like to try ISIM, simple question
    136421: 08/11/15: Duth: Re: Would like to try ISIM, simple question
135910: 08/10/21: Roger: Aurora / GTP clocking configuration
135916: 08/10/21: Jeff Brower: Spartan 3 IO banking rules problem in ISE
    135917: 08/10/21: Brian Davis: Re: Spartan 3 IO banking rules problem in ISE
    135918: 08/10/21: LittleAlex: Re: Spartan 3 IO banking rules problem in ISE
        135962: 08/10/24: Brian Drummond: Re: Spartan 3 IO banking rules problem in ISE
    135928: 08/10/22: Brian Drummond: Re: Spartan 3 IO banking rules problem in ISE
        135949: 08/10/23: Symon: Re: Spartan 3 IO banking rules problem in ISE
    135948: 08/10/23: Jeff Brower: Re: Spartan 3 IO banking rules problem in ISE
    135950: 08/10/23: Gabor: Re: Spartan 3 IO banking rules problem in ISE
    135952: 08/10/23: Jeff Brower: Re: Spartan 3 IO banking rules problem in ISE
135920: 08/10/21: <hanumaan81@gmail.com>: Virtex 5 DSP.
    135924: 08/10/22: Symon: Re: Virtex 5 DSP.
    135934: 08/10/22: Darol Klawetter: Re: Virtex 5 DSP.
135925: 08/10/21: knight: Interesting EDK error !!!
    135927: 08/10/22: knight: Re: Interesting EDK error !!!
    135933: 08/10/22: Gabor: Re: Interesting EDK error !!!
    135947: 08/10/23: knight: Re: Interesting EDK error !!!
135926: 08/10/22: Andreas Ehliar: Re: Design security
135929: 08/10/22: Tobias: Design security
    135930: 08/10/22: Allan Herriman: Re: Design security
    135964: 08/10/24: austin: Re: Design security
        136017: 08/10/28: Tobias: Re: Design security
            136019: 08/10/28: Martin Thompson: Re: Design security
135931: 08/10/22: Roger: Multiple GTPs used in a Virtex 5
    135943: 08/10/23: PatC: Re: Multiple GTPs used in a Virtex 5
        135946: 08/10/23: Roger: Re: Multiple GTPs used in a Virtex 5
135932: 08/10/22: bill: problem about an interface between sfifo and sopc avalon MM slave
135936: 08/10/22: Symon: Re: Virtex 5 DSP.
135937: 08/10/22: Mike Treseler: Re: Virtex 5 DSP.
135944: 08/10/23: adventurer: Soft core processor + CAD choose.Again
    135945: 08/10/23: Jon Beniston: Re: Soft core processor + CAD choose.Again
    135972: 08/10/24: adventurer: Re: Soft core processor + CAD choose.Again
    135977: 08/10/24: ghelbig: Re: Soft core processor + CAD choose.Again
135953: 08/10/23: Nagaraj: Altera - clock to output (pin) delay
135954: 08/10/23: Test: Need Lattice FUSE TABLE --->> LOGIC conversion service. $$$
    135974: 08/10/24: Gabor: Re: Need Lattice FUSE TABLE --->> LOGIC conversion service. $$$
135957: 08/10/24: John Adair: Hollybush2 - Soft Core Processor Board
    135958: 08/10/24: HT-Lab: Re: Hollybush2 - Soft Core Processor Board
    135979: 08/10/24: Uwe Bonnes: Re: Hollybush2 - Soft Core Processor Board
    136008: 08/10/27: John Adair: Re: Hollybush2 - Soft Core Processor Board
135963: 08/10/24: FP: quick question
135965: 08/10/24: <eubanksster@gmail.com>: Learning WinCUPL; Tried Atmel Suppport but no solution!
    135975: 08/10/24: Gabor: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
    135976: 08/10/24: <d_s_klein@yahoo.com>: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
        135988: 08/10/25: doug: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
    135980: 08/10/24: doug: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
    135985: 08/10/25: <eubanksster@gmail.com>: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
    135986: 08/10/25: <eubanksster@gmail.com>: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
    135990: 08/10/25: <eubanksster@gmail.com>: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
    136006: 08/10/27: Jim Granville: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
        136045: 08/10/29: Jim Granville: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
    136026: 08/10/28: Gabor: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
135966: 08/10/24: Alex: Small FPGA boards with USB/Ethernet
    135967: 08/10/24: John Adair: Re: Small FPGA boards with USB/Ethernet
        136011: 08/10/27: chris: Re: Small FPGA boards with USB/Ethernet
    136007: 08/10/27: Alex: Re: Small FPGA boards with USB/Ethernet
135968: 08/10/24: Frank Buss: again: statemachine bug in Quartus II Web Edition Software v8.0 SP1
    135969: 08/10/24: Mike Treseler: Re: again: statemachine bug in Quartus II Web Edition Software v8.0
        135970: 08/10/24: Frank Buss: Re: again: statemachine bug in Quartus II Web Edition Software v8.0 SP1
            135973: 08/10/24: Mike Treseler: Re: again: statemachine bug in Quartus II Web Edition Software v8.0
        135971: 08/10/24: KJ: Re: again: statemachine bug in Quartus II Web Edition Software v8.0
135983: 08/10/25: 500milesaway: how to program virtex 4?
    135987: 08/10/25: MM: Re: how to program virtex 4?
        135993: 08/10/26: 500milesaway: Re: how to program virtex 4?
            135994: 08/10/26: Frank Buss: Re: how to program virtex 4?
    136000: 08/10/26: Thomas Stanka: Re: how to program virtex 4?
    136005: 08/10/27: Rob: Re: how to program virtex 4?
        136027: 08/10/28: 500milesaway: Re: how to program virtex 4?
    136067: 08/10/29: <dave@x.com>: Re: how to program virtex 4?
135989: 08/10/25: thecreator: linux usb-drivers: Cable connection failed.
    136003: 08/10/27: unknown: Re: linux usb-drivers: Cable connection failed.
    136013: 08/10/27: David: Re: linux usb-drivers: Cable connection failed.
135992: 08/10/26: samliu: "Out of Order" problem in Xilinx V5 used as a PCI Express Endpoint
    135996: 08/10/26: PatC: Re: "Out of Order" problem in Xilinx V5 used as a PCI Express Endpoint
        135997: 08/10/26: Rube Bumpkin: Re: "Out of Order" problem in Xilinx V5 used as a PCI Express Endpoint
135995: 08/10/26: <graffitici@yahoo.com>: PSpice model for Virtex-II Pro
135998: 08/10/26: water9580@yahoo.com: pci-express sata host controller and Giga ethernet controller for V5
135999: 08/10/26: laserbeak43: S3E starter kit: LCD interface questions
    136002: 08/10/27: RedskullDC: Re: S3E starter kit: LCD interface questions
        136009: 08/10/27: Laserbeak43: Re: S3E starter kit: LCD interface questions
136004: 08/10/27: Jens Hagemeyer: vMAGIC 0.1.1 (alpha) released
136014: 08/10/27: <graffitici@yahoo.com>: PSpice model for Virtex-II Pro
136015: 08/10/27: water9580@yahoo.com: pci-express sata controller,bridge,ethernet controller
136016: 08/10/28: Enes Erdin: FPGA RAM clock connection
    136022: 08/10/28: KJ: Re: FPGA RAM clock connection
136020: 08/10/28: Moazzam: Possibility of Driving FPGA clock from an other FPGA ?
    136053: 08/10/29: jerzy.gbur@gmail.com: Re: Possibility of Driving FPGA clock from an other FPGA ?
    136083: 08/10/30: MM: Re: Possibility of Driving FPGA clock from an other FPGA ?
136021: 08/10/28: Andreas Ehliar: Re: Register File distributed all over the FPGA
    136023: 08/10/28: Andreas Ehliar: Re: Register File distributed all over the FPGA
        136036: 08/10/28: Philipp: Re: Register File distributed all over the FPGA
    136032: 08/10/28: Philipp: Re: Register File distributed all over the FPGA
        136037: 08/10/28: Philipp: Re: Register File distributed all over the FPGA
            136049: 08/10/29: Andreas Ehliar: Re: Register File distributed all over the FPGA
            136050: 08/10/29: Philipp: Re: Register File distributed all over the FPGA
                136052: 08/10/29: Philipp: Re: Register File distributed all over the FPGA
                    136057: 08/10/29: Philipp: Re: Register File distributed all over the FPGA
                        136060: 08/10/29: Philipp: Re: Register File distributed all over the FPGA
                        136061: 08/10/29: Philipp: Re: Register File distributed all over the FPGA
                        136072: 08/10/30: Philipp: Re: Register File distributed all over the FPGA
                            136075: 08/10/30: Philipp: Re: Register File distributed all over the FPGA
                            136076: 08/10/30: Brian Drummond: Re: Register File distributed all over the FPGA
136024: 08/10/28: EFR: XUPV2P & xps_tft controller
136028: 08/10/28: Eric: classic Spartan-3 DDR2 and IOBs
    136071: 08/10/30: Rob: Re: classic Spartan-3 DDR2 and IOBs
        136100: 08/10/31: Dan Kuechle: Re: classic Spartan-3 DDR2 and IOBs
            136105: 08/11/01: Brian Drummond: Re: classic Spartan-3 DDR2 and IOBs
            136114: 08/11/02: Nico Coesel: Re: classic Spartan-3 DDR2 and IOBs
    136096: 08/10/31: Eric: Re: classic Spartan-3 DDR2 and IOBs
    136133: 08/11/03: Gabor: Re: classic Spartan-3 DDR2 and IOBs
136030: 08/10/28: Philipp: Register File distributed all over the FPGA
    136033: 08/10/28: Alex: Re: Register File distributed all over the FPGA
    136038: 08/10/28: Alex: Re: Register File distributed all over the FPGA
    136051: 08/10/29: Benjamin Krill: Re: Register File distributed all over the FPGA
    136055: 08/10/29: Benjamin Krill: Re: Register File distributed all over the FPGA
    136058: 08/10/29: Benjamin Krill: Re: Register File distributed all over the FPGA
    136059: 08/10/29: Alex: Re: Register File distributed all over the FPGA
    136064: 08/10/29: Mike Treseler: Re: Register File distributed all over the FPGA
    136073: 08/10/30: Alex: Re: Register File distributed all over the FPGA
    136074: 08/10/30: Brian Drummond: Re: Register File distributed all over the FPGA
136031: 08/10/28: maxascent: system verilog state machine
    136104: 08/10/31: Jonathan Bromley: Re: system verilog state machine
        136118: 08/11/02: maxascent: Re: system verilog state machine
136034: 08/10/28: timinganalyzer: TimingAnalyzer beta version 0.90 -- beta testers wanted
    136035: 08/10/28: Pierre-François (f5bqp_pfm): Re: TimingAnalyzer beta version 0.90 -- beta testers wanted
        136044: 08/10/29: Pierre-François (f5bqp_pfm): Re: TimingAnalyzer beta version 0.90 -- beta testers wanted
    136039: 08/10/28: timinganalyzer: Re: TimingAnalyzer beta version 0.90 -- beta testers wanted
136041: 08/10/29: Mark McDougall: ISE 9.2.03i problem
    136042: 08/10/29: Mark McDougall: Re: ISE 9.2.03i problem - work-around
        136043: 08/10/28: sandeep: Re: ISE 9.2.03i problem - work-around
    136047: 08/10/29: Brian Drummond: Re: ISE 9.2.03i problem
        136069: 08/10/30: Mark McDougall: Re: ISE 9.2.03i problem
        136070: 08/10/30: Mark McDougall: Re: ISE 9.2.03i problem
            136079: 08/10/30: Duane Clark: Re: ISE 9.2.03i problem
                136087: 08/10/31: Mark McDougall: Re: ISE 9.2.03i problem
                    136094: 08/10/31: Brian Drummond: Re: ISE 9.2.03i problem
                        136142: 08/11/04: Mark McDougall: Re: ISE 9.2.03i problem
                            136147: 08/11/04: Brian Drummond: Re: ISE 9.2.03i problem
                                136155: 08/11/04: Brian Drummond: Re: ISE 9.2.03i problem
                                136348: 08/11/12: Brian Drummond: Re: ISE 9.2.03i problem
                                    136362: 08/11/13: Mark McDougall: Re: ISE 9.2.03i problem
                                        136364: 08/11/13: Brian Drummond: Re: ISE 9.2.03i problem
                                            136365: 08/11/13: Mark McDougall: Re: ISE 9.2.03i problem
            136088: 08/10/31: Mark McDougall: Re: ISE 9.2.03i problem
                136090: 08/10/30: KJ: Re: ISE 9.2.03i problem
                136095: 08/10/31: Brian Drummond: Re: ISE 9.2.03i problem
                    136102: 08/10/31: Mike Treseler: Re: ISE 9.2.03i problem
                    136106: 08/11/01: Brian Drummond: Re: ISE 9.2.03i problem
                        136112: 08/11/01: jtw: Re: ISE 9.2.03i problem
                            136115: 08/11/02: Brian Drummond: Re: ISE 9.2.03i problem
        136086: 08/10/30: <kennheinrich@sympatico.ca>: Re: ISE 9.2.03i problem
        136097: 08/10/31: <kennheinrich@sympatico.ca>: Re: ISE 9.2.03i problem
        136098: 08/10/31: KJ: Re: ISE 9.2.03i problem
        136113: 08/11/01: <kennheinrich@sympatico.ca>: Re: ISE 9.2.03i problem
        136149: 08/11/03: Brian Davis: Re: ISE 9.2.03i problem
    136080: 08/10/30: Dave: Re: ISE 9.2.03i problem
        136089: 08/10/31: Mark McDougall: Re: ISE 9.2.03i problem
136046: 08/10/29: <ales.gorkic@gmail.com>: PLBv4.6 with more than 16 slaves
    136048: 08/10/29: Brian Drummond: Re: PLBv4.6 with more than 16 slaves
    136065: 08/10/29: MM: Re: PLBv4.6 with more than 16 slaves
        136103: 08/10/31: MM: Re: PLBv4.6 with more than 16 slaves
            136116: 08/11/02: Jeff Cunningham: Re: PLBv4.6 with more than 16 slaves
    136099: 08/10/31: <ales.gorkic@gmail.com>: Re: PLBv4.6 with more than 16 slaves
136056: 08/10/29: simax: MPMC and DDR2 Simulation
    136063: 08/10/29: Jim Wu: Re: MPMC and DDR2 Simulation
    136066: 08/10/29: simax: Re: MPMC and DDR2 Simulation
    136068: 08/10/29: simax: Re: MPMC and DDR2 Simulation
136062: 08/10/29: Vivek Menon: verilog simulation of LogiCORE Complex Multiplier v2.1
136077: 08/10/30: Hans Dampf: Xilinx RapidIO 5.1
    136078: 08/10/30: Moritz Schmid: Re: Xilinx RapidIO 5.1
        136091: 08/10/30: jtw: Re: Xilinx RapidIO 5.1
            136092: 08/10/31: Hans Dampf: Re: Xilinx RapidIO 5.1
136081: 08/10/30: John Adair: Polmaddie1 - For Traffic Lights Junkies
    136082: 08/10/30: Gabor: Re: Polmaddie1 - For Traffic Lights Junkies
    136084: 08/10/30: John Adair: Re: Polmaddie1 - For Traffic Lights Junkies
136093: 08/10/31: axr0284: FPGA implementation of a PCI module
    136109: 08/11/01: Mike Treseler: Re: FPGA implementation of a PCI module
    136121: 08/11/02: Kolja Sulimma: Re: FPGA implementation of a PCI module
    136132: 08/11/03: Kolja Sulimma: Re: FPGA implementation of a PCI module
        136284: 08/11/09: H. Peter Anvin: Re: FPGA implementation of a PCI module
    136136: 08/11/03: axr0284: Re: FPGA implementation of a PCI module
136101: 08/10/31: Pete Fraser: GDDR3


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