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Threads Starting Sep 2007

123680: 07/09/01: Symon: Interesting FPGA/JTAG project.
123692: 07/09/01: <al.basili@gmail.com>: flip-flop enable
    123693: 07/09/02: Ralf Hildebrandt: Re: flip-flop enable
123706: 07/09/02: Sean Durkin: V5 Configuration via SPI
    123709: 07/09/02: austin: Re: V5 Configuration via SPI
        123737: 07/09/03: Sean Durkin: Re: V5 Configuration via SPI
            123743: 07/09/03: austin: Re: V5 Configuration via SPI
                123746: 07/09/03: Sean Durkin: Re: V5 Configuration via SPI
                    124081: 07/09/11: Max Baker: Re: V5 Configuration via SPI
    123714: 07/09/02: John Larkin: Re: V5 Configuration via SPI
123707: 07/09/02: <dormanpeter1@gmail.com>: opb_timer interrupt self test problem
    123749: 07/09/03: <benradu@gmail.com>: Re: opb_timer interrupt self test problem
    123751: 07/09/03: DoPeti: Re: opb_timer interrupt self test problem
123711: 07/09/02: James Harris: Beginning FPGA programming
    123712: 07/09/02: James Harris: FPGA CPU
        123713: 07/09/02: Andreas Ehliar: Re: FPGA CPU
            123734: 07/09/03: Andreas Ehliar: Re: FPGA CPU
                123736: 07/09/03: Andreas Ehliar: Re: FPGA CPU
                    123752: 07/09/03: glen herrmannsfeldt: Re: FPGA CPU
                        123755: 07/09/04: Göran Bilski: Re: FPGA CPU
                            123854: 07/09/05: glen herrmannsfeldt: Re: FPGA CPU
                123788: 07/09/04: Frank Buss: Re: FPGA CPU
                123834: 07/09/05: glen herrmannsfeldt: Re: FPGA CPU
    123728: 07/09/03: James Harris: Re: FPGA CPU
    123770: 07/09/04: <fpga_toys@yahoo.com>: Re: FPGA CPU
    123778: 07/09/04: <fpga_toys@yahoo.com>: Re: FPGA CPU
    123781: 07/09/04: glen herrmannsfeldt: Re: Beginning FPGA programming
    123785: 07/09/04: James Harris: Re: FPGA CPU
    123786: 07/09/04: James Harris: Re: FPGA CPU
    123787: 07/09/04: James Harris: Re: FPGA CPU
    123792: 07/09/04: <fpga_toys@yahoo.com>: Re: FPGA CPU
    123794: 07/09/04: <fpga_toys@yahoo.com>: Re: FPGA CPU
    123796: 07/09/04: James Harris: Re: FPGA CPU
    123797: 07/09/04: <fpga_toys@yahoo.com>: Re: FPGA CPU
123715: 07/09/02: fl: Cannot pass par in tcl, Xilinx webpack 9.1.
123716: 07/09/02: <drop669@gmail.com>: Low-level FPGA programming?
    123722: 07/09/03: Paul Leventis: Re: Low-level FPGA programming?
    123731: 07/09/03: <drop669@gmail.com>: Re: Low-level FPGA programming?
        123732: 07/09/03: Andreas Ehliar: Re: Low-level FPGA programming?
            123744: 07/09/03: austin: Re: Low-level FPGA programming?
                124613: 07/09/28: Andreas Ehliar: Re: Low-level FPGA programming?
    123735: 07/09/03: RedskullDC: Re: Low-level FPGA programming?
    123745: 07/09/03: Jon Beniston: Re: Low-level FPGA programming?
    124638: 07/09/28: <cs_posting@hotmail.com>: Re: Low-level FPGA programming?
    124886: 07/10/09: Adam Megacz: Re: Low-level FPGA programming?
123717: 07/09/02: <hezhikuan2007@gmail.com>: [Nios II] How Can I define the pio inputs as a interrupt?
    123718: 07/09/03: Mark McDougall: Re: [Nios II] How Can I define the pio inputs as a interrupt?
    123720: 07/09/02: <hezhikuan2007@gmail.com>: Re: How Can I define the pio inputs as a interrupt?
123719: 07/09/02: mk: GTKWave 3.1.0 for win32
123740: 07/09/03: xenix: Help on ocm
123741: 07/09/03: xenix: Help on OCM BRAM intercafe and assembly code
123747: 07/09/03: <ikogan@alumni.technion.ac.il>: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?
    124020: 07/09/11: Douglas: Re: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?
        137429: 09/01/15: robj: Re: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?
            137482: 09/01/19: robj: Re: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?
            137488: 09/01/20: whygee: FPGA granularity (was Re: Actel IGLOO FPGA)
                137489: 09/01/20: Jonathan Bromley: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
                    137490: 09/01/20: whygee: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
                        137496: 09/01/21: Andreas Ehliar: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
                            137520: 09/01/21: whygee: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
                        137505: 09/01/21: Jonathan Bromley: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
                            137522: 09/01/21: whygee: Re: FPGA granularity
                                137546: 09/01/22: Marty Ryba: Re: FPGA granularity
                                    137547: 09/01/22: whygee: Re: FPGA granularity
                                        137592: 09/01/23: Marty Ryba: Re: FPGA granularity
                    137509: 09/01/21: Brian Drummond: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
                        137527: 09/01/21: whygee: Re: FPGA granularity
                            137535: 09/01/22: whygee: Re: FPGA granularity
                            137536: 09/01/22: whygee: Re: FPGA granularity
                                137548: 09/01/22: whygee: Re: FPGA granularity
                                    137565: 09/01/22: Hal Murray: Re: FPGA granularity
                                        137589: 09/01/23: whygee: Re: FPGA granularity
                                    137584: 09/01/22: whygee: Re: FPGA granularity
                            137540: 09/01/22: Brian Drummond: Re: FPGA granularity
                            137541: 09/01/22: Brian Drummond: Re: FPGA granularity
                        137539: 09/01/22: Brian Drummond: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
                137503: 09/01/21: Jonathan Bromley: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
                    137525: 09/01/21: whygee: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
                        137537: 09/01/22: whygee: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
                            137560: 09/01/22: Florian Stock: Re: FPGA granularity
                                137586: 09/01/23: whygee: Re: FPGA granularity
                                137603: 09/01/23: Florian Stock: Re: FPGA granularity
        137551: 09/01/21: Antti: Re: FPGA granularity
    137428: 09/01/15: robj: Re: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?
        137431: 09/01/16: Matthias Alles: Re: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II
            137440: 09/01/16: robj: Re: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?
        137433: 09/01/16: Nial Stewart: Re: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?
            137455: 09/01/18: whygee: Re: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II
        137463: 09/01/18: robj: Re: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?
    137435: 09/01/16: Antti: Re: Actel IGLOO FPGA has lower power consumption then Xilinx
    137439: 09/01/16: <Petrov_101@hotmail.com>: Re: Actel IGLOO FPGA has lower power consumption then Xilinx
    137454: 09/01/17: Prevailing over Technology: Re: Actel IGLOO FPGA has lower power consumption then Xilinx
    137474: 09/01/19: Prevailing over Technology: Re: Actel IGLOO FPGA has lower power consumption then Xilinx
    137475: 09/01/19: rickman: Re: Actel IGLOO FPGA has lower power consumption then Xilinx
    137476: 09/01/19: rickman: Re: Actel IGLOO FPGA has lower power consumption then Xilinx
    137483: 09/01/19: rickman: Re: Actel IGLOO FPGA has lower power consumption then Xilinx
    137495: 09/01/20: rickman: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
    137521: 09/01/21: rickman: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
    137528: 09/01/21: Antti: Re: FPGA granularity
    137531: 09/01/21: rickman: Re: FPGA granularity
    137532: 09/01/21: rickman: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
    137538: 09/01/21: Prevailing over Technology: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
    137545: 09/01/21: rickman: Re: FPGA granularity
    137550: 09/01/21: rickman: Re: FPGA granularity
    137575: 09/01/22: rickman: Re: FPGA granularity
    137626: 09/01/24: rickman: Re: FPGA granularity
123758: 07/09/04: LilacSkin: Import Xilinx SDK Project in Wind River Workbench
123759: 07/09/04: L. Schreiber: ERROR:NgdBuild:604 with user ipcore
    123760: 07/09/04: Gabor: Re: ERROR:NgdBuild:604 with user ipcore
        123761: 07/09/04: L. Schreiber: Re: ERROR:NgdBuild:604 with user ipcore
            123771: 07/09/04: Paulo Dutra: Re: ERROR:NgdBuild:604 with user ipcore
                123805: 07/09/05: L. Schreiber: Re: ERROR:NgdBuild:604 with user ipcore
    125366: 07/10/23: ARRON: Re: ERROR:NgdBuild:604 with user ipcore
123768: 07/09/04: David: Actel Designer - Specifying multicycle path constraints (via .sdc file) when using synchronous clock enables
    123808: 07/09/05: HT-Lab: Re: Actel Designer - Specifying multicycle path constraints (via .sdc file) when using synchronous clock enables
123769: 07/09/04: NickNitro: Multiple CPLDs on a PCB.
    123775: 07/09/05: Jim Granville: Re: Multiple CPLDs on a PCB.
        123791: 07/09/05: Jim Granville: Re: Multiple CPLDs on a PCB.
        123793: 07/09/04: Hal Murray: Re: Multiple CPLDs on a PCB.
        123806: 07/09/05: Mike Harrison: Re: Multiple CPLDs on a PCB.
        123829: 07/09/05: Jon Elson: Re: Multiple CPLDs on a PCB.
    123783: 07/09/04: Gabor: Re: Multiple CPLDs on a PCB.
    123784: 07/09/04: NickNitro: Re: Multiple CPLDs on a PCB.
    123790: 07/09/04: NickNitro: Re: Multiple CPLDs on a PCB.
    123795: 07/09/04: Peter Alfke: Re: Multiple CPLDs on a PCB.
    123798: 07/09/04: John Larkin: Re: Multiple CPLDs on a PCB.
    123799: 07/09/04: NickNitro: Re: Multiple CPLDs on a PCB.
    123800: 07/09/04: Peter Alfke: Re: Multiple CPLDs on a PCB.
    123803: 07/09/05: Zara: Re: Multiple CPLDs on a PCB.
    123813: 07/09/05: NickNitro: Re: Multiple CPLDs on a PCB.
123774: 07/09/04: vasile: Re: PCB Impedance Control
123776: 07/09/04: kkoorndyk: vnavigator problem
123777: 07/09/04: vasile: Re: PCB Impedance Control
123804: 07/09/05: ankur: warning 1780 shown while synthesis, in xilinx 6.3i
    123814: 07/09/05: Dave Pollum: Re: warning 1780 shown while synthesis, in xilinx 6.3i
123811: 07/09/05: <rponsard@gmail.com>: EDK9.1 linux registration fails (vista ok)
    123888: 07/09/06: MM: Re: EDK9.1 linux registration fails (vista ok)
123815: 07/09/05: <michel.talon@gmail.com>: clock skew problems
    123819: 07/09/05: Gabor: Re: clock skew problems
    123863: 07/09/06: Joseph Samson: Re: clock skew problems
    124117: 07/09/12: <michel.talon@gmail.com>: Re: clock skew problems
    124262: 07/09/17: Gabor: Re: clock skew problems
123818: 07/09/05: eliben: high bandwitch ethernet communication
    123821: 07/09/05: Tim Wescott: Re: high bandwitch ethernet communication
        123874: 07/09/06: Brian Drummond: Re: high bandwitch ethernet communication
    123822: 07/09/05: Gabor: Re: high bandwitch ethernet communication
    123823: 07/09/05: John McCaskill: Re: high bandwitch ethernet communication
        123861: 07/09/06: Hal Murray: Re: high bandwitch ethernet communication
    123825: 07/09/05: Siva Velusamy: Re: high bandwitch ethernet communication
    123836: 07/09/05: glen herrmannsfeldt: Re: high bandwitch ethernet communication
        123856: 07/09/06: Paul Keinanen: Re: high bandwitch ethernet communication
            123873: 07/09/06: Paul Keinanen: Re: high bandwitch ethernet communication
                123876: 07/09/06: Grant Edwards: Re: high bandwitch ethernet communication
            123875: 07/09/06: Grant Edwards: Re: high bandwitch ethernet communication
            123928: 07/09/06: glen herrmannsfeldt: Re: high bandwitch ethernet communication
                123960: 07/09/07: Hal Murray: Re: high bandwitch ethernet communication
                    123965: 07/09/08: Paul Keinanen: Re: high bandwitch ethernet communication
                    123966: 07/09/08: glen herrmannsfeldt: Re: high bandwitch ethernet communication
                123961: 07/09/07: Hal Murray: Re: high bandwitch ethernet communication
    123847: 07/09/05: Janaka: Re: high bandwitch ethernet communication
    123852: 07/09/06: eliben: Re: high bandwitch ethernet communication
    123853: 07/09/06: eliben: Re: high bandwitch ethernet communication
    123855: 07/09/06: Tim Wescott: Re: high bandwitch ethernet communication
    123866: 07/09/06: eliben: Re: high bandwitch ethernet communication
    123879: 07/09/06: John McCaskill: Re: high bandwitch ethernet communication
    123892: 07/09/06: eliben: Re: high bandwitch ethernet communication
    123895: 07/09/06: John McCaskill: Re: high bandwitch ethernet communication
    123925: 07/09/07: eliben: Re: high bandwitch ethernet communication
    123940: 07/09/07: David Brown: Re: high bandwitch ethernet communication
    123948: 07/09/07: eliben: Re: high bandwitch ethernet communication
    123952: 07/09/07: John McCaskill: Re: high bandwitch ethernet communication
    123964: 07/09/08: eliben: Re: high bandwitch ethernet communication
    123987: 07/09/10: Guru: Re: high bandwitch ethernet communication
123826: 07/09/05: ZHI: How to deal with the tempary coefficient in the FPGA design
    123838: 07/09/05: glen herrmannsfeldt: Re: How to deal with the tempary coefficient in the FPGA design
        124051: 07/09/11: glen herrmannsfeldt: Re: How to deal with the tempary coefficient in the FPGA design
    123859: 07/09/06: ZHI: Re: How to deal with the tempary coefficient in the FPGA design
123848: 07/09/05: <hezhikuan2007@gmail.com>: =?gb2312?B?ob5OaW9zIElJob9Ib3cgQ2FuIEkgRmluZCBPdXQgVGhlc2UgRnVuY3Rpb25zIKO/?=
    123849: 07/09/06: Mark McDougall: Re: =?ISO-8859-1?Q?=A1=BENios_II=A1=BFHow_Can_I_Find_O?=
    123862: 07/09/06: Iwo Mergler: Re: ?Nios II?How Can I Find Out These Functions ?
    123935: 07/09/07: lexluthor: Re: ?Nios II?How Can I Find Out These Functions ?
123864: 07/09/06: <james.lbs@gmail.com>: FATAL ERROR ISE9.1i
    123865: 07/09/06: Helmut: Re: FATAL ERROR ISE9.1i
    124646: 07/09/28: <andrea.pellegrini@gmail.com>: Re: FATAL ERROR ISE9.1i
123867: 07/09/06: bunty: REGARDING ILA in FPGA EDITOR
123868: 07/09/06: Keith: JTAG CPLD Configuration
123869: 07/09/06: fl: Question about timing of Xilinx Core generated counter
123872: 07/09/06: xenix: load/read/ commands assembly PowerPC. Help Needed!
    123887: 07/09/06: John McCaskill: Re: load/read/ commands assembly PowerPC. Help Needed!
    123901: 07/09/06: xenix: Re: load/read/ commands assembly PowerPC. Help Needed!
    123934: 07/09/07: xenix: Re: load/read/ commands assembly PowerPC. Help Needed!
    123951: 07/09/07: John McCaskill: Re: load/read/ commands assembly PowerPC. Help Needed!
    124007: 07/09/10: Peter Ryser: Re: load/read/ commands assembly PowerPC. Help Needed!
    124054: 07/09/11: xenix: Re: load/read/ commands assembly PowerPC. Help Needed!
    124194: 07/09/14: xenix: Re: load/read/ commands assembly PowerPC. Help Needed!
    124740: 07/10/02: xenix: Re: load/read/ commands assembly PowerPC. Help Needed!
123881: 07/09/06: <aclegg1986@googlemail.com>: Is it possible to perform gate level simulation on a design without a reset?
    123882: 07/09/06: Peter Alfke: Re: Is it possible to perform gate level simulation on a design without a reset?
    123885: 07/09/06: John_H: Re: Is it possible to perform gate level simulation on a design without a reset?
        123971: 07/09/08: KJ: Re: Is it possible to perform gate level simulation on a design without a reset?
            123972: 07/09/08: John_H: Re: Is it possible to perform gate level simulation on a design without
                123973: 07/09/09: KJ: Re: Is it possible to perform gate level simulation on a design without a reset?
                123993: 07/09/10: John_H: Re: Is it possible to perform gate level simulation on a design without a reset?
                124008: 07/09/10: John_H: Re: Is it possible to perform gate level simulation on a design without a reset?
            124417: 07/09/20: Ray Andraka: Re: Is it possible to perform gate level simulation on a design without
    123990: 07/09/10: <aclegg1986@googlemail.com>: Re: Is it possible to perform gate level simulation on a design without a reset?
    123999: 07/09/10: <aclegg1986@googlemail.com>: Re: Is it possible to perform gate level simulation on a design without a reset?
    124002: 07/09/10: Andy: Re: Is it possible to perform gate level simulation on a design without a reset?
123889: 07/09/06: Symon: Free downloadable PDF graph paper.
    123893: 07/09/06: Gabor: Re: Free downloadable PDF graph paper.
    124010: 07/09/10: Kevin Neilson: Re: Free downloadable PDF graph paper.
        124029: 07/09/11: Martin Thompson: Re: Free downloadable PDF graph paper.
123894: 07/09/06: axr0284: Clock boundary crossing
    123913: 07/09/06: Peter Alfke: Re: Clock boundary crossing
    123923: 07/09/07: kkoorndyk: Re: Clock boundary crossing
        123927: 07/09/07: Hal Murray: Re: Clock boundary crossing
        124380: 07/09/20: Hal Murray: Re: Clock boundary crossing
            124396: 07/09/20: Mike Treseler: Re: Clock boundary crossing
                124404: 07/09/20: Hal Murray: Re: Clock boundary crossing
                    124432: 07/09/21: glen herrmannsfeldt: Re: Clock boundary crossing
                    125004: 07/10/15: Mike Treseler: Re: Clock boundary crossing
    123986: 07/09/10: Douglas: Re: Clock boundary crossing
    124415: 07/09/20: Alan Nishioka: Re: Clock boundary crossing
123896: 07/09/06: MM: Problem locking a DCM driven by FX output of another DCM
    123897: 07/09/06: MM: Re: Problem locking a DCM driven by FX output of another DCM
        123899: 07/09/06: MM: Re: Problem locking a DCM driven by FX output of another DCM
            123902: 07/09/06: MM: Re: Problem locking a DCM driven by FX output of another DCM
                123906: 07/09/06: MM: Re: Problem locking a DCM driven by FX output of another DCM
                    123910: 07/09/06: John_H: Re: Problem locking a DCM driven by FX output of another DCM
                        123911: 07/09/06: MM: Re: Problem locking a DCM driven by FX output of another DCM
            123903: 07/09/06: John_H: Re: Problem locking a DCM driven by FX output of another DCM
                123907: 07/09/06: MM: Re: Problem locking a DCM driven by FX output of another DCM
                    123938: 07/09/07: Symon: Re: Problem locking a DCM driven by FX output of another DCM
                        123946: 07/09/07: MM: Re: Problem locking a DCM driven by FX output of another DCM
                            123953: 07/09/07: MM: Re: Problem locking a DCM driven by FX output of another DCM
    123898: 07/09/06: John McCaskill: Re: Problem locking a DCM driven by FX output of another DCM
    123900: 07/09/06: John McCaskill: Re: Problem locking a DCM driven by FX output of another DCM
    123904: 07/09/06: John McCaskill: Re: Problem locking a DCM driven by FX output of another DCM
    123908: 07/09/06: John McCaskill: Re: Problem locking a DCM driven by FX output of another DCM
    123949: 07/09/07: John McCaskill: Re: Problem locking a DCM driven by FX output of another DCM
123909: 07/09/06: <skswrus@gmail.com>: ANNC: New Boundary-Scan Software
    123912: 07/09/06: Uwe Bonnes: Re: ANNC: New Boundary-Scan Software
    123917: 07/09/06: <skswrus@gmail.com>: Re: ANNC: New Boundary-Scan Software
    123936: 07/09/07: comp.arch.fpga: Re: ANNC: New Boundary-Scan Software
123914: 07/09/06: Dan K: VCCAUX too high on a Spartan 3 design
    123916: 07/09/07: Andrew Holme: Re: VCCAUX too high on a Spartan 3 design
        123924: 07/09/07: Jim Granville: Re: VCCAUX too high on a Spartan 3 design
    123922: 07/09/06: Peter Alfke: Re: VCCAUX too high on a Spartan 3 design
    123926: 07/09/06: Peter Alfke: Re: VCCAUX too high on a Spartan 3 design
    123939: 07/09/07: vasile: Re: VCCAUX too high on a Spartan 3 design
    123957: 07/09/07: John Larkin: Re: VCCAUX too high on a Spartan 3 design
        124266: 07/09/17: Dan K: Re: VCCAUX too high on a Spartan 3 design
    123958: 07/09/07: Peter Alfke: Re: VCCAUX too high on a Spartan 3 design
    123959: 07/09/07: <jonpry@gmail.com>: Re: VCCAUX too high on a Spartan 3 design
    124164: 07/09/13: vasile: Re: VCCAUX too high on a Spartan 3 design
123915: 07/09/06: motty: DDR Simulation via MIG
    123947: 07/09/07: motty: Re: DDR Simulation via MIG
    123992: 07/09/10: Duth: Re: DDR Simulation via MIG
123920: 07/09/07: vasile: Rocket IO clock
    123956: 07/09/07: Ed McGettigan: Re: Rocket IO clock
123937: 07/09/07: lexluthor: [Nios II] How does the PIO Core generate a interrupt?
    123955: 07/09/07: mjl296@hotmail.com: Re: How does the PIO Core generate a interrupt?
    123962: 07/09/07: lexluthor: Re: How does the PIO Core generate a interrupt?
    123968: 07/09/08: bigboss25@laposte.net: Re: [Nios II] How does the PIO Core generate a interrupt?
123943: 07/09/07: Andrew Burnside: Re: PCB Impedance Control
123944: 07/09/07: Bernard Esteban: How to simple convert a hex or mif file from Altera to Xilinx coe
    124009: 07/09/10: Gabor: Re: How to simple convert a hex or mif file from Altera to Xilinx coe file?
        124014: 07/09/11: Mark McDougall: Re: How to simple convert a hex or mif file from Altera to Xilinx
123945: 07/09/07: devices: SRAM on Cyclone Devices
    123969: 07/09/08: devices: Re: SRAM on Cyclone Devices
123950: 07/09/07: <khomeyard@googlemail.com>: RE: FPGA/VHDL digital Design permanent role - Oxford
123954: 07/09/07: Weng Tianxiang: New keyword 'OIF' and its implications
123963: 07/09/07: lexluthor: Nios II -- Why does this error occur ?
    123967: 07/09/08: newsleecher@spam.com: Re: Nios II -- Why does this error occur ?
123970: 07/09/08: johnblake2000@gmail.com: Help getting sdram running with EDK.
    123975: 07/09/10: John Williams: Re: Help getting sdram running with EDK.
    123976: 07/09/09: Alan Nishioka: Re: Help getting sdram running with EDK.
    124156: 07/09/12: johnblake2000@gmail.com: Re: Help getting sdram running with EDK.
    124157: 07/09/12: johnblake2000@gmail.com: Re: Help getting sdram running with EDK.
123974: 07/09/08: <frankzhangee@gmail.com>: Anyway to stop Altera Stratix II SignalTap data acquisition
    123978: 07/09/10: Mark McDougall: Re: Anyway to stop Altera Stratix II SignalTap data acquisition
123977: 07/09/09: <drop669@gmail.com>: Minimize power consumption
    123979: 07/09/10: John_H: Re: Minimize power consumption
        123982: 07/09/10: Jim Granville: Re: Minimize power consumption
            123985: 07/09/10: Jim Granville: Re: Minimize power consumption
            123988: 07/09/10: John_H: Re: Minimize power consumption
        123994: 07/09/10: John_H: Re: Minimize power consumption
    123980: 07/09/09: <drop669@gmail.com>: Re: Minimize power consumption
    123983: 07/09/09: <drop669@gmail.com>: Re: Minimize power consumption
    123989: 07/09/10: <drop669@gmail.com>: Re: Minimize power consumption
    124018: 07/09/10: glen herrmannsfeldt: Re: Minimize power consumption
        124065: 07/09/11: John_H: Re: Minimize power consumption
    124061: 07/09/11: <drop669@gmail.com>: Re: Minimize power consumption
123981: 07/09/10: nospam: Quick question for an Altera wizard
    123984: 07/09/09: Daniel S.: Re: Quick question for an Altera wizard
        124110: 07/09/12: Ben Jackson: Re: Quick question for an Altera wizard
    124115: 07/09/12: KJ: Re: Quick question for an Altera wizard
123991: 07/09/10: <=?ISO-8859-2?Q?G=F3rski_Adam?=>: LVDS pin placing on CYCLON II problem
    124015: 07/09/11: Rob: Re: LVDS pin placing on CYCLON II problem
        124027: 07/09/11: <=?ISO-8859-2?Q?G=F3rski_Adam?=>: Re: LVDS pin placing on CYCLON II problem
            124028: 07/09/11: <=?ISO-8859-2?Q?G=F3rski_Adam?=>: Re: LVDS pin placing on CYCLON II problem
123995: 07/09/10: <ray.delvecchio@gmail.com>: VHDL Synthesis Error
    123998: 07/09/10: Mike Treseler: Re: VHDL Synthesis Error
        124011: 07/09/10: Brad Smallridge: Re: VHDL Synthesis Error
    124001: 07/09/10: Andy: Re: VHDL Synthesis Error
    124003: 07/09/10: Ray D.: Re: VHDL Synthesis Error
123996: 07/09/10: Weng Tianxiang: What is the name of Altera latest and most advanced chip serial that is competable in technology with Vertex V in terms of system strucute(LUT6...)
    124006: 07/09/10: John_H: Re: What is the name of Altera latest and most advanced chip serial that is compatible in technology with Virtex-5 in terms of system strucute(LUT6...)
    124012: 07/09/10: Weng Tianxiang: Re: What is the name of Altera latest and most advanced chip serial that is compatible in technology with Virtex-5 in terms of system strucute(LUT6...)
123997: 07/09/10: Weng Tianxiang: What is called carry chain structure in FPGA is called in IC?
    124005: 07/09/10: John_H: Re: What is called carry chain structure in FPGA is called in IC?
        124016: 07/09/11: John_H: Re: What is called carry chain structure in FPGA is called in IC?
    124013: 07/09/10: Weng Tianxiang: Re: What is called carry chain structure in FPGA is called in IC?
    124017: 07/09/10: Peter Alfke: Re: What is called carry chain structure in FPGA is called in IC?
        124099: 07/09/11: glen herrmannsfeldt: Re: What is called carry chain structure in FPGA is called in IC?
    124026: 07/09/11: comp.arch.fpga: Re: What is called carry chain structure in FPGA is called in IC?
124000: 07/09/10: mits130: 1/2 Convolutional Encoding of CNAV Data
124004: 07/09/10: <ghelbig@lycos.com>: Question about Virtex-4 DCM
    124022: 07/09/10: austin: Re: Question about Virtex-4 DCM
    124092: 07/09/12: <ghelbig@lycos.com>: Re: Question about Virtex-4 DCM
124019: 07/09/11: <richard.melikson@gmail.com>: Uses of Gray code in digital design
    124021: 07/09/10: Peter Alfke: Re: Uses of Gray code in digital design
        124023: 07/09/11: Jonathan Kirwan: Re: Uses of Gray code in digital design
        124025: 07/09/11: Zara: Re: Uses of Gray code in digital design
        124041: 07/09/11: Jim Granville: Re: Uses of Gray code in digital design
            124044: 07/09/11: Hal Murray: Re: Uses of Gray code in digital design
                124101: 07/09/12: David Brown: Re: Uses of Gray code in digital design
                    124126: 07/09/12: Charles, NG: Re: Uses of Gray code in digital design
                        124165: 07/09/13: David Brown: Re: Uses of Gray code in digital design
        124069: 07/09/11: Mike Treseler: Re: Uses of Gray code in digital design
            124086: 07/09/11: CBFalconer: Re: Uses of Gray code in digital design
                124087: 07/09/11: Mike Treseler: Re: Uses of Gray code in digital design
                    124095: 07/09/12: CBFalconer: Re: Uses of Gray code in digital design
                        124125: 07/09/12: Mike Treseler: Re: Uses of Gray code in digital design
                    124096: 07/09/12: Paul Keinanen: Re: Uses of Gray code in digital design
                        124106: 07/09/12: Jim Granville: Re: Uses of Gray code in digital design
        124084: 07/09/11: glen herrmannsfeldt: Re: Uses of Gray code in digital design
        124088: 07/09/12: Jim Granville: Re: Uses of Gray code in digital design
    124024: 07/09/11: Jim Granville: Re: Uses of Gray code in digital design
        124039: 07/09/11: Jim Granville: Re: Uses of Gray code in digital design
            124070: 07/09/11: Mike Treseler: Re: Uses of Gray code in digital design
    124030: 07/09/11: Bill Davy: Re: Uses of Gray code in digital design
    124031: 07/09/11: Jonathan Kirwan: Re: Uses of Gray code in digital design
        124033: 07/09/11: Jonathan Kirwan: Re: Uses of Gray code in digital design
        124034: 07/09/11: David Brown: Re: Uses of Gray code in digital design
            124102: 07/09/12: David Brown: Re: Uses of Gray code in digital design
        124035: 07/09/11: Jonathan Kirwan: Re: Uses of Gray code in digital design
        124043: 07/09/11: Jonathan Kirwan: Re: Uses of Gray code in digital design
            124063: 07/09/11: Eric Smith: Re: Uses of Gray code in digital design
                124144: 07/09/12: Eric Smith: Re: Uses of Gray code in digital design
            124077: 07/09/11: Jonathan Kirwan: Re: Uses of Gray code in digital design
                124090: 07/09/12: Jim Granville: Re: Uses of Gray code in digital design
                    124097: 07/09/12: Jonathan Kirwan: Re: Uses of Gray code in digital design
        124050: 07/09/11: Nial Stewart: Re: Uses of Gray code in digital design
        124145: 07/09/12: Hal Murray: Re: Uses of Gray code in digital design
            124173: 07/09/13: Nial Stewart: Re: Uses of Gray code in digital design
                124184: 07/09/13: Hal Murray: Re: Uses of Gray code in digital design
                124187: 07/09/13: Hal Murray: Re: Uses of Gray code in digital design
                124195: 07/09/14: Nial Stewart: Re: Uses of Gray code in digital design
                    124223: 07/09/14: KJ: Re: Uses of Gray code in digital design
    124036: 07/09/11: slebetman: Re: Uses of Gray code in digital design
    124037: 07/09/11: <richard.melikson@gmail.com>: Re: Uses of Gray code in digital design
    124038: 07/09/11: <richard.melikson@gmail.com>: Re: Uses of Gray code in digital design
    124040: 07/09/11: <richard.melikson@gmail.com>: Re: Uses of Gray code in digital design
    124042: 07/09/11: <richard.melikson@gmail.com>: Re: Uses of Gray code in digital design
    124047: 07/09/11: <richard.melikson@gmail.com>: Re: Uses of Gray code in digital design
    124048: 07/09/11: <richard.melikson@gmail.com>: Re: Uses of Gray code in digital design
    124049: 07/09/11: <richard.melikson@gmail.com>: Re: Uses of Gray code in digital design
    124053: 07/09/11: John_H: Re: Uses of Gray code in digital design
    124060: 07/09/11: Andy: Re: Uses of Gray code in digital design
    124064: 07/09/11: dick: Re: Uses of Gray code in digital design
    124071: 07/09/11: CBFalconer: Re: Uses of Gray code in digital design
    124073: 07/09/11: slebetman@yahoo.com: Re: Uses of Gray code in digital design
    124089: 07/09/11: johnp: Re: Uses of Gray code in digital design
    124135: 07/09/12: Peter Alfke: Re: Uses of Gray code in digital design
    124170: 07/09/13: Nir Dahan: Re: Uses of Gray code in digital design
    124182: 07/09/13: KJ: Re: Uses of Gray code in digital design
    124192: 07/09/14: slebetman@yahoo.com: Re: Uses of Gray code in digital design
124032: 07/09/11: <damicha@gmx.de>: Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller
    124045: 07/09/11: Göran Bilski: Re: Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller
    124052: 07/09/11: <damicha@gmx.de>: Re: Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller
    124056: 07/09/11: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller
    124105: 07/09/12: <damicha@gmx.de>: Re: Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller
124046: 07/09/11: u_stadler@yahoo.de: hydraxc
124057: 07/09/11: taco: microblaze toolchain compilation question
    124072: 07/09/12: John Williams: Re: microblaze toolchain compilation question
        124100: 07/09/12: taco: Re: microblaze toolchain compilation question
            124143: 07/09/12: Vasanth Asokan: Re: microblaze toolchain compilation question
124058: 07/09/11: J.Wild: application about hardeware attributes
    125091: 07/10/16: J.Wild: Re: application about hardeware attributes
124059: 07/09/11: davew: Stratix III Memory usage efficiency
    124074: 07/09/11: Mike Treseler: Re: Stratix III Memory usage efficiency
        124118: 07/09/12: Kim Enkovaara: Re: Stratix III Memory usage efficiency
        124124: 07/09/12: Mike Treseler: Re: Stratix III Memory usage efficiency
    124116: 07/09/12: davew: Re: Stratix III Memory usage efficiency
    124128: 07/09/12: Subroto Datta: Re: Stratix III Memory usage efficiency
    124150: 07/09/12: davew: Re: Stratix III Memory usage efficiency
124062: 07/09/11: A.D.: PCI byte enalbes in read cycles
    124067: 07/09/11: John_H: Re: PCI byte enalbes in read cycles
    124082: 07/09/12: Mark McDougall: Re: PCI byte enalbes in read cycles
        124083: 07/09/12: Mark McDougall: Re: PCI byte enalbes in read cycles
        124094: 07/09/12: A.D.: Re: PCI byte enalbes in read cycles
            124098: 07/09/12: Mark McDougall: Re: PCI byte enalbes in read cycles
                124130: 07/09/12: A.D.: Re: PCI byte enalbes in read cycles
                    124153: 07/09/12: PeteS: Re: PCI byte enalbes in read cycles
                        124161: 07/09/13: A.D.: Re: PCI byte enalbes in read cycles
    124109: 07/09/12: Ben Jackson: Re: PCI byte enalbes in read cycles
    124152: 07/09/12: Mindspring Newsgroups: Re: PCI byte enalbes in read cycles
        124154: 07/09/12: Ben Jackson: Re: PCI byte enalbes in read cycles
        124162: 07/09/13: A.D.: Re: PCI byte enalbes in read cycles
            124172: 07/09/13: John_H: Re: PCI byte enalbes in read cycles
124066: 07/09/11: Nico Coesel: Good VHDL reference?
    124076: 07/09/11: Symon: Re: Good VHDL reference?
    124091: 07/09/12: Eli Bendersky: Re: Good VHDL reference?
        124122: 07/09/12: Dan K: Re: Good VHDL reference?
    124104: 07/09/12: xenix: Re: Good VHDL reference?
    124132: 07/09/12: Weng Tianxiang: Re: Good VHDL reference?
    124138: 07/09/12: Andy: Re: Good VHDL reference?
    157047: 14/09/13: pini_kr: Re: Good VHDL reference?
124068: 07/09/11: Brad Smallridge: FPGA Archives
    124107: 07/09/12: Martin Thompson: Re: FPGA Archives
        124140: 07/09/12: Brad Smallridge: Re: FPGA Archives
            124142: 07/09/12: MM: Re: FPGA Archives
            124166: 07/09/13: Martin Thompson: Re: FPGA Archives
    124695: 07/09/30: Philip Freidin: Re: FPGA Archives
124075: 07/09/11: <yoni.lan@gmail.com>: Address sensitive process, Xilinx virtex2pro
    124079: 07/09/11: Brad Smallridge: Re: Address sensitive process, Xilinx virtex2pro
        124108: 07/09/12: Symon: Re: Address sensitive process, Xilinx virtex2pro
            124134: 07/09/12: Brad Smallridge: Re: Address sensitive process, Xilinx virtex2pro
                124139: 07/09/12: Brad Smallridge: Re: Address sensitive process, Xilinx virtex2pro
                124168: 07/09/13: Symon: Re: Address sensitive process, Xilinx virtex2pro
    124119: 07/09/12: Erik Anderson: Re: Address sensitive process, Xilinx virtex2pro
    124123: 07/09/12: Jeff Cunningham: Re: Address sensitive process, Xilinx virtex2pro
    124137: 07/09/12: Andy: Re: Address sensitive process, Xilinx virtex2pro
    124146: 07/09/12: Andy: Re: Address sensitive process, Xilinx virtex2pro
124078: 07/09/12: Wren: ML410 Board & 1GB DDR2 DIMM Problem
    124080: 07/09/11: Brad Smallridge: Re: ML410 Board & 1GB DDR2 DIMM Problem
    124085: 07/09/11: Wren: Re: ML410 Board & 1GB DDR2 DIMM Problem
    124093: 07/09/12: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: ML410 Board & 1GB DDR2 DIMM Problem
124103: 07/09/12: lexluthor: [Nios II] How fast the cpu in Nios II can reach in the Cycone ?
    124114: 07/09/12: <=?GB2312?B?R6iucnNraSBBZGFt?=>: Re: [Nios II] How fast the cpu in Nios II can reach in the Cycone
    124155: 07/09/12: Ben Jackson: Re: [Nios II] How fast the cpu in Nios II can reach in the Cycone ?
124111: 07/09/12: Steven Derrien: Command line quartus_pgm very slow
    124113: 07/09/12: Petter Gustad: Re: Command line quartus_pgm very slow
124112: 07/09/12: chriskoh: precision errors. microblaze vs matlab single precision... huh?
124120: 07/09/12: Erik Anderson: VHDL Design Pattern Book
    124121: 07/09/12: Steven Derrien: Re: VHDL Design Pattern Book
124127: 07/09/12: chriskoh: Re: precision errors. microblaze vs matlab single precision... huh?
    124129: 07/09/12: Steven Derrien: Re: precision errors. microblaze vs matlab single precision... huh?
    124133: 07/09/12: Paul Keinanen: Re: precision errors. microblaze vs matlab single precision... huh?
        124160: 07/09/12: Robert Adsett: Re: precision errors. microblaze vs matlab single precision... huh?
124131: 07/09/12: chriskoh: Re: precision errors. microblaze vs matlab single precision... huh?
124136: 07/09/12: <vitek.vitek@gmail.com>: Altera + ARM Cortex-M1
124141: 07/09/12: <calkins@millenworks.com>: Ethernet Code Problem with Xilinx Spartan3E
    124163: 07/09/12: <vitek.vitek@gmail.com>: Re: Ethernet Code Problem with Xilinx Spartan3E
124147: 07/09/12: Brad Smallridge: XAPP851 fifo36 missing
    124148: 07/09/12: Brad Smallridge: Re: XAPP851 fifo36 missing
        124149: 07/09/12: Kevin Neilson: Re: XAPP851 fifo36 missing
            124151: 07/09/12: Brad Smallridge: Re: XAPP851 fifo36 missing
124158: 07/09/12: chriskoh: Re: precision errors. microblaze vs matlab single precision... huh?
124159: 07/09/12: cpope: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
    124174: 07/09/13: Alan Nishioka: Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
        124180: 07/09/13: cpope: Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
    124181: 07/09/13: Alan Nishioka: Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
    124183: 07/09/13: Petter Gustad: Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
        124201: 07/09/14: cpope: Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
            124206: 07/09/14: Petter Gustad: Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
            124213: 07/09/14: cpope: Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
    124203: 07/09/14: <neilla@pipstechnology.co.uk>: Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
124167: 07/09/13: Dolphin: overloading ' operators in VHDL
    124189: 07/09/14: Mark McDougall: Re: overloading ' operators in VHDL
    124265: 07/09/17: RCIngham: Re: overloading ' operators in VHDL
124169: 07/09/13: <james.lbs@gmail.com>: Xilinx System Generator Error!
124171: 07/09/13: MJ Pearson: Peripheral Trouble!
    124178: 07/09/13: Andrea05: Re: Peripheral Trouble!
        124318: 07/09/18: MJ Pearson: Re: Peripheral Trouble!
            124339: 07/09/18: John McCaskill: Re: Peripheral Trouble!
124175: 07/09/13: Barry: Virtex5 PLL for DDR2 interface
    124234: 07/09/15: austin: Re: Virtex5 PLL for DDR2 interface
124176: 07/09/13: <dcaulfield@lowtechsolutions.net>: genmcs.pl for a V4FX60 aka loading the cache from the prom on a multi processor device
124177: 07/09/13: Andrea05: Problem with Microblaze max clocking
    124179: 07/09/13: John_H: Re: Problem with Microblaze max clocking
    124191: 07/09/14: Göran Bilski: Re: Problem with Microblaze max clocking
124185: 07/09/13: Brad Smallridge: MicroBlaze Tutorial
    124188: 07/09/14: John Williams: Re: MicroBlaze Tutorial
        124219: 07/09/14: Brad Smallridge: Re: MicroBlaze Tutorial
    124277: 07/09/17: svenand: Re: MicroBlaze Tutorial
124186: 07/09/13: <cstring625@yahoo.com>: Virtex-4 PCB design
    124261: 07/09/17: Gabor: Re: Virtex-4 PCB design
124190: 07/09/13: LowSNR: Open-Source VHDL Synthesis for FPSLIC?
    124207: 07/09/14: Mike Treseler: Re: Open-Source VHDL Synthesis for FPSLIC?
    124221: 07/09/14: Eric Smith: Re: Open-Source VHDL Synthesis for FPSLIC?
    124885: 07/10/09: Adam Megacz: Re: Open-Source VHDL Synthesis for FPSLIC?
124193: 07/09/14: =?utf-8?B?R2FMYUt0SWtVc+KEog==?=: Is post-place and route simulation useful?
    124199: 07/09/14: KJ: Re: Is post-place and route simulation useful?
    124200: 07/09/14: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: Is post-place and route simulation useful?
    124205: 07/09/14: Kim Enkovaara: Re: Is post-place and route simulation useful?
        124222: 07/09/14: HT-Lab: Re: Is post-place and route simulation useful?
    124208: 07/09/14: Mike Treseler: Re: Is post-place and route simulation useful?
    124209: 07/09/14: Andy: Re: Is post-place and route simulation useful?
124196: 07/09/14: llandre: Xilinx GSRD reference design and 3rd party synthesizer
124197: 07/09/14: acd: Physical Design Contribution to FPGA/CPLD success
    124210: 07/09/14: Mike Treseler: Re: Physical Design Contribution to FPGA/CPLD success
        124214: 07/09/14: Mike Treseler: Re: Physical Design Contribution to FPGA/CPLD success
            124216: 07/09/14: Mike Treseler: Re: Physical Design Contribution to FPGA/CPLD success
        124224: 07/09/14: Alex Colvin: Re: Physical Design Contribution to FPGA/CPLD success
    124211: 07/09/14: Peter Alfke: Re: Physical Design Contribution to FPGA/CPLD success
    124212: 07/09/14: acd: Re: Physical Design Contribution to FPGA/CPLD success
    124220: 07/09/14: Andy: Re: Physical Design Contribution to FPGA/CPLD success
        124243: 07/09/16: glen herrmannsfeldt: Re: Physical Design Contribution to FPGA/CPLD success
    124252: 07/09/17: Jim Granville: Re: Physical Design Contribution to FPGA/CPLD success
        124288: 07/09/17: glen herrmannsfeldt: Re: Physical Design Contribution to FPGA/CPLD success
124198: 07/09/14: Andrew Greensted: Spartan-3E Slave Serial Configuration
    124202: 07/09/14: Symon: Re: Spartan-3E Slave Serial Configuration
        124204: 07/09/14: Andrew Greensted: Re: Spartan-3E Slave Serial Configuration
            124226: 07/09/14: John Larkin: Re: Spartan-3E Slave Serial Configuration
    124217: 07/09/14: Brian Davis: Re: Spartan-3E Slave Serial Configuration
        124244: 07/09/16: Andy: Re: Spartan-3E Slave Serial Configuration
124215: 07/09/14: <alleynb@gmail.com>: post translate and post PAR problems with XST and Modelsim
    124260: 07/09/17: Gabor: Re: post translate and post PAR problems with XST and Modelsim
124218: 07/09/14: Abhi: add_file -verilog +define ..... filename.v
124225: 07/09/15: RL: Beginner Advice (Languages, tools etc.)
    124227: 07/09/14: Mike Treseler: Re: Beginner Advice (Languages, tools etc.)
    124228: 07/09/14: Jeff Cunningham: Re: Beginner Advice (Languages, tools etc.)
        124231: 07/09/15: Nico Coesel: Re: Beginner Advice (Languages, tools etc.)
            124241: 07/09/16: Jeff Cunningham: Re: Beginner Advice (Languages, tools etc.)
    124230: 07/09/15: HT-Lab: Re: Beginner Advice (Languages, tools etc.)
    124232: 07/09/15: James Harris: Re: Beginner Advice (Languages, tools etc.)
    124235: 07/09/15: Bob Perlman: Re: Beginner Advice (Languages, tools etc.)
        124237: 07/09/16: RL: Re: Beginner Advice (Languages, tools etc.)
            124240: 07/09/16: Jeff Cunningham: Re: Beginner Advice (Languages, tools etc.)
            124242: 07/09/16: HT-Lab: Re: Beginner Advice (Languages, tools etc.)
            124269: 07/09/17: Bob Perlman: Re: Beginner Advice (Languages, tools etc.)
    124239: 07/09/16: Andrew FPGA: Re: Beginner Advice (Languages, tools etc.)
    124251: 07/09/17: Jim Granville: Re: Beginner Advice (Languages, tools etc.)
124229: 07/09/14: Manny: Virtex II pro design question
    124233: 07/09/15: Daniel S.: Re: Virtex II pro design question
    124236: 07/09/15: Manny: Re: Virtex II pro design question
124238: 07/09/15: Brad Smallridge: XAPP806 issues DCM Phase Shift
124245: 07/09/16: <carlmorada@gmail.com>: sounds
    124249: 07/09/16: Icky Thwacket: Re: sounds
        124250: 07/09/16: MikeJ: Re: sounds
124246: 07/09/16: <embeddedexpert2007@gmail.com>: FPGA power optimize! Help
124247: 07/09/16: Uncle Noah: [ANNOUNCE] YARDstick - custom processor development toolset
    124248: 07/09/16: Uncle Noah: Re: YARDstick - custom processor development toolset
    124290: 07/09/17: Uncle Noah: Re: YARDstick - custom processor development toolset
124253: 07/09/16: Weng Tianxiang: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124254: 07/09/16: Uncle Noah: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124255: 07/09/16: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124256: 07/09/16: Andrew FPGA: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124263: 07/09/17: Tricky: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124264: 07/09/17: Symon: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
        124328: 07/09/19: Jim Granville: Re: Guess: what is the largest number of state machines in a current
            124357: 07/09/19: Jim Lewis: Re: Guess: what is the largest number of state machines in a current
                124360: 07/09/19: Jeff Cunningham: Re: Guess: what is the largest number of state machines in a current
                124449: 07/09/21: Daniel S.: Re: Guess: what is the largest number of state machines in a current
        124386: 07/09/20: Thomas Entner: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124267: 07/09/17: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124268: 07/09/17: Philip Potter: Re: Guess: what is the largest number of state machines in a current
        124335: 07/09/19: Jim Granville: Re: Guess: what is the largest number of state machines in a current
            124362: 07/09/19: Jeff Cunningham: Re: Guess: what is the largest number of state machines in a current
            124365: 07/09/19: Hal Murray: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
                124370: 07/09/19: Hal Murray: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
                    124375: 07/09/19: Hal Murray: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
                    124376: 07/09/20: John_H: Re: Guess: what is the largest number of state machines in a current
                        124410: 07/09/20: glen herrmannsfeldt: Re: Guess: what is the largest number of state machines in a current
                            124414: 07/09/20: John_H: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
                        124411: 07/09/20: Hal Murray: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
                        124434: 07/09/21: glen herrmannsfeldt: Re: Guess: what is the largest number of state machines in a current
                            124442: 07/09/21: Hal Murray: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
                            124448: 07/09/21: glen herrmannsfeldt: Re: Guess: what is the largest number of state machines in a current
                            124529: 07/09/25: Ray Andraka: Re: Guess: what is the largest number of state machines in a current
        124373: 07/09/19: jtw: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124273: 07/09/17: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124274: 07/09/17: Shannon: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124275: 07/09/17: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124279: 07/09/17: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
        124284: 07/09/17: Tobias Weingartner: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
        124326: 07/09/18: glen herrmannsfeldt: Re: Guess: what is the largest number of state machines in a current
    124280: 07/09/18: Jim Granville: Re: Guess: what is the largest number of state machines in a current
        124321: 07/09/18: John_H: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
            124346: 07/09/19: John_H: Re: Guess: what is the largest number of state machines in a current
        124323: 07/09/18: glen herrmannsfeldt: Re: Guess: what is the largest number of state machines in a current
        124367: 07/09/19: glen herrmannsfeldt: Re: Guess: what is the largest number of state machines in a current
        124433: 07/09/21: Hal Murray: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124281: 07/09/17: Shannon: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124283: 07/09/17: glen herrmannsfeldt: Re: Guess: what is the largest number of state machines in a current
    124301: 07/09/18: comp.arch.fpga: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124319: 07/09/18: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124341: 07/09/18: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124344: 07/09/19: Shannon: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124348: 07/09/19: comp.arch.fpga: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124358: 07/09/19: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124361: 07/09/19: Shannon: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124368: 07/09/19: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124371: 07/09/19: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124372: 07/09/20: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124378: 07/09/19: Uncle Noah: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124406: 07/09/20: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124408: 07/09/20: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124409: 07/09/20: Shannon: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124429: 07/09/21: Amir: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124441: 07/09/21: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124446: 07/09/21: Bob Perlman: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124447: 07/09/21: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124450: 07/09/21: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124482: 07/09/24: comp.arch.fpga: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124484: 07/09/24: comp.arch.fpga: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124530: 07/09/26: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124540: 07/09/26: comp.arch.fpga: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124551: 07/09/26: Weng Tianxiang: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124257: 07/09/17: Sylvain Munaut <SomeOne@SomeDomain.com>: Unexplained behavior with DDR2 controller on Xilinx V5
    124285: 07/09/17: Brad Smallridge: Re: Unexplained behavior with DDR2 controller on Xilinx V5
    124295: 07/09/18: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Unexplained behavior with DDR2 controller on Xilinx V5
    124300: 07/09/18: jacobusn@xilinx.com: Re: Unexplained behavior with DDR2 controller on Xilinx V5
    124307: 07/09/18: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Unexplained behavior with DDR2 controller on Xilinx V5
124258: 07/09/17: vasile: global clock on virtex5 question
    124271: 07/09/17: Ed McGettigan: Re: global clock on virtex5 question
        124315: 07/09/18: Ed McGettigan: Re: global clock on virtex5 question
    124293: 07/09/18: vasile: Re: global clock on virtex5 question
    124352: 07/09/19: vasile: Re: global clock on virtex5 question
124259: 07/09/17: Martin Sauer: ECP2/M und Serdes
124270: 07/09/17: Amontec, Larry: Altera / Lattice / Xilinx CPLDs ?
    124272: 07/09/17: austin: Re: Altera / Lattice / Xilinx CPLDs ?
    124278: 07/09/17: John_H: Re: Altera / Lattice / Xilinx CPLDs ?
        124286: 07/09/17: Uwe Bonnes: Re: Altera / Lattice / Xilinx CPLDs ?
            124289: 07/09/17: John_H: Re: Altera / Lattice / Xilinx CPLDs ?
                124298: 07/09/18: Uwe Bonnes: Re: Altera / Lattice / Xilinx CPLDs ?
        124330: 07/09/19: Jim Granville: Re: Altera / Lattice / Xilinx CPLDs ?
        124334: 07/09/18: Jon Elson: Re: Altera / Lattice / Xilinx CPLDs ?
    124282: 07/09/17: <ghelbig@lycos.com>: Re: Altera / Lattice / Xilinx CPLDs ?
    124287: 07/09/17: Gabor: Re: Altera / Lattice / Xilinx CPLDs ?
    124294: 07/09/18: vasile: Re: Altera / Lattice / Xilinx CPLDs ?
    124327: 07/09/18: Dave Pollum: Re: Altera / Lattice / Xilinx CPLDs ?
    124331: 07/09/19: Jim Granville: Re: Altera / Lattice / Xilinx CPLDs ?
124276: 07/09/17: S: Directing data to DDR
124291: 07/09/17: Pasacco: Virtex-4 SELECT MAP configuration
    124384: 07/09/20: jerzy.gbur@gmail.com: Re: Virtex-4 SELECT MAP configuration
124292: 07/09/17: <fastgreen2000@yahoo.com>: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
    124303: 07/09/18: Martin Thompson: Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
        124311: 07/09/18: Martin Thompson: Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
    124309: 07/09/18: Gabor: Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
    124310: 07/09/18: Gabor: Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
    124313: 07/09/18: <fastgreen2000@yahoo.com>: Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
    124363: 07/09/19: Andy Peters: Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
124296: 07/09/18: aravind: Tristate bus on spartan FPGA
    124297: 07/09/18: RCIngham: Re: Tristate bus on spartan FPGA
        124304: 07/09/18: Amontec, Larry: Re: Tristate bus on spartan FPGA
            124322: 07/09/18: Mike Treseler: Re: Tristate bus on spartan FPGA
                124338: 07/09/18: glen herrmannsfeldt: Re: Tristate bus on spartan FPGA
            124324: 07/09/18: glen herrmannsfeldt: Re: Tristate bus on spartan FPGA
    124299: 07/09/18: Maki: Re: Tristate bus on spartan FPGA
    124305: 07/09/18: Jon Beniston: Re: Tristate bus on spartan FPGA
        124308: 07/09/18: Mike Lewis: Re: Tristate bus on spartan FPGA
    124343: 07/09/18: aravind: Re: Tristate bus on spartan FPGA
124306: 07/09/18: xenix: Data-side BRAM
124314: 07/09/19: Allan Herriman: Looking for fast AES cores with low latency
    124316: 07/09/18: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Looking for fast AES cores with low latency
    124342: 07/09/18: IDDLife: Re: Looking for fast AES cores with low latency
    124347: 07/09/19: backhus: Re: Looking for fast AES cores with low latency
    124355: 07/09/19: Allan Herriman: Re: Looking for fast AES cores with low latency
        124379: 07/09/20: backhus: Re: Looking for fast AES cores with low latency
            124389: 07/09/21: Allan Herriman: Re: Looking for fast AES cores with low latency
                124436: 07/09/21: glen herrmannsfeldt: Re: Looking for fast AES cores with low latency
                    124451: 07/09/22: Allan Herriman: Re: Looking for fast AES cores with low latency
                        124465: 07/09/22: glen herrmannsfeldt: Re: Looking for fast AES cores with low latency
    124369: 07/09/19: IDDLife: Re: Looking for fast AES cores with low latency
124317: 07/09/18: Topi Rinkinen: Re: Symbolic names for pll derived clocks in SDC file? (quartus)
124320: 07/09/18: davew: Verilog simple dual port memory with different input and output widths?
    124496: 07/09/24: Kevin Neilson: Re: Verilog simple dual port memory with different input and output
    124511: 07/09/25: davew: Re: Verilog simple dual port memory with different input and output widths?
124325: 07/09/18: acd: Population Count circuit
    124329: 07/09/18: John_H: Re: Population Count circuit
        124333: 07/09/18: John_H: Re: Population Count circuit
        124340: 07/09/18: glen herrmannsfeldt: Re: Population Count circuit
    124332: 07/09/18: acd: Re: Population Count circuit
    124336: 07/09/18: John McCaskill: Re: Population Count circuit
        124349: 07/09/19: Symon: Re: Population Count circuit
    124337: 07/09/18: glen herrmannsfeldt: Re: Population Count circuit
    124354: 07/09/19: comp.arch.fpga: Re: Population Count circuit
124350: 07/09/19: Sven Heithecker: FPGA history
    124351: 07/09/19: Sven Heithecker: Re: FPGA history
    124353: 07/09/19: Rafael Deliano: Re: FPGA history
        124366: 07/09/19: Hal Murray: Re: FPGA history
    124356: 07/09/19: comp.arch.fpga: Re: FPGA history
    124364: 07/09/19: Uwe Bonnes: Re: FPGA history
124359: 07/09/19: merche: help! ACTEL PROASIC PLUS clock buffer
    124377: 07/09/19: Thomas Stanka: Re: help! ACTEL PROASIC PLUS clock buffer
        124437: 07/09/21: Mike Treseler: Re: help! ACTEL PROASIC PLUS clock buffer
    124382: 07/09/20: merche: Re: help! ACTEL PROASIC PLUS clock buffer
    124418: 07/09/20: Thomas Stanka: Re: help! ACTEL PROASIC PLUS clock buffer
    124427: 07/09/21: merche: Re: help! ACTEL PROASIC PLUS clock buffer
    124475: 07/09/23: Thomas Stanka: Re: help! ACTEL PROASIC PLUS clock buffer
    124476: 07/09/23: Thomas Stanka: Re: help! ACTEL PROASIC PLUS clock buffer
124374: 07/09/19: Hal Murray: Re: Gated Clock Problems
    124488: 07/09/24: Jon Elson: Re: Gated Clock Problems
124381: 07/09/20: GKnittel: Multi-cycle paths in VHDL libraries
124383: 07/09/20: merche: proasic plus. actel
    124439: 07/09/21: dscolson@rcn.com: Re: proasic plus. actel
124385: 07/09/20: vasile: Re: Gated Clock Problems
    124387: 07/09/20: Mike Lewis: Re: Gated Clock Problems
        124390: 07/09/20: Symon: Re: Gated Clock Problems
            124393: 07/09/20: Stef: Re: Gated Clock Problems
                124394: 07/09/20: Symon: Re: Gated Clock Problems
                124395: 07/09/20: mk: Re: Gated Clock Problems
                124401: 07/09/20: Hal Murray: Re: Gated Clock Problems
                    124444: 07/09/22: Stef: Re: Gated Clock Problems
                        124445: 07/09/21: Hal Murray: Re: Gated Clock Problems
                        124458: 07/09/22: mk: Re: Gated Clock Problems
                        124490: 07/09/24: Jon Elson: Re: Gated Clock Problems
                            124497: 07/09/25: Symon: Re: Gated Clock Problems
                                124505: 07/09/25: Symon: Re: Gated Clock Problems
                            124514: 07/09/26: Allan Herriman: Re: Gated Clock Problems
            124435: 07/09/21: glen herrmannsfeldt: Re: Gated Clock Problems
                124438: 07/09/21: Symon: Re: Gated Clock Problems
        124399: 07/09/20: Hal Murray: Re: Gated Clock Problems
        124471: 07/09/23: Uwe Bonnes: Re: Gated Clock Problems
        124472: 07/09/23: Eric Smith: Re: Gated Clock Problems
        124485: 07/09/24: Mike Lewis: Re: Gated Clock Problems
            124491: 07/09/24: Symon: Re: Gated Clock Problems
    124489: 07/09/24: Jon Elson: Re: Gated Clock Problems
124388: 07/09/20: Wei Wang: Is it possible for two wires to share the same FPGA pin?
    124391: 07/09/20: Dave Pollum: Re: Is it possible for two wires to share the same FPGA pin?
    124392: 07/09/20: mk: Re: Is it possible for two wires to share the same FPGA pin?
124397: 07/09/20: cesarp: DMA scatter gather with PLB bus?
    124402: 07/09/20: Jeff Cunningham: Re: DMA scatter gather with PLB bus?
    124425: 07/09/21: cesarp: Re: DMA scatter gather with PLB bus?
124398: 07/09/20: Joseph: Comparing Adder synthesis techniques
    124400: 07/09/21: David R Brooks: Re: Comparing Adder synthesis techniques
    124403: 07/09/20: Mike Treseler: Re: Comparing Adder synthesis techniques
    124413: 07/09/20: John_H: Re: Comparing Adder synthesis techniques
124405: 07/09/20: Guenter: Re: Free downloadable PDF graph paper.
124407: 07/09/20: <gks.1981@hotmail.com>: hardware software codesign
    124412: 07/09/20: Hal Murray: Re: hardware software codesign
    124416: 07/09/20: John Retta: Re: hardware software codesign
124419: 07/09/21: <nanaware_amit@rediffmail.com>: how interfacing of cpld and cpu done?
    124421: 07/09/21: Antti: Re: how interfacing of cpld and cpu done?
124420: 07/09/21: Antti: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
    124422: 07/09/21: Manny: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
    124423: 07/09/21: Antti: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
    124424: 07/09/21: Manny: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
    124473: 07/09/23: Eric Smith: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
        124494: 07/09/25: Jim Granville: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost
        124570: 07/09/26: Eric Smith: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
    124483: 07/09/24: Antti: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
    125447: 07/10/25: <martin_pager@yahoo.com>: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
    125476: 07/10/26: Antti: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
124426: 07/09/21: <gilbert1219com@gmail.com>: Using PlanAhead for Partial Reconfiguration
    124824: 07/10/05: hiroyuki.kawai@gmail.com: Re: Using PlanAhead for Partial Reconfiguration
124428: 07/09/21: John Adair: Enterpoint Web Site
124430: 07/09/21: fp: baord for learning softcore processor
    124431: 07/09/21: John_H: Re: baord for learning softcore processor
    124440: 07/09/21: svenand: Re: baord for learning softcore processor
124443: 07/09/21: Gabor: Re: Gated Clock Problems
124452: 07/09/22: Ankit: Configuring Impact on any version of linux
    124453: 07/09/22: svenand: Re: Configuring Impact on any version of linux
    124493: 07/09/24: MM: Re: Configuring Impact on any version of linux
124454: 07/09/22: pwie42: DDR RAM timing contraints
124455: 07/09/22: Weng Tianxiang: Answer: maximum number of state machines in a current chip: > 500k
    124456: 07/09/22: Jonathan Bromley: Re: Answer: maximum number of state machines in a current chip: > 500k
        124463: 07/09/22: Evan Lavelle: Re: Answer: maximum number of state machines in a current chip: > 500k
    124462: 07/09/22: John Retta: Re: Answer: maximum number of state machines in a current chip: > 500k
    124480: 07/09/24: <neilla@pipstechnology.co.uk>: Re: Answer: maximum number of state machines in a current chip: > 500k
    124486: 07/09/24: Mike Lewis: Re: Answer: maximum number of state machines in a current chip: > 500k
    124487: 07/09/24: <ghelbig@lycos.com>: Re: Answer: maximum number of state machines in a current chip: > 500k
124457: 07/09/22: Helpme: Xilinx Microblaze EDK and Virtex5/LXT TEMAC core?
124459: 07/09/22: Helpme: Does Modelsim work under Windows Vista?
    124461: 07/09/22: John Retta: Re: Does Modelsim work under Windows Vista?
        124672: 07/09/29: Paul Floyd: Re: Does Modelsim work under Windows Vista?
    124657: 07/09/29: <prince@dyumnin.com>: Re: Does Modelsim work under Windows Vista?
124460: 07/09/22: <lembke.stefan@googlemail.com>: CRC calculation of Virtex 4 bitstream
    124464: 07/09/22: Mike Treseler: Re: CRC calculation of Virtex 4 bitstream
        135531: 08/10/06: shahram: Re: CRC calculation of Virtex 4 bitstream
    124479: 07/09/24: <lembke.stefan@googlemail.com>: Re: CRC calculation of Virtex 4 bitstream
124466: 07/09/23: James Peters: Any advice on Steve Kilts' "Advanced FPGA Design: Architecture, Implementation,
124467: 07/09/23: vasile: Re: Gated Clock Problems
124468: 07/09/23: Sanka Piyaratna: Xilinx GTP based serial link
124469: 07/09/23: Marlboro: Re: Gated Clock Problems
124470: 07/09/23: Weng Tianxiang: Re: Gated Clock Problems
124474: 07/09/23: Uncle Noah: ANNOUNCE: Embedded hw/sw developer freebies by Nikolaos Kavvadias
124477: 07/09/24: bharat_in: BRAM bytewide write enable problem
124478: 07/09/24: Martin Thompson: [ANN] FPGAOptim - Do you know where your slices are going...?
    124495: 07/09/24: MM: Re: [ANN] FPGAOptim - Do you know where your slices are going...?
        124498: 07/09/25: Martin Thompson: Re: [ANN] FPGAOptim - Do you know where your slices are going...?
    124850: 07/10/08: Martin Thompson: Re: [ANN] FPGAOptim - Do you know where your slices are going...?
        124853: 07/10/08: Martin Thompson: Re: [ANN] FPGAOptim - Do you know where your slices are going...?
124481: 07/09/24: <gilbert1219com@gmail.com>: partial reconfiguration, par error
    124560: 07/09/26: Erik Anderson: Re: partial reconfiguration, par error
124492: 07/09/24: icegray: Automotive Electronic Control
    124499: 07/09/25: Martin Thompson: Re: Automotive Electronic Control
        124500: 07/09/25: Jonathan Bromley: Re: Automotive Electronic Control
            124504: 07/09/25: Martin Thompson: Re: Automotive Electronic Control
    124502: 07/09/25: Jonathan Bromley: Re: Automotive Electronic Control
124501: 07/09/25: sai: DRAM modules - RIMM, SODIMM,UDIMM..etc
    124516: 07/09/25: Joseph Samson: Re: DRAM modules - RIMM, SODIMM,UDIMM..etc
124503: 07/09/25: <schirinboy@yahoo.de>: Variable Phase Shifting for VirtexII DCM
124506: 07/09/25: <cs_posting@hotmail.com>: Never buy Altera!!!!
    124507: 07/09/25: Mike Treseler: Re: Never buy Altera!!!!
    124508: 07/09/25: <cs_posting@hotmail.com>: Re: Never buy Altera!!!!
    124509: 07/09/25: comp.arch.fpga: Re: Never buy Altera!!!!
    124510: 07/09/25: Karl: Re: Never buy Altera!!!!
    124513: 07/09/25: <jinkeles@hotmail.com>: Re: Never buy Altera!!!!
        124520: 07/09/25: Mike Treseler: Re: Never buy Altera!!!!
        124524: 07/09/25: Nico Coesel: Re: Never buy Altera!!!!
        124528: 07/09/26: Symon: Re: Never buy Altera!!!!
            124531: 07/09/26: Mark McDougall: Re: Never buy Altera!!!!
                124533: 07/09/26: John_H: Re: Never buy Altera!!!!
                    124538: 07/09/26: Hal Murray: Re: Never buy Altera!!!!
                    124596: 07/09/27: Jon Elson: Re: Never buy Altera!!!!
                    124604: 07/09/28: Mark McDougall: Re: Never buy Altera!!!!
                124543: 07/09/26: Symon: Re: Never buy Altera!!!!
                    124544: 07/09/26: Jim Granville: Re: Never buy Altera!!!!
                    124603: 07/09/28: Mark McDougall: Re: Never buy Altera!!!!
            124532: 07/09/25: Hal Murray: Re: Never buy Altera!!!!
                124542: 07/09/26: Symon: Re: Never buy Altera!!!!
                    124632: 07/09/28: Hal Murray: Re: Never buy Altera!!!!
            124556: 07/09/26: Nico Coesel: Re: Never buy Altera!!!!
        124541: 07/09/26: Uwe Bonnes: Re: Never buy Altera!!!!
        124552: 07/09/26: Mike Lewis: Re: Never buy Altera!!!!
        124598: 07/09/27: Jon Elson: Re: Never buy Altera!!!!
            124602: 07/09/27: Jeff Cunningham: Re: Never buy Altera!!!!
                124605: 07/09/28: Matthew Hicks: Re: Never buy Altera!!!!
                    124614: 07/09/28: Martin Thompson: Re: Never buy Altera!!!!
                    124637: 07/09/28: Jon Elson: Re: Never buy Altera!!!!
                124606: 07/09/28: Tommy Thorn: Re: Never buy Altera!!!!
                124621: 07/09/28: Ray Andraka: Re: Never buy Altera!!!!
                124636: 07/09/28: Jon Elson: Re: Never buy Altera!!!!
                    124641: 07/09/28: Matthew Hicks: Re: Never buy Altera!!!!
                    124660: 07/09/29: Gabor: Re: Never buy Altera!!!!
    124525: 07/09/25: <cs_posting@hotmail.com>: Re: Never buy Altera!!!!
    124527: 07/09/25: Andy Peters: Re: Never buy Altera!!!!
    124558: 07/09/26: fpgabuilder: Re: Never buy Altera!!!!
    124563: 07/09/26: Andy Peters: Re: Never buy Altera!!!!
    124565: 07/09/26: <cs_posting@hotmail.com>: Re: Never buy Altera!!!!
124512: 07/09/25: Wei Wang: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
    124518: 07/09/25: Weng Tianxiang: Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
    124521: 07/09/25: Gabor: Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
    124526: 07/09/25: Wei Wang: Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
    124545: 07/09/26: Gabor: Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
    124550: 07/09/26: Wei Wang: Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
    124559: 07/09/26: Wei Wang: Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
    124588: 07/09/27: Gabor: Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
    124615: 07/09/28: Wei Wang: Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
124515: 07/09/25: <drop669@gmail.com>: Own soft-processor
    124517: 07/09/25: Uncle Noah: Re: Own soft-processor
    124519: 07/09/25: Jon Beniston: Re: Own soft-processor
    124522: 07/09/25: Hal Murray: Re: Own soft-processor
    124571: 07/09/26: Eric Smith: Re: Own soft-processor
    124658: 07/09/29: Jarek Rozanski: Re: Own soft-processor
    124661: 07/09/29: Nicolas Matringe: Re: Own soft-processor
        125320: 07/10/21: Hal Murray: Re: Own soft-processor
    124669: 07/09/29: emu: Re: Own soft-processor
    124682: 07/09/30: sdf: Re: Own soft-processor
    124683: 07/09/30: Tommy Thorn: Re: Own soft-processor
    124684: 07/09/30: Andrew Burnside: Re: Own soft-processor
    124697: 07/10/01: Tommy Thorn: Re: Own soft-processor
    124699: 07/10/01: Andrew Burnside: Re: Own soft-processor
    125330: 07/10/22: <cs_posting@hotmail.com>: Re: Own soft-processor
124523: 07/09/25: <dudesinmexico@gmail.com>: Logic minimization software with LUT6 support?
    124536: 07/09/26: Marc Randolph: Re: Logic minimization software with LUT6 support?
        124568: 07/09/26: Hal Murray: Re: Logic minimization software with LUT6 support?
        124569: 07/09/26: Ray Andraka: Re: Logic minimization software with LUT6 support?
            124573: 07/09/26: Ray Andraka: Re: Logic minimization software with LUT6 support?
            124574: 07/09/26: John_H: Re: Logic minimization software with LUT6 support?
                124575: 07/09/26: Ray Andraka: Re: Logic minimization software with LUT6 support?
    124553: 07/09/26: comp.arch.fpga: Re: Logic minimization software with LUT6 support?
    124567: 07/09/26: <dudesinmexico@gmail.com>: Re: Logic minimization software with LUT6 support?
    124572: 07/09/26: <dudesinmexico@gmail.com>: Re: Logic minimization software with LUT6 support?
    124587: 07/09/27: comp.arch.fpga: Re: Logic minimization software with LUT6 support?
124534: 07/09/26: NickNitro: Very basic clock questions.
    124535: 07/09/26: David Spencer: Re: Very basic clock questions.
    124537: 07/09/26: NickNitro: Re: Very basic clock questions.
    124539: 07/09/26: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Very basic clock questions.
    124555: 07/09/26: fpgabuilder: Re: Very basic clock questions.
124546: 07/09/26: heinerlitz@googlemail.com: XST corrupts my state machine. Only disabling FSM encoding helps
    124547: 07/09/26: Joseph Samson: Re: XST corrupts my state machine. Only disabling FSM encoding helps
    124548: 07/09/26: heinerlitz@googlemail.com: Re: XST corrupts my state machine. Only disabling FSM encoding helps
    124549: 07/09/26: John McCaskill: Re: XST corrupts my state machine. Only disabling FSM encoding helps
    124676: 07/09/29: Helpme: Re: XST corrupts my state machine. Only disabling FSM encoding helps
124554: 07/09/26: fpgabuilder: Altera PowerPlay Early Power Estimator Spreadsheet and MXCOMCT2.OCX
    124825: 07/10/05: <vaughnbetz@gmail.com>: Re: Altera PowerPlay Early Power Estimator Spreadsheet and MXCOMCT2.OCX
124557: 07/09/26: Uncle Noah: YARDstick custom processor design tool homepage updates
124561: 07/09/26: Kevin Neilson: Inferring wide adders comprising multiple DSP48s
    124564: 07/09/26: John_H: Re: Inferring wide adders comprising multiple DSP48s
    124566: 07/09/26: Ray Andraka: Re: Inferring wide adders comprising multiple DSP48s
124562: 07/09/26: jon: Stratix GX
    124592: 07/09/27: jon: Re: Stratix GX
124576: 07/09/26: Peter Alfke: Re: Gated Clock Problems
124577: 07/09/27: NickNitro: Basic questions about the Nios II.
    124578: 07/09/26: Uncle Noah: Re: Basic questions about the Nios II.
        124600: 07/09/27: Hal Murray: Re: Basic questions about the Nios II.
    124579: 07/09/27: NickNitro: Re: Basic questions about the Nios II.
    124580: 07/09/27: NickNitro: Re: Basic questions about the Nios II.
    124582: 07/09/26: Uncle Noah: Re: Basic questions about the Nios II.
    124583: 07/09/26: Uncle Noah: Re: Basic questions about the Nios II.
    124584: 07/09/27: NickNitro: Re: Basic questions about the Nios II.
    124585: 07/09/26: Uncle Noah: Re: Basic questions about the Nios II.
    124586: 07/09/27: NickNitro: Re: Basic questions about the Nios II.
124581: 07/09/26: Thomas Stanka: Bug in Synplify?
    124589: 07/09/27: John_H: Re: Bug in Synplify?
    124595: 07/09/27: Andy: Re: Bug in Synplify?
        124622: 07/09/28: Ray Andraka: Re: Bug in Synplify?
    124607: 07/09/27: Thomas Stanka: Re: Bug in Synplify?
    124608: 07/09/27: Thomas Stanka: Re: Bug in Synplify?
    124609: 07/09/28: Tommy Thorn: Re: Bug in Synplify?
    124623: 07/09/28: Andy: Re: Bug in Synplify?
    124639: 07/09/28: Andy: Re: Bug in Synplify?
    124742: 07/10/02: Thomas Stanka: Re: Bug in Synplify?
    124743: 07/10/02: Thomas Stanka: Re: Bug in Synplify?
    124794: 07/10/04: Andy: Re: Bug in Synplify?
124590: 07/09/27: Sanka Piyaratna: FPDP to PCIe
    124627: 07/09/28: vasile: Re: FPDP to PCIe
124591: 07/09/27: Pablo: UCF Constraints: drive and slew
    124593: 07/09/27: Gabor: Re: UCF Constraints: drive and slew
    124612: 07/09/28: Pablo: Re: UCF Constraints: drive and slew
124594: 07/09/27: <emrith@gmail.com>: Xilinx upgrade
    124599: 07/09/27: motty: Re: Xilinx upgrade
    124601: 07/09/27: Jeff Cunningham: Re: Xilinx upgrade
    124610: 07/09/28: svenand: Re: Xilinx upgrade
    124611: 07/09/28: pemiliv: Re: Xilinx upgrade
124597: 07/09/27: motty: PowerPC Simulation
    124692: 07/09/30: Ken Ryan: Re: PowerPC Simulation
    124698: 07/09/30: motty: Re: PowerPC Simulation
124616: 07/09/28: Antti: FPGA NTSC signal with 2 resistors and PWM
    124617: 07/09/28: Gabor: Re: FPGA NTSC signal with 2 resistors and PWM
        124619: 07/09/28: John_H: Re: FPGA NTSC signal with 2 resistors and PWM
    124618: 07/09/28: Antti: Re: FPGA NTSC signal with 2 resistors and PWM
    124620: 07/09/28: Antti: Re: FPGA NTSC signal with 2 resistors and PWM
    124624: 07/09/28: Kevin Neilson: Re: FPGA NTSC signal with 2 resistors and PWM
        124720: 07/10/01: Mike Treseler: Re: FPGA NTSC signal with 2 resistors and PWM
    124625: 07/09/28: Antti: Re: FPGA NTSC signal with 2 resistors and PWM
    124644: 07/09/28: Jecel: Re: FPGA NTSC signal with 2 resistors and PWM
    124653: 07/09/29: Antti: Re: FPGA NTSC signal with 2 resistors and PWM
    124677: 07/09/29: Jecel: Re: FPGA NTSC signal with 2 resistors and PWM
    124708: 07/10/01: Jon Elson: Re: FPGA NTSC signal with 2 resistors and PWM
        124741: 07/10/02: glen herrmannsfeldt: Re: FPGA NTSC signal with 2 resistors and PWM
    124716: 07/10/01: Jecel: Re: FPGA NTSC signal with 2 resistors and PWM
    124722: 07/10/01: Jecel: Re: FPGA NTSC signal with 2 resistors and PWM
    124751: 07/10/03: Nial Stewart: Re: FPGA NTSC signal with 2 resistors and PWM
        124781: 07/10/04: glen herrmannsfeldt: Re: FPGA NTSC signal with 2 resistors and PWM
    124753: 07/10/03: Antti: Re: FPGA NTSC signal with 2 resistors and PWM
    124772: 07/10/03: Jecel: Re: FPGA NTSC signal with 2 resistors and PWM
124626: 07/09/28: vasile: LVDS clock management
    124628: 07/09/28: BobW: Re: LVDS clock management
124629: 07/09/28: Antti: 2 leg crystal on FPGA: Lattice vs Xilinx
    124635: 07/09/28: austin: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
        124650: 07/09/29: Hal Murray: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
            124673: 07/09/29: KJ: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
        124655: 07/09/29: Nico Coesel: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
            124671: 07/09/29: John_H: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
                124675: 07/09/29: Nico Coesel: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
            124707: 07/10/01: Jon Elson: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
        124678: 07/09/29: Ray Andraka: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
        124679: 07/09/29: Ray Andraka: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
            124819: 07/10/05: <lb.edc@telenet.be>: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
        124731: 07/10/02: Jim Granville: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
        124732: 07/10/02: Jim Granville: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
        124829: 07/10/06: Jim Granville: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124643: 07/09/28: John Adair: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124645: 07/09/28: Peter Alfke: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124647: 07/09/29: vasile: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
        124648: 07/09/29: Hal Murray: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
            124656: 07/09/29: Nico Coesel: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124649: 07/09/29: Antti: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124651: 07/09/29: Antti: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124652: 07/09/29: Antti: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124665: 07/09/29: johnp: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124666: 07/09/29: John Adair: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124674: 07/09/29: Antti: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124680: 07/09/30: Antti: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124706: 07/10/01: Jon Elson: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124712: 07/10/01: Antti: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124630: 07/09/28: Dan K: Programming the ARM7 used to download our Xilinx FPGA
    124631: 07/09/28: Antti: Re: Programming the ARM7 used to download our Xilinx FPGA
    124633: 07/09/28: Sean Durkin: Re: Programming the ARM7 used to download our Xilinx FPGA
    124634: 07/09/28: Hal Murray: Re: Programming the ARM7 used to download our Xilinx FPGA
    124729: 07/10/02: Amontec, Larry: Re: Programming the ARM7 used to download our Xilinx FPGA
124640: 07/09/28: <theanonymous83@gmail.com>: [offtopic] job inquiry; entry/trainee FPGA/ASIC designer
    124642: 07/09/28: John Adair: Re: job inquiry; entry/trainee FPGA/ASIC designer
    124662: 07/09/29: Symon: Re: [offtopic] job inquiry; entry/trainee FPGA/ASIC designer
        124693: 07/09/30: Symon: Re: job inquiry; entry/trainee FPGA/ASIC designer
    124664: 07/09/29: <theanonymous83@gmail.com>: Re: job inquiry; entry/trainee FPGA/ASIC designer
    124668: 07/09/29: John McCaskill: Re: job inquiry; entry/trainee FPGA/ASIC designer
124654: 07/09/29: <johnzulu>: XUPV2P from digilentinc
    124659: 07/09/29: stephen.craven@gmail.com: Re: XUPV2P from digilentinc
        124663: 07/09/29: <johnzulu>: Re: XUPV2P from digilentinc
            124670: 07/09/29: John_H: Re: XUPV2P from digilentinc
        124686: 07/09/30: Brian Drummond: Re: XUPV2P from digilentinc
            124688: 07/09/30: <johnzulu>: Re: XUPV2P from digilentinc
                124821: 07/10/05: John_H: Re: XUPV2P from digilentinc
                    124840: 07/10/06: <johnzulu>: Re: XUPV2P from digilentinc
                124823: 07/10/06: <johnzulu>: Re: XUPV2P from digilentinc
    124667: 07/09/29: emu: Re: XUPV2P from digilentinc
    124690: 07/09/30: vasile: Re: XUPV2P from digilentinc
    124818: 07/10/05: spartan3wiz: Re: XUPV2P from digilentinc
    124828: 07/10/05: emeb: Re: XUPV2P from digilentinc
    124875: 07/10/09: <cs_posting@hotmail.com>: Re: XUPV2P from digilentinc
124681: 07/09/30: Antti: www.fpga-games.com website died?
    124709: 07/10/01: Eric Crabill: Re: www.fpga-games.com website died?
        124717: 07/10/02: Symon: Re: www.fpga-games.com website died?
124685: 07/09/30: Walters: Walking 1's
    124687: 07/09/30: Jonathan Bromley: Re: Walking 1's
    124689: 07/09/30: <MikeShepherd564@btinternet.com>: Re: Walking 1's
    124691: 07/09/30: PeteS: Re: Walking 1's
124694: 07/09/30: To: Kshitij Arora <: Planning to switch to FPGA domain, any advice would be highly appreciated
    124719: 07/10/02: Narsi: Re: Planning to switch to FPGA domain, any advice would be highly appreciated
124696: 07/09/30: Tim (one of many): Synplicity and the Xilinx MAP Memory Monster
    124701: 07/10/01: Brian Drummond: Re: Synplicity and the Xilinx MAP Memory Monster
    124702: 07/10/01: John_H: Re: Synplicity and the Xilinx MAP Memory Monster


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