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Messages from 125425

Article: 125425
Subject: Re: Nios II, ThreadX, NetX
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Thu, 25 Oct 2007 13:14:27 +0100
Links: << >>  << T >>  << A >>
> Hi,
> I'm looking for a very compact TCP/IP stack for the Nios II, and the ThreadX/NetX combo seems to 
> be, at least on paper, the smallest.  Anyone using this combo?  How small are you able to build 
> it, and with what services?  How is their support?  Any issues integrating it with the Nios IDE?
> Thanks,
> Paul


Paul,

I can't help, have you tried...

http://www.niosforum.com/

?



Nial 



Article: 125426
Subject: Re: LEDs, buttons and LCD
From: Vagant <vladimir.v.korostelev@rambler.ru>
Date: Thu, 25 Oct 2007 05:17:23 -0700
Links: << >>  << T >>  << A >>
On Oct 24, 9:29 pm, "Eric Crabill" <eric.crab...@xilinx.com> wrote:
> If you have the Spartan-3E Starter Kit, and are interested in using Verilog
> as your hardware description language, there are a few tutorials and small
> projects you can try at:
>
> http://www.engr.sjsu.edu/crabill/
>
> Eric
>
> "DialTone" <DialT...@faked.com> wrote in message
>
> news:Xns99D3D2E5CC88Edialtonentlworld@62.253.170.163...
>
>
>
>
>
> >> Hi,
> >> thanks a lot for reply. I also got idea that it's a great board,
> >> mainly from others. I have just started and have not find any detailed
> >> examples how to move forward learning this.
>
> >> There are many materials on Xilinx's Web Site but
> >> all these are mainly about advanced
> >> programming and there is almost nothing for beginners.
>
> > Hi,
>
> > I'm very new to VHDL/FPGA myself and also have a S3E (the smaller
> > XC4S500) board. Bought from digilent, it came with no software or manuals
> > (the manuals are all available from xilinx web site though, of course).
>
> > Not sure if you mean the reference designs at
> >http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm
>
> > They're certainly quite detailed and complex - I really only looked at
> > the Rotary Encoder example as this gave quite a simple VHDL design to
> > experiment with, plus it showed how to read the Rotary thingamajig.
>
> > What I _did_ find really useful to look at (besides the web-based
> > tutorials and suchlike that you can find with google), was the FPGA
> > Arcade projecthttp://www.fpgaarcade.com. Both PACMAN and Space Invaders
> > have been ported to the S3E board, and of course full source is provided.
> > I also looked at John Kent's excellent FPGA page at
> >http://members.optushome.com.au/jekent/FPGA.htm- In particular the
> > System09 project interested me: although there's no version specifically
> > for the S3E board, there is an S3 version which (although not close
> > enough to use unmodified) is an interesting insight into VHDL for me.
>
> > I guess it all depends what exactly you want to do with the FPGA, but
> > perhaps those sites might be useful?
>
> > Good Luck
> > DT- Hide quoted text -
>
> - Show quoted text -

Thanks for this. I am not using Verilog really so perhaps cannot enjoy
much from the site.
I just wonder, whether you might consider to give VHDL expamples too,
in parallel to Verilog code.


Article: 125427
Subject: Re: xilinx spi flash programming
From: colin <colin_toogood@yahoo.com>
Date: Thu, 25 Oct 2007 05:57:04 -0700
Links: << >>  << T >>  << A >>
On 25 Oct, 12:20, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid> wrote:
> In comp.arch.fpga,
>
>
>
>
>
> Antti <Antti.Luk...@googlemail.com> wrote:
> > On 25 Okt., 11:33, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid>
> > wrote:
> >> In comp.arch.fpga,
>
> >> colin <colin_toog...@yahoo.com> wrote:
> >> > I'm about to place an SPI flash for spartan 3e but I'm a bit
> >> > disapointed in having to place another header to program it via
> >> > impact.
>
> >> What will you use the JTAG for? If it's only for testing/debugging
> >> your prototype, you can consider placing only a few solder pads for
> >> the JTAG connection. The little extra hassle is not a problem for
> >> debugging and production will only use the SPI connector.
>
> > the OP is right being disappointed! really he has.
>
> > i you have JTAG connector or testpads, but can not not use indirect
> > jtag configuration for the SPI programming then its really PITA to add
> > separate SPI header, just because impact doesnt handle indirect SPI
> > for S3e then same way it handles it for S3A
>
> Oh yes, I was disappointed as well. And I didn't even know things are
> different with the S3A!
>
> But I have to get on with my schematics and layout, so I decided to add
> some pads for the JTAG and a header for the SPI (hope I can find the
> space for it :-) ).
>
> --
> Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)- Hide quoted text -
>
> - Show quoted text -

The board has been designed for JTAG testing by a third party. They
will use Scanworks (Asset intertech) for boundary scan and to program
the flash and we can use the same header for JTAG development. You've
worried me about using Impact for SPI programming as I assumed the S3e
will be dormant, will read the datasheet again later.

Colin


Article: 125428
Subject: Re: xilinx spi flash programming
From: Antti <Antti.Lukats@googlemail.com>
Date: Thu, 25 Oct 2007 13:06:49 -0000
Links: << >>  << T >>  << A >>
On 25 Okt., 14:57, colin <colin_toog...@yahoo.com> wrote:
> On 25 Oct, 12:20, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid> wrote:
>
>
>
>
>
> > In comp.arch.fpga,
>
> > Antti <Antti.Luk...@googlemail.com> wrote:
> > > On 25 Okt., 11:33, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid>
> > > wrote:
> > >> In comp.arch.fpga,
>
> > >> colin <colin_toog...@yahoo.com> wrote:
> > >> > I'm about to place an SPI flash for spartan 3e but I'm a bit
> > >> > disapointed in having to place another header to program it via
> > >> > impact.
>
> > >> What will you use the JTAG for? If it's only for testing/debugging
> > >> your prototype, you can consider placing only a few solder pads for
> > >> the JTAG connection. The little extra hassle is not a problem for
> > >> debugging and production will only use the SPI connector.
>
> > > the OP is right being disappointed! really he has.
>
> > > i you have JTAG connector or testpads, but can not not use indirect
> > > jtag configuration for the SPI programming then its really PITA to add
> > > separate SPI header, just because impact doesnt handle indirect SPI
> > > for S3e then same way it handles it for S3A
>
> > Oh yes, I was disappointed as well. And I didn't even know things are
> > different with the S3A!
>
> > But I have to get on with my schematics and layout, so I decided to add
> > some pads for the JTAG and a header for the SPI (hope I can find the
> > space for it :-) ).
>
> > --
> > Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)- Hide quoted text -
>
> > - Show quoted text -
>
> The board has been designed for JTAG testing by a third party. They
> will use Scanworks (Asset intertech) for boundary scan and to program
> the flash and we can use the same header for JTAG development. You've
> worried me about using Impact for SPI programming as I assumed the S3e
> will be dormant, will read the datasheet again later.
>
> Colin- Zitierten Text ausblenden -
>
> - Zitierten Text anzeigen -

for SPI programming on S3E you need "JTAG_SPI_GATEWAY" from Xilant ;)
or make your own...

the SPI programming on S3A is done by special bitstreams: .COR files
as the protocol is secret so a 3rd party JTAG company can also not use
xilinx solution for S3A
(unless they use impact in background)

Antti






Article: 125429
Subject: Re: is Quartus 7.1 really that S*** !?
From: Antti <Antti.Lukats@googlemail.com>
Date: Thu, 25 Oct 2007 13:08:42 -0000
Links: << >>  << T >>  << A >>
On 25 Okt., 12:54, Antti <Antti.Luk...@googlemail.com> wrote:
> Hi
>
> so far I hear that "Altera tools are getting better" - now I wonder
> how long should one wait til they become useable?
>
> Q II 7.1, very small design for smallex MAX2
>
> Quartus will self-terminate every few hours, the PC has 2GB RAM, isnt
> that enought for the ultimate smallest MAX2 !?
>
> also the UFM block simulation doesnt want to work at all, well maybe i
> am doing something wrong yet, but I havent seen the UFM content ever
> been shifter out in the simulation :(
>
> Antti

ok, the situation with quartus isnt that bad.
well it did self-terminated itself again 5 times in the last 2 hours
but at least the UFM simulation works ok, was possible only
caused by the mis-interpreted by quartus HEX file. with MIF
the UFM sims do work ok

Antti










Article: 125430
Subject: Signetics N82F101F
From: "tagough@gmail.com" <tagough@gmail.com>
Date: Thu, 25 Oct 2007 06:21:53 -0700
Links: << >>  << T >>  << A >>
Hello all

Does anyone have a Signetics data sheet / data book with this part?

Thank you


Article: 125431
Subject: Re: difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES
From: michel.talon@gmail.com
Date: Thu, 25 Oct 2007 13:32:33 -0000
Links: << >>  << T >>  << A >>
Thank you for your answers!

Now I understand ! :-)




On 18 oct, 16:44, austin <aus...@xilinx.com> wrote:
> Eric,
>
> F/A rarely shows us anything useful.  If the part has been fried
> (electrical over-stress) that is easily determined with an ohmmeter.
>
> If the part has a particle defect, or some other process defect, we
> already knew these parts are from the first ever lots of a new process,
> and yes, that happens quite often.  Statistics on defects are kept with
> "defect monitor" vehicles, so we don't care to tear apart one known
> early part and see one defect we already have seen before in the monitors.
>
> As long as the part is on the customer's board, we have a chance at
> determining the problem.  Once removed, determination of root cause
> drops to less than 5% success rate (as most problems are with the user's
> design, followed by their signal integrity, followed by solder problems).
>
> So, yes, we are interested in why production parts fail, but no, we are
> not interested in performing costly F/A on an ES part.
>
> We might actually request return of an ES part because we feel we may
> learn something (like develop a better production test), but that is
> pretty rare.
>
> Good question.  Thanks for asking it so I can educate folks,
>
> Austin
>
> Eric Smith wrote:
> > austin wrote:
> >> As an example, ES parts are never accepted for a "RMA" (returned
> >> merchandise authorization)
>
> > Makes perfect sense.
>
> >> or for F/A (failure analysis).
>
> > You guys don't want to determine why ES parts fail?  That seems
> > really strange.



Article: 125432
Subject: Re: Changing refresh rate for DRAM while in operation?
From: Andy <jonesandy@comcast.net>
Date: Thu, 25 Oct 2007 06:46:08 -0700
Links: << >>  << T >>  << A >>
On Oct 24, 1:40 pm, Dave Pollum <vze24...@verizon.net> wrote:
> On Oct 24, 2:15 am, Antti <Antti.Luk...@googlemail.com> wrote:
>
>
>
> > On 24 Okt., 07:50, Peter Alfke <al...@sbcglobal.net> wrote:
>
> > > On Oct 23, 5:27 pm, "David Spencer" <davidmspen...@verizon.net> wrote:
>
> > > > <MikeShepherd...@btinternet.com> wrote in message
>
> > > >news:1evsh3ds7i44iqhrsc4kldthlo2vb0tul2@4ax.com...
>
> > > > > Although it's not expressed in DRAM specs and you wouldn't want to
> > > > > rely on it, the effect of reducing refresh rate is to increase the
> > > > > access time.  I'm not up-to-date with DRAM technology, but my
> > > > > experience with devices 30 years ago was that you could turn off
> > > > > refresh (and all other access) for 10s or more without losing the
> > > > > contents, provided you weren't pushing the device to its access time
> > > > > limits.
>
> > > > > So, it's not impossible that reducing refresh rate would have a use
> > > > > (albeit outside the published device spec).  But, as you suggest, it
> > > > > would help if he would just tell us what he's trying to do.
>
> > > > > Mike
>
> > > > Although that may well be the case for asynchronous DRAMs (because the
> > > > reduced charge in the memory cell capacitor would mean that the sense
> > > > amplifier took longer to register the state), this would not be the case for
> > > > SDRAM since this registers the outputs a fixed number of clocks after the
> > > > access starts. If the underlying access time increased by too much then the
> > > > data would just be wrong.
>
> > > For certain addressing patterns, the refresh can be eliminated
> > > alltogether, when the addressing sequence is such that all (used)
> > > memory cells are naturally being read, and thus refreshed, within the
> > > required time.
> > > Peter Alfke- Zitierten Text ausblenden -
>
> > > - Zitierten Text anzeigen -
>
> > Sinclair ZX?
> > at least some old Z80 homecomputers used refresh by video scan
>
> > Antti
>
> If I recall, the Apple II also refreshed its RAM this way, too.
> -Dave Pollum

The TRS-80 Color Computer (Moto 6809 based) refreshed during the
vertical retrace. But there was a bit in the system controller that
could be set to turn it and video access off, while doubling the
processor clock. As long as your Basic code was running, and not
waiting on a keyboard input or other event, the ROM interpreter's RAM
accesses managed to keep the RAM (at least the part of it being used)
refreshed. But if/when the code hit an error (and thus waited for user
response) you could watch the screen go from random pixels to all
white. Once the coding errors were eliminated, it was a reliable way
to double the processing speed when you did not need video.

Ah the good old days... but, I digress.

Andy


Article: 125433
Subject: Re: Changing refresh rate for DRAM while in operation?
From: CBFalconer <cbfalconer@yahoo.com>
Date: Thu, 25 Oct 2007 09:54:14 -0400
Links: << >>  << T >>  << A >>
MitchAlsup wrote:
> CBFalconer <cbfalco...@yahoo.com> wrote:
>
>> Since the only purpose of the refresh circuitry is to avoid the
>> memory dropping bits, it should already be running at the slowest
>> possible rate, and speed reduction will be harmful, while speed
>> increase will do no good.  So this is not a good idea.
> 
> I disagree (softly), having designed several memory controllers,
> I always found it easier to just insert a READ DATA command into
> the DRAM when a refresh was needed, rather than insert a refresh
> command. The timing differences between refresh and a loosly
> coupled string of READS is such that one can refresh ahead with
> READs easier and then be in a position to absorb a longer string
> of demand requests by not using the REFRESH commands. Thus while
> running at the slowest overall rate, one can bunch and distribute
> the refresh mechanics to better interleave same with the demand
> memory requests and gain something.
> 
> But I will state the overall performance differences are a
> fraction of the refresh overhead anyways.
> 
>> What are you trying to do?
> 
> That is the real question.

Since the OP seems to have disappeared to wherever OPs go, I
suspect we will never find out.

-- 
 Chuck F (cbfalconer at maineline dot net)
   Available for consulting/temporary embedded and systems.
   <http://cbfalconer.home.att.net>



-- 
Posted via a free Usenet account from http://www.teranews.com


Article: 125434
Subject: Re: MPMC2 NPI Help!
From: motty <mottoblatto@yahoo.com>
Date: Thu, 25 Oct 2007 06:58:07 -0700
Links: << >>  << T >>  << A >>
OK, so the same problem arises from answers here:

Sovan, you are saying that the address request (and subsequent address
ack) goes BEFORE the data push into the FIFO?  Or is the address
request in that statement the one from a previous transfer?

Guru says that the address request should go AFTER pushing data into
the FIFO (or at least this is the safest way).  This is currently what
I am doing, but still having problems.  This doesn't seem like a real
difficult task, but it just isn't working like I expect.


Article: 125435
Subject: Re: MGT
From: "MM" <mbmsv@yahoo.com>
Date: Thu, 25 Oct 2007 10:26:43 -0400
Links: << >>  << T >>  << A >>
<shakith.fernando@gmail.com> wrote in message 
news:1193295873.796190.95790@t8g2000prg.googlegroups.com...
>
> Regarding initialization, was reading that chapter...One question I
> have is, does the 1st MGT(sender for example) need to be linked to 2nd
> MGT(receiver for example) to be initialized. There must be some sort of 
> handshaking  mechanism
> there..

Yes, the transmitter has to be connected to the receiver with the main link 
AND you either have to add another connection (back channel) or implement 
some other tricks, which I personally couldn't get to work in my design.

The simplest implementation of the back channel would be to directly connect 
the following 4 pairs of signals:
TX_ALIGNED - RX_ALIGNED
TX_BONDED - RX_BONDED
TX_VERIFY - RX_VERIFY
TX_RESET - RX_RESET

And then you just watch  the LANE_UP and CHANNEL_UP signals to go up a while 
after simulation starts...


/Mikhail



Article: 125436
Subject: Re: MGT
From: "MM" <mbmsv@yahoo.com>
Date: Thu, 25 Oct 2007 10:29:45 -0400
Links: << >>  << T >>  << A >>
A small addition:

The TX_BONDED-RX_BONDED connection is only required when channel bonding is 
used.

/Mikhail



Article: 125437
Subject: Re: MPMC2 NPI Help!
From: sovan <sovan.kundu@gmail.com>
Date: Thu, 25 Oct 2007 14:30:29 -0000
Links: << >>  << T >>  << A >>
I am using NPI for Double-word and Eight-Word bursts. For Double-word
writes I am requesting address before I push the data. For Eight-Word
writes I am pushing data before address request.

In my case I have one NPI port connected to one RTL block doing Double-
word read/writes and another NPI port is connected to a different RTL
block which does Eight word read/writes. I had to write slightly
different logic for the difference in behavior for different burst
size.


Article: 125438
Subject: compile EDIF(generated by Celoxica DK4) using Quartus II
From: lyfieryflame@gmail.com
Date: Thu, 25 Oct 2007 07:47:13 -0700
Links: << >>  << T >>  << A >>
Hi all,

I got an error when I compile the EDIF file generated by Celoxica DK4.
The code is written in Handel-C. I add the EDIF file and the TCL file
generated by DK4 to the project, the error is following:
Error: Node "B57_testforQuartusII_hcc_8_DTYPE0IR" is missing source

the TCL file is following:

##############################################################################
#
# Assignment and Constraints Quartus TCL script for design N:\myhome
\my stuff\handel-c\test\testforQuartusII\EDIF\testforQuartusII.edf
#
# Generated by Celoxica Hardware Compiler (Version 3.5.3555.63181)
# Timestamp 2007 4 17 15 54 52
#
##############################################################################


# Set family and part
set_global_assignment -name FAMILY "STRATIX II"
set_global_assignment -name DEVICE "ep2s15f484c5"

# Set compilation options
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE Off
set_global_assignment -name AUTO_PACKED_REGISTERS Normal


############################### IO assignments
###############################

set_instance_assignment -name IO_STANDARD "LVTTL" -to
PADIN_testforQuartusII_hcc_ClockInPin
set_instance_assignment -name IO_STANDARD "LVTTL" -to
PADIN_testforQuartusII_hcc_Read_read_4
set_instance_assignment -name IO_STANDARD "LVTTL" -to
PADIN_testforQuartusII_hcc_Read_read_3
set_instance_assignment -name IO_STANDARD "LVTTL" -to
PADIN_testforQuartusII_hcc_Read_read_2
set_instance_assignment -name IO_STANDARD "LVTTL" -to
PADIN_testforQuartusII_hcc_Read_read_1
set_instance_assignment -name IO_STANDARD "LVTTL" -to
PADIN_testforQuartusII_hcc_Read_read_0
set_instance_assignment -name IO_STANDARD "LVTTL" -to
PADOUT_testforQuartusII_hcc_Write_write_4
set_instance_assignment -name IO_STANDARD "LVTTL" -to
PADOUT_testforQuartusII_hcc_Write_write_3
set_instance_assignment -name IO_STANDARD "LVTTL" -to
PADOUT_testforQuartusII_hcc_Write_write_2
set_instance_assignment -name IO_STANDARD "LVTTL" -to
PADOUT_testforQuartusII_hcc_Write_write_1
set_instance_assignment -name IO_STANDARD "LVTTL" -to
PADOUT_testforQuartusII_hcc_Write_write_0


############################# Timing requirements
############################

set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to
B48_testforQuartusII_hcc_8_DTYPE0IR
set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to
B49_testforQuartusII_hcc_8_DTYPE0IR
set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to
B50_testforQuartusII_hcc_8_DTYPE0IR
set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to
B51_testforQuartusII_hcc_8_DTYPE0IR
set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to
B52_testforQuartusII_hcc_8_DTYPE0IR
set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to
B53_testforQuartusII_hcc_8_DTYPE0IR
set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to
B54_testforQuartusII_hcc_8_DTYPE0IR
set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to
B55_testforQuartusII_hcc_8_DTYPE0IR
set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to
B56_testforQuartusII_hcc_8_DTYPE0IR
set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to
B57_testforQuartusII_hcc_8_DTYPE0IR


The EDIF file generated by DK4 is working fine with Xillinx ISE. Is
there any special requirement for compiling EDIF using QuartusII?

Many Thanks,
Ying


Article: 125439
Subject: Re: HELP, how to time constraint part of a design?
From: llombard@gmail.com
Date: Thu, 25 Oct 2007 08:26:07 -0700
Links: << >>  << T >>  << A >>
On 10 oct, 21:21, Duane Clark <junkm...@junkmail.com> wrote:
> DoVHDL wrote:
> > I'm using Xilinx ISE WebPack for my design. I have 4 ADC interface entities
> > that operaates on a 80MHz clk that I'm creating from an external 20MHz clock
> > with a DCM. The calculation part (having a MAC-operation) must run on a
> > 40MHz clock (divided from the 80MHz clock).
>
> Are you going to have a separate clock domain clocked at 40MHz? Then you
> put a 25nS period constraint on the entire domain, not an entity. The
> same kind of constraint as on your 80MHz clock. But how are you handling
> getting data across the domain boundaries? That can be tricky.
>
> Or are you going to clock everything at 80MHz, but have an enable in
> your "calculation part" that toggles, effectively operating it at 40MHz?
> This would be a better idea. You would apply a multicycle constraint,
> but that also can be a tricky thing to get right.
>
> But the best thing to do would be to figure out why your MAC cannot
> operate at 80MHz, and fix it. How you do that depends somewhat on what
> device you are using. Are you using a device with builtin hardware
> multipliers? Then the first step would be to look in the project.syr
> file, and look for the word "pipeline". Look down through that section
> and see if there is something like:
> INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the
> multiplier Mmult__mult0004 by adding 1 register level(s).
> If so, you probably just need to pipeline your multipliers more. Make
> sure to go through the file and find all instances of the word "pipeline".

Hello,
I'm very interested into this topic as I am tryin to implement a
feedback loop (PID controller) with a spartan3e starter kit with
xilinx ISE. The + and * operation is taking almost 40ns which is much
more than 20ns limit for 50MHz operation. So I cut the operation is 3
sub operations so it fits into 19.98ns. I'm not sure it is the right
way to do it but it seems to work. But still I get the message
"INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the
multiplier Mmult_sig_d_00_mult0001 by adding 2 register level(s)." for
the operation "sig_p <= pid_p*erreur/8192;" All variables are integer
signals. Could you advise me on what to do?
Thanks in advance,
Laurent


Article: 125440
Subject: Re: xilinx spi flash programming
From: Stef <stef33d@yahooI-N-V-A-L-I-D.com.invalid>
Date: Thu, 25 Oct 2007 17:26:21 +0200
Links: << >>  << T >>  << A >>
In comp.arch.fpga,
colin <colin_toogood@yahoo.com> wrote:
> On 25 Oct, 12:20, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid> wrote:
>>
>> But I have to get on with my schematics and layout, so I decided to add
>> some pads for the JTAG and a header for the SPI (hope I can find the
>> space for it :-) ).
>
> The board has been designed for JTAG testing by a third party. They
> will use Scanworks (Asset intertech) for boundary scan and to program
> the flash and we can use the same header for JTAG development. You've

In that case, just a few pads for the JTAG is not an option for you.

> worried me about using Impact for SPI programming as I assumed the S3e
> will be dormant, will read the datasheet again later.

From what I understand, you will need to make sure the S3E puts it's
SPI pins in high impedance mode. One way to do that is to pull the
PROG_B input low (That's somewhere in te datasheet, search it for
PROG_B).

But please do read the datasheet again. If you find that the above is
incorrect, please notify me. I've almost finished my schematics and will
start layout soon. On my board, I have connected PROG_B to one of the
pins assigned to GND on the programming connector. That way, the
programming cable will automaticaly pull PROG_B low when inserted.


-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)


Article: 125441
Subject: ISE PACE Question
From: rg.jones@rogers.com
Date: Thu, 25 Oct 2007 08:37:02 -0700
Links: << >>  << T >>  << A >>
HI, I have a Xilinx ISE - PACE editor question-

I am using the schematic editor for now just to get familar with the
tools and the fact I don't understand a HDL yet.

What Iam trying to do is very basic and I am just missing a step or
setting somewhere most likely ...

To reproduce the issue - using ISE 9.2i (or 8.2i)

1) Start ISE project navigator
2) Create a new project called TESTPACE
3) TopLevel source is schematic
4) Family XC95000 CPLD, XC95108, PC84, -7, XST (VHDL/Verilog),
MOdelsim XE Verilog, verilog
5) New Source, Schematic, name - top
6) Finish, next, finish
7) Add logic symbol - decoder d2_4e
8) Add7 i/o markers - Leave default names
9) Save top.sch
10) Run Assign package pins
11) UCF file is created message
12) Rreview I/O pins - all are visible and can be placed - close file
- don't save
13) Add second symbol - flip flop - fd
14) remove the i/o marker from D0 on the decoder and run a wire from
D0 to C
15) Add I/o markers to D and Q
16) Save top.sch
17) Run Assign package pins
18) only D C and Q are available to be placed (Note why is C available
to be placed on a pin when it is now only used internally.

Suggestions welcome.

Thanks

Glenn


Article: 125442
Subject: Re: builing a SPI interface in vhdl
From: Joseph Samson <user@not.my.company>
Date: Thu, 25 Oct 2007 15:49:08 GMT
Links: << >>  << T >>  << A >>
> The problem with SPI is that it comes in a near-infinity of different
> flavours, so IP designed for 1 flavour might be difficult to adapt for a
> different flavour.

But the OP has a flash memory already specified.

> 
> Good luck! (You will need it)

The SPI interface is fairly trivial (once you've mastered the shift 
register); it's a good project for a beginner.


---
Joe Samson
Pixel Velocity


Article: 125443
Subject: Re: MPMC2 NPI Help!
From: motty <mottoblatto@yahoo.com>
Date: Thu, 25 Oct 2007 09:36:05 -0700
Links: << >>  << T >>  << A >>
Thanks Sovan,

I am going to try requesting the address before pushing data to see
what happens!



Article: 125444
Subject: Re: Changing refresh rate for DRAM while in operation?
From: "David Spencer" <davidmspencer@verizon.net>
Date: Thu, 25 Oct 2007 16:59:18 GMT
Links: << >>  << T >>  << A >>

"CBFalconer" <cbfalconer@yahoo.com> wrote in message 
news:4720A006.98AA398B@yahoo.com...

>>> What are you trying to do?
>>
>> That is the real question.
>
> Since the OP seems to have disappeared to wherever OPs go, I
> suspect we will never find out.
>
Don't you just hate it when that happens? Even if the OP now realises that 
what he was trying to do wasn't appropriate or necessary, it would be nice 
if he just explained his original intentions to us.



Article: 125445
Subject: Re: Changing refresh rate for DRAM while in operation?
From: Gabor <gabor@alacron.com>
Date: Thu, 25 Oct 2007 10:25:00 -0700
Links: << >>  << T >>  << A >>
On Oct 25, 12:59 pm, "David Spencer" <davidmspen...@verizon.net>
wrote:
> "CBFalconer" <cbfalco...@yahoo.com> wrote in message
>
> news:4720A006.98AA398B@yahoo.com...
>
> >>> What are you trying to do?
>
> >> That is the real question.
>
> > Since the OP seems to have disappeared to wherever OPs go, I
> > suspect we will never find out.
>
> Don't you just hate it when that happens? Even if the OP now realises that
> what he was trying to do wasn't appropriate or necessary, it would be nice
> if he just explained his original intentions to us.


He's probably sorry about the flame war he unintentionally created
but thinks it would have been nice if one of the 25 replies answered
his original question...


Article: 125446
Subject: Re: ISE PACE Question
From: Gabor <gabor@alacron.com>
Date: Thu, 25 Oct 2007 10:28:04 -0700
Links: << >>  << T >>  << A >>
On Oct 25, 11:37 am, rg.jo...@rogers.com wrote:
> HI, I have a Xilinx ISE - PACE editor question-
>
> I am using the schematic editor for now just to get familar with the
> tools and the fact I don't understand a HDL yet.
>
> What Iam trying to do is very basic and I am just missing a step or
> setting somewhere most likely ...
>
> To reproduce the issue - using ISE 9.2i (or 8.2i)
>
> 1) Start ISE project navigator
> 2) Create a new project called TESTPACE
> 3) TopLevel source is schematic
> 4) Family XC95000 CPLD, XC95108, PC84, -7, XST (VHDL/Verilog),
> MOdelsim XE Verilog, verilog
> 5) New Source, Schematic, name - top
> 6) Finish, next, finish
> 7) Add logic symbol - decoder d2_4e
> 8) Add7 i/o markers - Leave default names
> 9) Save top.sch
> 10) Run Assign package pins
> 11) UCF file is created message
> 12) Rreview I/O pins - all are visible and can be placed - close file
> - don't save
> 13) Add second symbol - flip flop - fd
> 14) remove the i/o marker from D0 on the decoder and run a wire from
> D0 to C
> 15) Add I/o markers to D and Q
> 16) Save top.sch
> 17) Run Assign package pins
> 18) only D C and Q are available to be placed (Note why is C available
> to be placed on a pin when it is now only used internally.
>
> Suggestions welcome.
>
> Thanks
>
> Glenn


One of the known bugs of recent ISE releases requires you to clean up
the project (remove old object files).  I don't use the schematic
flow, but this sounds like one of those issues, i.e. remainders of
the first build showing up when you run PACE.

HTH,
Gabor


Article: 125447
Subject: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
From: martin_pager@yahoo.com
Date: Thu, 25 Oct 2007 10:38:02 -0700
Links: << >>  << T >>  << A >>
On Sep 21, 12:09 am, Antti <Antti.Luk...@googlemail.com> wrote:
> Hi
>
> information from reliable source (but not verified by actual test-
> purchases):
>
> "Actel silicon with and without Cortex-M1 enable option cost exactly
> the same, not a penny more"
>
> I requested to verify and repeat that claim, and the source did stand
> to it.
>
> If this is really so - this can only be verified when buying Actel M1
> silicon and non-M1 at same time from same vendor, then it means that
> there really is no hidden fee any more in theARMsoftcore.
>
> let me remind that while Actel also claimed M7 to be "free" the actual
> M7 enabled silicon cost 1 USD (qty 100k) or 100 USD (qty 1)  more then
> silicon without M7 AES key.
>
> Antti

Antti et al,

Antti is correct our pricing model for the M1 (ARM enabled Cortex-M1)
products is to offer them at the same price as our regular ProASIC3,
Igloo and Fusion device prices. Basically ARM enabled for free.

However it should be noted than we do not set final resales for our
devices through distribution so you may see small variations in price
(for all products) which are not under Actel's control.

Martin Mason
Actel Corp.


Article: 125448
Subject: Re: Changing refresh rate for DRAM while in operation?
From: KJ <Kevin.Jennings@Unisys.com>
Date: Thu, 25 Oct 2007 11:19:00 -0700
Links: << >>  << T >>  << A >>
On Oct 25, 1:25 pm, Gabor <ga...@alacron.com> wrote:
> On Oct 25, 12:59 pm, "David Spencer" <davidmspen...@verizon.net>
> but thinks it would have been nice if one of the 25 replies answered
> his original question...

The very first reply to the original post did answer the OP's original
question.

The rest of the thread has been for entertainment and educational
value.

KJ


Article: 125449
Subject: Re: Paper about selecting fixed point bit widths?
From: "Marc Reinig" <Marco@newsgroups.nospam>
Date: Thu, 25 Oct 2007 12:48:24 -0700
Links: << >>  << T >>  << A >>
Try:
http://personal.bellsouth.net/y/a/yatesc/fp.pdf
http://personal.bellsouth.net/y/a/yatesc/fir.pdf

-- 
Marco
________________________
Marc Reinig
UCO/Lick Observatory
Laboratory for Adaptive Optics

<paragon.john@gmail.com> wrote in message 
news:1193248586.389559.81630@e34g2000pro.googlegroups.com...
> Hello all,
>
> Can anyone point me to a good general purpose paper about selecting
> appropriate bit-widths for a fixed point implementation of a signal
> processing algorithm?  I've looked around and haven't found anything
> that describes a general methodology to use.  I have implemented a
> design and it isn't performing as well as I would like.  I suspect it
> has to do with some poor selection of bit slicing when it comes to
> multipiers and accumulators.
>
> Thanks for your help!
> 





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