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Threads Starting Aug 2009

142278: 09/08/01: Nico Coesel: Single ended LVDS into FPGA
    142279: 09/08/01: Kolja: Re: Single ended LVDS into FPGA
    142281: 09/08/01: BobW: Re: Single ended LVDS into FPGA
        142282: 09/08/01: Nico Coesel: Re: Single ended LVDS into FPGA
            142283: 09/08/01: BobW: Re: Single ended LVDS into FPGA
        142304: 09/08/03: gabor: Re: Single ended LVDS into FPGA
142284: 09/08/02: Giuseppe Marullo: [newbie] Verilog test bench with automatic verification
    142288: 09/08/02: maxascent: Re: [newbie] Verilog test bench with automatic verification
        142298: 09/08/03: Giuseppe Marullo: Re: [newbie] Verilog test bench with automatic verification
            142301: 09/08/03: maxascent: Re: [newbie] Verilog test bench with automatic verification
    142289: 09/08/02: Jonathan Bromley: Re: [newbie] Verilog test bench with automatic verification
        142290: 09/08/02: Jonathan Bromley: Re: [newbie] Verilog test bench with automatic verification
        142292: 09/08/02: Jonathan Bromley: Re: [newbie] Verilog test bench with automatic verification
            142297: 09/08/03: Giuseppe Marullo: Re: [newbie] Verilog test bench with automatic verification
142286: 09/08/01: Steve: Xilinx 3E design programs fine with 500E but fails with 250E
    142287: 09/08/02: Nico Coesel: Re: Xilinx 3E design programs fine with 500E but fails with 250E
        142295: 09/08/02: Nico Coesel: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142291: 09/08/02: Steve: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142299: 09/08/02: Brian Davis: Re: Xilinx 3E design programs fine with 500E but fails with 250E
        142305: 09/08/03: Mike Harrison: Re: Xilinx 3E design programs fine with 500E but fails with 250E
        142612: 09/08/20: Alex Freed: Re: Xilinx 3E design programs fine with 500E but fails with 250E
            142614: 09/08/21: Petter Gustad: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142302: 09/08/03: Steve: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142303: 09/08/03: Steve: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142312: 09/08/03: Brian Davis: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142313: 09/08/03: Steve: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142556: 09/08/16: Steve: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142586: 09/08/18: cs_posting@hotmail.com: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142587: 09/08/18: Antti.Lukats@googlemail.com: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142601: 09/08/20: Steve: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142602: 09/08/20: Steve: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142604: 09/08/20: Antti.Lukats@googlemail.com: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142611: 09/08/20: Steve: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142615: 09/08/21: Antti.Lukats@googlemail.com: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142616: 09/08/21: Antti.Lukats@googlemail.com: Re: Xilinx 3E design programs fine with 500E but fails with 250E
142293: 09/08/02: Zorjak: Questa price
    142294: 09/08/02: Mike Treseler: Re: Questa price
        142296: 09/08/02: Charles Gardiner: Re: Questa price
142300: 09/08/02: Gints: Ethernet PHY and Endianness
142306: 09/08/03: JanW: ucf and clock pin placement on Spartan 3E?
    142307: 09/08/03: Symon: Re: ucf and clock pin placement on Spartan 3E?
    142308: 09/08/03: maxascent: Re: ucf and clock pin placement on Spartan 3E?
    142309: 09/08/03: gabor: Re: ucf and clock pin placement on Spartan 3E?
        142311: 09/08/03: JanW: Re: ucf and clock pin placement on Spartan 3E?
142314: 09/08/03: Nauman Mir: Program Memory Space for Microblaze Processor in Spartan-3A
    142315: 09/08/03: Antti.Lukats@googlemail.com: Re: Program Memory Space for Microblaze Processor in Spartan-3A
142316: 09/08/04: DAJ: File I/O read in verilog
    142317: 09/08/04: Jon: Re: File I/O read in verilog
    142318: 09/08/04: mike: Re: File I/O read in verilog
    142319: 09/08/04: gabor: Re: File I/O read in verilog
142320: 09/08/04: Rajesh Gandhi: AES encryption of bitstream - is my design secure?
    142321: 09/08/04: untergangsprophet: Re: AES encryption of bitstream - is my design secure?
        142329: 09/08/05: Nial Stewart: Re: AES encryption of bitstream - is my design secure?
            142331: 09/08/05: Brian Drummond: Re: AES encryption of bitstream - is my design secure?
            142343: 09/08/05: glen herrmannsfeldt: Re: AES encryption of bitstream - is my design secure?
    142322: 09/08/04: austin: Re: AES encryption of bitstream - is my design secure?
        142332: 09/08/05: Dave Farrance: Re: AES encryption of bitstream - is my design secure?
            142344: 09/08/05: Dave Farrance: Re: AES encryption of bitstream - is my design secure?
            142346: 09/08/05: glen herrmannsfeldt: Re: AES encryption of bitstream - is my design secure?
                142355: 09/08/05: glen herrmannsfeldt: Re: AES encryption of bitstream - is my design secure?
                    142408: 09/08/10: Theo Markettos: Re: AES encryption of bitstream - is my design secure?
            142347: 09/08/05: glen herrmannsfeldt: Re: AES encryption of bitstream - is my design secure?
                142350: 09/08/05: Dave Farrance: Re: AES encryption of bitstream - is my design secure?
            142348: 09/08/05: glen herrmannsfeldt: Re: AES encryption of bitstream - is my design secure?
    142323: 09/08/04: alan@nishioka.com: Re: AES encryption of bitstream - is my design secure?
    142324: 09/08/04: Rajesh Gandhi: Re: AES encryption of bitstream - is my design secure?
    142325: 09/08/04: Rajesh Gandhi: Re: AES encryption of bitstream - is my design secure?
    142326: 09/08/04: Rajesh Gandhi: Re: AES encryption of bitstream - is my design secure?
    142327: 09/08/04: gabor: Re: AES encryption of bitstream - is my design secure?
    142328: 09/08/04: Rajesh Gandhi: Re: AES encryption of bitstream - is my design secure?
    142330: 09/08/05: Antti.Lukats@googlemail.com: Re: AES encryption of bitstream - is my design secure?
    142334: 09/08/05: Rajesh Gandhi: Re: AES encryption of bitstream - is my design secure?
    142336: 09/08/05: gabor: Re: AES encryption of bitstream - is my design secure?
    142338: 09/08/05: Antti.Lukats@googlemail.com: Re: AES encryption of bitstream - is my design secure?
    142339: 09/08/05: austin: Re: AES encryption of bitstream - is my design secure?
    142341: 09/08/05: Antti.Lukats@googlemail.com: Re: AES encryption of bitstream - is my design secure?
    142342: 09/08/05: Rajesh Gandhi: Re: AES encryption of bitstream - is my design secure?
    142349: 09/08/05: austin: Re: AES encryption of bitstream - is my design secure?
    142354: 09/08/05: Rajesh Gandhi: Re: AES encryption of bitstream - is my design secure?
    142358: 09/08/06: Symon: Re: AES encryption of bitstream - is my design secure?
        142365: 09/08/06: glen herrmannsfeldt: Re: AES encryption of bitstream - is my design secure?
            142366: 09/08/06: Symon: Re: AES encryption of bitstream - is my design secure?
                142367: 09/08/06: glen herrmannsfeldt: Re: AES encryption of bitstream - is my design secure?
            142371: 09/08/07: glen herrmannsfeldt: Re: AES encryption of bitstream - is my design secure?
    142369: 09/08/06: Rajesh Gandhi: Re: AES encryption of bitstream - is my design secure?
    142370: 09/08/06: Rajesh Gandhi: Re: AES encryption of bitstream - is my design secure?
    142453: 09/08/11: Rajesh Gandhi: Re: AES encryption of bitstream - is my design secure?
    142454: 09/08/11: Rajesh Gandhi: Re: AES encryption of bitstream - is my design secure?
142333: 09/08/05: nithin jayavarapu: dcm
142335: 09/08/05: snowball67: Driving Multiple FPGAs and Fanout (Cyclone III)
    142337: 09/08/05: gabor: Re: Driving Multiple FPGAs and Fanout (Cyclone III)
    142340: 09/08/05: BobW: Re: Driving Multiple FPGAs and Fanout (Cyclone III)
142345: 09/08/05: nachum: xilinx ise verilog constraint with concatenated string name
142351: 09/08/05: blakaxe@gmail.com: how to sign extend or round?
    142352: 09/08/05: gabor: Re: how to sign extend or round?
    142353: 09/08/05: blakaxe: Re: how to sign extend or round?
    142356: 09/08/05: gabor: Re: how to sign extend or round?
    142357: 09/08/05: Uwe Bonnes: Re: how to sign extend or round?
142359: 09/08/06: Sudhir Singh: What would be the best method to terminate GTX_CLK signal in Gigabit
    142360: 09/08/06: Fredxx: Re: What would be the best method to terminate GTX_CLK signal in Gigabit Ethernet PHY
        142376: 09/08/07: MM: Re: What would be the best method to terminate GTX_CLK signal in Gigabit Ethernet PHY
            142417: 09/08/10: MM: Re: What would be the best method to terminate GTX_CLK signal in Gigabit Ethernet PHY
    142375: 09/08/07: MM: Re: What would be the best method to terminate GTX_CLK signal in Gigabit Ethernet PHY
    142399: 09/08/09: Sudhir Singh: Re: What would be the best method to terminate GTX_CLK signal in
142361: 09/08/06: Zorjak: ise simulator simple question
142363: 09/08/06: austin: Peter Alfke
    142372: 09/08/06: Moazzam: Re: Peter Alfke
    142373: 09/08/07: Clyder: Re: Peter Alfke
    142374: 09/08/07: MM: Re: Peter Alfke
    142388: 09/08/08: EdV: Re: Peter Alfke
    142389: 09/08/08: Jonathan Bromley: Re: Peter Alfke
    142390: 09/08/08: glen herrmannsfeldt: Re: Peter Alfke
    142392: 09/08/08: Nico Coesel: Re: Peter Alfke
        142403: 09/08/09: Nico Coesel: Re: Peter Alfke
    142393: 09/08/08: Peter Alfke: Re: Peter Alfke
    142488: 09/08/12: luudee: Re: Peter Alfke
142377: 09/08/07: vlsi: diff b/w synthesis and implementation in xilinx ISE
142378: 09/08/07: nskri: can't write to a bram module (verilog)
    142379: 09/08/07: gabor: Re: can't write to a bram module (verilog)
        142386: 09/08/08: nskri: Re: can't write to a bram module (verilog)
            142387: 09/08/08: Jonathan Bromley: Re: can't write to a bram module (verilog)
                142768: 09/08/31: nskri: Re: can't write to a bram module (verilog)
142380: 09/08/07: jadwin79: Stale RTL schematic from VHDL in Xilinx ISE 11.1
    142381: 09/08/08: Alan Fitch: Re: Stale RTL schematic from VHDL in Xilinx ISE 11.1
142382: 09/08/07: shamanth: Bram access on FPGA
142384: 09/08/08: kclo4: Quartus fitter put a user pin on an already assigned pin
    142414: 09/08/10: Nial Stewart: Re: Quartus fitter put a user pin on an already assigned pin
142385: 09/08/08: kclo4: Quartus fitter trouble in auto assignement
142391: 09/08/08: Laserbeak43: Spartan3e Starter kit and Ethernet tutorials
142394: 09/08/09: BarNash: EVERAGE ?
    142395: 09/08/09: Antti.Lukats@googlemail.com: Re: EVERAGE ?
    142396: 09/08/09: Antti.Lukats@googlemail.com: Re: EVERAGE ?
        142398: 09/08/09: Jonathan Bromley: Re: EVERAGE ?
    142397: 09/08/09: Brian Drummond: Re: EVERAGE ?
142400: 09/08/09: John Adair: Spartan-6 Boards - Your Wish List
    142401: 09/08/09: Antti.Lukats@googlemail.com: Re: Spartan-6 Boards - Your Wish List
    142402: 09/08/09: Nico Coesel: Re: Spartan-6 Boards - Your Wish List
    142404: 09/08/09: John Adair: Re: Spartan-6 Boards - Your Wish List
    142405: 09/08/09: John Adair: Re: Spartan-6 Boards - Your Wish List
    142406: 09/08/09: Muzaffer Kal: Re: Spartan-6 Boards - Your Wish List
    142407: 09/08/09: glen herrmannsfeldt: Re: Spartan-6 Boards - Your Wish List
        142420: 09/08/10: glen herrmannsfeldt: Re: Spartan-6 Boards - Your Wish List
            142427: 09/08/10: glen herrmannsfeldt: Re: Spartan-6 Boards - Your Wish List
                142430: 09/08/11: Herbert Kleebauer: Re: Spartan-6 Boards - Your Wish List
                    142436: 09/08/11: Marko Zec: Re: Spartan-6 Boards - Your Wish List
                    142438: 09/08/11: glen herrmannsfeldt: Re: Spartan-6 Boards - Your Wish List
                        142441: 09/08/11: Nico Coesel: Re: Spartan-6 Boards - Your Wish List
                        142455: 09/08/12: M.Randelzhofer: Re: Spartan-6 Boards - Your Wish List
                            142456: 09/08/12: DJ Delorie: Re: Spartan-6 Boards - Your Wish List
                                142457: 09/08/12: Frank Buss: Re: Spartan-6 Boards - Your Wish List
                                    142465: 09/08/12: Rainer Buchty: Re: Spartan-6 Boards - Your Wish List
                                        142472: 09/08/12: Rainer Buchty: Re: Spartan-6 Boards - Your Wish List
                                            142484: 09/08/12: Frank Buss: Re: Spartan-6 Boards - Your Wish List
                                        142479: 09/08/12: glen herrmannsfeldt: Re: Spartan-6 Boards - Your Wish List
                                    142476: 09/08/12: DJ Delorie: Re: Spartan-6 Boards - Your Wish List
                                        142480: 09/08/12: glen herrmannsfeldt: Re: Spartan-6 Boards - Your Wish List
                                            142501: 09/08/13: Nico Coesel: Re: Spartan-6 Boards - Your Wish List
                                                142502: 09/08/13: DJ Delorie: Re: Spartan-6 Boards - Your Wish List
                                                    142524: 09/08/14: Nico Coesel: Re: Spartan-6 Boards - Your Wish List
                                                        142525: 09/08/14: DJ Delorie: Re: Spartan-6 Boards - Your Wish List
                                                142505: 09/08/13: glen herrmannsfeldt: Re: Spartan-6 Boards - Your Wish List
                                    142477: 09/08/12: Nico Coesel: Re: Spartan-6 Boards - Your Wish List
                                        142483: 09/08/12: Frank Buss: Re: Spartan-6 Boards - Your Wish List
                            142458: 09/08/12: Olaf Kaluza: Re: Spartan-6 Boards - Your Wish List
                            142460: 09/08/12: Mike Harrison: Re: Spartan-6 Boards - Your Wish List
                                142463: 09/08/12: Uwe Bonnes: Re: Spartan-6 Boards - Your Wish List
                                142470: 09/08/12: Mike Harrison: Re: Spartan-6 Boards - Your Wish List
    142410: 09/08/10: John Adair: Re: Spartan-6 Boards - Your Wish List
    142411: 09/08/10: John Adair: Re: Spartan-6 Boards - Your Wish List
    142412: 09/08/10: kclo4: Re: Spartan-6 Boards - Your Wish List
    142413: 09/08/10: Nial Stewart: Re: Spartan-6 Boards - Your Wish List
    142418: 09/08/10: John Adair: Re: Spartan-6 Boards - Your Wish List
    142419: 09/08/10: John Adair: Re: Spartan-6 Boards - Your Wish List
    142423: 09/08/10: Pete Fraser: Re: Spartan-6 Boards - Your Wish List
    142424: 09/08/10: John Adair: Re: Spartan-6 Boards - Your Wish List
    142425: 09/08/10: John Adair: Re: Spartan-6 Boards - Your Wish List
    142433: 09/08/11: John Adair: Re: Spartan-6 Boards - Your Wish List
    142437: 09/08/11: Andy Peters: Re: Spartan-6 Boards - Your Wish List
    142439: 09/08/11: Dave Pollum: Re: Spartan-6 Boards - Your Wish List
    142446: 09/08/11: John Adair: Re: Spartan-6 Boards - Your Wish List
    142447: 09/08/11: John Adair: Re: Spartan-6 Boards - Your Wish List
    142448: 09/08/11: John Adair: Re: Spartan-6 Boards - Your Wish List
    142462: 09/08/12: John Adair: Re: Spartan-6 Boards - Your Wish List
    142466: 09/08/12: John Adair: Re: Spartan-6 Boards - Your Wish List
    142467: 09/08/12: John Adair: Re: Spartan-6 Boards - Your Wish List
    142468: 09/08/12: Andy: Re: Spartan-6 Boards - Your Wish List
    142475: 09/08/12: Ed McGettigan: Re: Spartan-6 Boards - Your Wish List
    142478: 09/08/12: John Adair: Re: Spartan-6 Boards - Your Wish List
    142526: 09/08/14: Ed McGettigan: Re: Spartan-6 Boards - Your Wish List
142415: 09/08/10: Antti: delta-signa DAC with FPGA
    142426: 09/08/10: langwadt@fonz.dk: Re: delta-signa DAC with FPGA
142421: 09/08/10: Vikram: FPGA-Camp - A mini conference on FPGAs, (Aug'26, Silicon Valley)
142428: 09/08/11: jogging: algorithm implementation in IC
    142429: 09/08/11: Jon: Re: algorithm implementation in IC
    142431: 09/08/11: Kolja: Re: algorithm implementation in IC
        142442: 09/08/11: Muzaffer Kal: Re: algorithm implementation in IC
            142444: 09/08/11: glen herrmannsfeldt: Re: algorithm implementation in IC
                142445: 09/08/11: Muzaffer Kal: Re: algorithm implementation in IC
                    142459: 09/08/12: HT-Lab: Re: algorithm implementation in IC
        142490: 09/08/13: HT-Lab: Re: algorithm implementation in IC
    142440: 09/08/11: glen herrmannsfeldt: Re: algorithm implementation in IC
    142443: 09/08/11: Muzaffer Kal: Re: algorithm implementation in IC
    142487: 09/08/12: jogging: Re: algorithm implementation in IC
142432: 09/08/11: jc: DDR2 Controllers: Bursting to Odd Addresses
    142434: 09/08/11: maxascent: Re: DDR2 Controllers: Bursting to Odd Addresses
        142451: 09/08/11: Ben Jackson: Re: DDR2 Controllers: Bursting to Odd Addresses
    142435: 09/08/11: jc: Re: DDR2 Controllers: Bursting to Odd Addresses
142449: 09/08/11: Test01: Is it possible to use OSERDES and ISERDES primitives internal to
    142450: 09/08/11: Antti.Lukats@googlemail.com: Re: Is it possible to use OSERDES and ISERDES primitives internal to
    142452: 09/08/11: Test01: Re: Is it possible to use OSERDES and ISERDES primitives internal to
    142464: 09/08/12: KJ: Re: Is it possible to use OSERDES and ISERDES primitives internal to
    142473: 09/08/12: Test01: Re: Is it possible to use OSERDES and ISERDES primitives internal to
    142474: 09/08/12: Antti.Lukats@googlemail.com: Re: Is it possible to use OSERDES and ISERDES primitives internal to
    142485: 09/08/12: KJ: Re: Is it possible to use OSERDES and ISERDES primitives internal to
    142503: 09/08/13: Test01: Re: Is it possible to use OSERDES and ISERDES primitives internal to
142461: 09/08/12: Fabian Schuh: Partial Reconfiguration - Pin access from within the module
    142491: 09/08/13: Fabian Schuh: Re: Partial Reconfiguration - Pin access from within the module
        142492: 09/08/13: Fabian Schuh: Re: Partial Reconfiguration - Pin access from within the module
142469: 09/08/12: Nagaraj: System gates: Altera <-> Actel
    142471: 09/08/12: Antti.Lukats@googlemail.com: Re: System gates: Altera <-> Actel
    142481: 09/08/12: Walter: Re: System gates: Altera <-> Actel
142482: 09/08/12: MM: V5 GTX and V4 MGT interoperability
    142498: 09/08/13: austin: Re: V5 GTX and V4 MGT interoperability
        142500: 09/08/13: MM: Re: V5 GTX and V4 MGT interoperability
            142515: 09/08/13: MM: Re: V5 GTX and V4 MGT interoperability
        142511: 09/08/13: Ed McGettigan: Re: V5 GTX and V4 MGT interoperability
142486: 09/08/12: coredev: Can I suppress invoking Block SelectRAMs in virtex5?
    142489: 09/08/12: Antti.Lukats@googlemail.com: Re: Can I suppress invoking Block SelectRAMs in virtex5?
142493: 09/08/13: braver: why synthesize not work?
    142499: 09/08/13: Mike Treseler: Re: why synthesize not work?
        142527: 09/08/14: Mike Treseler: Re: why synthesize not work?
    142514: 09/08/13: braver: Re: why synthesize not work?
142494: 09/08/13: Simon Heinzle: Simulating Xilinx EDK Systems
142495: 09/08/13: sdaau: JTAGkey-Tiny with Altera/Xilinx FPGA?
    142496: 09/08/13: Jon: Re: JTAGkey-Tiny with Altera/Xilinx FPGA?
    142497: 09/08/13: Antti.Lukats@googlemail.com: Re: JTAGkey-Tiny with Altera/Xilinx FPGA?
142504: 09/08/13: Rob Gaddi: Mixed language simulation on the cheap
    142506: 09/08/13: John McCaskill: Re: Mixed language simulation on the cheap
    142507: 09/08/13: Mike Treseler: Re: Mixed language simulation on the cheap
    142508: 09/08/13: Rob Gaddi: Re: Mixed language simulation on the cheap
    142509: 09/08/14: Charles Gardiner: Re: Mixed language simulation on the cheap
    142510: 09/08/13: evilkidder@googlemail.com: Re: Mixed language simulation on the cheap
    142512: 09/08/14: Brian Drummond: Re: Mixed language simulation on the cheap
    142516: 09/08/14: HT-Lab: Re: Mixed language simulation on the cheap
    142736: 09/08/29: Alan Fitch: Re: Mixed language simulation on the cheap
142513: 09/08/13: timinganalyzer: new version TimingAnalyzer
142517: 09/08/14: Oscar: Initializing BRAM & ISE 10.1
    142518: 09/08/14: gabor: Re: Initializing BRAM & ISE 10.1
142519: 09/08/14: Test01: Is it possible to generate double data rate stream in the Virtex4
    142520: 09/08/14: Antti.Lukats@googlemail.com: Re: Is it possible to generate double data rate stream in the Virtex4
    142521: 09/08/14: Antti.Lukats@googlemail.com: Re: Is it possible to generate double data rate stream in the Virtex4
    142522: 09/08/14: Test01: Re: Is it possible to generate double data rate stream in the Virtex4
    142523: 09/08/14: Andy: Re: Is it possible to generate double data rate stream in the Virtex4
142528: 09/08/14: rickman: Using carry chain of counters for term count detect
    142529: 09/08/14: KJ: Re: Using carry chain of counters for term count detect
    142530: 09/08/15: rickman: Re: Using carry chain of counters for term count detect
    142542: 09/08/16: Brian Davis: Re: Using carry chain of counters for term count detect
    142547: 09/08/16: Andy: Re: Using carry chain of counters for term count detect
    142565: 09/08/17: JimLewis: Re: Using carry chain of counters for term count detect
    142567: 09/08/17: Andy: Re: Using carry chain of counters for term count detect
    142580: 09/08/17: rickman: Re: Using carry chain of counters for term count detect
    142613: 09/08/20: JimLewis: Re: Using carry chain of counters for term count detect
    142618: 09/08/21: Andy: Re: Using carry chain of counters for term count detect
142532: 09/08/16: Antti: Soft Processor IP core report
    142533: 09/08/16: Nico Coesel: Re: Soft Processor IP core report
        142535: 09/08/16: glen herrmannsfeldt: Re: Soft Processor IP core report
            142537: 09/08/16: Frank Buss: Re: Soft Processor IP core report
        142540: 09/08/16: Nico Coesel: Re: Soft Processor IP core report
        142644: 09/08/24: David Brown: Re: Soft Processor IP core report
    142534: 09/08/16: Antti.Lukats@googlemail.com: Re: Soft Processor IP core report
    142536: 09/08/16: Antti.Lukats@googlemail.com: Re: Soft Processor IP core report
    142541: 09/08/16: Herbert Kleebauer: Re: Soft Processor IP core report
        142546: 09/08/16: Nico Coesel: Re: Soft Processor IP core report
            142550: 09/08/16: Herbert Kleebauer: Re: Soft Processor IP core report
                142551: 09/08/16: Nico Coesel: Re: Soft Processor IP core report
    142543: 09/08/16: Moti Litochevski: Re: Soft Processor IP core report
        142554: 09/08/17: Frank Buss: Re: Soft Processor IP core report
            142585: 09/08/18: Walter Banks: Re: Soft Processor IP core report
        142557: 09/08/17: David Brown: Re: Soft Processor IP core report
        142561: 09/08/17: David Brown: Re: Soft Processor IP core report
    142544: 09/08/16: Antti.Lukats@googlemail.com: Re: Soft Processor IP core report
    142549: 09/08/16: Herbert Kleebauer: Re: Soft Processor IP core report
    142553: 09/08/16: Antti.Lukats@googlemail.com: Re: Soft Processor IP core report
    142558: 09/08/17: Antti.Lukats@googlemail.com: Re: Soft Processor IP core report
    142560: 09/08/17: Herbert Kleebauer: Re: Soft Processor IP core report
    142576: 09/08/17: Ben Jackson: Re: Soft Processor IP core report
    142621: 09/08/21: green: Re: Soft Processor IP core report
    142622: 09/08/21: Antti.Lukats@googlemail.com: Re: Soft Processor IP core report
    142638: 09/08/23: -jg: Re: Soft Processor IP core report
    142640: 09/08/23: Antti.Lukats@googlemail.com: Re: Soft Processor IP core report
    142660: 09/08/24: -jg: Re: Soft Processor IP core report
    142661: 09/08/24: green: Re: Soft Processor IP core report
142538: 09/08/16: Andrew Holme: BCD in FPGA
    142555: 09/08/16: backhus: Re: BCD in FPGA
        142559: 09/08/17: Andrew Holme: Re: BCD in FPGA
        142592: 09/08/19: backhus: Re: BCD in FPGA
142539: 09/08/16: Andrew Holme: BCD in FPGA
    142589: 09/08/19: Andrew Holme: Re: BCD in FPGA
142545: 09/08/16: maxascent: Virtex 4 package code
    142548: 09/08/16: Muzaffer Kal: Re: Virtex 4 package code
    142562: 09/08/17: MM: Re: Virtex 4 package code
        142564: 09/08/17: MM: Re: Virtex 4 package code
    142563: 09/08/17: <johnbean_uk@hotmail.com>: Re: Virtex 4 package code
142552: 09/08/16: zgora: ANNC: Parallel flash programming using boundary-scan
142566: 09/08/17: fpgabuilder: Operating same logic at two frequencies
    142568: 09/08/17: Andy: Re: Operating same logic at two frequencies
    142569: 09/08/17: Symon: Re: Operating same logic at two frequencies
    142570: 09/08/17: fpgabuilder: Re: Operating same logic at two frequencies
    142575: 09/08/17: fpgabuilder: Re: Operating same logic at two frequencies
142571: 09/08/17: Pratap: VHDL code for finding standard deviation for a chunk of numbers
    142572: 09/08/17: Rob Gaddi: Re: VHDL code for finding standard deviation for a chunk of numbers
        142579: 09/08/18: Marty Ryba: Re: VHDL code for finding standard deviation for a chunk of numbers
    142574: 09/08/17: Pratap: Re: VHDL code for finding standard deviation for a chunk of numbers
142573: 09/08/17: Roger: Embedded Memory Controller
    142577: 09/08/18: Brian Drummond: Re: Embedded Memory Controller
142581: 09/08/18: cris: Post sythesys vs FPGA board implementation
    142582: 09/08/18: KJ: Re: Post sythesys vs FPGA board implementation
        142584: 09/08/18: Thorsten Kiefer: Re: Post sythesys vs FPGA board implementation
142588: 09/08/19: sdaau: Help with crystal oscillator (MG-7010SA replacement)?
    142590: 09/08/19: Brian Drummond: Re: Help with crystal oscillator (MG-7010SA replacement)?
    142591: 09/08/19: Antti.Lukats@googlemail.com: Re: Help with crystal oscillator (MG-7010SA replacement)?
    142593: 09/08/19: gabor: Re: Help with crystal oscillator (MG-7010SA replacement)?
        142594: 09/08/19: John Larkin: Re: Help with crystal oscillator (MG-7010SA replacement)?
    142596: 09/08/19: Peter Alfke: Re: Help with crystal oscillator (MG-7010SA replacement)?
        142610: 09/08/20: John Larkin: Re: Help with crystal oscillator (MG-7010SA replacement)?
            142647: 09/08/24: sdaau: Re: Help with crystal oscillator (MG-7010SA replacement)?
    142648: 09/08/24: Antti.Lukats@googlemail.com: Re: Help with crystal oscillator (MG-7010SA replacement)?
142595: 09/08/19: Test01: Emulation of highly complex superscaler processor using FPGAs
    142597: 09/08/20: Matthew Hicks: Re: Emulation of highly complex superscaler processor using FPGAs
        142598: 09/08/20: Frank Buss: Re: Emulation of highly complex superscaler processor using FPGAs
    142600: 09/08/19: John Adair: Re: Emulation of highly complex superscaler processor using FPGAs
    142603: 09/08/20: Florian Stock: Re: Emulation of highly complex superscaler processor using FPGAs
    142620: 09/08/21: Muzaffer Kal: Re: Emulation of highly complex superscaler processor using FPGAs
142599: 09/08/19: moon: Multiple Interrupt handling in XPS 8.2i
    142656: 09/08/24: Jason Agron: Re: Multiple Interrupt handling in XPS 8.2i
142605: 09/08/20: shruti: FPGA to ASIC conversion
    142607: 09/08/20: Jon: Re: FPGA to ASIC conversion
142606: 09/08/20: Niieg: Wildcards in Quartus TCL Scripting
    142608: 09/08/20: HT-Lab: Re: Wildcards in Quartus TCL Scripting
    142609: 09/08/20: Petter Gustad: Re: Wildcards in Quartus TCL Scripting
        142623: 09/08/22: Niieg: Re: Wildcards in Quartus TCL Scripting
142617: 09/08/21: aliumair926: FM Broadcast receiver on Lyrtech SFF SDR Kit using vertex 4
    142619: 09/08/21: Antti.Lukats@googlemail.com: Re: FM Broadcast receiver on Lyrtech SFF SDR Kit using vertex 4
    142629: 09/08/22: Niieg: Re: FM Broadcast receiver on Lyrtech SFF SDR Kit using vertex 4
    142630: 09/08/22: Antti.Lukats@googlemail.com: Re: FM Broadcast receiver on Lyrtech SFF SDR Kit using vertex 4
142624: 09/08/22: morp: Ideas needed for implementing SerDes on low-cost fpga (like
    142625: 09/08/22: gabor: Re: Ideas needed for implementing SerDes on low-cost fpga (like
    142626: 09/08/22: rickman: Re: Ideas needed for implementing SerDes on low-cost fpga (like
142627: 09/08/22: maxascent: Virtex 5 config Virtex 4
142628: 09/08/22: morp: Need support for LVDS to Tmds translation on altera device
    142631: 09/08/22: Antti.Lukats@googlemail.com: Re: Need support for LVDS to Tmds translation on altera device
142632: 09/08/23: Antti: xc3sprog support for Altera Byteblaster
    142822: 09/09/02: Uwe Bonnes: Re: xc3sprog support for Altera Byteblaster
    142861: 09/09/04: Antti.Lukats@googlemail.com: Re: xc3sprog support for Altera Byteblaster
142633: 09/08/23: Frank Buss: Yet Another Graphics Controller
    142634: 09/08/23: Antti.Lukats@googlemail.com: Re: Yet Another Graphics Controller
        142635: 09/08/23: Frank Buss: Re: Yet Another Graphics Controller
            142649: 09/08/24: Nico Coesel: Re: Yet Another Graphics Controller
                142652: 09/08/24: Frank Buss: Re: Yet Another Graphics Controller
                    142654: 09/08/24: Frank Buss: Re: Yet Another Graphics Controller
                    142659: 09/08/24: Nico Coesel: Re: Yet Another Graphics Controller
                        142662: 09/08/25: Robert Swindells: Re: Yet Another Graphics Controller
                            142664: 09/08/25: Mark McDougall: Re: Yet Another Graphics Controller
                        142663: 09/08/25: Mark McDougall: Re: Yet Another Graphics Controller
                142655: 09/08/24: Torfinn Ingolfsen: Re: Yet Another Graphics Controller
            142650: 09/08/24: Nico Coesel: Re: Yet Another Graphics Controller
        142641: 09/08/23: Antti.Lukats@googlemail.com: Re: Yet Another Graphics Controller
        142651: 09/08/24: Antti.Lukats@googlemail.com: Re: Yet Another Graphics Controller
        142653: 09/08/24: Antti.Lukats@googlemail.com: Re: Yet Another Graphics Controller
142636: 09/08/23: Robert Kaiser (FH): Suitable starter kit for learning VHDL
    142637: 09/08/23: Frank Buss: Re: Suitable starter kit for learning VHDL
        142639: 09/08/23: Antti.Lukats@googlemail.com: Re: Suitable starter kit for learning VHDL
            142718: 09/08/28: Robert Kaiser (FH): Re: Suitable starter kit for learning VHDL
142642: 09/08/23: Sharath Raju: Operating the Spartan 3A FPGA at maximum speed (320 MHz)
    142643: 09/08/23: Antti.Lukats@googlemail.com: Re: Operating the Spartan 3A FPGA at maximum speed (320 MHz)
    142645: 09/08/24: Sharath Raju: Re: Operating the Spartan 3A FPGA at maximum speed (320 MHz)
    142646: 09/08/24: Antti.Lukats@googlemail.com: Re: Operating the Spartan 3A FPGA at maximum speed (320 MHz)
142657: 09/08/24: James: Help with altera_attribute and AUTO_GLOBAL_CLOCK
142658: 09/08/24: fl: Why there is multi-source error in these VHDL code?
    142665: 09/08/25: Matthias Alles: Re: Why there is multi-source error in these VHDL code?
    142672: 09/08/25: Brian Drummond: Re: Why there is multi-source error in these VHDL code?
    142674: 09/08/25: Brad Smallridge: Re: Why there is multi-source error in these VHDL code?
    142688: 09/08/26: KJ: Re: Why there is multi-source error in these VHDL code?
142666: 09/08/25: c d saunter: Xilinx at LLVM developers meeting
142667: 09/08/25: icefish711: [help]error from my own hard macro by FPGA edit
    142669: 09/08/25: Fabian Schuh: Re: [help]error from my own hard macro by FPGA edit
    142702: 09/08/26: Moazzam: Re: error from my own hard macro by FPGA edit
142668: 09/08/25: Pallavi: Timing properties of FPGA devices at sub-clock frequencies
    142670: 09/08/25: glen herrmannsfeldt: Re: Timing properties of FPGA devices at sub-clock frequencies
        142671: 09/08/25: Frank Buss: Re: Timing properties of FPGA devices at sub-clock frequencies
            142673: 09/08/25: glen herrmannsfeldt: Re: Timing properties of FPGA devices at sub-clock frequencies
                142675: 09/08/25: Frank Buss: Re: Timing properties of FPGA devices at sub-clock frequencies
        142676: 09/08/25: Jon Elson: Re: Timing properties of FPGA devices at sub-clock frequencies
            142677: 09/08/25: glen herrmannsfeldt: Re: Timing properties of FPGA devices at sub-clock frequencies
    142678: 09/08/25: Andy: Re: Timing properties of FPGA devices at sub-clock frequencies
142679: 09/08/25: Nicholas Kinar: Reading from ADC and writing to DAC at same time
    142680: 09/08/25: Antti.Lukats@googlemail.com: Re: Reading from ADC and writing to DAC at same time
        142681: 09/08/26: Frank Buss: Re: Reading from ADC and writing to DAC at same time
            142683: 09/08/25: Nicholas Kinar: Re: Reading from ADC and writing to DAC at same time
                142691: 09/08/26: Frank Buss: Re: Reading from ADC and writing to DAC at same time
                    142694: 09/08/26: Nicholas Kinar: Re: Reading from ADC and writing to DAC at same time
        142682: 09/08/25: Nicholas Kinar: Re: Reading from ADC and writing to DAC at same time
            142686: 09/08/26: Nicholas Kinar: Re: Reading from ADC and writing to DAC at same time
        142684: 09/08/25: Antti.Lukats@googlemail.com: Re: Reading from ADC and writing to DAC at same time
    142685: 09/08/26: glen herrmannsfeldt: Re: Reading from ADC and writing to DAC at same time
        142687: 09/08/26: Nicholas Kinar: Re: Reading from ADC and writing to DAC at same time
    142689: 09/08/26: langwadt@fonz.dk: Re: Reading from ADC and writing to DAC at same time
        142690: 09/08/26: Nicholas Kinar: Re: Reading from ADC and writing to DAC at same time
            142692: 09/08/26: Frank Buss: Re: Reading from ADC and writing to DAC at same time
                142695: 09/08/26: Nicholas Kinar: Re: Reading from ADC and writing to DAC at same time
                    142699: 09/08/27: Frank Buss: Re: Reading from ADC and writing to DAC at same time
                        142700: 09/08/26: Nicholas Kinar: Re: Reading from ADC and writing to DAC at same time
                            142707: 09/08/27: Nico Coesel: Re: Reading from ADC and writing to DAC at same time
                                142708: 09/08/27: Nicholas Kinar: Re: Reading from ADC and writing to DAC at same time
                142696: 09/08/26: Nicholas Kinar: Re: Reading from ADC and writing to DAC at same time
            142697: 09/08/26: Nicholas Kinar: Re: Reading from ADC and writing to DAC at same time
                142698: 09/08/27: Frank Buss: Re: Reading from ADC and writing to DAC at same time
                    142701: 09/08/26: Nicholas Kinar: Re: Reading from ADC and writing to DAC at same time
                        142703: 09/08/26: Nicholas Kinar: Re: Reading from ADC and writing to DAC at same time
                            142706: 09/08/27: Frank Buss: Re: Reading from ADC and writing to DAC at same time
                                142709: 09/08/27: Nicholas Kinar: Re: Reading from ADC and writing to DAC at same time
        142693: 09/08/26: -jg: Re: Reading from ADC and writing to DAC at same time
    142704: 09/08/27: Nico Coesel: Re: Reading from ADC and writing to DAC at same time
        142705: 09/08/27: Nicholas Kinar: Re: Reading from ADC and writing to DAC at same time
            142721: 09/08/28: Nico Coesel: Re: Reading from ADC and writing to DAC at same time
                142722: 09/08/28: Nicholas Kinar: Re: Reading from ADC and writing to DAC at same time
142710: 09/08/27: Weng Tianxiang: Where is Altera On-Demand Webinars show on radar signal processing?
    142772: 09/08/31: andi: Re: Where is Altera On-Demand Webinars show on radar signal
    142774: 09/08/31: Weng Tianxiang: Re: Where is Altera On-Demand Webinars show on radar signal
142711: 09/08/27: Nicholas Kinar: Is free-to-use IP included with downloadable FPGA tools?
    142712: 09/08/27: glen herrmannsfeldt: Re: Is free-to-use IP included with downloadable FPGA tools?
        142714: 09/08/27: Nicholas Kinar: Re: Is free-to-use IP included with downloadable FPGA tools?
            142725: 09/08/28: Nicholas Kinar: Re: Is free-to-use IP included with downloadable FPGA tools?
        142724: 09/08/28: Andy Peters: Re: Is free-to-use IP included with downloadable FPGA tools?
    142713: 09/08/27: Phil: Re: Is free-to-use IP included with downloadable FPGA tools?
        142715: 09/08/27: Nicholas Kinar: Re: Is free-to-use IP included with downloadable FPGA tools?
            142723: 09/08/28: Nicholas Kinar: Re: Is free-to-use IP included with downloadable FPGA tools?
    142726: 09/08/28: Andy Peters: Re: Is free-to-use IP included with downloadable FPGA tools?
        142727: 09/08/28: Nicholas Kinar: Re: Is free-to-use IP included with downloadable FPGA tools?
            142728: 09/08/28: Nicholas Kinar: Re: Is free-to-use IP included with downloadable FPGA tools?
                142729: 09/08/28: Nicholas Kinar: Re: Is free-to-use IP included with downloadable FPGA tools?
                    142730: 09/08/28: Nicholas Kinar: Re: Is free-to-use IP included with downloadable FPGA tools?
                        142731: 09/08/28: Nicholas Kinar: Re: Is free-to-use IP included with downloadable FPGA tools?
                            142732: 09/08/28: Nicholas Kinar: Re: Is free-to-use IP included with downloadable FPGA tools?
                        142734: 09/08/28: Nicholas Kinar: Re: Is free-to-use IP included with downloadable FPGA tools?
142716: 09/08/27: Thorsten Kiefer: program spartan3 under linux
    142717: 09/08/27: Antti.Lukats@googlemail.com: Re: program spartan3 under linux
        142747: 09/08/30: Thorsten Kiefer: Re: program spartan3 under linux
            142751: 09/08/30: Frank Buss: Re: program spartan3 under linux
                142754: 09/08/30: Thorsten Kiefer: Re: program spartan3 under linux
                142794: 09/09/01: Jon Elson: Re: program spartan3 under linux
                    142802: 09/09/02: Brian Drummond: Re: program spartan3 under linux
                        142878: 09/09/04: Jon Elson: Re: program spartan3 under linux
            142756: 09/08/30: Nico Coesel: Re: program spartan3 under linux
            142773: 09/08/31: Petter Gustad: Re: program spartan3 under linux
                142792: 09/09/01: Torfinn Ingolfsen: Re: program spartan3 under linux
                    142800: 09/09/02: Petter Gustad: Re: program spartan3 under linux
        142749: 09/08/30: Antti.Lukats@googlemail.com: Re: program spartan3 under linux
        142750: 09/08/30: Antti.Lukats@googlemail.com: Re: program spartan3 under linux
        142757: 09/08/30: Antti.Lukats@googlemail.com: Re: program spartan3 under linux
        142758: 09/08/30: Antti.Lukats@googlemail.com: Re: program spartan3 under linux
    142793: 09/09/01: Jon Elson: Re: program spartan3 under linux
    142823: 09/09/02: Uwe Bonnes: Re: program spartan3 under linux
142719: 09/08/28: water: usb3.0 PHY wrapper for Xilinx V5/V6 device
    142720: 09/08/28: Antti.Lukats@googlemail.com: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
    142742: 09/08/29: murlary@gmail.com: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
    142743: 09/08/29: Antti.Lukats@googlemail.com: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
    142759: 09/08/30: murlary@gmail.com: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
    142763: 09/08/31: Antti.Lukats@googlemail.com: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
    142775: 09/08/31: murlary@gmail.com: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
    142776: 09/08/31: Antti.Lukats@googlemail.com: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
    142797: 09/09/01: murlary@gmail.com: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
    142798: 09/09/01: Antti.Lukats@googlemail.com: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
    142816: 09/09/02: kclo4: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
    142818: 09/09/02: Antti.Lukats@googlemail.com: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
    142828: 09/09/02: murlary@gmail.com: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
142733: 09/08/28: john1529: sharing sdram and parallel nor flash address/data bus using xilinx
    142735: 09/08/28: Antti.Lukats@googlemail.com: Re: sharing sdram and parallel nor flash address/data bus using
142737: 09/08/29: Weng Tianxiang: Does ModelSim or any simulator software have a function similar to
    142738: 09/08/29: Jonathan Bromley: Re: Does ModelSim or any simulator software have a function similar to the standard function any logic analizer has?
        142744: 09/08/30: HT-Lab: Re: Does ModelSim or any simulator software have a function similar to the standard function any logic analizer has?
            142753: 09/08/30: Jonathan Bromley: Re: Does ModelSim or any simulator software have a function similar to the standard function any logic analizer has?
    142739: 09/08/29: KJ: Re: Does ModelSim or any simulator software have a function similar
    142741: 09/08/29: Weng Tianxiang: Re: Does ModelSim or any simulator software have a function similar
    142748: 09/08/30: gabor: Re: Does ModelSim or any simulator software have a function similar
    142752: 09/08/30: Weng Tianxiang: Re: Does ModelSim or any simulator software have a function similar
    142972: 09/09/11: <ehliar@isy.liu.se>: Re: Does ModelSim or any simulator software have a function similar
    142983: 09/09/12: Weng Tianxiang: Re: Does ModelSim or any simulator software have a function similar
142740: 09/08/29: Amit: low power FPGA
    142745: 09/08/30: Phil Jessop: Re: low power FPGA
        142746: 09/08/30: HT-Lab: Re: low power FPGA
    142829: 09/09/02: Amit: Re: low power FPGA
142755: 09/08/30: maxascent: Virtex 5 HDMI
    142764: 09/08/31: Antti.Lukats@googlemail.com: Re: Virtex 5 HDMI
        142766: 09/08/31: maxascent: Re: Virtex 5 HDMI
            142767: 09/08/31: Phil Jessop: Re: Virtex 5 HDMI
                143373: 09/10/07: raven1322: Re: Virtex 5 HDMI
    142765: 09/08/31: Sandro: Re: Virtex 5 HDMI
    143378: 09/10/07: Chris Maryan: Re: Virtex 5 HDMI
142760: 09/08/30: Nicholas Kinar: Selection of external clocks for FPGA system and bus interfacing
    142761: 09/08/30: John Adair: Re: Selection of external clocks for FPGA system and bus interfacing
        142762: 09/08/30: John Adair: Re: Selection of external clocks for FPGA system and bus interfacing
            142771: 09/08/31: Nicholas Kinar: Re: Selection of external clocks for FPGA system and bus interfacing
        142770: 09/08/31: Nicholas Kinar: Re: Selection of external clocks for FPGA system and bus interfacing
        142777: 09/08/31: John Adair: Re: Selection of external clocks for FPGA system and bus interfacing
142769: 09/08/31: Dennis Yurichev: OpenSPARC T1 or T2 on Altera EP2S60 or EP2S90
    142801: 09/09/02: HT-Lab: Re: OpenSPARC T1 or T2 on Altera EP2S60 or EP2S90
        142806: 09/09/02: HT-Lab: Re: OpenSPARC T1 or T2 on Altera EP2S60 or EP2S90


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