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Threads Starting Jun 2008

132575: 08/06/01: Sam Worth: Combinatorial logic delay plus routing delay exceeds clock period
    132576: 08/06/01: Peter Alfke: Re: Combinatorial logic delay plus routing delay exceeds clock period
        132579: 08/06/01: Sam Worth: Re: Combinatorial logic delay plus routing delay exceeds clock period
            132580: 08/06/01: Mike Treseler: Re: Combinatorial logic delay plus routing delay exceeds clock period
                132581: 08/06/01: Mike Treseler: Re: Combinatorial logic delay plus routing -- typo
    132577: 08/06/02: Symon: Re: Combinatorial logic delay plus routing delay exceeds clock period
        132586: 08/06/02: Sam Worth: Re: Combinatorial logic delay plus routing delay exceeds clock period
            132601: 08/06/02: Sam Worth: Re: Combinatorial logic delay plus routing delay exceeds clock period
                132607: 08/06/02: Sam Worth: Re: Combinatorial logic delay plus routing delay exceeds clock period
                    132627: 08/06/03: Sam Worth: Re: Combinatorial logic delay plus routing delay exceeds clock period
        132594: 08/06/02: Peter Alfke: Re: Combinatorial logic delay plus routing delay exceeds clock period
        132603: 08/06/02: Peter Alfke: Re: Combinatorial logic delay plus routing delay exceeds clock period
        132618: 08/06/03: Peter Alfke: Re: Combinatorial logic delay plus routing delay exceeds clock period
    132578: 08/06/01: glen herrmannsfeldt: Re: Combinatorial logic delay plus routing delay exceeds clock period
132583: 08/06/02: FP: Help with $setuphold
    132584: 08/06/02: KJ: Re: Help with $setuphold
132587: 08/06/02: <ghuardian@gmail.com>: Problem with Xilinx 9.2i and Modelsim 6.0
    132620: 08/06/03: HT-Lab: Re: Problem with Xilinx 9.2i and Modelsim 6.0
132590: 08/06/02: FP: clock divider
    132591: 08/06/02: KJ: Re: clock divider
132592: 08/06/02: Andy Peters: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132593: 08/06/02: Simon: Celoxica (AgilityDS) running on Gentoo
132595: 08/06/02: timinganalyzer: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132596: 08/06/03: Andreas Ehliar: Re: Checksums
    132652: 08/06/04: glen herrmannsfeldt: Re: Checksums
132598: 08/06/02: Ambreen Ashfaq Afridi: Checksums
    132599: 08/06/02: Ambreen Ashfaq Afridi: Re: Checksums
    132600: 08/06/02: Thomas Stanka: Re: Checksums
    132606: 08/06/02: Ambreen Ashfaq Afridi: Re: Checksums
132602: 08/06/02: <chrisdekoh@gmail.com>: using hard tri-mode ethernet MAC and MPMC on virtex 5
    132615: 08/06/03: Aiken: Re: using hard tri-mode ethernet MAC and MPMC on virtex 5
    132661: 08/06/04: beeraka@gmail.com: Re: using hard tri-mode ethernet MAC and MPMC on virtex 5
        132749: 08/06/06: John Williams: Re: using hard tri-mode ethernet MAC and MPMC on virtex 5
    132713: 08/06/05: <chrisdekoh@gmail.com>: Re: using hard tri-mode ethernet MAC and MPMC on virtex 5
    132744: 08/06/05: beeraka@gmail.com: Re: using hard tri-mode ethernet MAC and MPMC on virtex 5
132605: 08/06/02: Ambreen Ashfaq Afridi: VHDL to Verilog Converter
    132608: 08/06/02: ALuPin@web.de: Re: VHDL to Verilog Converter
    132614: 08/06/03: Aiken: Re: VHDL to Verilog Converter
    132634: 08/06/04: taco: Re: VHDL to Verilog Converter
132610: 08/06/03: vikram: Interrupt handler for Xilinx EMAC- URGENT!!
    132611: 08/06/03: morphiend: Re: Interrupt handler for Xilinx EMAC- URGENT!!
    132617: 08/06/03: vikram: Re: Interrupt handler for Xilinx EMAC- URGENT!!
    132630: 08/06/04: vikram: Re: Interrupt handler for Xilinx EMAC- URGENT!!
132612: 08/06/03: Zorjak: Counter implementation with ise problem
    132613: 08/06/03: Jonathan Bromley: Re: Counter implementation with ise problem
    132628: 08/06/04: backhus: Re: Counter implementation with ise problem
        132631: 08/06/04: Jonathan Bromley: Re: Counter implementation with ise problem
        132667: 08/06/05: backhus: Re: Counter implementation with ise problem
    132629: 08/06/03: Zorjak: Re: Counter implementation with ise problem
    132636: 08/06/04: KJ: Re: Counter implementation with ise problem
    132669: 08/06/05: Zorjak: Re: Counter implementation with ise problem
132616: 08/06/03: Dave Vanden Bout: ANNC: ISE WebPACK 10.1i tutorial available
132626: 08/06/04: whygee: puzzling [and deceiving ?] Actel kit
    132632: 08/06/04: HT-Lab: Re: puzzling [and deceiving ?] Actel kit
    132741: 08/06/06: whygee: Re: puzzling [and deceiving ?] Actel kit
132635: 08/06/04: AchatesAVC: Using ethernet on a Xilnx board (Help appreciated)
    132637: 08/06/04: MikeWhy: Re: Using ethernet on a Xilnx board (Help appreciated)
    132641: 08/06/04: PFC: Re: Using ethernet on a Xilnx board (Help appreciated)
        132647: 08/06/04: PFC: Re: Using ethernet on a Xilnx board (Help appreciated)
        132649: 08/06/04: PFC: Re: Using ethernet on a Xilnx board (Help appreciated)
        132650: 08/06/04: glen herrmannsfeldt: Re: Using ethernet on a Xilnx board (Help appreciated)
    132643: 08/06/04: AchatesAVC: Re: Using ethernet on a Xilnx board (Help appreciated)
    132666: 08/06/05: Andreas Ehliar: Re: Using ethernet on a Xilnx board (Help appreciated)
    132671: 08/06/05: bommels: Re: Using ethernet on a Xilnx board (Help appreciated)
    132770: 08/06/06: Pat Magnet: Re: Using ethernet on a Xilnx board (Help appreciated)
        133034: 08/06/14: Giuseppe Marullo: Re: Using ethernet on a Xilnx board (Help appreciated)
132638: 08/06/04: rickman: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132639: 08/06/04: rickman: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132640: 08/06/04: <paragon.john@gmail.com>: Xilinx Fifo Generator Direct Instantiation?
    132642: 08/06/04: <ghelbig@gmail.com>: Re: Xilinx Fifo Generator Direct Instantiation?
        132646: 08/06/04: PFC: Re: Xilinx Fifo Generator Direct Instantiation?
    132722: 08/06/05: <paragon.john@gmail.com>: Re: Xilinx Fifo Generator Direct Instantiation?
132644: 08/06/04: rickman: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
    132682: 08/06/05: Brian Drummond: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
        132704: 08/06/05: Robert Miles: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
            132708: 08/06/05: Robert Miles: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
        132725: 08/06/06: Jim Granville: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
        132731: 08/06/05: Andrew Smallshaw: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
            132733: 08/06/05: Andrew Smallshaw: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
            132752: 08/06/06: Andrew Jackson: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
            132791: 08/06/06: Everett M. Greene: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
                132796: 08/06/06: Jerry Avins: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
                132807: 08/06/07: Jim Granville: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
                132866: 08/06/09: Vladimir Vassilevsky: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
                    133225: 08/06/21: Albert van der Horst: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
                132883: 08/06/09: glen herrmannsfeldt: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
        132753: 08/06/06: David Brown: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
        132789: 08/06/06: Brian Drummond: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132645: 08/06/04: PFC: Xilinx vs Altera
    132651: 08/06/04: Jeff Cunningham: Re: Xilinx vs Altera
        132655: 08/06/05: PFC: Re: Xilinx vs Altera
            132657: 08/06/05: Jim Granville: Re: Xilinx vs Altera
            132663: 08/06/04: Rob: Re: Xilinx vs Altera
            132693: 08/06/05: whygee: Re: Xilinx vs Altera
            132698: 08/06/05: Nico Coesel: Re: Xilinx vs Altera
                132709: 08/06/05: PFC: Re: Xilinx vs Altera
                    132784: 08/06/06: Nico Coesel: Re: Xilinx vs Altera
        132683: 08/06/05: Brian Drummond: Re: Xilinx vs Altera
    132653: 08/06/04: KJ: Re: Xilinx vs Altera
    132654: 08/06/05: Jim Granville: Re: Xilinx vs Altera
    132668: 08/06/05: David Brown: Re: Xilinx vs Altera
        132675: 08/06/05: PFC: Re: Xilinx vs Altera
            132677: 08/06/05: David Brown: Re: Xilinx vs Altera
                132679: 08/06/05: PFC: Re: Xilinx vs Altera
                    132685: 08/06/05: David Brown: Re: Xilinx vs Altera
            132723: 08/06/05: Philipp Klaus Krause: Re: Xilinx vs Altera
            132724: 08/06/05: MikeWhy: Re: Xilinx vs Altera
                132728: 08/06/05: MikeWhy: Re: Xilinx vs Altera
                    132736: 08/06/06: PFC: Re: Xilinx vs Altera
                    132763: 08/06/06: PFC: Re: Xilinx vs Altera
                132735: 08/06/06: Jim Granville: Re: Xilinx vs Altera
132648: 08/06/04: Stef: Compare and update in same clock cycle synthesis problem
    132665: 08/06/04: Thomas Stanka: Re: Compare and update in same clock cycle synthesis problem
        132757: 08/06/06: Stef: Re: Compare and update in same clock cycle synthesis problem
            132760: 08/06/06: RCIngham: Re: Compare and update in same clock cycle synthesis problem
                132765: 08/06/06: Stef: Re: Compare and update in same clock cycle synthesis problem
                    132799: 08/06/06: Mike Treseler: Re: Compare and update in same clock cycle synthesis problem
                        132801: 08/06/07: Stef: Re: Compare and update in same clock cycle synthesis problem
    132820: 08/06/07: rickman: Re: Compare and update in same clock cycle synthesis problem
        132836: 08/06/08: Stef: Re: Compare and update in same clock cycle synthesis problem
    132869: 08/06/09: Andy: Re: Compare and update in same clock cycle synthesis problem
132656: 08/06/05: Symon: Xilinx cuts 250 jobs.
    132659: 08/06/05: Jim Granville: Re: Xilinx cuts 250 jobs.
        132662: 08/06/04: Peter Alfke: Re: Xilinx cuts 250 jobs.
            132689: 08/06/05: Frank Buss: Re: Xilinx cuts 250 jobs.
                132694: 08/06/05: austin: Re: Xilinx cuts 250 jobs.
                132703: 08/06/05: Frank Buss: Re: Xilinx cuts 250 jobs.
        132672: 08/06/05: Jon Beniston: Re: Xilinx cuts 250 jobs.
        132692: 08/06/05: Peter Alfke: Re: Xilinx cuts 250 jobs.
        132696: 08/06/05: rickman: Re: Xilinx cuts 250 jobs.
        132705: 08/06/05: rickman: Re: Xilinx cuts 250 jobs.
            132734: 08/06/05: krw: Re: Xilinx cuts 250 jobs.
                132767: 08/06/06: Symon: Re: Xilinx cuts 250 jobs.
                    132768: 08/06/06: Symon: Re: Xilinx cuts 250 jobs.
                    132773: 08/06/06: PFC: Re: Xilinx cuts 250 jobs.
                    132802: 08/06/07: Symon: Re: Xilinx cuts 250 jobs.
                        132810: 08/06/07: Matthew Hicks: Re: Xilinx cuts 250 jobs.
                            132812: 08/06/07: MikeWhy: Re: Xilinx cuts 250 jobs.
                            132822: 08/06/07: rickman: Re: Xilinx cuts 250 jobs.
                    132805: 08/06/07: Matthew Hicks: Re: Xilinx cuts 250 jobs.
                        132813: 08/06/07: Andy Botterill: Re: Xilinx cuts 250 jobs.
            132737: 08/06/05: John_H: Re: Xilinx cuts 250 jobs.
                132739: 08/06/05: MikeWhy: Re: Xilinx cuts 250 jobs.
                    132742: 08/06/05: John_H: Re: Xilinx cuts 250 jobs.
                        132745: 08/06/05: MikeWhy: Re: Xilinx cuts 250 jobs.
            132743: 08/06/05: rickman: Re: Xilinx cuts 250 jobs.
                132758: 08/06/06: Matthew Hicks: Re: Xilinx cuts 250 jobs.
                132775: 08/06/06: rickman: Re: Xilinx cuts 250 jobs.
                    132806: 08/06/07: Matthew Hicks: Re: Xilinx cuts 250 jobs.
            132746: 08/06/06: Matthew Hicks: Re: Xilinx cuts 250 jobs.
        132759: 08/06/06: Jon Beniston: Re: Xilinx cuts 250 jobs.
        132779: 08/06/06: rickman: Re: Xilinx cuts 250 jobs.
        132781: 08/06/06: John_H: Re: Xilinx cuts 250 jobs.
    132701: 08/06/05: joe4702: Re: Xilinx cuts 250 jobs.
    132804: 08/06/06: Bob Perlman: Re: Xilinx cuts 250 jobs.
132658: 08/06/04: <leumig78@hotmail.com>: EAPR and EDK 9.1.02i
132660: 08/06/05: Jim Granville: A new FPGA company comes out of Stealth mode - SiliconBlue
    132686: 08/06/05: Gabor: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
        132695: 08/06/05: austin: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
            132720: 08/06/05: austin: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
            132727: 08/06/06: Jim Granville: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
                132829: 08/06/07: Steve Knapp: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
            132776: 08/06/06: Mike Harrison: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
            132785: 08/06/06: Steve Knapp: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
        132719: 08/06/05: Leon: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
        132721: 08/06/05: rickman: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
        132726: 08/06/05: Thomas Stanka: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
        132730: 08/06/06: Jim Granville: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
        132828: 08/06/07: Steve Knapp: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
    132782: 08/06/06: Steve Knapp: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
        132793: 08/06/06: Tommy Thorn: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
            132826: 08/06/07: Steve Knapp: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
        132800: 08/06/07: Jim Granville: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
            132827: 08/06/07: Steve Knapp: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
132664: 08/06/04: <muthusnv@gmail.com>: UART master core
    132678: 08/06/05: Moti Litochevski: Re: UART master core
132670: 08/06/05: fazulu deen: FPGA clock frequency
    132674: 08/06/05: Jonathan Bromley: Re: FPGA clock frequency
        132684: 08/06/05: Symon: Re: FPGA clock frequency
            132690: 08/06/05: Jonathan Bromley: Re: FPGA clock frequency
                132702: 08/06/05: Jonathan Bromley: Re: FPGA clock frequency
                    132716: 08/06/05: Jonathan Bromley: Re: FPGA clock frequency
                    132798: 08/06/06: Mike Treseler: Re: FPGA clock frequency
                        132815: 08/06/07: Jonathan Bromley: Re: FPGA clock frequency
                            132842: 08/06/09: Symon: Re: FPGA clock frequency
                            132844: 08/06/09: PFC: Re: FPGA clock frequency
                                132864: 08/06/09: PFC: Re: FPGA clock frequency
                                    132899: 08/06/10: PFC: Re: FPGA clock frequency
                                        132931: 08/06/10: MikeWhy: Re: FPGA clock frequency
                                            132988: 08/06/12: Symon: Re: FPGA clock frequency
                                                132996: 08/06/12: MikeWhy: Re: FPGA clock frequency
                                                    133002: 08/06/13: Symon: Re: FPGA clock frequency
                                            133013: 08/06/13: MikeWhy: Re: FPGA clock frequency
                                            133021: 08/06/13: glen herrmannsfeldt: Re: FPGA clock frequency
                                                133049: 08/06/16: Mike Lewis: Re: FPGA clock frequency
                                                133066: 08/06/16: glen herrmannsfeldt: Re: FPGA clock frequency
                            132853: 08/06/09: John_H: Re: FPGA clock frequency
        132850: 08/06/09: glen herrmannsfeldt: Re: FPGA clock frequency
    132681: 08/06/05: faza: Re: FPGA clock frequency
    132700: 08/06/05: faza: Re: FPGA clock frequency
    132706: 08/06/05: faza: Re: FPGA clock frequency
    132738: 08/06/05: John_H: Re: FPGA clock frequency
        132740: 08/06/05: MikeWhy: Re: FPGA clock frequency
    132761: 08/06/06: faza: Re: FPGA clock frequency
    132841: 08/06/09: faza: Re: FPGA clock frequency
    132848: 08/06/09: faza: Re: FPGA clock frequency
    132858: 08/06/09: faza: Re: FPGA clock frequency
    132860: 08/06/09: John_H: Re: FPGA clock frequency
    132894: 08/06/10: faza: Re: FPGA clock frequency
    132905: 08/06/10: faza: Re: FPGA clock frequency
    132906: 08/06/10: faza: Re: FPGA clock frequency
    132987: 08/06/12: faza: Re: FPGA clock frequency
    133046: 08/06/16: faza: Re: FPGA clock frequency
    133063: 08/06/16: faza: Re: FPGA clock frequency
    133075: 08/06/17: faza: Re: FPGA clock frequency
132676: 08/06/05: <muthusnv@gmail.com>: Anyone used HiTech global boards?
132680: 08/06/05: timinganalyzer: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132688: 08/06/05: FP: Spartan3 interface with DDR SDRAM
    132697: 08/06/05: <ghelbig@gmail.com>: Re: Spartan3 interface with DDR SDRAM
    132699: 08/06/05: Symon: Re: Spartan3 interface with DDR SDRAM
132691: 08/06/05: rickman: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132707: 08/06/05: KJ: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132710: 08/06/05: KJ: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132711: 08/06/05: Jonathan Bromley: Your favourite DSP textbooks/websites?
    132714: 08/06/05: MikeWhy: Re: Your favourite DSP textbooks/websites?
        132717: 08/06/05: Jonathan Bromley: Re: Your favourite DSP textbooks/websites?
        132755: 08/06/06: Martin Thompson: Re: Your favourite DSP textbooks/websites?
    132715: 08/06/05: Gabor: Re: Your favourite DSP textbooks/websites?
    132762: 08/06/06: Maik H.: Re: Your favourite DSP textbooks/websites?
    132766: 08/06/06: Symon: Re: Your favourite DSP textbooks/websites?
    132816: 08/06/07: Jonathan Bromley: Re: Your favourite DSP textbooks/websites?
132712: 08/06/05: rickman: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132718: 08/06/05: JeDi: HDL tricks for better timing closure in FPGAs
    132729: 08/06/05: KJ: Re: HDL tricks for better timing closure in FPGAs
        132747: 08/06/05: jtw: Re: HDL tricks for better timing closure in FPGAs
            132794: 08/06/06: Icky Thwacket: Re: HDL tricks for better timing closure in FPGAs
            132811: 08/06/06: jtw: Re: HDL tricks for better timing closure in FPGAs
            132817: 08/06/07: Joseph Samson: Re: HDL tricks for better timing closure in FPGAs
                132818: 08/06/07: Joseph Samson: Re: HDL tricks for better timing closure in FPGAs
                    132824: 08/06/07: Mike Treseler: Re: HDL tricks for better timing closure in FPGAs
            132823: 08/06/07: Nico Coesel: Re: HDL tricks for better timing closure in FPGAs
                132830: 08/06/07: jtw: Re: HDL tricks for better timing closure in FPGAs
            132849: 08/06/09: glen herrmannsfeldt: Re: HDL tricks for better timing closure in FPGAs
    132787: 08/06/06: JeDi: Re: HDL tricks for better timing closure in FPGAs
    132788: 08/06/06: Aiken: Re: HDL tricks for better timing closure in FPGAs
    132795: 08/06/06: KJ: Re: HDL tricks for better timing closure in FPGAs
132732: 08/06/05: Randy Yates: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132748: 08/06/05: iCE65 Ultra-Low Power FPGAs: ANNOUNCE: SiliconBlue Pioneers New FPGA Technology for Handheld, Ultra-Low Power Applications
    132750: 08/06/06: Jim Granville: Re: ANNOUNCE: SiliconBlue Pioneers New FPGA Technology for Handheld,
    132751: 08/06/05: John_H: Re: ANNOUNCE: SiliconBlue Pioneers New FPGA Technology for Handheld,
132769: 08/06/06: Jack: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132780: 08/06/06: Denkedran Joe: length compensation for RocketIO channels
    132792: 08/06/06: Symon: Re: length compensation for RocketIO channels
132783: 08/06/06: Denkedran Joe: FPGA to FLASH and back?
    132790: 08/06/06: morphiend: Re: FPGA to FLASH and back?
        132981: 08/06/12: Denkedran Joe: Re: FPGA to FLASH and back?
    132982: 08/06/12: Hauke D: Re: FPGA to FLASH and back?
132786: 08/06/06: HT-Lab: 1 Pin MTE Cable
    132797: 08/06/06: Rich Webb: Re: 1 Pin MTE Cable
    132819: 08/06/07: M.Randelzhofer: Re: 1 Pin MTE Cable
132803: 08/06/06: rickman: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
    133226: 08/06/21: Albert van der Horst: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132808: 08/06/06: CBFalconer: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132809: 08/06/07: Randy Yates: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132814: 08/06/07: Didi: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132821: 08/06/07: rickman: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132825: 08/06/07: Randy Yates: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132831: 08/06/07: bjzhangwn@gmail.com: NIOS-II+LAN91C111
    132833: 08/06/08: bjzhangwn@gmail.com: Re: NIOS-II+LAN91C111
        132846: 08/06/09: PFC: Re: NIOS-II+LAN91C111
132832: 08/06/07: bjzhangwn@gmail.com: NIOS-II+LAN91C111
132834: 08/06/08: kookoo4systemverilog: Aldec Active-HDL and Xilinx/Altera FPGA-vendor library support
    132835: 08/06/08: Mike Treseler: Re: Aldec Active-HDL and Xilinx/Altera FPGA-vendor library support
        132887: 08/06/09: TSIuser: Re: Aldec Active-HDL and Xilinx/Altera FPGA-vendor library support
            132902: 08/06/10: Mike Treseler: Re: Aldec Active-HDL and Xilinx/Altera FPGA-vendor library support
    132904: 08/06/10: <pontus.stenstrom@gmail.com>: Re: Aldec Active-HDL and Xilinx/Altera FPGA-vendor library support
132837: 08/06/08: timinganalyzer: ANNOUNCE: TimingAnalyzer -- new updated version
    132962: 08/06/11: rickman: Re: ANNOUNCE: TimingAnalyzer -- new updated version
    132999: 08/06/12: timinganalyzer: Re: ANNOUNCE: TimingAnalyzer -- new updated version
    133003: 08/06/12: rickman: Re: ANNOUNCE: TimingAnalyzer -- new updated version
132838: 08/06/08: Bill Ngo: Deskew Clock on Synchronous Bus
    132852: 08/06/09: Gabor: Re: Deskew Clock on Synchronous Bus
        132884: 08/06/09: Bill Ngo: Re: Deskew Clock on Synchronous Bus
        132908: 08/06/10: Gabor: Re: Deskew Clock on Synchronous Bus
        132912: 08/06/10: kkoorndyk: Re: Deskew Clock on Synchronous Bus
132839: 08/06/08: vikram: FPGA reprogrammable? (urgent)
    132840: 08/06/08: Tom: Re: FPGA reprogrammable? (urgent)
    132843: 08/06/09: PFC: Re: FPGA reprogrammable? (urgent)
    132889: 08/06/09: vikram: Re: FPGA reprogrammable? (urgent)
132845: 08/06/09: techG: TI DSP + Virtex-5 using EMIF interface
    132847: 08/06/09: Kolja Sulimma: Re: TI DSP + Virtex-5 using EMIF interface
    132851: 08/06/09: Moazzam: Re: TI DSP + Virtex-5 using EMIF interface
132854: 08/06/09: rickman: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132855: 08/06/09: FP: SDRAM controller
    132865: 08/06/09: Nico Coesel: Re: SDRAM controller
    132867: 08/06/09: PFC: Re: SDRAM controller
    132877: 08/06/09: Eric Smith: Re: SDRAM controller
    132895: 08/06/10: Martin Thompson: Re: SDRAM controller
132856: 08/06/09: rickman: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132857: 08/06/09: Wei Wang: readmem[b|h]
    132862: 08/06/09: Guenter Dannoritzer: Re: readmem[b|h]
    132870: 08/06/09: Kevin Neilson: Re: readmem[b|h]
132859: 08/06/09: <chrisdekoh@gmail.com>: how to prevent timer code firmware running on Microblaze from being
    132863: 08/06/09: <ghelbig@lycos.com>: Re: how to prevent timer code firmware running on Microblaze from
    132868: 08/06/09: PFC: Re: how to prevent timer code firmware running on Microblaze from being optimised
        132872: 08/06/09: David Brown: Re: how to prevent timer code firmware running on Microblaze from
            132875: 08/06/09: Rich Webb: Re: how to prevent timer code firmware running on Microblaze from being optimised
            132885: 08/06/10: PFC: Re: how to prevent timer code firmware running on Microblaze from being optimised
                132893: 08/06/10: David Brown: Re: how to prevent timer code firmware running on Microblaze from
                    132929: 08/06/10: David Brown: Re: how to prevent timer code firmware running on Microblaze from
        132886: 08/06/09: Jack Klein: Re: how to prevent timer code firmware running on Microblaze from being optimised
    132871: 08/06/09: <cs_posting@hotmail.com>: Re: how to prevent timer code firmware running on Microblaze from
    132881: 08/06/09: <cs_posting@hotmail.com>: Re: how to prevent timer code firmware running on Microblaze from
    132911: 08/06/10: <chrisdekoh@gmail.com>: Re: how to prevent timer code firmware running on Microblaze from
132861: 08/06/09: Randy Yates: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132873: 08/06/09: CBFalconer: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132874: 08/06/09: Andy Botterill: how to track down an optimised away signal
    132876: 08/06/09: Mike Treseler: Re: how to track down an optimised away signal
        132878: 08/06/09: Andy Botterill: Re: how to track down an optimised away signal
            132879: 08/06/09: Mike Treseler: Re: how to track down an optimised away signal
    132880: 08/06/09: Symon: Re: how to track down an optimised away signal
    132907: 08/06/10: Muzaffer Kal: Re: how to track down an optimised away signal
        132926: 08/06/10: Andy Botterill: Re: how to track down an optimised away signal
            132927: 08/06/10: Mike Treseler: Re: how to track down an optimised away signal
132882: 08/06/09: ajith.thamara@gmail.com: aurora channel initialization fails
132888: 08/06/09: vikram: fpga reprogrammable?
    132890: 08/06/09: Peter Alfke: Re: fpga reprogrammable?
        132941: 08/06/10: Alex Freed: Re: fpga reprogrammable?
            132945: 08/06/10: Alex Freed: Re: fpga reprogrammable?
                132973: 08/06/11: PFC: Re: fpga reprogrammable?
            133022: 08/06/13: glen herrmannsfeldt: Re: fpga reprogrammable?
    132909: 08/06/10: Gabor: Re: fpga reprogrammable?
    132943: 08/06/10: Peter Alfke: Re: fpga reprogrammable?
    132958: 08/06/11: Peter Alfke: Re: fpga reprogrammable?
132891: 08/06/10: ALuPin@web.de: FSM running with unstable clock
    132897: 08/06/10: RCIngham: Re: FSM running with unstable clock
    132915: 08/06/10: Peter Alfke: Re: FSM running with unstable clock
    132946: 08/06/11: ALuPin@web.de: Re: FSM running with unstable clock
    133026: 08/06/13: glen herrmannsfeldt: Re: FSM running with unstable clock
132892: 08/06/10: Ambreen Ashfaq Afridi: where is the IP address assigned to the fpga in Trimode Ethernet MAC
    132896: 08/06/10: RL: Re: where is the IP address assigned to the fpga in Trimode Ethernet
    132898: 08/06/10: PFC: Re: where is the IP address assigned to the fpga in Trimode Ethernet MAC Core???
        132989: 08/06/12: RCIngham: Re: where is the IP address assigned to the fpga in Trimode Ethernet MAC Core???
        133025: 08/06/13: glen herrmannsfeldt: Re: where is the IP address assigned to the fpga in Trimode Ethernet
    132900: 08/06/10: glen herrmannsfeldt: Re: where is the IP address assigned to the fpga in Trimode Ethernet
    132980: 08/06/12: <silver.glimmer@gmail.com>: Re: where is the IP address assigned to the fpga in Trimode Ethernet
132901: 08/06/10: Saransh: Error while compiling uClinux image for Microblaze
132910: 08/06/10: Modellpilot: Digital VSB (Vestigial Side Band) Modulator for Analog TV
    132914: 08/06/10: John_H: Re: Digital VSB (Vestigial Side Band) Modulator for Analog TV
    132922: 08/06/10: John_H: Re: Digital VSB (Vestigial Side Band) Modulator for Analog TV
    133024: 08/06/13: glen herrmannsfeldt: Re: Digital VSB (Vestigial Side Band) Modulator for Analog TV
132913: 08/06/10: Kolja Sulimma: Strange Virtex-4FX 8b10b encoding behaviour
132916: 08/06/10: John_H: Whitepapers are taking over the lost TechXclusives
    132917: 08/06/10: Peter Alfke: Re: Whitepapers are taking over the lost TechXclusives
    132918: 08/06/10: Steve Knapp: Re: Whitepapers are taking over the lost TechXclusives
    132919: 08/06/10: Tommy Thorn: Re: Whitepapers are taking over the lost TechXclusives
    132930: 08/06/10: Peter Alfke: Re: Whitepapers are taking over the lost TechXclusives
132920: 08/06/10: Rob Gaddi: Cheating the FPGA clock speed
    132923: 08/06/10: <raghunandan85@gmail.com>: Re: Cheating the FPGA clock speed
    132924: 08/06/10: Mike Treseler: Re: Cheating the FPGA clock speed
    132925: 08/06/11: Jim Granville: Re: Cheating the FPGA clock speed
    132928: 08/06/10: HT-Lab: Re: Cheating the FPGA clock speed
    132932: 08/06/10: Gabor: Re: Cheating the FPGA clock speed
    132953: 08/06/11: austin: Re: Cheating the FPGA clock speed
        132966: 08/06/11: Gabor: Re: Cheating the FPGA clock speed
            132967: 08/06/11: austin: Re: Cheating the FPGA clock speed
    133067: 08/06/17: backhus: Re: Cheating the FPGA clock speed
132921: 08/06/10: Leon: Altera Quartus Web Edition 8.0 available
    132947: 08/06/11: Henry Wong: Re: Altera Quartus Web Edition 8.0 available
        132995: 08/06/12: Henry Wong: Re: Altera Quartus Web Edition 8.0 available
        132997: 08/06/12: Mike Treseler: Re: Altera Quartus Web Edition 8.0 available
            132998: 08/06/12: Frank Buss: Re: Altera Quartus Web Edition 8.0 available
    132978: 08/06/11: Tommy Thorn: Re: Altera Quartus Web Edition 8.0 available
    133010: 08/06/13: Tommy Thorn: Re: Altera Quartus Web Edition 8.0 available
132933: 08/06/10: MM: Trouble programming V4FX40
    132935: 08/06/11: Fred: Re: Trouble programming V4FX40
        132937: 08/06/10: MM: Re: Trouble programming V4FX40
    132936: 08/06/10: John_H: Re: Trouble programming V4FX40
        132938: 08/06/10: MM: Re: Trouble programming V4FX40
            132939: 08/06/10: John_H: Re: Trouble programming V4FX40
                132942: 08/06/10: MM: Re: Trouble programming V4FX40
                132950: 08/06/11: John_H: Re: Trouble programming V4FX40
                    132952: 08/06/11: MM: Re: Trouble programming V4FX40
            132940: 08/06/10: Ed McGettigan: Re: Trouble programming V4FX40
                132944: 08/06/10: MM: Re: Trouble programming V4FX40
                    132955: 08/06/11: Ed McGettigan: Re: Trouble programming V4FX40
                        132960: 08/06/11: MM: Re: Trouble programming V4FX40
                            132969: 08/06/11: MM: Re: Trouble programming V4FX40
                                132970: 08/06/11: MM: Re: Trouble programming V4FX40
                                    132975: 08/06/11: PFC: Re: Trouble programming V4FX40
                                        132976: 08/06/11: MM: Re: Trouble programming V4FX40
                                        132983: 08/06/12: Symon: Re: Trouble programming V4FX40
                                            132984: 08/06/12: PFC: Re: Trouble programming V4FX40
                                                132985: 08/06/12: Symon: Re: Trouble programming V4FX40
                                                    132986: 08/06/12: PFC: Re: Trouble programming V4FX40
                                            133006: 08/06/12: BobW: Re: Trouble programming V4FX40
                                132971: 08/06/11: PFC: Re: Trouble programming V4FX40
132934: 08/06/10: Jim Flanagan: Dram Refresh Controller Tutorial wanted
    132949: 08/06/11: Gabor: Re: Dram Refresh Controller Tutorial wanted
132951: 08/06/11: Charles Xavier: FPGA to solve the two most annoying problems on usenet - Suggestions
    132954: 08/06/11: Atilla Filiz: Re: FPGA to solve the two most annoying problems on usenet -
    132956: 08/06/11: Jon Beniston: Re: FPGA to solve the two most annoying problems on usenet -
    132957: 08/06/11: Charles Xavier: Re: FPGA to solve the two most annoying problems on usenet -
    132974: 08/06/11: PFC: Re: FPGA to solve the two most annoying problems on usenet - Suggestions Welcome
    133011: 08/06/13: Eric Smith: Re: FPGA to solve the two most annoying problems on usenet - Suggestions Welcome
        133036: 08/06/14: Symon: Re: FPGA to solve the two most annoying problems on usenet - Suggestions Welcome
            133052: 08/06/16: Mike Treseler: Re: FPGA to solve the two most annoying problems on usenet - Suggestions
    133031: 08/06/14: Charles Xavier: Re: FPGA to solve the two most annoying problems on usenet -
    133043: 08/06/15: Charles Xavier: Re: FPGA to solve the two most annoying problems on usenet -
    133044: 08/06/16: Andreas Ehliar: Re: FPGA to solve the two most annoying problems on usenet - Suggestions Welcome
    133048: 08/06/16: John Larkin: Re: FPGA to solve the two most annoying problems on usenet - Suggestions Welcome
    133050: 08/06/16: Aiken: Re: FPGA to solve the two most annoying problems on usenet -
    133088: 08/06/17: Arash Partow: Re: FPGA to solve the two most annoying problems on usenet -
132959: 08/06/11: austin: New Home
    132963: 08/06/11: Joseph H Allen: Re: New Home
        132964: 08/06/11: austin: Re: New Home
    132968: 08/06/11: Jon Elson: Re: New Home
132961: 08/06/11: ni: DISABLING POWERPC IN VIRTEXII PRO
    132965: 08/06/11: austin: Re: DISABLING POWERPC IN VIRTEXII PRO
    132991: 08/06/12: ni: Re: DISABLING POWERPC IN VIRTEXII PRO
132972: 08/06/11: <tejaswyh@gmail.com>: PLB master : Split bus architecture
132977: 08/06/11: <cpld.fpga.asic@gmail.com>: Link for Joining the FPGA/CPLD Design Group on LinkedIn
132979: 08/06/11: vikram: Xilinx EDK - LibGen Error!!!
132990: 08/06/12: ni: chipscope analyzer error
    132992: 08/06/12: Alan Nishioka: Re: chipscope analyzer error
        132993: 08/06/12: Symon: Re: chipscope analyzer error
    133005: 08/06/12: Alan Nishioka: Re: chipscope analyzer error
    133009: 08/06/13: Nitesh: Re: chipscope analyzer error
    133017: 08/06/13: ni: Re: chipscope analyzer error
    133480: 08/07/01: oscar: Re: chipscope analyzer error
132994: 08/06/12: <cpld.fpga.asic@gmail.com>: Automotive Temperature +100 deg C+ FPGA's -- who's parts are
    133000: 08/06/12: Icky Thwacket: Re: Automotive Temperature +100 deg C+ FPGA's -- who's parts are available from stock
    133001: 08/06/12: austin: Re: Automotive Temperature +100 deg C+ FPGA's -- who's parts are
133012: 08/06/13: ni: export to project naigator
    133018: 08/06/13: ni: Re: export to project naigator
133014: 08/06/13: aleksa: CPLD beginner questions
    133015: 08/06/14: PFC: Re: CPLD beginner questions
    133016: 08/06/14: Jim Granville: Re: CPLD beginner questions
        133019: 08/06/14: Uwe Bonnes: Re: CPLD beginner questions
            133020: 08/06/14: Jim Granville: Re: CPLD beginner questions
    133028: 08/06/14: aleksa: Re: CPLD beginner questions
        133029: 08/06/14: Jim Granville: Re: CPLD beginner questions
        133032: 08/06/14: PFC: Re: CPLD beginner questions
    133035: 08/06/14: Nitro: Re: CPLD beginner questions
    133047: 08/06/16: Dave Pollum: Re: CPLD beginner questions
133030: 08/06/14: Jim Flanagan: Old Mits Dram Datasheet Search
    133033: 08/06/14: Jonathan Bromley: Re: Old Mits Dram Datasheet Search
133037: 08/06/14: Klaus Petersen: Simulate Microblaze in System Generator
133038: 08/06/14: WyndyPickle: FPGA IO Pin Unwanted Coupling
    133039: 08/06/14: Peter Alfke: Re: FPGA IO Pin Unwanted Coupling
    133040: 08/06/15: Jim Granville: Re: FPGA IO Pin Unwanted Coupling
133041: 08/06/15: fl: How to define the Dout width of DA FIR logic Core
    133054: 08/06/16: Kevin Neilson: Re: How to define the Dout width of DA FIR logic Core
133042: 08/06/15: arko: Will Modelsim XE 6.3c (Win32) run in Linux/WINE?
    133051: 08/06/16: morphiend: Re: Will Modelsim XE 6.3c (Win32) run in Linux/WINE?
    133080: 08/06/17: ghelbig: Re: Will Modelsim XE 6.3c (Win32) run in Linux/WINE?
        133081: 08/06/17: HT-Lab: Re: Will Modelsim XE 6.3c (Win32) run in Linux/WINE?
            133083: 08/06/17: HT-Lab: Re: Will Modelsim XE 6.3c (Win32) run in Linux/WINE?
        133082: 08/06/17: ghelbig: Re: Will Modelsim XE 6.3c (Win32) run in Linux/WINE?
133045: 08/06/16: RealInfo: WARP
    133053: 08/06/16: Mike Treseler: Re: WARP
        133055: 08/06/16: ghelbig: Re: WARP
            133057: 08/06/17: RealInfo: Re: WARP
                133065: 08/06/17: backhus: Re: WARP
                    133071: 08/06/17: RealInfo: Re: WARP
133056: 08/06/16: water9580@yahoo.com: TXCOMSTART/TXCMOTYPE of V5 SATA GTP with ISE10.1.1
133058: 08/06/16: explore: XAUI v7.2 - timing issue - *channel bonding attributes*
    133059: 08/06/16: Ed McGettigan: Re: XAUI v7.2 - timing issue - *channel bonding attributes*
        133061: 08/06/16: Ed McGettigan: Re: XAUI v7.2 - timing issue - *channel bonding attributes*
            134037: 08/07/22: jaink: Re: XAUI v7.2 - timing issue - *channel bonding attributes*
                136309: 08/11/10: pkirchhoff: Re: XAUI v7.2 - timing issue - *channel bonding attributes*
    133060: 08/06/16: explore: Re: XAUI v7.2 - timing issue - *channel bonding attributes*
133062: 08/06/16: <fpgaasicdesigner@gmail.com>: Rocket IO alignment, clocks
133064: 08/06/16: vikram: Base System Builder problem... no board
133068: 08/06/17: vikram: FPGA configuration Beginner questions...
    133078: 08/06/17: Hauke D: Re: FPGA configuration Beginner questions...
        133086: 08/06/17: MikeWhy: Re: FPGA configuration Beginner questions...
    133079: 08/06/17: Hauke D: Re: FPGA configuration Beginner questions...
    133089: 08/06/17: vikram: Re: FPGA configuration Beginner questions...
133069: 08/06/17: XSterna: Virtex5 FPGA Board and USB interface
    133070: 08/06/17: Nial Stewart: Re: Virtex5 FPGA Board and USB interface
    133077: 08/06/17: Hauke D: Re: Virtex5 FPGA Board and USB interface
    133095: 08/06/18: XSterna: Re: Virtex5 FPGA Board and USB interface
    133121: 08/06/18: <biancimass@gmail.com>: Re: Virtex5 FPGA Board and USB interface
    133192: 08/06/20: XSterna: Re: Virtex5 FPGA Board and USB interface
133072: 08/06/17: jack.harvard@googlemail.com: Xilinx Spartan FPGA BlockRAM in Simulation
    133074: 08/06/17: Zorjak: Re: Xilinx Spartan FPGA BlockRAM in Simulation
133073: 08/06/17: Zorjak: Basic Questions about MIG (Memory Interface Generator)
    133114: 08/06/18: Barry: Re: Basic Questions about MIG (Memory Interface Generator)
    133144: 08/06/19: Zorjak: Re: Basic Questions about MIG (Memory Interface Generator)
    133204: 08/06/20: Barry: Re: Basic Questions about MIG (Memory Interface Generator)
133076: 08/06/17: Dave: Cadence offers to buy Mentor Graphics for $1.45B
    133084: 08/06/17: HT-Lab: Re: Cadence offers to buy Mentor Graphics for $1.45B
    133087: 08/06/18: Joseph H Allen: Re: Cadence offers to buy Mentor Graphics for $1.45B
    133099: 08/06/18: RCIngham: Re: Cadence offers to buy Mentor Graphics for $1.45B
133085: 08/06/17: jon: Altera Cyclone II EP2C20F484C6N
    133116: 08/06/18: jon: Re: Altera Cyclone II EP2C20F484C6N
133090: 08/06/18: RealInfo: Xilinx Webpack
    133091: 08/06/18: Uwe Bonnes: Re: Xilinx Webpack
    133107: 08/06/18: austin: Re: Xilinx Webpack
        133122: 08/06/18: BobW: Re: Xilinx Webpack
        133126: 08/06/18: Pete Fraser: Re: Xilinx Webpack
            133127: 08/06/18: austin: Re: Xilinx Webpack
                133129: 08/06/18: Pete Fraser: Re: Xilinx Webpack
                    133134: 08/06/18: austin: Re: Xilinx Webpack
                    133136: 08/06/18: MikeWhy: Re: Xilinx Webpack
                        133166: 08/06/19: austin: Re: Xilinx Webpack
133092: 08/06/18: Rob: Synthesis results when testing for 'X' and 'U'
    133093: 08/06/18: Kolja Sulimma: Re: Synthesis results when testing for 'X' and 'U'
        133105: 08/06/18: Brian Drummond: Re: Synthesis results when testing for 'X' and 'U'
            133106: 08/06/18: HT-Lab: Re: Synthesis results when testing for 'X' and 'U'
                133109: 08/06/18: HT-Lab: Re: Synthesis results when testing for 'X' and 'U'
                    133115: 08/06/18: HT-Lab: Re: Synthesis results when testing for 'X' and 'U'
            133130: 08/06/18: Hal Murray: Re: Synthesis results when testing for 'X' and 'U'
            133154: 08/06/19: Brian Drummond: Re: Synthesis results when testing for 'X' and 'U'
                133169: 08/06/19: Mike Treseler: Re: Synthesis results when testing for 'X' and 'U'
        133152: 08/06/19: Brian Drummond: Re: Synthesis results when testing for 'X' and 'U'
    133097: 08/06/18: rickman: Re: Synthesis results when testing for 'X' and 'U'
    133098: 08/06/18: Rob: Re: Synthesis results when testing for 'X' and 'U'
    133103: 08/06/18: Kolja Sulimma: Re: Synthesis results when testing for 'X' and 'U'
    133104: 08/06/18: Kolja Sulimma: Re: Synthesis results when testing for 'X' and 'U'
    133108: 08/06/18: KJ: Re: Synthesis results when testing for 'X' and 'U'
    133110: 08/06/18: Kolja Sulimma: Re: Synthesis results when testing for 'X' and 'U'
    133117: 08/06/18: Rob: Re: Synthesis results when testing for 'X' and 'U'
    133119: 08/06/18: Rob: Re: Synthesis results when testing for 'X' and 'U'
    133123: 08/06/18: rickman: Re: Synthesis results when testing for 'X' and 'U'
    133124: 08/06/18: rickman: Re: Synthesis results when testing for 'X' and 'U'
    133125: 08/06/18: Mike Treseler: Re: Synthesis results when testing for 'X' and 'U'
    133156: 08/06/19: rickman: Re: Synthesis results when testing for 'X' and 'U'
133094: 08/06/18: faza: Fixed point number hardware implementation
    133096: 08/06/18: KJ: Re: Fixed point number hardware implementation
        133720: 08/07/11: kami: Re: Fixed point number hardware implementation
            133728: 08/07/11: kami: Re: Fixed point number hardware implementation
                133743: 08/07/12: kami: Re: Fixed point number hardware implementation
            133749: 08/07/12: kami: Re: Fixed point number hardware implementation
                133761: 08/07/13: KJ: Re: Fixed point number hardware implementation
                    134231: 08/07/31: kami: Re: Fixed point number hardware implementation
                        134237: 08/07/31: MikeWhy: Re: Fixed point number hardware implementation
                            134242: 08/07/31: kami: Re: Fixed point number hardware implementation
                                134251: 08/08/01: MikeWhy: Re: Fixed point number hardware implementation
                                    134270: 08/08/03: kami: Re: Fixed point number hardware implementation
    133100: 08/06/18: RCIngham: Re: Fixed point number hardware implementation
        133140: 08/06/19: Jeff Cunningham: Re: Fixed point number hardware implementation
            133150: 08/06/19: KJ: Re: Fixed point number hardware implementation
            133161: 08/06/19: John_H: Re: Fixed point number hardware implementation
        133155: 08/06/19: Brian Drummond: Re: Fixed point number hardware implementation
    133111: 08/06/18: faza: Re: Fixed point number hardware implementation
    133112: 08/06/18: KJ: Re: Fixed point number hardware implementation
    133135: 08/06/18: Andrew FPGA: Re: Fixed point number hardware implementation
    133147: 08/06/19: faza: Re: Fixed point number hardware implementation
    133191: 08/06/20: faza: Re: Fixed point number hardware implementation
    133195: 08/06/20: Andrew FPGA: Re: Fixed point number hardware implementation
    133198: 08/06/20: faza: Re: Fixed point number hardware implementation
    133724: 08/07/11: KJ: Re: Fixed point number hardware implementation
    133727: 08/07/11: rickman: Re: Fixed point number hardware implementation
    133730: 08/07/11: rickman: Re: Fixed point number hardware implementation
    133735: 08/07/12: dadabuley@gmail.com: Re: Fixed point number hardware implementation
    133753: 08/07/13: rickman: Re: Fixed point number hardware implementation
133101: 08/06/18: Zorjak: MIG core generator problem
    133145: 08/06/19: Thomas Reinemann: Re: MIG core generator problem
133102: 08/06/18: <robquigley@gmail.com>: Precision Synthesis verilog netlist black box question
133113: 08/06/18: Beantown: Mapping the DCM clock output onto a global buffer
    133120: 08/06/18: John_H: Re: Mapping the DCM clock output onto a global buffer
    133128: 08/06/18: Beantown: Re: Mapping the DCM clock output onto a global buffer
    133131: 08/06/18: John_H: Re: Mapping the DCM clock output onto a global buffer
    133173: 08/06/19: Beantown: Re: Mapping the DCM clock output onto a global buffer
    133175: 08/06/19: Beantown: Re: Mapping the DCM clock output onto a global buffer
    133176: 08/06/19: John_H: Re: Mapping the DCM clock output onto a global buffer
    133180: 08/06/19: Kolja Sulimma: Re: Mapping the DCM clock output onto a global buffer
133118: 08/06/18: fl: Question about coefficient padding
133132: 08/06/18: Patrick Dubois: =?windows-1252?Q?NVIDIA=92s_Tesla_T10P_Blurs_Some_Lines?=
    133133: 08/06/19: Jim Granville: Re: =?windows-1252?Q?NVIDIA=92s_Tesla_T10P_Blurs_Some_?=
        133138: 08/06/18: Jeff Cunningham: Re: =?windows-1252?Q?NVIDIA=92s_Tesla_T10P_Blurs_Some_?=
            133146: 08/06/19: Symon: Re: NVIDIA’s Tesla T10P Blurs Some Lines
                133149: 08/06/19: Jonathan Bromley: Re: NVIDIA’s Tesla T10P Blurs Some Lines
                    133158: 08/06/19: Brian Drummond: Re: NVIDIA’s Tesla T10P Blurs Some Lines
                133266: 08/06/23: c d saunter: Re: NVIDIA’s Tesla T10P Blurs Some Lines
            133179: 08/06/19: Dave: Re: =?windows-1252?Q?NVIDIA=92s_Tesla_T10P_Blurs_Some_?=
                133181: 08/06/19: MikeWhy: =?Windows-1252?Q?Re:_NVIDIA=92s_Tesla_T10P_Blurs_Some_Lines?=
                    133182: 08/06/20: Symon: Re: NVIDIA’s Tesla T10P Blurs Some Lines
                        133189: 08/06/19: MikeWhy: =?Windows-1252?Q?Re:_NVIDIA=92s_Tesla_T10P_Blurs_Some_Lines?=
                            133194: 08/06/20: Symon: Re: NVIDIA’s Tesla T10P Blurs Some Lines
                    133187: 08/06/19: Dave: Re: =?windows-1252?Q?NVIDIA=92s_Tesla_T10P_Blurs_Some_?=
                        133188: 08/06/19: MikeWhy: =?Windows-1252?Q?Re:_NVIDIA=92s_Tesla_T10P_Blurs_Some_Lines?=
                            133190: 08/06/20: Dave: Re: =?windows-1252?Q?NVIDIA=92s_Tesla_T10P_Blurs_Some_?=
                                133208: 08/06/20: MikeWhy: =?Windows-1252?Q?Re:_NVIDIA=92s_Tesla_T10P_Blurs_Some_Lines?=
                                    133224: 08/06/21: Dave: Re: =?windows-1252?Q?NVIDIA=92s_Tesla_T10P_Blurs_Some_?=
    133171: 08/06/19: Patrick Dubois: =?windows-1252?Q?Re=3A_NVIDIA=92s_Tesla_T10P_Blurs_Some_Lines?=
133137: 08/06/18: SynopsysFPGAexpress: which commercial HDL-Simulator for FPGA?
    133142: 08/06/18: Mike Treseler: Re: which commercial HDL-Simulator for FPGA?
        133183: 08/06/19: SynopsysFPGAexpress: Re: which commercial HDL-Simulator for FPGA?
    133143: 08/06/18: Muzaffer Kal: Re: which commercial HDL-Simulator for FPGA?
        133159: 08/06/19: Brian Drummond: Re: which commercial HDL-Simulator for FPGA?
        133163: 08/06/19: <jprovidenza@yahoo.com>: Re: which commercial HDL-Simulator for FPGA?
    133170: 08/06/19: Kevin Neilson: Re: which commercial HDL-Simulator for FPGA?
        133172: 08/06/19: Joseph H Allen: Re: which commercial HDL-Simulator for FPGA?
            133177: 08/06/19: Joseph H Allen: Re: which commercial HDL-Simulator for FPGA?
            133260: 08/06/23: Kim Enkovaara: Re: which commercial HDL-Simulator for FPGA?
                133267: 08/06/23: Petter Gustad: Re: which commercial HDL-Simulator for FPGA?
                    133276: 08/06/23: SynopsysFPGAexpress: Re: which commercial HDL-Simulator for FPGA?
                        133299: 08/06/24: Petter Gustad: Re: which commercial HDL-Simulator for FPGA?
        133185: 08/06/19: rickman: Re: which commercial HDL-Simulator for FPGA?
        133202: 08/06/20: kkoorndyk: Re: which commercial HDL-Simulator for FPGA?
    133174: 08/06/19: Jason Zheng: Re: which commercial HDL-Simulator for FPGA?
    133178: 08/06/19: Patrick Dubois: Re: which commercial HDL-Simulator for FPGA?
        133186: 08/06/19: rickman: Re: which commercial HDL-Simulator for FPGA?
            133243: 08/06/22: Mike Treseler: Re: which commercial HDL-Simulator for FPGA?
            133244: 08/06/22: SynopsysFPGAexpress: Re: which commercial HDL-Simulator for FPGA?
        133205: 08/06/20: Patrick Dubois: Re: which commercial HDL-Simulator for FPGA?
        133217: 08/06/20: Mike Treseler: Re: which commercial HDL-Simulator for FPGA?
        133240: 08/06/22: rickman: Re: which commercial HDL-Simulator for FPGA?
    133200: 08/06/20: General Schvantzkopf: Re: which commercial HDL-Simulator for FPGA?
        133201: 08/06/20: HT-Lab: Re: which commercial HDL-Simulator for FPGA?
        133206: 08/06/20: Mike Treseler: Re: which commercial HDL-Simulator for FPGA?
            133211: 08/06/20: Joseph H Allen: Re: which commercial HDL-Simulator for FPGA?
            133212: 08/06/20: Joseph H Allen: Re: which commercial HDL-Simulator for FPGA?
            133218: 08/06/20: Mike Treseler: Re: which commercial HDL-Simulator for FPGA?
            133231: 08/06/21: Petter Gustad: Re: which commercial HDL-Simulator for FPGA?
        133221: 08/06/20: ghelbig: Re: which commercial HDL-Simulator for FPGA?
    133209: 08/06/20: General Schvantzkopf: Re: which commercial HDL-Simulator for FPGA?
    133214: 08/06/20: General Schvantzkopf: Re: which commercial HDL-Simulator for FPGA?
        133216: 08/06/20: Stephen Williams: Re: which commercial HDL-Simulator for FPGA?
    133215: 08/06/20: Jason Zheng: Re: which commercial HDL-Simulator for FPGA?
    133219: 08/06/20: General Schvantzkopf: Re: which commercial HDL-Simulator for FPGA?
    133220: 08/06/20: General Schvantzkopf: Re: which commercial HDL-Simulator for FPGA?
        133323: 08/06/24: Stephen Williams: Re: which commercial HDL-Simulator for FPGA?
    133232: 08/06/21: General Schvantzkopf: Re: which commercial HDL-Simulator for FPGA?
133139: 08/06/18: rickman: Synplify beeping
    133141: 08/06/19: Hal Murray: Re: Synplify beeping
        133160: 08/06/19: MK: Re: Synplify beeping
    133157: 08/06/19: rickman: Re: Synplify beeping
    133164: 08/06/19: rickman: Re: Synplify beeping
    133165: 08/06/19: rickman: Re: Synplify beeping
    133167: 08/06/19: John_H: Re: Synplify beeping
    133184: 08/06/19: rickman: Re: Synplify beeping
133148: 08/06/19: Saransh: Error while doing 'Generate Netlist' in xilinx 9.2i
    133222: 08/06/20: mahesh: Re: Error while doing 'Generate Netlist' in xilinx 9.2i
    133425: 08/06/28: <Winfried.Gehrke@freenet.de>: Re: Error while doing 'Generate Netlist' in xilinx 9.2i
133151: 08/06/19: c d saunter: VHDL refactoring tools
    133153: 08/06/19: Andy: Re: VHDL refactoring tools
133162: 08/06/19: fatfpga@googlemail.com: DMA_BURST_SIZE in Xilinx EDK 9.1i
133168: 08/06/19: _TK_: FPGA JTAG commands
    133265: 08/06/23: Andreas Ehliar: Re: FPGA JTAG commands
133193: 08/06/20: <andy730215@gmail.com>: altera technical question?
    133213: 08/06/20: Icky Thwacket: Re: altera technical question?
    133223: 08/06/21: Brian Drummond: Re: altera technical question?
133196: 08/06/20: <meralonurlu@gmail.com>: beginner
    133210: 08/06/20: MikeWhy: Re: beginner
133197: 08/06/20: Steve: DDR2 termination
    133199: 08/06/20: Symon: Re: DDR2 termination
133203: 08/06/20: <swissiyoussef@gmail.com>: virtex 5 security / embedded key memory
    133207: 08/06/20: Muzaffer Kal: Re: virtex 5 security / embedded key memory
133227: 08/06/21: vikram: help using lwIP with xilinx EMAC
    133228: 08/06/21: Jon Beniston: Re: help using lwIP with xilinx EMAC
        133230: 08/06/21: MikeWhy: Re: help using lwIP with xilinx EMAC
133233: 08/06/22: bob elkind: Altera, Cyclone III, PCI, LVCMOS, & 3.3V
    133234: 08/06/21: Rob: Re: Altera, Cyclone III, PCI, LVCMOS, & 3.3V
        133236: 08/06/22: bob elkind: Re: Altera, Cyclone III, PCI, LVCMOS, & 3.3V
            133250: 08/06/22: Rob: Re: Altera, Cyclone III, PCI, LVCMOS, & 3.3V
                133255: 08/06/22: John_H: Re: Altera, Cyclone III, PCI, LVCMOS, & 3.3V
    133235: 08/06/21: Rob: Re: Altera, Cyclone III, PCI, LVCMOS, & 3.3V
133237: 08/06/22: RL: Newbie Verilog Question / ModelSim
    133238: 08/06/21: Muzaffer Kal: Re: Newbie Verilog Question / ModelSim
        133239: 08/06/22: RL: Re: Newbie Verilog Question / ModelSim
        133246: 08/06/22: <jprovidenza@yahoo.com>: Re: Newbie Verilog Question / ModelSim
        133249: 08/06/22: <parekh.sh@gmail.com>: Re: Newbie Verilog Question / ModelSim
133241: 08/06/22: ertw: Image Sensor Interface.
    133242: 08/06/22: ertw: Re: Image Sensor Interface.
    133245: 08/06/22: Jonathan Bromley: Re: Image Sensor Interface.
        133291: 08/06/23: MikeWhy: Re: Image Sensor Interface.
    133251: 08/06/22: MikeWhy: Re: Image Sensor Interface.
        133281: 08/06/23: glen herrmannsfeldt: Re: Image Sensor Interface.
            133290: 08/06/23: MikeWhy: Re: Image Sensor Interface.
                133295: 08/06/24: MikeWhy: Re: Image Sensor Interface.
                    133298: 08/06/24: Jonathan Bromley: Re: Image Sensor Interface.
                    133321: 08/06/24: glen herrmannsfeldt: Re: Image Sensor Interface.
                        133332: 08/06/25: MikeWhy: Re: Image Sensor Interface.
                133296: 08/06/23: glen herrmannsfeldt: Re: Image Sensor Interface.
            133305: 08/06/24: PFC: Re: Image Sensor Interface.
    133282: 08/06/23: ertw: Re: Image Sensor Interface.
    133283: 08/06/23: ertw: Re: Image Sensor Interface.
    133285: 08/06/23: ertw: Re: Image Sensor Interface.
    133330: 08/06/24: ertw: Re: Image Sensor Interface.
133247: 08/06/22: techG: virtex-5: can't use DCM (too low input frequency)
    133248: 08/06/22: Hauke D: Re: virtex-5: can't use DCM (too low input frequency)
    133252: 08/06/22: Symon: Re: virtex-5: can't use DCM (too low input frequency)
        133256: 08/06/23: Symon: Re: virtex-5: can't use DCM (too low input frequency)
        133264: 08/06/23: Symon: Re: virtex-5: can't use DCM (too low input frequency)
        133292: 08/06/23: John_H: Re: virtex-5: can't use DCM (too low input frequency)
    133253: 08/06/22: Peter Alfke: Re: virtex-5: can't use DCM (too low input frequency)
    133254: 08/06/22: Hauke D: Re: virtex-5: can't use DCM (too low input frequency)
    133257: 08/06/22: techG: Re: virtex-5: can't use DCM (too low input frequency)
    133258: 08/06/22: Peter Alfke: Re: virtex-5: can't use DCM (too low input frequency)
    133263: 08/06/23: Kolja Sulimma: Re: virtex-5: can't use DCM (too low input frequency)
    133278: 08/06/23: John_H: Re: virtex-5: can't use DCM (too low input frequency)
    133293: 08/06/23: Peter Alfke: Re: virtex-5: can't use DCM (too low input frequency)
    133301: 08/06/24: Symon: Re: virtex-5: can't use DCM (too low input frequency)
    133310: 08/06/24: techG: Re: virtex-5: can't use DCM (too low input frequency)
133259: 08/06/22: vikram: is lwIP absolutely necessary for tcp-ip?
    133262: 08/06/23: Mark McDougall: Re: is lwIP absolutely necessary for tcp-ip?
    133307: 08/06/24: PFC: Re: is lwIP absolutely necessary for tcp-ip?
133261: 08/06/22: checo: Cellular automata on a S3E SK
133268: 08/06/23: Norman Bollmann: FPGA based database searching
    133269: 08/06/23: Jon Beniston: Re: FPGA based database searching
    133270: 08/06/23: Symon: Re: FPGA based database searching
    133271: 08/06/23: Jonathan Bromley: Re: FPGA based database searching
    133274: 08/06/23: RCIngham: Re: FPGA based database searching
        133340: 08/06/25: Symon: Re: FPGA based database searching
            133349: 08/06/25: Mike Treseler: Re: FPGA based database searching
                133352: 08/06/25: Symon: Re: FPGA based database searching
                    133353: 08/06/25: Mike Treseler: Re: FPGA based database searching
                        133354: 08/06/25: Symon: Re: FPGA based database searching
                133361: 08/06/25: glen herrmannsfeldt: Re: FPGA based database searching
    133279: 08/06/23: Mike Treseler: Re: FPGA based database searching
    133284: 08/06/23: Ben Jackson: Re: FPGA based database searching
    133288: 08/06/23: Andy: Re: FPGA based database searching
    133306: 08/06/24: PFC: Re: FPGA based database searching
        133359: 08/06/25: Gavin Scott: Re: FPGA based database searching
    133337: 08/06/25: Kolja Sulimma: Re: FPGA based database searching
    133350: 08/06/25: Nico Coesel: Re: FPGA based database searching
        133409: 08/06/27: Norman Bollmann: Re: FPGA based database searching
    133415: 08/06/27: Chris Maryan: Re: FPGA based database searching
    133452: 08/06/30: rponsard@gmail.com: Re: FPGA based database searching
    133453: 08/06/30: rponsard@gmail.com: Re: FPGA based database searching
133272: 08/06/23: ALuPin@web.de: DC-Fifo with write pointer confirm/clear
    133303: 08/06/24: ALuPin@web.de: Re: DC-Fifo with write pointer confirm/clear
133273: 08/06/23: Leon: =?windows-1252?Q?Re=3A_NVIDIA=92s_Tesla_T10P_Blurs_Some_Lines?=
133275: 08/06/23: SynopsysFPGAexpress: Xilinx SecureIP simulation and third-party simulators?
    133286: 08/06/23: HT-Lab: Re: Xilinx SecureIP simulation and third-party simulators?
        133357: 08/06/25: Duth: Re: Xilinx SecureIP simulation and third-party simulators?
    133355: 08/06/25: Duth: Re: Xilinx SecureIP simulation and third-party simulators?
        133389: 08/06/26: <wdc.crest2@gmail.com>: Re: Xilinx SecureIP simulation and third-party simulators?
        133421: 08/06/27: Duth: Re: Xilinx SecureIP simulation and third-party simulators?
133277: 08/06/23: XSterna: Xilinx and RAM/ROM monitoring
    133413: 08/06/27: Gabor: Re: Xilinx and RAM/ROM monitoring
133280: 08/06/23: vikashrungta@gmail.com: Linked Group for FPGAs & CPLDs
    133311: 08/06/24: Dave Pollum: Re: Linked Group for FPGAs & CPLDs
        133317: 08/06/24: austin: Re: Linked Group for FPGAs & CPLDs
133287: 08/06/23: explore: XAUI - INTERNAL LOOPBACK SETUP - DRP (DYNAMIC RECONFIGURATION PORT)
    133289: 08/06/23: austin: Re: XAUI - INTERNAL LOOPBACK SETUP - DRP (DYNAMIC RECONFIGURATION
        133320: 08/06/24: austin: Re: XAUI - INTERNAL LOOPBACK SETUP - DRP (DYNAMIC RECONFIGURATION
    133319: 08/06/24: explore: Re: XAUI - INTERNAL LOOPBACK SETUP - DRP (DYNAMIC RECONFIGURATION
    134219: 08/07/31: Ragu: Re: XAUI - INTERNAL LOOPBACK SETUP - DRP (DYNAMIC RECONFIGURATION
133294: 08/06/23: vikram: How to include the Xilnet library in an EDK project?
133297: 08/06/24: grant0920: 1D or 2D Placement for dynamically partially reconfigurable
    133326: 08/06/24: stephen.craven@gmail.com: Re: 1D or 2D Placement for dynamically partially reconfigurable
    133334: 08/06/25: Jens Hagemeyer: Re: 1D or 2D Placement for dynamically partially reconfigurable
    133401: 08/06/26: grant0920: Re: 1D or 2D Placement for dynamically partially reconfigurable
    138740: 09/03/06: Dirk Koch: Re: 1D or 2D Placement for dynamically partially reconfigurable
133300: 08/06/24: karthick: Migrating to 9.2i from 8.2i
    133302: 08/06/24: Symon: Re: Migrating to 9.2i from 8.2i
        133314: 08/06/24: Jeff Cunningham: Re: Migrating to 9.2i from 8.2i
    133308: 08/06/24: karthick: Re: Migrating to 9.2i from 8.2i
    133312: 08/06/24: Joseph Samson: Re: Migrating to 9.2i from 8.2i
    133313: 08/06/24: KJ: Re: Migrating to 9.2i from 8.2i
    133315: 08/06/24: General Schvantzkopf: Re: Migrating to 9.2i from 8.2i
133304: 08/06/24: <muthusnv@gmail.com>: Cycle-based or Event-based simulation?
    133309: 08/06/24: KJ: Re: Cycle-based or Event-based simulation?
    133325: 08/06/24: Andy: Re: Cycle-based or Event-based simulation?
    133331: 08/06/24: Thomas Stanka: Re: Cycle-based or Event-based simulation?
133316: 08/06/24: Matthias Alles: PPC440 hangs after first interrupt
    133333: 08/06/25: Matthias Alles: Re: PPC440 hangs after first interrupt
        133335: 08/06/25: Matthias Alles: Re: PPC440 hangs after first interrupt
            133363: 08/06/26: Matthew Hicks: Re: PPC440 hangs after first interrupt
                133372: 08/06/26: Matthias Alles: Re: PPC440 hangs after first interrupt
133318: 08/06/24: <alessandro.strazzero@gmail.com>: External memory access
133322: 08/06/24: Erik Anderson: Configuration Management Best Practices
    133324: 08/06/24: Matthew Hicks: Re: Configuration Management Best Practices
        133329: 08/06/25: Mark McDougall: Re: Configuration Management Best Practices
            133364: 08/06/26: Matthew Hicks: Re: Configuration Management Best Practices
                133365: 08/06/26: Hal Murray: Re: Configuration Management Best Practices
    133328: 08/06/24: Mike Treseler: Re: Configuration Management Best Practices
133327: 08/06/24: mozilla: edk peripheral communication
    133371: 08/06/26: PFC: Re: edk peripheral communication
133336: 08/06/25: Klaus Petersen: Writing to memory shared with System Generator
133338: 08/06/25: <meralonurlu@gmail.com>: Beginner : Rotary switch (quad sw)
    133342: 08/06/25: John_H: Re: Beginner : Rotary switch (quad sw)
    133395: 08/06/26: -jg: Re: Beginner : Rotary switch (quad sw)
    133397: 08/06/26: Peter Alfke: Re: Beginner : Rotary switch (quad sw)
        133403: 08/06/27: MikeWhy: Re: Beginner : Rotary switch (quad sw)
133339: 08/06/25: <sumansrb@gmail.com>: interfacing lcd to spartan3a dsp 1800
133341: 08/06/25: Heinrich: Signal forwarding between FPGAs
    133368: 08/06/25: Tom: Re: Signal forwarding between FPGAs
        133378: 08/06/26: Heinrich: Re: Signal forwarding between FPGAs
            133406: 08/06/27: Heinrich: Re: Signal forwarding between FPGAs
                133410: 08/06/27: Heinrich: Re: Signal forwarding between FPGAs
                    133420: 08/06/27: Rob Gaddi: Re: Signal forwarding between FPGAs
                    133438: 08/06/28: MikeWhy: Re: Signal forwarding between FPGAs
        133396: 08/06/26: Tom: Re: Signal forwarding between FPGAs
        133407: 08/06/27: Tom: Re: Signal forwarding between FPGAs
        133419: 08/06/27: Tom: Re: Signal forwarding between FPGAs
        133422: 08/06/27: Tom: Re: Signal forwarding between FPGAs
        133439: 08/06/28: Tom: Re: Signal forwarding between FPGAs
        133440: 08/06/29: Peter Alfke: Re: Signal forwarding between FPGAs
    133370: 08/06/26: backhus: Re: Signal forwarding between FPGAs
        133377: 08/06/26: Heinrich: Re: Signal forwarding between FPGAs
133343: 08/06/25: <muthusnv@gmail.com>: Xilinx tools in Windows or Linux - Suggestions
    133351: 08/06/25: Alex.Louie: Re: Xilinx tools in Windows or Linux - Suggestions
    133791: 08/07/15: Goli: Re: Xilinx tools in Windows or Linux - Suggestions
    133794: 08/07/15: Uwe Bonnes: Re: Xilinx tools in Windows or Linux - Suggestions
    133795: 08/07/15: Uwe Bonnes: Re: Xilinx tools in Windows or Linux - Suggestions
133344: 08/06/25: fmostafa: RAM and shift register constraints
    133345: 08/06/25: austin: Re: RAM and shift register constraints
        133348: 08/06/25: austin: Re: RAM and shift register constraints
    133346: 08/06/25: fmostafa: Re: RAM and shift register constraints
    133347: 08/06/25: fmostafa: Re: RAM and shift register constraints
133356: 08/06/26: Philip Herzog: FPGA area use by module?
    133358: 08/06/25: ghelbig: Re: FPGA area use by module?
    133360: 08/06/25: glen herrmannsfeldt: Re: FPGA area use by module?
    133362: 08/06/25: John McGrath: Re: FPGA area use by module?
    133366: 08/06/26: Andreas Ehliar: Re: FPGA area use by module?
    133367: 08/06/26: backhus: Re: FPGA area use by module?
    133373: 08/06/26: Rob: Re: FPGA area use by module?
    133375: 08/06/26: <jetmarc@hotmail.com>: Re: FPGA area use by module?
        133381: 08/06/26: Martin Thompson: Re: FPGA area use by module?
    133379: 08/06/26: Jim Wu: Re: FPGA area use by module?
    133386: 08/06/26: John McCaskill: Re: FPGA area use by module?
133369: 08/06/25: Ambreen Ashfaq Afridi: Hardware Demonstration Platform
133374: 08/06/26: Rob: Xilinx register inits
    133376: 08/06/26: backhus: Re: Xilinx register inits
        133385: 08/06/26: backhus: Re: Xilinx register inits
            133393: 08/06/26: KJ: Re: Xilinx register inits
                133394: 08/06/26: KJ: Re: Xilinx register inits
                    133402: 08/06/27: backhus: Re: Xilinx register inits
    133380: 08/06/26: Rob: Re: Xilinx register inits
    133412: 08/06/27: Gabor: Re: Xilinx register inits
    133414: 08/06/27: KJ: Re: Xilinx register inits
133382: 08/06/26: <paolo.furia@gmail.com>: SYSACE problems on ML402 (virtex 4)
133383: 08/06/26: fmostafa: mapping error
    133390: 08/06/26: Jim Wu: Re: mapping error
    133391: 08/06/26: Jim Wu: Re: mapping error
    133404: 08/06/27: fmostafa: Re: mapping error
133384: 08/06/26: fatfpga@googlemail.com: How to start DMA from user_logic.vhdl (hardware side)
133387: 08/06/26: eric: System Generator Xilinx ML403
133388: 08/06/26: Mike Lewis: Re: synthesis error
    133392: 08/06/26: Ed McGettigan: Re: synthesis error
133398: 08/06/26: jay: NVRAM design in CPLD
    133400: 08/06/27: Jim Granville: Re: NVRAM design in CPLD
    133405: 08/06/27: jay: Re: NVRAM design in CPLD
    133436: 08/06/28: Alex: Re: NVRAM design in CPLD
133399: 08/06/26: Thomas Stanka: Re: synthesis error
133408: 08/06/27: Brian Drummond: Re: synthesis error
133411: 08/06/27: Evan Lavelle: Standard forms for Karnaugh maps?
    133417: 08/06/27: Leon: Re: Standard forms for Karnaugh maps?
    133418: 08/06/28: Jim Granville: Re: Standard forms for Karnaugh maps?
        133423: 08/06/28: Evan Lavelle: Re: Standard forms for Karnaugh maps?
            133424: 08/06/28: Jim Granville: Re: Standard forms for Karnaugh maps?
            133429: 08/06/28: KJ: Re: Standard forms for Karnaugh maps?
                133433: 08/06/29: Jim Granville: Re: Standard forms for Karnaugh maps?
                133481: 08/07/01: Evan Lavelle: Re: Standard forms for Karnaugh maps?
            133505: 08/07/01: Eric Smith: Re: Standard forms for Karnaugh maps?
        133426: 08/06/28: Gabor: Re: Standard forms for Karnaugh maps?
    133428: 08/06/28: General Schvantzkopf: Re: Standard forms for Karnaugh maps?
    133435: 08/06/28: ajjc: Re: Standard forms for Karnaugh maps?
        133482: 08/07/01: Evan Lavelle: Re: Standard forms for Karnaugh maps?
133416: 08/06/27: dscolson@rcn.com: Xilinx abandoning IEEE-1532 as programming option for iMPACT
133427: 08/06/28: <meralonurlu@gmail.com>: Still a Beginner: Accumulator has no reset
    133431: 08/06/28: Hauke D: Re: Still a Beginner: Accumulator has no reset
    133432: 08/06/28: Alvin Andries: Re: Still a Beginner: Accumulator has no reset
    133434: 08/06/28: <meralonurlu@gmail.com>: Re: Still a Beginner: Accumulator has no reset
133430: 08/06/28: Jim Flanagan: Missing the simplest things - Active HDL - Beginners Questions
    133459: 08/06/30: Dave: Re: Missing the simplest things - Active HDL - Beginners Questions
133437: 08/06/29: Philipp Hachtmann: EDK DMA peripherals?
    133441: 08/06/30: PFC: Re: EDK DMA peripherals?
    133451: 08/06/30: Guru: Re: EDK DMA peripherals?
133442: 08/06/29: timinganalyzer: ANNOUNCE: TimingAnalyzer version beta 0.85
    133446: 08/06/29: mahesh: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
        133449: 08/06/30: Nial Stewart: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
    133456: 08/06/30: timinganalyzer: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
    133461: 08/06/30: mahesh: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
    133463: 08/06/30: timinganalyzer: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
    133475: 08/06/30: mahesh: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
    133600: 08/07/05: rickman: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
    133605: 08/07/05: timinganalyzer: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
    133608: 08/07/05: rickman: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
133443: 08/06/29: hlao: Quartus-II 8.0 resource-sharing? (why inferred addsub takes 2x LUTs?)
    133476: 08/07/01: Joseph H Allen: Re: Quartus-II 8.0 resource-sharing? (why inferred addsub takes 2x LUTs?)
133444: 08/06/29: <cheapforwholesale666@126.com>: Discount Price !! Richmond D&G Shoes, Chanel Bape Belts , Jimmy Choo
133445: 08/06/29: jhamz: I-map Websolution...turning possibility into reality...
133447: 08/06/29: <rajeshobli@yahoo.co.in>: FIR filter with integer coefficients
    133470: 08/06/30: alonzo: Re: FIR filter with integer coefficients
133448: 08/06/30: Jonathan Bromley: Re: arithmetic problem
    133458: 08/06/30: Dave: Re: arithmetic problem
    133460: 08/06/30: Andy: Re: arithmetic problem
    133462: 08/06/30: Dave: Re: arithmetic problem
133450: 08/06/30: <chrisdekoh@gmail.com>: lwip for FPGA
    133483: 08/07/01: beeraka@gmail.com: Re: lwip for FPGA
        133493: 08/07/01: CBFalconer: Re: lwip for FPGA
    133646: 08/07/08: <chrisdekoh@gmail.com>: Re: lwip for FPGA
133454: 08/06/30: fmostafa: EDK question
    133489: 08/07/01: Matthew Hicks: Re: EDK question
    133526: 08/07/02: fmostafa: Re: EDK question
        133534: 08/07/03: Matthew Hicks: Re: EDK question
133455: 08/06/30: Brian Drummond: Re: arithmetic problem
133457: 08/06/30: Andy: Re: Standard forms for Karnaugh maps?
133464: 08/06/30: <rha_x@yahoo.com>: on FRAME_ECC_VIRTEX4 functionality
    133465: 08/06/30: austin: Re: on FRAME_ECC_VIRTEX4 functionality
        133468: 08/06/30: austin: Re: on FRAME_ECC_VIRTEX4 functionality
    133466: 08/06/30: austin: Re: on FRAME_ECC_VIRTEX4 functionality
        133484: 08/07/01: austin: Re: on FRAME_ECC_VIRTEX4 functionality
    133469: 08/06/30: alonzo: Re: on FRAME_ECC_VIRTEX4 functionality
133467: 08/06/30: chestnut: What is TIEOFF_X0Y31
    133471: 08/06/30: austin: Re: What is TIEOFF_X0Y31
    133487: 08/07/01: austin: Re: What is TIEOFF_X0Y31
    133560: 08/07/03: chestnut: Re: What is TIEOFF_X0Y31
133472: 08/06/30: <kvoskaki@nps.edu>: Design of a BFSK transmitter/receiver using Xilinx System Generator
    133474: 08/07/01: Frank Buss: Re: Design of a BFSK transmitter/receiver using Xilinx System Generator
133473: 08/06/30: Zhane: Translate problem
    133477: 08/06/30: PatC: Re: Translate problem
        133479: 08/07/01: Sean Durkin: Re: Translate problem
    133478: 08/06/30: Zhane: Re: Translate problem
    133485: 08/07/01: Zhane: Re: Translate problem
    133532: 08/07/02: Gabor: Re: Translate problem
    133538: 08/07/02: Zhane: Re: Translate problem


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