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Messages from 133625

Article: 133625
Subject: Re: OPB_CENTRAL_DMA
From: Pablo <pbantunez@gmail.com>
Date: Mon, 7 Jul 2008 00:58:57 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 5, 7:48 pm, "MikeWhy" <boat042-nos...@yahoo.com> wrote:
> "Pablo" <pbantu...@gmail.com> wrote in message
>
> news:2f27c020-f771-40e2-86b0-05d0675f3290@34g2000hsf.googlegroups.com...
>
> > int main (void) {
> > int i;
> > int array[100];
> > int array1[100];
> > for (i = 0; i < 100 ; i++) {
> > array[i]=1;
> > array1[i]=0;
> > }
> > dma_init(0xC0000004);
> > dma_transfer(&array[0],&array1[0],60);
> > return 0;
> > }
>
> Where is the stack memory?

Everything resides on Internal BRAM.

Article: 133626
Subject: Re: basic chipscope pro query
From: Guru <ales.gorkic@email.si>
Date: Mon, 7 Jul 2008 00:59:28 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 6, 8:39=A0pm, irfan.moham...@gmail.com wrote:
> On Jul 6, 5:08=A0am, "Symon" <symon_bre...@hotmail.com> wrote:
>
> > Irfan,
> > What ChipScope stuff have you tried so far?
> > Syms.
>
> Hello Symon,
>
> Thank you for your reply,
>
> i looked at ug029,user guide and some tutorial.i want to go through
> chipscope inserter and then analyze it.
>
> how can i verify a simple program? where i want to give some inputs
> and look at the output or signal.
>
> i have synthesized and opened core inserter through xilinx and then i
> took one trigger with width 24 and i connected the input and output
> signals(this is where i am getting problem)
>
> for example in xilinx simulator
>
> entity ram1 is
> port(
> clk:in std_logic;
> wr_addr:in std_logic_vector(2 downto 0);
> rd_addr:in std_logic_vector(2 downto0);
> we:in std_logic;
> oe:in std_logic;
> din:in std_logic_vector(7 downto 0);
> dout:out std_logic_vector(7 downto 0));
>
> end ram1
>
> first i make write operation
>
> normally in xilinx simulator i give we =3D1 and wr_addr=3D101 and din
> 10101010
>
> then after some delay of 10ns i make read operation
>
> i give we=3D0 re=3D1 ,oe_addr=3D101 and i get the output dout=3D10101010
>
> now when i want to test in chipscope how can i give din,we,wr_addr
>
> and after 10 ns sec how can i give inputs we,re,oe_addr
>
> Its very urgent or else u can give some example other than counter
> using core inserter and analyzer.
>
> Thanks in advance
> Irfan

Hi Irfan,

You have several options for you problem.
There are two Chipsope cores that you could use:
ILA - integrated logic analyser
VIO - virtual IO

The ILA is used to capture a consecutive set(or sets) of signals
whenever the triggered. Similar to oscilloscope or real logic
analyser.
The VIO is used to send or monitor the current state of signals. You
can also send some simple signal sequence, but I do not think you can
capture consecutive signals iwth VIO.

For inserting the core you need to:
1. generate the core
2. insert the core:
 a) directly into the pre generated deisign netlist using the core
inserter
 b) use the Chipscope core as a module in ISE flow.

ad a) Write down the nets you would like to monitor. Generate the
Chipscope core with appropritate number of IO ports. The run the Core
Inserter and connect the core to appropriate nets in your design
netlist. Then run the ISE P&R.
ad b) Simply use the CS core as a submodule in you design. After
generating the cores you get some examples for module declaration and
instantiation - use them. If you plan to alter the design use this
approach, it will save you a lot of time, since you do not have to re-
insert the core each time the netlist is altered.
BTW: The Chipscope netlists (*.ngc) must be copied to your ISE project
dir prior running P&R!!!

Cheers,

Guru

Article: 133627
Subject: Re: Serial Pheripheral Interface for XILINX FPGA
From: Goli <togoli@gmail.com>
Date: Mon, 7 Jul 2008 01:21:46 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 4, 4:13 pm, Zorjak <Zor...@gmail.com> wrote:
> Hi,
>
> I have one question if anyone can give me some clues. I need to
> realize SPI (Serial Pheriferal Interface for my project). Does anybody
> knows is there any free version of this core that can be foud on the
> net. TO be honest, I tought that I will find this easy on the net but
> it turns out that it was not.. I need that my interface be fully
> programed.
>
> Please if someone can give me any clue where can I find this. If you
> don't know, some good literature would also help if I must to do it by
> myself from the beginning.
>
> Thank you very much
> Zoran

Hi,
Zorjak,
You will find one set of SPI design files here
http://www.xilinx.com/products/silicon_solutions/cplds/resources/coolvhdlq.htm

Hope that helps.

@alfreeeed,
Hi,
My only point with Microblaze is that it takes far too many resources.
Why would I want to instantiate full microblaze which takes about 800
LUTS for something like SPI which in itself might just take 200-300
LUTs.

--
Goli

Article: 133628
Subject: Re: FiFo Help Needed
From: Gabor <gabor@alacron.com>
Date: Mon, 7 Jul 2008 05:26:30 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 5, 3:43 am, Zhane <m...@hotmail.com> wrote:
> On Jul 4, 11:38 pm, Mike Treseler <mtrese...@gmail.com> wrote:
>
> > Zhane wrote:
> > > # ** Warning: Design size of 11167 statements or 0 non-Xilinx leaf
> > > instances exceeds ModelSim XE-Starter recommended capacity.
>
> > Why does it take 11,167 statements to describe a fifo?
> > Seehttp://mysite.verizon.net/miketreseler/sync_fifo.vhd
>
> no idea
> I used the Core generator to generate
> and used the structural one to simulate
> and end up getting that error

It is not an error, only a warning.  It does not prevent you from
simulating
the design.  It only states that your license type will force ModelSim
to run very slowly.  However I think this has nothing to do with your
problem simulating.

What do you mean by "there doesnt seem to be
any data coming out of my FIFO during the clock cycles"?  Can you look
at the simulation and see that the data is going in to the
FIFO and the write enable is active?  Does the FIFO become non-empty
and read enable asserted?  Have you dealt with the global reset
for the core model?  Perhaps it's always being held reset?

Regards,
Gabor

Article: 133629
Subject: Understanding PPC405 execution.
From: mg <mariusz.grad@googlemail.com>
Date: Mon, 7 Jul 2008 05:28:08 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi all.

I'm trying to figure out how much time does it take for a such code to
execute.
I'm using modelsim on ppc405 processor (fpga virtex4 fx-12).


ffffc1d0 <main>:
...
ffffc1fc:       7c 00 01 24     mtmsr   r0
ffffc200:       80 1f 00 10     lwz     r0,16(r31)
ffffc204:       7c 03 03 78     mr      r3,r0
ffffc208:       48 00 01 89     bl      ffffc390 <swap>
ffffc20c:       7c 60 1b 78     mr      r0,r3
ffffc210:       90 1f 00 20     stw     r0,32(r31)
ffffc214:       38 00 00 00     li      r0,0
...

ffffc390 <swap>:
ffffc390:       54 64 c4 2e     rlwinm  r4,r3,24,16,23
ffffc394:       54 65 c0 0e     rlwinm  r5,r3,24,0,7
ffffc398:       50 65 42 1e     rlwimi  r5,r3,8,8,15
ffffc39c:       50 64 46 3e     rlwimi  r4,r3,8,24,31
ffffc3a0:       7c a3 2b 78     mr      r3,r5
ffffc3a4:       50 83 04 3e     rlwimi  r3,r4,0,16,31
ffffc3a8:       4e 80 00 20     blr

As you can see in main() function when pc = ffffc208 we have function
call (swap).

In modelsim I am looking on these signals:

* exeAddr = Instruction address in the exe stage (program counter
execution)
* exeFull = There is a valid instruction in the exe stage (execution
in exec stage)
* dcdAddr = Address of instruction at decode stage (program counter
decode phase)
* dcdData = Instruction at decode stage (opcode in decode phase)
* exeAReg = Operand A
* exeBReg = Operand B
* exeResult = Result of the operation


I turned off all optimizations in modelsim.
I'm looking how much time (clock cycles) each instruction needs to
execute.
Normally each rlw* instruction should take around 2 clock cycles (you
can read that in documentation) and it does with one exception.

It takes 13 clock cycles to jump from exeaddr = fffc39c to fffc3a0.
I will describe briefly what is going on in modelsim when entering
that address.
cycle 1: exeaddr = ffffc39c | exeFull = 1 | dcdAddr = ffffc3a0 |
dcdData = 801f0010
cycle 2: changes: exeFull = 0 | exe{Result, AReg, BReg}
cycle 3: changes in gpr4
cycles 4..11: no changes
cycle 12: changes in dcdData = 7ca32b78
cycle 13: exeaddr = ffffc3a4 ... - next instruction.

My interpretation of that is:
cycle 1 - starting to execute instruction
cycle 2 - leaving execution stage - we have results
cycle 3 - storing results to gpr4
cycle 4-12 when we look at dcdData we see that in decode phase there
is 801f0010 opcode (from ffffc200 address).
Are these 8 cycles used for execution that instruction in background?
One can see that r0 is used for mr r3,r0 and swap() uses r3 a lot, so
why is he doing that right now (not before)?

Can someone help me to interpret that debug informations or point me
to some materials where I can figure out what is going on?
How much time does it take for that instruction to execute?
Can it be that there is problem with ppc405 smartmodel?
I have other question concerning that debug which are confusing me
quite a lot but I will leave then for later discussion.

Thank you in advance,
Mariusz.
--
mg.

Article: 133630
Subject: ANNOUNCE: TimingAnalyzer version beta 0.86
From: timinganalyzer <timinganalyzer@gmail.com>
Date: Mon, 7 Jul 2008 08:26:02 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi All,

I am pleased to announce this new version of the TimingAnalyzer.  The
scripting interface has been added in this version,  so users can
develop scripts to draw simple and complex timing diagrams,  generate
test vectors, or add new features to the program.

Also,  all the currently functioning standard edition(SE) features
have been enabled so users can try these features and beta testers can
test them.  All beta versions from now on will have the SE features
enabled for this purpose. This version, beta 0.86,  has the SE enabled
until 9/4/08. So users can work with the SE beta versions now,  and be
guaranteed a smooth transition to the final release in the fall.

Working SE Features currently include savings images in other formats
such as eps, pdf, svg, png, and gif, as also the scripting interface.
There is updated website documentation for scripting with examples,
code reviews, sample outputs, and the initial API.

Fixed auto increment bug.
Updated save so the Save-as dialog is not always displayed.
Should work with JRE1.5 or newer but expect the final version to work
with JRE1.6 or newer.

You can download the TimingAnalyzer now and read all about it at:

www.timing-diagrams.com

Article: 133631
Subject: Re: ANNOUNCE: TimingAnalyzer version beta 0.86
From: "Pete Fraser" <pfraser@covad.net>
Date: Mon, 7 Jul 2008 10:15:15 -0700
Links: << >>  << T >>  << A >>
"timinganalyzer" <timinganalyzer@gmail.com> wrote in message 
news:90d4289c-fa23-43c0-b569-ac969df7ccf8@l64g2000hse.googlegroups.com...
> Hi All,
> You can download the TimingAnalyzer now and read all about it at:

You have too much faith in my abilities.
The only download reference I could find (Beta 0.70) was a dead link.

I tried editing the link in the obvious way:

http://members.aol.com/linuxr2d2/ta_b86_install.jar

but that didn't work either.

Pete 



Article: 133632
Subject: Re: ANNOUNCE: TimingAnalyzer version beta 0.86
From: timinganalyzer <timinganalyzer@gmail.com>
Date: Mon, 7 Jul 2008 10:29:16 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 7, 1:15 pm, "Pete Fraser" <pfra...@covad.net> wrote:
> "timinganalyzer" <timinganaly...@gmail.com> wrote in message
>
> news:90d4289c-fa23-43c0-b569-ac969df7ccf8@l64g2000hse.googlegroups.com...
>
> > Hi All,
> > You can download the TimingAnalyzer now and read all about it at:
>
> You have too much faith in my abilities.
> The only download reference I could find (Beta 0.70) was a dead link.
>
> I tried editing the link in the obvious way:
>
> http://members.aol.com/linuxr2d2/ta_b86_install.jar
>
> but that didn't work either.
>
> Pete

Hi Pete,

I was trying a new ftp application and corrupted the website.
Please try again and let me know if you have any problems.

-Dan

Article: 133633
Subject: Virtex 4 expected production end-of-life
From: Nobby Here <nobby@invalid.invalid>
Date: Mon, 07 Jul 2008 13:49:09 -0500
Links: << >>  << T >>  << A >>
Is there any information about the expected purchase lifetime for
the Virtex-4 series, specifically the FX12?  We've been using it for
a couple of years now in small quantities but we want to expand 
the product range we're using it in, because we're familiar with it
and have a bunch of software for the PPC processor.  However we'd
like to make a value judgement based on how long we might be able to
expect to buy them.

We're looking at very small quantities, a few 10s a year max, so it's
not something that Xilinx or anyone else is going to specially extend 
production for.  Also, becasue it's small quantities, the R&D cost
figures heavily in the final product sale cost, so we don't want to
redesign very often.

How many years can we expect them to remain in production?  Of course, 
I realise we could buy a few years' worth if they do go out of 
production, but we'd rather not go down that route if possible,
particularly if end of life is expected to be within the next 4 or 5 
years in which case it might be better to move on to something newer
for future developments.

Nobby

Article: 133634
Subject: Re: Virtex 4 expected production end-of-life
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Tue, 08 Jul 2008 09:10:26 +1200
Links: << >>  << T >>  << A >>
Nobby Here wrote:
> Is there any information about the expected purchase lifetime for
> the Virtex-4 series, specifically the FX12?  We've been using it for
> a couple of years now in small quantities but we want to expand 
> the product range we're using it in, because we're familiar with it
> and have a bunch of software for the PPC processor.  However we'd
> like to make a value judgement based on how long we might be able to
> expect to buy them.
> 
> We're looking at very small quantities, a few 10s a year max, so it's
> not something that Xilinx or anyone else is going to specially extend 
> production for.  Also, becasue it's small quantities, the R&D cost
> figures heavily in the final product sale cost, so we don't want to
> redesign very often.
> 
> How many years can we expect them to remain in production?  Of course, 
> I realise we could buy a few years' worth if they do go out of 
> production, but we'd rather not go down that route if possible,
> particularly if end of life is expected to be within the next 4 or 5 
> years in which case it might be better to move on to something newer
> for future developments.

Look at their older parts, and see what their lifetimes & prices were.

This can also be a package question (sometimes just the lowest volume
package variants are pruned),
so you need to back a 'preferred package'.

It would be nice if Xilinx indicated what those 'mainstream' poackages 
were, for low volume users like yourself.
Other sectors do this, and it is a good idea.

Another 'indicator' that appears before the EOL, is the NFND, and
that also shows up in what we call the 'go away' price :
The older device becomes more costly, than a newer model.

-jg


Article: 133635
Subject: Re: QPSK SymbolRate generator ...
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Mon, 07 Jul 2008 15:14:30 -0600
Links: << >>  << T >>  << A >>
Kappa wrote:
> I have built a QPSK modulator, but I have some doubts about the generation 
> of SymbolRate variable.
> 
> The SymbolRate range should from 1 to 45 Msymb/s. I intend to use an 
> external AD9850 DDS, which generates the clock from 1 MHz to 45 MHz for 
> clockout the Symbol.
> 
> The Symbols (I and Q) is interpolated by x2 or x4.
> 
> How can multiply internally this clock (1 to 45 MHz) by x2 or x4 ? I 
> remember that the clock is variable.
> 
> It's possible ?
> 
> Thansk.
> 
> Kappa
> 
> 
Here's the best solution, although it's also the one requiring the most 
skilz:  You use a constant sample rate.  You design a 
continuously-variable irrational interpolation FIR.  This is made 
possible by using ROMs to sample the impulse response at thousands of 
locations.  Then you use an NCO to adjust the symbol rate to whatever 
you wish, while keeping the sample rate constant.  This makes the design 
of the post-DAC reconstruction filter easier as well.  -Kevin

Article: 133636
Subject: Re: Virtex 4 expected production end-of-life
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 07 Jul 2008 14:48:26 -0700
Links: << >>  << T >>  << A >>
Nobby, don't worry.
Virtex-4 is our best-selling family. We will keep it in production for 
several years. Whenever the time comes where we finally decide to drop a 
part, we give you a total of 18 months warning to place your order and 
take delivery. So there will be no ugly surprises.
Hope this helps.
Peter Alfke, Xilinx Applications.


Nobby Here wrote:
> Is there any information about the expected purchase lifetime for
> the Virtex-4 series, specifically the FX12?  We've been using it for
> a couple of years now in small quantities but we want to expand 
> the product range we're using it in, because we're familiar with it
> and have a bunch of software for the PPC processor.  However we'd
> like to make a value judgement based on how long we might be able to
> expect to buy them.
> 
> We're looking at very small quantities, a few 10s a year max, so it's
> not something that Xilinx or anyone else is going to specially extend 
> production for.  Also, becasue it's small quantities, the R&D cost
> figures heavily in the final product sale cost, so we don't want to
> redesign very often.
> 
> How many years can we expect them to remain in production?  Of course, 
> I realise we could buy a few years' worth if they do go out of 
> production, but we'd rather not go down that route if possible,
> particularly if end of life is expected to be within the next 4 or 5 
> years in which case it might be better to move on to something newer
> for future developments.
> 
> Nobby

Article: 133637
Subject: SBC with ADC, 1GE, and SATA2?
From: mikemac@mikemac.com (Mike McDonald)
Date: Mon, 07 Jul 2008 21:59:57 GMT
Links: << >>  << T >>  << A >>
  I'm lokking for a small (4x6", 6x8", range) SBC that has a reasonably good A/D converter (100+MSPS),
at least one 1G ethernet, and one or more SATA-2 ports. I'm not picky about the processor. Anything that
runs Linux or an FPGA would be fine. A nice option would be an LCD and keypad interface.

  Has anyone got any recommendations? All of my Google queries are possessed! I keep getting the same 
wedsite under 15 different names that only has 6U and bigger boards.

-- 

  Mike McDonald
  mikemac@mikemac.com

Article: 133638
Subject: Re: Help to SImulate Uart TX
From: Mike Treseler <mike_treseler@comcast.net>
Date: Mon, 07 Jul 2008 15:46:51 -0700
Links: << >>  << T >>  << A >>
Zhane wrote:

> I'm noob, so trying to save some effort from recoding by using this
> code which I found somewhere ~_~

If you want to understand it well enough to test it,
read up on direct digital synthesis.

> it did work when I try on the actual fpga...

Good luck.

     -- Mike Treseler

Article: 133639
Subject: Re: Virtex 4 expected production end-of-life
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 8 Jul 2008 00:42:04 +0100
Links: << >>  << T >>  << A >>
"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message 
news:48728654@clear.net.nz...
>
> It would be nice if Xilinx indicated what those 'mainstream' poackages 
> were, for low volume users like yourself.
>
Hi Jim,
They do, although you need to work it out from the pricelist! :-)
Cheers, Syms. 



Article: 133640
Subject: Re: Virtex 4 expected production end-of-life
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 8 Jul 2008 00:48:18 +0100
Links: << >>  << T >>  << A >>

"Nobby Here" <nobby@invalid.invalid> wrote in message 
news:af2dnWFwxJm4-O_VnZ2dnUVZ8uadnZ2d@posted.plusnet...
> Is there any information about the expected purchase lifetime for
> the Virtex-4 series, specifically the FX12?  We've been using it for
> a couple of years now in small quantities but we want to expand
> the product range we're using it in, because we're familiar with it
> and have a bunch of software for the PPC processor.  However we'd
> like to make a value judgement based on how long we might be able to
> expect to buy them.
>
> We're looking at very small quantities, a few 10s a year max, so it's
> not something that Xilinx or anyone else is going to specially extend
> production for.  Also, becasue it's small quantities, the R&D cost
> figures heavily in the final product sale cost, so we don't want to
> redesign very often.
>
> How many years can we expect them to remain in production?  Of course,
> I realise we could buy a few years' worth if they do go out of
> production, but we'd rather not go down that route if possible,
> particularly if end of life is expected to be within the next 4 or 5
> years in which case it might be better to move on to something newer
> for future developments.
>
> Nobby

Hi Nobby,

What's your alternative if they do stop making it? You gotta port it. So the 
question is, spend the port money now, or later? Later's better, right?

No point worrying about stuff you can't influence!

Cheers, Syms.
p.s. Xilinx are pretty good at keeping stuff available. So, you'll probably 
have got a new job long before the part goes obsolete! :-) 



Article: 133641
Subject: Re: FiFo Help Needed
From: Zhane <me75@hotmail.com>
Date: Mon, 7 Jul 2008 17:59:20 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 7, 8:26=A0pm, Gabor <ga...@alacron.com> wrote:
> On Jul 5, 3:43 am, Zhane <m...@hotmail.com> wrote:
>
> > On Jul 4, 11:38 pm, Mike Treseler <mtrese...@gmail.com> wrote:
>
> > > Zhane wrote:
> > > > # ** Warning: Design size of 11167 statements or 0 non-Xilinx leaf
> > > > instances exceeds ModelSim XE-Starter recommended capacity.
>
> > > Why does it take 11,167 statements to describe a fifo?
> > > Seehttp://mysite.verizon.net/miketreseler/sync_fifo.vhd
>
> > no idea
> > I used the Core generator to generate
> > and used the structural one to simulate
> > and end up getting that error
>
> It is not an error, only a warning. =A0It does not prevent you from
> simulating
> the design. =A0It only states that your license type will force ModelSim
> to run very slowly. =A0However I think this has nothing to do with your
> problem simulating.
>
> What do you mean by "there doesnt seem to be
> any data coming out of my FIFO during the clock cycles"? =A0Can you look
> at the simulation and see that the data is going in to the
> FIFO and the write enable is active? =A0Does the FIFO become non-empty
> and read enable asserted? =A0Have you dealt with the global reset
> for the core model? =A0Perhaps it's always being held reset?
>
> Regards,
> Gabor

erm

i've found it
I didnt expand my timing far enough to observe the data output.

Article: 133642
Subject: Re: Virtex 4 expected production end-of-life
From: Peter Alfke <alfke@sbcglobal.net>
Date: Mon, 7 Jul 2008 21:00:33 -0700 (PDT)
Links: << >>  << T >>  << A >>
Nobby,
as I wrote earlier (did it get lost?), you should not worry.
Virtex-4 is the bets product line in Xilinx history (we expect
Virtex-5 to become even better in due course).
We will keep it in production for many years to come. When the day
comes where we announce "Last buy", we give you an additional 18
months to place your order and take delivery.
Don't worry, be happy...
Peter Alfke, Xilinx Applications

Article: 133643
Subject: Re: Re:V4FX20 upgrade to FX40 problem (was: Xilinx ISE speed files compatibilit)
From: "MM" <mbmsv@yahoo.com>
Date: Tue, 8 Jul 2008 01:08:07 -0400
Links: << >>  << T >>  << A >>
The problem has been fixed, although I still need to investigate why the fix 
was needed. EDK by default uses FX DCM output to generate PPC clock. I 
changed it to use CLK0 (as I didn't need the synthesizer anyways) and now it 
works fine. Again, it worked perfectly fine in FX20 using the synthesizer.


/Mikhail 



Article: 133644
Subject: Re: QPSK SymbolRate generator ...
From: "Kappasm" <_NOSPAM_78kappa78_NO_SPAM@virgilio.it>
Date: Tue, 8 Jul 2008 08:59:16 +0200
Links: << >>  << T >>  << A >>
Hi Kevin Neilson,

I did not understand, you might be more accurate ?

> You design a continuously-variable irrational interpolation FIR.  This is 
> made possible by using ROMs to sample the impulse response at thousands of 
> locations.  Then you use an NCO to adjust the symbol rate to whatever you 
> wish, while keeping the sample rate constant.  This makes the design of 
> the post-DAC reconstruction filter easier as well.

But if I clocking data output (I and Q) as a constant speed, how can have a 
variable SymbolRate ?

I do not understand.

Kappa.



Article: 133645
Subject: Re: Virtex 4 expected production end-of-life
From: Nobody Here <nobby@invalid.invalid>
Date: Tue, 08 Jul 2008 02:09:32 -0500
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> wrote:
> Nobby, don't worry.
> Virtex-4 is our best-selling family. We will keep it in production for 
> several years. Whenever the time comes where we finally decide to drop a 
> part, we give you a total of 18 months warning to place your order and 
> take delivery. So there will be no ugly surprises.
> Hope this helps.
> Peter Alfke, Xilinx Applications.

Thanks Peter and all who replied.  That's reassuring then so we'll continue
on the path we're taking.  As you say, with 18 months in NFND we can do a
lot in that time (including go out of business ;) ), and as someone 
else pointed out it is really a matter of pushing the redevelopment 
costs out into the future or facing them now.  Future's definitely
better.

Thanks
Nobby.

>
>
> Nobby Here wrote:
>> Is there any information about the expected purchase lifetime for
>> the Virtex-4 series, specifically the FX12?  We've been using it for
>> a couple of years now in small quantities but we want to expand 
>> the product range we're using it in, because we're familiar with it
>> and have a bunch of software for the PPC processor.  However we'd
>> like to make a value judgement based on how long we might be able to
>> expect to buy them.
>> 
>> We're looking at very small quantities, a few 10s a year max, so it's
>> not something that Xilinx or anyone else is going to specially extend 
>> production for.  Also, becasue it's small quantities, the R&D cost
>> figures heavily in the final product sale cost, so we don't want to
>> redesign very often.
>> 
>> How many years can we expect them to remain in production?  Of course, 
>> I realise we could buy a few years' worth if they do go out of 
>> production, but we'd rather not go down that route if possible,
>> particularly if end of life is expected to be within the next 4 or 5 
>> years in which case it might be better to move on to something newer
>> for future developments.
>> 
>> Nobby

Article: 133646
Subject: Re: lwip for FPGA
From: chrisdekoh@gmail.com
Date: Tue, 8 Jul 2008 02:23:33 -0700 (PDT)
Links: << >>  << T >>  << A >>
hi Chuck,
   I do not want to use TFTP as i will eventually need to write a
customised program to do this.

   Let me extend my question further.


1)  Are there any examples available or could anybody kindly guide me
as to how to modify xapp1026 to convert the microblaze running on FPGA
to a client instead of a server? I would like the PC to act as the
server instead and would like to transfer data to the FPGA board from
the PC

http://www.xilinx.com/support/documentation/application_notes/xapp1026.pdf

just curious, would it be straightforward just to omit the 2 lines on
page 5 of the notes:

pcb = tcp_listen(pcb);
tcp_accept(pcb,accept_callback);

and just add in

tcp_connect(pcb, accept_callback);

have i missed out anything?


2) what program should be running on the PC if i need it to behave as
a server? could i just create a server program eg...from the link
below (under server model)

http://people.cs.uchicago.edu/~mark/51081/labs/LAB6/sock.html

will the PC be able to communicate with FPGA with this configuration?


thanks in advance for your time and patience. I am really new to this
and have been stuck for quite a while on this.

Chris

Article: 133647
Subject: Re: V4FX20 upgrade to FX40 problem (was: Xilinx ISE speed files compatibilit)
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Tue, 08 Jul 2008 13:14:17 +0100
Links: << >>  << T >>  << A >>
On Tue, 8 Jul 2008 01:08:07 -0400, "MM" <mbmsv@yahoo.com> wrote:

>The problem has been fixed, although I still need to investigate why the fix 
>was needed. EDK by default uses FX DCM output to generate PPC clock. I 
>changed it to use CLK0 (as I didn't need the synthesizer anyways) and now it 
>works fine. Again, it worked perfectly fine in FX20 using the synthesizer.

And clk0 comes from.... ?

There is advice somewhere against chaining too many DCMs (accumulating
clock jitter); chaining two is about the maximum that is guaranteed to
work, assuming a reasonably clean input clock. Add some input jitter and
even two in series may be unreliable.

Could this explain the problem?

- Brian

Article: 133648
Subject: What's wrong with this Virtex4 DCM?
From: Nemesis <gnemesis2001@gmail.com>
Date: Tue, 8 Jul 2008 06:46:28 -0700 (PDT)
Links: << >>  << T >>  << A >>
I'm using the DCM instantiation reported below, on a Virtex4fx60
target.
I have two different boards (ICS-8550) the differ only for the
ruggedization level, the boards are almost the same and so should be
the FPGAs, maybe only the stepping level is different.

But on one board is working and on another one is not working.

I'm providing a 300ms long reset signal as requested on the V4 user
guide but the DCM doesn't get locked.

The input is a 100MHz clock and the sys_clock_dcm signal is valid, but
I don't get the divided, multiplied and FX clocks, and the lock signal
is down.

The same bitstream is working on

    SYSTEM_DCM: DCM
    generic map (
        CLKFX_DIVIDE    => 8,
        CLKFX_MULTIPLY  => 2
        )
    port map (
        CLKIN    => adc1_clk_in,
        CLKFB    => sys_clock_dcmfb,
        DSSEN    => '0',
        PSINCDEC => '0',
        PSEN     => '0',
        PSCLK    => '0',
        RST      => my_dcm_reset,
        CLK0     => sys_clock_dcm,
        CLKDV    => sys_clock_x05_i,
        CLK2X    => sys_clock_x2_i,
        CLKFX    => sys_clock_fx_i,
        LOCKED   => sys_lock
        );

    sys_clock_dcm_bufg: BUFG port map( I => sys_clock_dcm, O =>
sys_clock_dcmfb);

Article: 133649
Subject: Re: OPB_CENTRAL_DMA
From: Guru <ales.gorkic@email.si>
Date: Tue, 8 Jul 2008 06:54:04 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 4, 12:40=A0pm, Pablo <pbantu...@gmail.com> wrote:
> On Jul 4, 10:34 am, Guru <ales.gor...@email.si> wrote:
>
> > On Jul 3, 2:32 pm, Pablo <pbantu...@gmail.com> wrote:
>
> > > Has anybody used central_dma to copy data between peripherals and
> > > processors, or between two buffers in bram mermory. I have added it t=
o
> > > the design and configure but, I receive a DMA BUS TIMEOUT.
>
> > > Best Regards
>
> > Obviously one of the addresses you are trying to access does not
> > exist. Check the address map.
>
> This was my first opinion, so I create two buffers in internal memory
> as follows:
>
> #include "xparameters.h"
> #include "xdmacentral.h"
> #include "xutil.h"
>
> //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D
> #define uint =A0 =A0unsigned int
> void dma_init(uint config);
> void dma_transfer (int *src, int *dst, uint length);
>
> int main (void) {
> =A0 =A0 =A0 =A0 int i;
> =A0 =A0 =A0 =A0 int array[100];
> =A0 =A0 =A0 =A0 int array1[100];
> =A0 =A0 =A0 =A0 for (i =3D 0; i < 100 ; i++) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 array[i]=3D1;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 array1[i]=3D0;
> =A0 =A0 =A0 =A0 }
> =A0 =A0 =A0 =A0 dma_init(0xC0000004);
> =A0 =A0 =A0 =A0 dma_transfer(&array[0],&array1[0],60);
> =A0 =A0 =A0 =A0 return 0;
>
> }
>
> // Function to control DMA
>
> void dma_init(uint config) {
> =A0 =A0 =A0 =A0 int *dma =3D (int *)0x41e00000;
> =A0 =A0 =A0 =A0 *dma =3D 0xA; // Reset
> =A0 =A0 =A0 =A0 dma++;
> =A0 =A0 =A0 =A0 *dma =3D config; // Config}
>
> void dma_transfer (int *src, int *dst, uint length) {
> =A0 =A0 =A0 =A0 int *dma =3D (int *)0x41e00008;
> =A0 =A0 =A0 =A0 *dma =3D (int)src; // Src Address
> =A0 =A0 =A0 =A0 dma++;
> =A0 =A0 =A0 =A0 *dma =3D (int)dst;
> =A0 =A0 =A0 =A0 dma++;
> =A0 =A0 =A0 =A0 *dma =3D length;
>
> > Otherwise the CENTRAL_DMA has low performance since the data needs to
> > travel twice: source_peripheral -> DMA and DMA ->
> > destination_peripheral
> > Not to mention that is not capable of long bursts.
>
> Is it possible to avoid this timeout?
>
> > Cheers,
>
> > Guru
>
> Guru I have seen a post in which you said that dma registers are
> located at:
> baseaddr + 0x400.
>
> but in the documentation it said that registers positions are:
> baseaddr + 0x4.
>
> am I ok?
>
> again, my best regards
>
> pablo

Use the predefined functions (driver) for DMA engine.
Verify the DMA registers, source and destiantion operation using
XIo_Out32 and XIo_In32 as defined in "xio.h".
The timeout only happens if somethins is WRONG.
You could identify the problem using the Chipscope bus analyser, but
that is another story.

Cheers,

Guru



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