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Messages from 133825

Article: 133825
Subject: Re: Low cost solution to program Spartan 3AN DSP development board
From: Etantonio <etantonio@gmail.com>
Date: Wed, 16 Jul 2008 08:18:24 -0700 (PDT)
Links: << >>  << T >>  << A >>
Thanks Dave
 the board I've is the dsp version,

http://www.xilinx.com/support/documentation/boards_and_kits/ug454_sp3a_dsp_start_ug.pdf

and there's not usb cable to download the bitstream to the board,

at the moment Xilinx and Digilent seems to be the lonely possible
solutions.



Article: 133826
Subject: Re: Fifo Simulation Error
From: Dave <dhschetz@gmail.com>
Date: Wed, 16 Jul 2008 08:31:01 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 16, 10:51 am, Zhane <m...@hotmail.com> wrote:
> On Jul 16, 10:39 pm, Zhane <m...@hotmail.com> wrote:
>
>
>
> > On Jul 16, 8:58 pm, KJ <kkjenni...@sbcglobal.net> wrote:
>
> > > On Jul 16, 8:52 am, KJ <kkjenni...@sbcglobal.net> wrote:
>
> > > > On Jul 16, 5:39 am, Zhane <m...@hotmail.com> wrote:
>
> > > Woops, failed basic mathematics myself on the previous post.  115200
> > > baud will translate to ~11KB/sec which is 3000x slower than the
> > > implied input rate of 33 MB/sec...not 3x.  Replace all 3x with 3000x
> > > in the previous post...get a reeeeeally big memory buffer
>
> > > KJ
>
> > :(
> > im trying to sample the LPC bus though... I've already reduced to the
> > minimal that I think I need...and with what I have now, there are
> > weird extra cycles appearing at places where they shuoldnt be. Without
> > these samples, I cant determine if those weird cycles are relevant or
> > not.
>
> > >.<
>
> > :( how? my Spartan 3E has a USB interface, but... it's used to program
> > my board.
>
> > Can I remove my usb cable after downloading my program, and use it to
> > transfer instead?
> > what kind of program (eg.hyperterminal for rs232) is required for usb?
>
> hmmm
> I guess I can give up on usb.. I cant find a VHDL usb core to use
> anyway ~_~

Maybe you could build a module to look for a condition on the bus that
is interesting to you, and store everything just before and after that
event? Then you could transmit the stored data out the UART. You just
need to figure out how to detect your error on-the-fly.

Dave

Article: 133827
Subject: Re: Fifo Simulation Error
From: Zhane <me75@hotmail.com>
Date: Wed, 16 Jul 2008 08:49:47 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 16, 11:31=A0pm, Dave <dhsch...@gmail.com> wrote:
> On Jul 16, 10:51 am, Zhane <m...@hotmail.com> wrote:
>
>
>
> > On Jul 16, 10:39 pm, Zhane <m...@hotmail.com> wrote:
>
> > > On Jul 16, 8:58 pm, KJ <kkjenni...@sbcglobal.net> wrote:
>
> > > > On Jul 16, 8:52 am, KJ <kkjenni...@sbcglobal.net> wrote:
>
> > > > > On Jul 16, 5:39 am, Zhane <m...@hotmail.com> wrote:
>
> > > > Woops, failed basic mathematics myself on the previous post. =A0115=
200
> > > > baud will translate to ~11KB/sec which is 3000x slower than the
> > > > implied input rate of 33 MB/sec...not 3x. =A0Replace all 3x with 30=
00x
> > > > in the previous post...get a reeeeeally big memory buffer
>
> > > > KJ
>
> > > :(
> > > im trying to sample the LPC bus though... I've already reduced to the
> > > minimal that I think I need...and with what I have now, there are
> > > weird extra cycles appearing at places where they shuoldnt be. Withou=
t
> > > these samples, I cant determine if those weird cycles are relevant or
> > > not.
>
> > > >.<
>
> > > :( how? my Spartan 3E has a USB interface, but... it's used to progra=
m
> > > my board.
>
> > > Can I remove my usb cable after downloading my program, and use it to
> > > transfer instead?
> > > what kind of program (eg.hyperterminal for rs232) is required for usb=
?
>
> > hmmm
> > I guess I can give up on usb.. I cant find a VHDL usb core to use
> > anyway ~_~
>
> Maybe you could build a module to look for a condition on the bus that
> is interesting to you, and store everything just before and after that
> event? Then you could transmit the stored data out the UART. You just
> need to figure out how to detect your error on-the-fly.
>
> Dave

ya
im sort of trying to do it now
but it's either my condition aint met

or the bus go crazy =3DP

A
B
C
C
D

It's supposed to be A,B,C,D,E, but sometimes it has repeats like ABCCD
or ABBCDE o_o!!

Article: 133828
Subject: Re: unified protocol
From: John_H <newsgroup@johnhandwork.com>
Date: Wed, 16 Jul 2008 11:16:20 -0700 (PDT)
Links: << >>  << T >>  << A >>
raj wrote:
> hai ,
>
> can anyone suggest how to test and verify unified protocol layers?
>
> regards,
> raj

It seems there is no "Unified Protocol" standard that is obvious from
a quick Google search.

Is there a *specific* "Unified Protocol" you are interested in and, if
so, have you looked at the official website fo the group that controls
that standard?  Often there are test standards available or links to
companies that can provide testing IP.

- John_H

Article: 133829
Subject: Xilinx/Altera gate equivalence
From: dudesinmexico <dudesinmexico@gmail.com>
Date: Wed, 16 Jul 2008 11:24:29 -0700 (PDT)
Links: << >>  << T >>  << A >>
Are there any rules of thumb to figure out the equivalent number of
logic resources
needed to implement the same design on Stratix IV vs., say,
Virtex-4/5?
I am thinking of random logic, i.e. a CLB vs. LAB conversion factor...

Thanks!

Article: 133830
Subject: Re: Xilinx/Altera gate equivalence
From: Mike Treseler <mike_treseler@comcast.net>
Date: Wed, 16 Jul 2008 11:57:37 -0700
Links: << >>  << T >>  << A >>
dudesinmexico wrote:
> Are there any rules of thumb to figure out the equivalent number of
> logic resources
> needed to implement the same design on Stratix IV vs., say,
> Virtex-4/5?
> I am thinking of random logic, i.e. a CLB vs. LAB conversion factor...

Quartus will give the exact utilization
and pick a device for you, if you have source code.

        -- Mike Treseler

Article: 133831
Subject: Xilinx Spartan-3E Microblaze Program Execution
From: "Ray D." <ray.delvecchio@gmail.com>
Date: Wed, 16 Jul 2008 12:02:16 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello all,

I am a beginner with the Xilinx EDK and Platform Studio software for
programming a Microblaze processor.  I have googled several EDK
tutorials, but few have met my platform specifications (v10.1,
Microblaze processor) and I'm having some trouble downloading my
software design to the Spartan-3E board.

Currently, I have the hardware design in place and I wrote a simple
program to turn on a few of the LED's on the starter board.  Now after
wrestling with this for a few days I finally got the program to run
via the XMD (Xilinx Microprocessor Debugger) by connecting to the
processor and executing the 'run' command.

My question is this - how do you run the program after you download
the bit file (with both the hardware design and the software
application) without using the debugger?

Any help or input would be greatly appreciated.  Thanks!

Ray

P.S.  My program code is below:

#include "xparameters.h"
#include "stdio.h"
#include "xbasic_types.h"
#include "xgpio.h"
#include "gpio_header.h"
#include "uartlite_header.h"

int main (void) {

	XGpio Lights;

	if (XGpio_Initialize(&Lights, XPAR_LEDS_8BIT_DEVICE_ID) !=
XST_SUCCESS) {
		printf("Failed to initalize the LEDs.\r\n");
	}
	else {
		while(1){
			XGpio_SetDataDirection(&Lights, 1, 0x00);
			XGpio_DiscreteWrite(&Lights, 1, 0x0A);
		}
	}

   return 0;
}

Article: 133832
Subject: Re: Xilinx/Altera gate equivalence
From: dudesinmexico <dudesinmexico@gmail.com>
Date: Wed, 16 Jul 2008 14:48:41 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 16, 11:57=A0am, Mike Treseler <mike_trese...@comcast.net> wrote:
> dudesinmexico wrote:
> > Are there any rules of thumb to figure out the equivalent number of
> > logic resources
> > needed to implement the same design on Stratix IV vs., say,
> > Virtex-4/5?
> > I am thinking of random logic, i.e. a CLB vs. LAB conversion factor...
>
> Quartus will give the exact utilization
> and pick a device for you, if you have source code.
>

I don't, and that's why I am asking... I have a Virtex-4 design and
I'd like to find what Stratix IV
part it will fit in.


dudesinmexico

Article: 133833
Subject: Re: Xilinx/Altera gate equivalence
From: austin <austin@xilinx.com>
Date: Wed, 16 Jul 2008 15:15:54 -0700
Links: << >>  << T >>  << A >>
dudes,

If you contact your Xilinx FAE I am sure they would be happy to help you.

If this is an academic study, then I suggest you will have to get
somewhere from one to five hundred designs, and then target them to each
architecture, and then examine the results, and try to draw some
conclusions.

Of course, whatever designs you choose will be challenged as being the
'wrong' ones, or ones that are 'obviously biased.'

Personally, I believe market forces are at work so that the cost of
doing whatever you want to do is roughly equal between the two choices.

Then it becomes a question of component availability, lowest power, or
fastest speed, or best IP libraries, or best support.

Or, a question of all of the above.

Austin

Article: 133834
Subject: Re: Xilinx/Altera gate equivalence
From: Mike Treseler <mike_treseler@comcast.net>
Date: Wed, 16 Jul 2008 16:24:07 -0700
Links: << >>  << T >>  << A >>
dudesinmexico wrote:

> I don't, and that's why I am asking... I have a Virtex-4 design and
> I'd like to find what Stratix IV
> part it will fit in.

I agree with Austin.
Pricing is roughly equivalent because of competition.
There is no better estimate without a redesign.
Porting a design without source code sounds painful to me.
I would leave it alone if cost is the only reason for change.

         -- Mike Treseler

Article: 133835
Subject: Re: Xilinx/Altera gate equivalence
From: dudesinmexico <dudesinmexico@gmail.com>
Date: Wed, 16 Jul 2008 17:20:10 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 16, 3:15=A0pm, austin <aus...@xilinx.com> wrote:
> dudes,
>
> If you contact your Xilinx FAE I am sure they would be happy to help you.
>

So these days Xilinx FAEs help their customers to port their designs
to Altera?
Sorry Austin, I could not resist.. ;)
Anyway, this is not an academic exercise. Porting a very complex
Virtex4 design
to Stratix is not something that one can do in a few days, so I was
looking
for ballpark estimates about the equivalence between Xilinx and Altera
"gates".


> If this is an academic study, then I suggest you will have to get
> somewhere from one to five hundred designs, and then target them to each
> architecture, and then examine the results, and try to draw some
> conclusions.
>
> Of course, whatever designs you choose will be challenged as being the
> 'wrong' ones, or ones that are 'obviously biased.'
>
> Personally, I believe market forces are at work so that the cost of
> doing whatever you want to do is roughly equal between the two choices.
>
> Then it becomes a question of component availability, lowest power, or
> fastest speed, or best IP libraries, or best support.
>
> Or, a question of all of the above.
>
> Austin


Article: 133836
Subject: Re: Xilinx/Altera gate equivalence
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Wed, 16 Jul 2008 22:00:58 -0500
Links: << >>  << T >>  << A >>

>Anyway, this is not an academic exercise. Porting a very complex
>Virtex4 design
>to Stratix is not something that one can do in a few days, so I was
>looking
>for ballpark estimates about the equivalence between Xilinx and Altera
>"gates".

Have you looked at the Stratix data sheet?  Did you find anything
close to a CLB/FF pair?  If so, assume they are 1:1.

Then count the special things you use: BRAMs, clock buffers, multipliers
and whatevber.  Then see if Altera has something similar.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 133837
Subject: Re: First CPLD project
From: "Nitro" <nitro-57@no_spam_please_usa.net>
Date: Thu, 17 Jul 2008 00:11:29 -0400 (EDT)
Links: << >>  << T >>  << A >>
On 14 Jul 2008 13:02:02 -0400, DJ Delorie wrote:

>
>
>
>gregben <gregbdelete@laserlabdelete.com> writes:
>> I'm doing an internal project for my tiny company and have chosen to
>> use a Xilinx XC9572 and an Atmel ATMEGA324P along with 6 74LS245
>> transceivers for this portion.
>> 
>> I have both Windows XP SP3 and Ubuntu 8.04 available for
>> development. I'd prefer to do most or all work under Ubuntu. Is that
>> practical using the Xilinx toolset?
>
>I can do XC9572XL development 100% on Linux (Fedora 6) so you
>shouldn't have a problem with that.  I don't use the USB cable,
>though, I made my own programmer from a spare MCU and the XAPP058
>sample program.  I can program an XC9572XL in about 12 seconds with
>it.
We have used the "Platform USB" cable and the Parallel port CABLE IV from
Xilinx under Redhat EL4 using the impact software.  (You need root PW to
install the parallel port drivers and I believe the kernel source installed)

The Digilentinc parallel cable also seems to work with impact under EL4. 
This cable comes with the Digilent Coolrunner CPLD development board. 
(Remember your PC needs a parallel port for this, many new laptops dropped
the PP)



Article: 133838
Subject: Re: What's wrong with this Virtex4 DCM?
From: Nemesis <gnemesis2001@gmail.com>
Date: Wed, 16 Jul 2008 23:45:27 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 9, 4:14=A0pm, "Symon" <symon_bre...@hotmail.com> wrote:
> "Gabor" <ga...@alacron.com> wrote in message
>
> news:e1dcc819-76e0-4f8b-8e0a-7ee345bacdbb@8g2000hse.googlegroups.com...
>
> > On Jul 8, 9:46 am,Nemesis<gnemesis2...@gmail.com> wrote:
> >> I have two different boards (ICS-8550) the differ only for the
> >> ruggedization level, the boards are almost the same and so should be
> >> the FPGAs, maybe only the stepping level is different.
>
> >> But on one board is working and on another one is not working.
>
> > With a sample size of just two boards, it's possible that your clock
> > source is not within the required jitter specs to achieve lock. =A0What
> > is the source? =A0Possibly an oscillator with a PLL to produce the
> > required frequency?
>
> Or maybe cascaded DCMs?

We use a good quartz oscillator ... and just one DCM. I think I found
the problem in the frequency ranges, I use the FX output to generate a
25MHz ... but on the Virtex DataSheet is written that in the Max Speed
Mode, the lower limit for FX output is 32.
Still I don't understand why it is working on the other boards ...

Article: 133839
Subject: Re: unified protocol
From: raj <rajesh.obli@gmail.com>
Date: Thu, 17 Jul 2008 00:00:16 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hai,

Unified protocol is MIPI standard.

In general i would like to know what is the maximum data that can be
exchanged between the devices using this protocol?

what are the various modes of data exchange?


regards,
raj

Article: 133840
Subject: usb core
From: hmmudassir82@gmail.com
Date: Thu, 17 Jul 2008 00:28:03 -0700 (PDT)
Links: << >>  << T >>  << A >>
I am mudassir.
I want to get usb core in verilog without any bug.
please give me this core if any one have design
 it or get from any other resources.
thanks with best regard.

Article: 133841
Subject: defunct Platform USB cable
From: Gerhard Hoffmann <dk4xp@hoffmann-hochfrequenz.de>
Date: Thu, 17 Jul 2008 09:29:05 +0200
Links: << >>  << T >>  << A >>
Yesterday, one of my Platform USB cables ceased working.
I opened the box and found cold solder joints at the
USB connector.

Since 1.) the connector pads are in the shadow of the shield,
they probably don't get enough InfraRed to heat and 
2.) solder joints under mechanical stress tend to open, I expect 
more USB platform cables out there that can be salvaged
with 4 blobs of solder.

regards, Gerhard

Article: 133842
Subject: Re: Xilinx/Altera gate equivalence
From: Bert <XaBerSas@gmail.com>
Date: Thu, 17 Jul 2008 00:35:58 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 17 jul, 05:00, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal
Murray) wrote:
> >Anyway, this is not an academic exercise. Porting a very complex
> >Virtex4 design
> >to Stratix is not something that one can do in a few days, so I was
> >looking
> >for ballpark estimates about the equivalence between Xilinx and Altera
> >"gates".
>
> Have you looked at the Stratix data sheet? =A0Did you find anything
> close to a CLB/FF pair? =A0If so, assume they are 1:1.
>
> Then count the special things you use: BRAMs, clock buffers, multipliers
> and whatevber. =A0Then see if Altera has something similar.
>
> --
> These are my opinions, not necessarily my employer's. =A0I hate spam.

Hi,

I have searched before about the comparison Logic Elements and Logic
Cells. Most of the result say LE =3D LC, but once (@ Altera website) I
found that LE =3D 1.125*LC

Bye
Bert

Article: 133843
Subject: Re: Xilinx/Altera gate equivalence
From: "HT-Lab" <hans64@ht-lab.com>
Date: Thu, 17 Jul 2008 08:44:38 +0100
Links: << >>  << T >>  << A >>

"dudesinmexico" <dudesinmexico@gmail.com> wrote in message 
news:2e6bf67c-1107-4af3-8452-6b7598a4bf98@25g2000hsx.googlegroups.com...
On Jul 16, 11:57 am, Mike Treseler <mike_trese...@comcast.net> wrote:
> dudesinmexico wrote:
> > Are there any rules of thumb to figure out the equivalent number of
> > logic resources
> > needed to implement the same design on Stratix IV vs., say,
> > Virtex-4/5?
> > I am thinking of random logic, i.e. a CLB vs. LAB conversion factor...
>
> Quartus will give the exact utilization
> and pick a device for you, if you have source code.
>
>
>I don't, and that's why I am asking... I have a Virtex-4 design and
>I'd like to find what Stratix IV
>part it will fit in.
>
> dudesinmexico

1) Get an evaluation license for Precision/Synplicity
2) Download a number of large free design from the web
3) Synthesize for Virtex4/Stratix4
4) P&R the designs, compare Area/Delay

IMHO there is very little point in comparing large FPGA's from an 
architectural point of view without including the Synthesis/P&R factor.

Hans
www.ht-lab.com






Article: 133844
Subject: usb core block diagram
From: hmmudassir82@gmail.com
Date: Thu, 17 Jul 2008 00:46:14 -0700 (PDT)
Links: << >>  << T >>  << A >>
I am mudassir.
I want to get internal block diagram of usb core 2.0 or any other.
Please give me if any one have this internal block diagram with full
signals and timing diagram so that i
can easily understand  functionality and design core .
thanks.

Article: 133845
Subject: Re: unified protocol
From: "RCIngham" <robert.ingham@gmail.com>
Date: Thu, 17 Jul 2008 03:02:04 -0500
Links: << >>  << T >>  << A >>
For anyone but 'raj' who is interested, apparently he is talking about an
as-yet-to-be-released standard:
http://www.mipi.org/wgoverview.shtml

I think he's going to be on his own here...

Toodle-pip!


Article: 133846
Subject: XAPP240 - Design Files
From: "ALuPin@web.de" <ALuPin@web.de>
Date: Thu, 17 Jul 2008 01:19:14 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi newsgroup,

does someone know whether there are design files available
for Xilinx application note "XAPP240 - High-Speed Buffered Crossbar
Switch Design Using Virtex-EM Devices" ?

I did not found any files on the Xilinx archives.

Rgds
Andre

Article: 133847
Subject: Re: What's wrong with this Virtex4 DCM?
From: "jerzy.gbur@gmail.com" <jerzy.gbur@gmail.com>
Date: Thu, 17 Jul 2008 01:36:30 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 8 Lip, 15:46, Nemesis <gnemesis2...@gmail.com> wrote:
> I'm using the DCM instantiation reported below, on a Virtex4fx60
> target.
> I have two different boards (ICS-8550) the differ only for the
> ruggedization level, the boards are almost the same and so should be
> the FPGAs, maybe only the stepping level is different.
>
> But on one board is working and on another one is not working.
>
> I'm providing a 300ms long reset signal as requested on the V4 user
> guide but the DCM doesn't get locked.
>
> The input is a 100MHz clock and the sys_clock_dcm signal is valid, but
> I don't get the divided, multiplied and FX clocks, and the lock signal
> is down.
>
> The same bitstream is working on
>
> =A0 =A0 SYSTEM_DCM: DCM
> =A0 =A0 generic map (
> =A0 =A0 =A0 =A0 CLKFX_DIVIDE =A0 =A0=3D> 8,
> =A0 =A0 =A0 =A0 CLKFX_MULTIPLY =A0=3D> 2
> =A0 =A0 =A0 =A0 )
> =A0 =A0 port map (
> =A0 =A0 =A0 =A0 CLKIN =A0 =A0=3D> adc1_clk_in,
> =A0 =A0 =A0 =A0 CLKFB =A0 =A0=3D> sys_clock_dcmfb,
> =A0 =A0 =A0 =A0 DSSEN =A0 =A0=3D> '0',
> =A0 =A0 =A0 =A0 PSINCDEC =3D> '0',
> =A0 =A0 =A0 =A0 PSEN =A0 =A0 =3D> '0',
> =A0 =A0 =A0 =A0 PSCLK =A0 =A0=3D> '0',
> =A0 =A0 =A0 =A0 RST =A0 =A0 =A0=3D> my_dcm_reset,
> =A0 =A0 =A0 =A0 CLK0 =A0 =A0 =3D> sys_clock_dcm,
> =A0 =A0 =A0 =A0 CLKDV =A0 =A0=3D> sys_clock_x05_i,
> =A0 =A0 =A0 =A0 CLK2X =A0 =A0=3D> sys_clock_x2_i,
> =A0 =A0 =A0 =A0 CLKFX =A0 =A0=3D> sys_clock_fx_i,
> =A0 =A0 =A0 =A0 LOCKED =A0 =3D> sys_lock
> =A0 =A0 =A0 =A0 );
>
> =A0 =A0 sys_clock_dcm_bufg: BUFG port map( I =3D> sys_clock_dcm, O =3D>
> sys_clock_dcmfb);

Hi,

I had similar problem with locking FX outputs.
I found following solution:

---------------------------------------------------------------------------=
-----
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.VComponents.all;

entity dfs is
   generic        (
                  MVAL                 :  integer range 1 to 32:=3D 4;
                  DVAL                 :  integer range 1 to 32:=3D 2;
                  CLKINPERIOD          :  real :=3D 10.0
--                  CLKINPERIOD          :  integer range 2 to 1000 :=3D
10
                  );
   port           (
                  CLKIN                :  in    std_logic;
                  DFS_RESET            :  in    std_logic;
                  CLKFX_OUT            :  out   std_logic;
                  CLKFX180_OUT         :  out   std_logic;
                  DFS_LOCKED           :  out   std_logic
                  );
end dfs;

architecture rtl of dfs is

   signal         DRP_OUT              :  std_logic_vector(15 downto
0);
   signal         DRP_RDY              :  std_logic;
   signal         DRP_ADR              :  std_logic_vector(6 downto
0);
   signal         DRP_EN               :  std_logic;
   signal         DRP_WE               :  std_logic;
   signal         RESET_FLOP           :  std_logic;

   signal         logic0               :  std_logic;
   signal         logic1               :  std_logic;
   signal         logic0_16b           :  std_logic_vector(15 downto
0);

begin

logic0 <=3D '0';
logic1 <=3D '1';
logic0_16b <=3D "0000000000000000";
DFS_LOCKED <=3D DRP_OUT(0);

dfsinst:
   DCM_ADV
      generic map (
                  CLK_FEEDBACK         =3D> "NONE",
                  CLKDV_DIVIDE         =3D> 2.0,
                  CLKFX_DIVIDE         =3D> DVAL,
                  CLKFX_MULTIPLY       =3D> MVAL,
                  CLKIN_DIVIDE_BY_2    =3D> FALSE,
                  CLKIN_PERIOD         =3D> CLKINPERIOD,
                  CLKOUT_PHASE_SHIFT   =3D> "NONE",
                  DCM_AUTOCALIBRATION  =3D> FALSE,
                  DCM_PERFORMANCE_MODE =3D> "MAX_SPEED",
                  DESKEW_ADJUST        =3D> "SYSTEM_SYNCHRONOUS",
                  DFS_FREQUENCY_MODE   =3D> "LOW",
                  DLL_FREQUENCY_MODE   =3D> "LOW",
                  DUTY_CYCLE_CORRECTION =3D> TRUE,
                  FACTORY_JF           =3D> x"F0F0",
                  PHASE_SHIFT          =3D> 0,
                  STARTUP_WAIT         =3D> FALSE
                  )
      port map    (
                  CLK0                 =3D> open,
                  CLK180               =3D> open,
                  CLK270               =3D> open,
                  CLK2X                =3D> open,
                  CLK2X180             =3D> open,
                  CLK90                =3D> open,
                  CLKDV                =3D> open,
                  CLKFX                =3D> CLKFX_OUT,
                  CLKFX180             =3D> CLKFX180_OUT,
                  DO                   =3D> DRP_OUT,
                  DRDY                 =3D> DRP_RDY,
                  LOCKED               =3D> open,
                  PSDONE               =3D> open,
                  CLKFB                =3D> logic0,
                  CLKIN                =3D> CLKIN,
                  DADDR                =3D> DRP_ADR,
                  DCLK                 =3D> CLKIN,
                  DEN                  =3D> DRP_EN,
                  DI                   =3D> logic0_16b,
                  DWE                  =3D> DRP_WE,
                  PSCLK                =3D> logic0,
                  PSEN                 =3D> logic0,
                  PSINCDEC             =3D> logic0,
                  RST                  =3D> DFS_RESET
                  );
P0000:
   process(CLKIN)
   begin
      if rising_edge(CLKIN) then
         if (DFS_RESET =3D '1') then
            RESET_FLOP <=3D logic0;
            DRP_EN <=3D logic0;
            DRP_WE <=3D logic0;
            DRP_ADR <=3D "0111111";
         elsif (RESET_FLOP =3D '0' and DFS_RESET =3D '0') then
            RESET_FLOP <=3D logic1;
            DRP_EN <=3D logic1;
            DRP_WE <=3D logic1;
            DRP_ADR <=3D "0111111";
         elsif (DRP_RDY =3D '1') then
            RESET_FLOP <=3D RESET_FLOP;
            DRP_EN <=3D logic1;
            DRP_WE <=3D logic0;
            DRP_ADR <=3D "0110000";
         else
            RESET_FLOP <=3D RESET_FLOP;
            DRP_EN <=3D logic0;
            DRP_WE <=3D DRP_WE;
            DRP_ADR <=3D DRP_ADR;
         end if;
      end if;
   end process;

end rtl;
---------------------------------------------------------------------------=
-----------------------

Maybe it can help you.

Best Regards,

Jerzy Gbur

Article: 133848
Subject: Re: Fifo Simulation Error
From: Rob <BertyBooster@googlemail.com>
Date: Thu, 17 Jul 2008 01:58:05 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 16, 3:49 pm, Zhane <m...@hotmail.com> wrote:
> On Jul 16, 11:31 pm, Dave <dhsch...@gmail.com> wrote:
>
>
>
> > On Jul 16, 10:51 am, Zhane <m...@hotmail.com> wrote:
>
> > > On Jul 16, 10:39 pm, Zhane <m...@hotmail.com> wrote:
>
> > > > On Jul 16, 8:58 pm, KJ <kkjenni...@sbcglobal.net> wrote:
>
> > > > > On Jul 16, 8:52 am, KJ <kkjenni...@sbcglobal.net> wrote:
>
> > > > > > On Jul 16, 5:39 am, Zhane <m...@hotmail.com> wrote:
>
> > > > > Woops, failed basic mathematics myself on the previous post.  115200
> > > > > baud will translate to ~11KB/sec which is 3000x slower than the
> > > > > implied input rate of 33 MB/sec...not 3x.  Replace all 3x with 3000x
> > > > > in the previous post...get a reeeeeally big memory buffer
>
> > > > > KJ
>
> > > > :(
> > > > im trying to sample the LPC bus though... I've already reduced to the
> > > > minimal that I think I need...and with what I have now, there are
> > > > weird extra cycles appearing at places where they shuoldnt be. Without
> > > > these samples, I cant determine if those weird cycles are relevant or
> > > > not.
>
> > > > >.<
>
> > > > :( how? my Spartan 3E has a USB interface, but... it's used to program
> > > > my board.
>
> > > > Can I remove my usb cable after downloading my program, and use it to
> > > > transfer instead?
> > > > what kind of program (eg.hyperterminal for rs232) is required for usb?
>
> > > hmmm
> > > I guess I can give up on usb.. I cant find a VHDL usb core to use
> > > anyway ~_~
>
> > Maybe you could build a module to look for a condition on the bus that
> > is interesting to you, and store everything just before and after that
> > event? Then you could transmit the stored data out the UART. You just
> > need to figure out how to detect your error on-the-fly.
>
> > Dave
>
> ya
> im sort of trying to do it now
> but it's either my condition aint met
>
> or the bus go crazy =P
>
> A
> B
> C
> C
> D
>
> It's supposed to be A,B,C,D,E, but sometimes it has repeats like ABCCD
> or ABBCDE o_o!!

If I was you i'd go back to pen and paper and carefully think about
and plan the design. Then probably start again with the coding.

Article: 133849
Subject: Read files from Compact Flash
From: "paolo.furia" <paolo.furia@gmail.com>
Date: Thu, 17 Jul 2008 02:28:14 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi all,
I'm working on a dynamically reconfigurable project on ML402 (virtex-4
sx35) and, for this, I have to load partial bitstreams from a Compact
Flash. I successfully generated a system.ace file that works fine and
configure my fpga at turn on. The problems come when I try to load a
partial bitstream stored on the CF: it always isn't possible and the
error led turn on. The first time I try to open bitstream the program
stalls, the second time it says that it can't open the file. Always
so.
I tried to open and read an image .bmp, using sysace_fopen and
sysace_fread, and it works. The problem comes with bitstreams
(both .bit and .bin).
I have this problem both in my reconfigurable system and in a normal
system based on MicroBlaze.

Have you any suggestion? I would be grateful for your help.

Paolo



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