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Messages from 126450

Article: 126450
Subject: Re: VHDL language is out of date! Why? I will explain.
From: Wolfgang Grafen <wolfgang.grafen@gmx.de>
Date: 22 Nov 2007 19:19:44 GMT
Links: << >>  << T >>  << A >>
In <47449ab1$1_4@mk-nntp-2.news.uk.tiscali.com> Paul Taylor  wrote:
> On Wed, 21 Nov 2007 15:55:46 +0100, Colin Paul Gloster wrote:
> 
>> One of the main goals of static strong typing such as in VHDL and Ada
>> is to detect mistakes early... <snip>
> 
> Compiling a small program that you want to change/run is a pain, so
> dynamic/scripting languages are great here. 
Think about that producing code means 80% or more testing effort. Compiling
VHDL is really not the problem for a simulation but testing. A dynamic language
allows you also a kind of "dynamic testing" which would speed up the overall
process dramatically.

You could test a function or process written in the architecture from one or
more separate test programs with a Python like HDL language, with life inspection! 
There is nothing close to that useability in VHDL. And the code would be at 
least as readable as VHDL.

> But then for larger programs,
> scripting languages are a pain for the reasons you state. Others
> like/advocate them for writing large programs but I can't understand that.
> So I'm with you here.
Large programs mainly benefit from a clean concept. If you don't have a clean
concept you will fail both in a dynamic and static programming language. This
is the main difference between small and large programs.

If we neglect peformance issues a modern scripting language is as least as good
as a static language. If you did all the regression tests properly you will not
experience any surprises with e.g. Python.
> 
>> Python with the Stratus hardware description language has not
>> displaced VHDL yet. Nor has Python with MyHDL.
MyHDL is a one man show. I doubt that Python is the ideal language based for
hardware description. I believe it is possible to design a very concise dynamic
language for hardware design. But this will significantly more than one person
to bring it up. My impression is MyHDL is not very suitable for large projects now.
> 
> Probably nothing will displace vhdl/verilog. Just like nothing has
> and probably won't replace C for embedded programming, for example. That's
> been around for years as well.
Of course there will come something, no doubt. Hopefully it will be better... 
> 
>SNIP>
> Paul Taylor.
> 
Regards

Wolfgang Grafen

Article: 126451
Subject: Re: DCM with instable clock
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Thu, 22 Nov 2007 13:57:44 -0600
Links: << >>  << T >>  << A >>
In article <4b0dadd1-4bdb-4825-ad06-6d8ca2c6df02@i29g2000prf.googlegroups.com>, wxy0624@gmail.com writes:
>In a design, I have to generate several clocks with precisely phase
>relationship, I'd like to use DCM. But the clock_input is not stable.
>It could possiblely change frequency, even stop for a while. I dont
>have input signal to reset DCM. How can I use DCM in this condition?
>Or, if don't use DCM, how can I chieve precise phase relationship?

What sort of frequency range are you interested in?

This isn't "phase" as measured in degrees, but have you
considered an external delay line?  If you pick the delays
for the fastest frequency the logic should still work when
the clock slows down.  But it might not give you the output
you want.

Have you looked at clock generator chips?  Some of them
have multiple outputs at different speeds.  You might get
lucky and find something that fits you needs.

In the old days, the do-it-yourself clock generator was
a PAL clocked at twice the highest speed you needed.
(Or a '374 and a few gates.)

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 126452
Subject: Re: VHDL language is out of date! Why? I will explain.
From: Mike Treseler <mike_treseler@comcast.net>
Date: Thu, 22 Nov 2007 13:33:14 -0800
Links: << >>  << T >>  << A >>
Paul Taylor wrote:
> ...
> I also have a marked keyword, which is a safeguard
> because sometimes I stupidly use the wrong variable, e.g. an
> unsynchronised signal instead of one that I have synchronised for use
> (especially when I come back to change some code). 

Interesting.
I now handle this manually by using annoying
identifiers for the unsynch nodes.
Maybe "run_glitchy" vs "run".

> I would be interested to know what mistakes others commonly make, that are
> found by the VHDL compiler.

OK here's mine.
I get automated mistake-finding at the
editor, analysis, and elaboration level
of each library unit.

1. Emacs vhdl-mode completes keywords
and identifiers, matches most parens
and prompts for clauses in a keyword statement.
This prevents most syntax errors from happening.

2. I run simulation analysis
 vcom -c mydesign.vhd
from an editor function key every few lines of code.
This step finds the most errors
but puts the cursor right on each one
and tells me what's wrong.

I would estimate:
90% syntax punctuation: missing or excess : ; ) etc.
10% static mismatch of code with local or library subtypes.
    Length, range etc.
10% signature mismatch of code and local or library subprograms

At the top level, Emacs vhdl-make automatically finds
units with multiple declarations in the project path, like this:
WARNING:  Architecture declared twice (used 1.): "synth" of "cnt_decode"
  1. in "~/vhdl/play/cnt__decode.vhd" (line 18)
  2. in "~/vhdl/play/cnt_decode.vhd"  (line 18)

3. elaboration:
   vsim -c mydesign
will find most runtime mismatches
and give a pretty good description of what's wrong.
Some messages are more cryptic hints at infinite loops,like
** Fatal: Write failure in vlm process (32,-1)

That leaves the functional errors to simulation
viewers and assertions, but I have no automated
method for this.

        -- Mike Treseler

Article: 126453
Subject: Re: Virtex 5 PCB Designers Guide: required capacitors
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 22 Nov 2007 13:39:12 -0800
Links: << >>  << T >>  << A >>
<michel.talon@gmail.com> wrote in message 
news:b72afc41-d770-40ba-b71d-e9eb2142fb8a@e6g2000prf.googlegroups.com...
> Hi all,
>
>
> So my question is, what do you think about that ? and what will you
> advice to me ? Do you think it would be better if I add 1nF capacitors
> for very high frequencies variations ?
>
> Thanks by advance,
>
> Best regards, Michel.

Hi Michel,
Instead of starting yet another thread on bypass caps, perhaps you could go 
and read the ones we've already had? There's plenty to choose from. Google 
groups or fpga-faq.com for comp.arch.fpga .
If you want the latest and greatest technology, do a google search for X2Y 
caps.
Cheers, Syms. 



Article: 126454
Subject: Re: DDR2 dqs pin // virtex4
From: Joseph Samson <user@not.my.company>
Date: Fri, 23 Nov 2007 00:28:40 GMT
Links: << >>  << T >>  << A >>
bhb wrote:
> Thank you for comment.
> I need to change my file.ucf to route the FPGA. So, the information is
> opposite.
I'm sorry that I still don't understand what you're telling me. Can you 
explain why fixing the ucf file isn't the correct solution and can you 
please tell me what the original ISE error was?

> I changed IOBUFDS for only DQS1, DSQ1_N
> I invert DQS1 bit in the DQS1 generation logic, but I have no result in the
> board (the source code was tested
> in a other DDR2 memory with success).

Can you explain this in much more detail? What do you mean that the 
source code was tested in another DDR2 memory with success?

> Could you indicate me an example (please find the code in my first mail) to
> invert  DQS1 bit

My VHDL is rusty, how about:
   iobuf_dqs : IOBUFDS
     port map (
       O   => dqs1_in,
       IO  => DDR_DQS1,
       IOB => DDR_DQS1_L,
       I   => not dqs1_out,
       T   => ctrl_dqs_en_r1
       );

---
Joe

Article: 126455
Subject: Re: EDK + Modelsim simulation : Memory allocation failure
From: Kim Enkovaara <kim.enkovaara@iki.fi>
Date: Fri, 23 Nov 2007 08:56:02 +0200
Links: << >>  << T >>  << A >>
Pasacco wrote:
> The "memory allocation problem" occurred when I tried to run "Post PAR
> simulation" in Modelsim.
> SDF file size is 29MB. The system contains 12 MicroBlaze and totally
> 125 BRAMs.
> It seems that 29MB of SDF file and 12 MicroBlazes are too much for
> Modelsim.

That should not be a problem. I have simulated with Modelsim designs
that have 2+Gbyte SDFs and hundreds of big memories. And those
simulations needed about 3G of memory with Modelsim-SE.

Netlist simulations are usually quite hard to get going. Why do you even
need them? RTL-simulations + STA should usually be enough, unless
synthesis bug is suspected or some error in STA scripts.

At ASIC side netlist simulations are more common, but there the errors
also cost millions of dollars. I consider netlist simulations to be
aid for STA script verification, if formal tools for that are not
available for the user.

> If anyone has experience to "simulate (relatively) large system",
> please let me know.

You could try without vopt, just add -novopt to the vsim command line.
It seems that vopt is running out of memory, and that is the
optimizer before simulations. I have been more successful with the old
-fast flow especially for big netlists.

--Kim

Article: 126456
Subject: Re: VHDL language is out of date! Why? I will explain.
From: Helmut <helmut.leonhardt@gmail.com>
Date: Fri, 23 Nov 2007 00:59:11 -0800 (PST)
Links: << >>  << T >>  << A >>
I agree that VHDL has some disadvantages when I comes to syntax
features.But if there is not a synthesis tools, I just can=B4t use any
other language to program my FPGA.

Article: 126457
Subject: xilinx spartan 3 + 16 adc
From: wojjed@gmail.com
Date: Fri, 23 Nov 2007 01:08:53 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi

I'd like to ask if that device will process data from 16 ADC (20 bit,
44,1kHz)  to one output stream (does it depend on ADC clock - i mean
adc input clock = amount of output samples/s ? ) ?  Or maybe i should
consider using external input buffers ?

thx in advance

Article: 126458
Subject: Re: xilinx spartan 3 + 16 adc
From: "jerzy.gbur@gmail.com" <jerzy.gbur@gmail.com>
Date: Fri, 23 Nov 2007 01:40:58 -0800 (PST)
Links: << >>  << T >>  << A >>
On 23 Lis, 10:08, woj...@gmail.com wrote:
> Hi
>
> I'd like to ask if that device will process data from 16 ADC (20 bit,
> 44,1kHz)  to one output stream (does it depend on ADC clock - i mean
> adc input clock = amount of output samples/s ? ) ?  Or maybe i should
> consider using external input buffers ?

Could you be more specific?
What kind of ADC?
What kind of spartan3?
What exactly do you want to do?

Regards,

Jerzy Gbur

Article: 126459
Subject: Re: PCI Mezzanine Card with Xilinx Virtex-II
From: cmoore <moore_craig96@yahoo.co.uk>
Date: Fri, 23 Nov 2007 01:53:02 -0800 (PST)
Links: << >>  << T >>  << A >>
On 22 Nov, 10:24, Philipp <Patrick.Batema...@gmx.at> wrote:
> Hi
>
> I would like to use the following evaluation board to run my
> implementation:
>
> http://www.alpha-data.com/adm-xrc-ii.html
>
> My intention was to use Chipscope in combination with JTAG to
> download the bitstream to the FPGA and then use Chipscope to
> analyse whats going on in the chip. Unfortunately the documentation
> for this card doesnt not say a lot how this can be accomplished.
>
> It says that there is a External JTAG connector and it supports
> Chipscope but I couldnt find any information how this can be done,
> for instance what additional hardware do I need to connect to the
> JTAG interface. Anyone made an experience with such a card and
> could give me some hints?
>
> Many thanks,
> Philipp


Hi,

You may also want to consider a Nallatech board as another option.
There is a standard JTAG header on their boards which is easy to
access.  I've used Chipscope quite successfully on a few of their
boards - http://www.nallatech.com/

Craig

Article: 126460
Subject: Re: FPGA for hobby use
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Fri, 23 Nov 2007 12:12:17 -0000
Links: << >>  << T >>  << A >>
> Nobody should be instantiating discrete gates in an FPGA (iobuffers
> and other special ones exempted), instead they should be writing
> equations - HDL code - that accomplish the intended function in a
> concise and comprehensible way.


I don't think Symon's suggesting that schematics should be used at this
level, but an introduction via shematics will give some background in
what's being implemented.


It might help someone undertand why it's not a good idea to have
too many layers of 'if' statements in a process if they're trying
to meet tight timing requirements etc.



Nial. 



Article: 126461
Subject: Re: xilinx spartan 3 + 16 adc
From: wojjed@gmail.com
Date: Fri, 23 Nov 2007 04:31:24 -0800 (PST)
Links: << >>  << T >>  << A >>

sorry i did miss "xc3s50"
i want to connect 16 outputs from ADC (dont know specification yet) to
FPGA inputs and convert them to one stream.

regards

On 23 Lis, 10:40, "jerzy.g...@gmail.com" <jerzy.g...@gmail.com> wrote:
> On 23 Lis, 10:08, woj...@gmail.com wrote:
>
> > Hi
>
> > I'd like to ask if that device will process data from 16 ADC (20 bit,
> > 44,1kHz)  to one output stream (does it depend on ADC clock - i mean
> > adc input clock = amount of output samples/s ? ) ?  Or maybe i should
> > consider using external input buffers ?
>
> Could you be more specific?
> What kind of ADC?
> What kind of spartan3?
> What exactly do you want to do?
>
> Regards,
>
> Jerzy Gbur


Article: 126462
Subject: Re: xilinx spartan 3 + 16 adc
From: taco <tralalal@joepie.nl>
Date: Fri, 23 Nov 2007 13:52:22 +0100
Links: << >>  << T >>  << A >>
wojjed@gmail.com wrote:

> 
> sorry i did miss "xc3s50"
> i want to connect 16 outputs from ADC (dont know specification yet) to
> FPGA inputs and convert them to one stream.
> 
> regards
> 
the 44.1 khz is a serial output rate of the ADC? and the total output rate
without headers, dataprocessing or whatever is 44.1*20*16= 14 Mbps?  Should
be possible with such a device if you choose a correct clock frequency.
Taco


> On 23 Lis, 10:40, "jerzy.g...@gmail.com" <jerzy.g...@gmail.com> wrote:
>> On 23 Lis, 10:08, woj...@gmail.com wrote:
>>
>> > Hi
>>
>> > I'd like to ask if that device will process data from 16 ADC (20 bit,
>> > 44,1kHz)  to one output stream (does it depend on ADC clock - i mean
>> > adc input clock = amount of output samples/s ? ) ?  Or maybe i should
>> > consider using external input buffers ?
>>
>> Could you be more specific?
>> What kind of ADC?
>> What kind of spartan3?
>> What exactly do you want to do?
>>
>> Regards,
>>
>> Jerzy Gbur


Article: 126463
Subject: Re: EDK + Modelsim simulation : Memory allocation failure
From: Pasacco <pasacco@gmail.com>
Date: Fri, 23 Nov 2007 04:58:28 -0800 (PST)
Links: << >>  << T >>  << A >>
> You could try without vopt, just add -novopt to the vsim command line.
> It seems that vopt is running out of memory, and that is the
> optimizer before simulations. I have been more successful with the old
> -fast flow especially for big netlists.

Actually i did wish to obtain VCD file.
Using -novopt option, "memory failure" message disappeared, for EDK
project with 12 MicroBlazes.
Now I can proceed, for even larger system.
Thanks Kim

Article: 126464
Subject: Re: Xilinx Virtex-II Newbie
From: Andreas Ehliar <ehliar-nospam@isy.liu.se>
Date: Fri, 23 Nov 2007 13:37:00 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2007-11-16, Brian Drummond <brian_drummond@btconnect.com> wrote:
> What Andreas is suggesting (I think) is to divide your "register" space
> into two subspaces - even numbered registers, and odd regs. Each space
> uses the 1-W, N-R structure above.

Exactly, though I could certainly have made the point more clear in
my original posting.

/Andreas

Article: 126465
Subject: can't read/load memory contents
From: dartanian <dartanians@gmail.com>
Date: Fri, 23 Nov 2007 06:35:09 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello there, one of new members around here.

I've got a problem while i try to retrieve/pass over some values to
memory. I use EDK 9.1 and a system of microblaze, opb bus and opb
bram
memory.
I try to retrieve some values from memory through a vhdl testbench,
which is port mapped in the PORT B of Bram (by making Bram's PORT B
external) and then write back these contents in other blocks - after
some processing.
I use Eclipse SDK 9.1 for that and write the following code (load and
store instructions) within a loop:


 asm(" lwi r8,r8,0x7a810001 ");
 asm(" sw r8,r8(r8) ");


I don't seem to get the contents of 0x7a810001 address (which is
'bbbbbbbb' - given by vhdl testbench) into the simulation outcome.
Is there sth wrong with the use of instructions? Should i use an OR/
ORI as well? Any problems with 16 or 32 bit values?


Thank you very much guys in advance!

Article: 126466
Subject: Re: VHDL language is still quite useful.
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 23 Nov 2007 10:56:22 -0800
Links: << >>  << T >>  << A >>
Helmut wrote:
> I agree that VHDL has some disadvantages when I comes to syntax
> features.But if there is not a synthesis tools, I just canīt use any
> other language to program my FPGA.

Sorry. Let me fix that subject line.
I agree with you.
The thread went off on a tangent
as they often do :)

       -- Mike Treseler



Article: 126467
Subject: How to simulate these example CORDIC code?
From: fl <rxjwg98@gmail.com>
Date: Fri, 23 Nov 2007 11:48:33 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi,
I want to learn the implementation of CORDIC. I find the following
website has some code which I would like begin with it.


http://www.ht-lab.com/freecores/cordic/cordic.html

But I cannot simply simulate it in my Modelsim PE (student version)
because of the setup problem. Could you, the FPGA and VHDL experts can
tell me how to simulate it? Especially could you tell me how its
structure about the behaviour and synthesis files arranged?


Thanks in advance.

Article: 126468
Subject: Re: How to simulate these example CORDIC code?
From: "KJ" <kkjennings@sbcglobal.net>
Date: Fri, 23 Nov 2007 21:05:59 GMT
Links: << >>  << T >>  << A >>

"fl" <rxjwg98@gmail.com> wrote in message 
news:ccb086d1-775c-44cf-8666-bc357a309d93@b15g2000hsa.googlegroups.com...
> Hi,
> I want to learn the implementation of CORDIC. I find the following
> website has some code which I would like begin with it.
>
>
> http://www.ht-lab.com/freecores/cordic/cordic.html
>
> But I cannot simply simulate it in my Modelsim PE (student version)
> because of the setup problem.
What is the 'setup problem'?  I'd suggest solving that first.

>Could you, the FPGA and VHDL experts can
> tell me how to simulate it?
I'd use Modelsim

> Especially could you tell me how its
> structure about the behaviour and synthesis files arranged?
>
Modelsim's GUI interface has a function that figures out the correct 
ordering of the files in the project.  Right click on one of the source 
files and then under 'Compile' look for something that says about 
auto-generating the compile order (I forget what the exact verbage is, but 
it's there).

KJ 



Article: 126469
Subject: Re: How to simulate these example CORDIC code?
From: fl <rxjwg98@gmail.com>
Date: Fri, 23 Nov 2007 13:12:09 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 23, 4:05 pm, "KJ" <kkjenni...@sbcglobal.net> wrote:
> "fl" <rxjw...@gmail.com> wrote in message
>
> news:ccb086d1-775c-44cf-8666-bc357a309d93@b15g2000hsa.googlegroups.com...> Hi,
> > I want to learn the implementation of CORDIC. I find the following
> > website has some code which I would like begin with it.
>
> >http://www.ht-lab.com/freecores/cordic/cordic.html
>
> > But I cannot simply simulate it in my Modelsim PE (student version)
> > because of the setup problem.
>
> What is the 'setup problem'?  I'd suggest solving that first.
>
> >Could you, the FPGA and VHDL experts can
> > tell me how to simulate it?
>
> I'd use Modelsim
>
> > Especially could you tell me how its
> > structure about the behaviour and synthesis files arranged?
>
> Modelsim's GUI interface has a function that figures out the correct
> ordering of the files in the project.  Right click on one of the source
> files and then under 'Compile' look for something that says about
> auto-generating the compile order (I forget what the exact verbage is, but
> it's there).
>
> KJ

Thank you for your reply. The following is from the add_files.tcl in
the work_ps directory. I guess these files to form work library.


add_input_file -format {VHDL} -work Cordic {D:/DEMO/demo_hdl_designer/
Cordic/hdl/shiftn_synthesis.vhd}
add_input_file -format {VHDL} -work Cordic {D:/DEMO/demo_hdl_designer/
Cordic/hdl/addsub_synthesis.vhd}
add_input_file -format {VHDL} -work Cordic {D:/DEMO/demo_hdl_designer/
Cordic/hdl/atan32_Arch1.vhd}
add_input_file -format {VHDL} -work Cordic {D:/DEMO/demo_hdl_designer/
Cordic/hdl/fsm_synthesis.vhd}
add_input_file -format {VHDL} -work Cordic {D:/DEMO/demo_hdl_designer/
Cordic/hdl/cordic_pkg_pkg.vhd}
add_input_file -format {VHDL} -work Cordic {D:/DEMO/demo_hdl_designer/
Cordic/hdl/cordic_synthesis.vhd}

Then, I form cordic_pkg to Cordic library. But the compiling error is

** Error: (vcom-11) Could not find cordic.addsub.
** Error: C:/Modeltech_pe_edu_6.3c/cordic_learn/hdl/
cordic_synthesis.vhd(143): (vcom-1195) Cannot find expanded name
"cordic.addsub".

That is the compiler looks for addsub in the Cordic lib, not work lib.
What's wrong? What is the function and differences of the directory
files. I cannot what are for simulation, what are for synthesis.
Thanks again.

Article: 126470
Subject: Re: How to simulate these example CORDIC code?
From: fl <rxjwg98@gmail.com>
Date: Fri, 23 Nov 2007 13:19:49 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 23, 4:05 pm, "KJ" <kkjenni...@sbcglobal.net> wrote:
> "fl" <rxjw...@gmail.com> wrote in message
>
> news:ccb086d1-775c-44cf-8666-bc357a309d93@b15g2000hsa.googlegroups.com...> Hi,
> > I want to learn the implementation of CORDIC. I find the following
> > website has some code which I would like begin with it.
>
> >http://www.ht-lab.com/freecores/cordic/cordic.html
>
> > But I cannot simply simulate it in my Modelsim PE (student version)
> > because of the setup problem.
>
> What is the 'setup problem'?  I'd suggest solving that first.
>
> >Could you, the FPGA and VHDL experts can
> > tell me how to simulate it?
>
> I'd use Modelsim
>
> > Especially could you tell me how its
> > structure about the behaviour and synthesis files arranged?
>
> Modelsim's GUI interface has a function that figures out the correct
> ordering of the files in the project.  Right click on one of the source
> files and then under 'Compile' look for something that says about
> auto-generating the compile order (I forget what the exact verbage is, but
> it's there).
>
> KJ


BTW, part of the contents in the cordic_synthesis.vhl is as the below.
Is it useful to understand the configuration?

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ADD1 : addsub USE ENTITY cordic.addsub;
   FOR ADD2 : addsub USE ENTITY cordic.addsub;
   FOR ADD3 : addsub USE ENTITY cordic.addsub;
   FOR ALL : atan32 USE ENTITY cordic.atan32;
   FOR ALL : fsm USE ENTITY cordic.fsm;
   FOR ALL : shiftn USE ENTITY cordic.shiftn;
   -- pragma synthesis_on

Thank you very much.

Article: 126471
Subject: Re: How to simulate these example CORDIC code?
From: fl <rxjwg98@gmail.com>
Date: Fri, 23 Nov 2007 13:37:20 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 23, 4:05 pm, "KJ" <kkjenni...@sbcglobal.net> wrote:
> "fl" <rxjw...@gmail.com> wrote in message
>
> news:ccb086d1-775c-44cf-8666-bc357a309d93@b15g2000hsa.googlegroups.com...> Hi,
> > I want to learn the implementation of CORDIC. I find the following
> > website has some code which I would like begin with it.
>
> >http://www.ht-lab.com/freecores/cordic/cordic.html
>
> > But I cannot simply simulate it in my Modelsim PE (student version)
> > because of the setup problem.
>
> What is the 'setup problem'?  I'd suggest solving that first.
>
> >Could you, the FPGA and VHDL experts can
> > tell me how to simulate it?
>
> I'd use Modelsim
>
> > Especially could you tell me how its
> > structure about the behaviour and synthesis files arranged?
>
> Modelsim's GUI interface has a function that figures out the correct
> ordering of the files in the project.  Right click on one of the source
> files and then under 'Compile' look for something that says about
> auto-generating the compile order (I forget what the exact verbage is, but
> it's there).
>
> KJ

Another question, how to run the "compile.scr "?

Article: 126472
Subject: Re: How to simulate these example CORDIC code?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 23 Nov 2007 13:55:13 -0800
Links: << >>  << T >>  << A >>
fl wrote:

> Another question, how to run the "compile.scr "?

I expect that you have to find modelsim.ini
and fix up the source paths to match
where they are on your machine.

Note that learning cordic theory has nothing
to do with learning vhdl or modelsim.
I would suggest starting with simpler examples
or tutorials for each topic.

And I would recommend not spending
any time learning hdl designer.
Just use an editor and modelsim directly.

    -- Mike Treseler

Article: 126473
Subject: Re: VHDL language is out of date! Why? I will explain.
From: nico@puntnl.niks (Nico Coesel)
Date: Fri, 23 Nov 2007 22:27:23 GMT
Links: << >>  << T >>  << A >>
Paul Taylor <ptaylor_ng@tiscali.co.uk> wrote:

>On Sat, 17 Nov 2007 20:52:59 +0100, Jan Decaluwe wrote:
>
>> The synthesizable RTL subset is what it is. Conceptually, there's little
>> to be gained from using MyHDL or whatever instead of VHDL for this.
>
>I think that there is something to be gained from using 'whatever', but it
>depends - if you are full-time vhdler working on small or large FPGA
>designs then fine; if you are an electronics engineer who on a reasonably
>regular basis has an FPGA that needs to be designed/verified then vhdl is
>(IMO of course) too complex, and, for test benches in particular, too
>cumbersome.

In that perpective, using C would have made much more sense. Most
electronics engineers can write software in C. Having to use python is
like trading one obscure language for another.

Anyway, I've been using VHDL for a couple of years now (on and off)
and I must say it has its disadvantages, but it also is pretty
powerfull. I particulary like the functions and records. They allow me
to write complex stuff in just a few lines.

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Article: 126474
Subject: Re: DCM with instable clock
From: wxy0624@gmail.com
Date: Fri, 23 Nov 2007 19:06:58 -0800 (PST)
Links: << >>  << T >>  << A >>
On 11=D4=C223=C8=D5, =C9=CF=CE=E73=CA=B157=B7=D6, hal-use...@ip-64-139-1-69.=
sjc.megapath.net (Hal
Murray) wrote:
> In article <4b0dadd1-4bdb-4825-ad06-6d8ca2c6d...@i29g2000prf.googlegroups.=
com>, wxy0...@gmail.com writes:
>
> >In a design, I have to generate several clocks with precisely phase
> >relationship, I'd like to useDCM. But the clock_input is not stable.
> >It could possiblely change frequency, even stop for a while. I dont
> >have input signal to resetDCM. How can I useDCMin this condition?
> >Or, if don't useDCM, how can I chieve precise phase relationship?
>
> What sort of frequency range are you interested in?
>
> This isn't "phase" as measured in degrees, but have you
> considered an external delay line?  If you pick the delays
> for the fastest frequency the logic should still work when
> the clock slows down.  But it might not give you the output
> you want.
>
> Have you looked at clock generator chips?  Some of them
> have multiple outputs at different speeds.  You might get
> lucky and find something that fits you needs.
>
> In the old days, the do-it-yourself clock generator was
> a PAL clocked at twice the highest speed you needed.
> (Or a '374 and a few gates.)
>
> --
> These are my opinions, not necessarily my employer's.  I hate spam.

Thank you, Murray

It's my fault that I didn't make a clear description.

My whole project is based on a virtex-4 SX55 FPGA, only one
clock_input, frequency up to 300MHz, and may chang to any frequency
slower, but not under my control. So, in  FPGA, I have to use some
logic to generate some slower clock in the FPGA to feed internal
logic, which have precisely phase relationship.

As the clock may change frequency while not even notified, how can I
use DCM wihout any UNLOCKED problem? Or, how can I got the clocks with
given phase relationship without DCM? Can I use the LOCKED signal to
reset DCM? Is it reliable?

Thanks!



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