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Messages from 126400

Article: 126400
Subject: Re: Xilinx XST 8.2, Error on multi-source, bug?
From: John McCaskill <jhmccaskill@gmail.com>
Date: Wed, 21 Nov 2007 03:32:16 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 21, 5:09 am, Timo Gerber <tim...@web.de> wrote:
> Hi,
> I'm using Xilinx 8.2.03i and I get an Error Xst:528 "Multi-source in
> Unit ..."
> It's a wire in a submodule and i checked the code:
> The signal is an output to module A and an input to module B.
> There is no other assignment to this signal. Inside module B the signal
> is only on the right-side of any "=" assignments.
>
> Could there be a bug in Xst when using a design containig both VHDL and
> verilog files?
>
> Timo


We use EDK, ISE, and ModelSim with mixed VHDL and Verilog designs, and
it works. We have instances of VHDL instantiating Verilog modules, and
Verilog instantiating VHDL. We are currently using 8.1 and 8.2.

The biggest problem that we have encountered is when passing generics
from VHDL to Verilog.  For example, if we are passing a generic from
VHDL to Verilog, and Verilog considers it an integer, ISE wants it
done one way, and ModelSim wants it done a different way.

The rest of the error message should tell you what it thinks the
multiple sources are, track that down to see if they really exit.

Regards,

John McCaskill
www.fastertechnology.com

Article: 126401
Subject: Re: simulating xilinx block ram with modelsim
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Wed, 21 Nov 2007 12:13:47 +0000
Links: << >>  << T >>  << A >>
On Tue, 20 Nov 2007 07:15:31 -0800 (PST), "u_stadler@yahoo.de"
<u_stadler@yahoo.de> wrote:

>
>hi
>
>thanks for all your advices! i found the problem.
>somehow the signals in the component instantiation got messd up
>(although i used the testbench generated by ise).
>anyway the problem was that data_in, data_out and RD, WR, CLK where in
>the wrong order. 

That sounds like the real problem was the use of positional association
rather than named association in the port map, making the error hard to
find.

- Brian


Article: 126402
Subject: Measuring setup and hold time in Lab
From: Ved <vedpsingh@gmail.com>
Date: Wed, 21 Nov 2007 04:22:26 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi all,
How can we measure setup and hold time of a flip-flop on FPGA in lab ?

Regards,
Ved

Article: 126403
Subject: Re: did i miss edk 9.2
From: satih82@gmail.com
Date: Wed, 21 Nov 2007 04:49:54 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi,

Does someone has the serial number for EDK 9.2i?

Article: 126404
Subject: Re: An error occured while using Dual Port Block Memory
From: Joseph Samson <user@not.my.company>
Date: Wed, 21 Nov 2007 07:55:16 -0500
Links: << >>  << T >>  << A >>
spygame81@gmail.com wrote:
> Hi!
> 
> I am using Dual Port Block Memory in Virtex-II, V8.2. During
> simulation in Modelsim, i have encountered an error that reports to me
> is:
> 
> $recovery(posedge clk B: .... ps, posedge clk A &&&
> collision_posa_posb: ... ns, 1ns);
> 
> How can i cater this issue and how can i remove this error in my
> simulation???

What have you tried and and why didn't it work?


Here's what I did:

1. Google "verilog $recovery"

2. Read the first citation
<http://toolbox.xilinx.com/docsan/xilinx5/data/docs/sim/sim0066_10.html>

---
Joe Samson
Pixel Velocity

Article: 126405
Subject: Re: partial dynamic reconfiguration on Virtex-4 SX35
From: rickman <gnuarm@gmail.com>
Date: Wed, 21 Nov 2007 05:54:04 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 21, 3:30 am, G_Abg <Gael.Abgr...@gmail.com> wrote:
> Hi,
>
> I have just begin my PhD on SDR and I will have to use a FPGA with
> partial dynamic reconfiguration. The system which interest me have a
> Xilinx Virtex-4 SX35 integrated on it and I'm not sure this FPGA can
> do it.
>
> If someone could answer me, it'll be great.

I haven't looked at the Virtex-4 devices in detail, but Xilinx has
included partial dynamic reconfiguration in their parts for several
generations now.   The trick is that they don't support this in
software... at least very well.  PDC sounds good on paper, but seems
to be hard to implement and clearly there is not much demand for it.

I'm curious, what is SDR and why are you working on it?

Article: 126406
Subject: Re: FPGA Editor (9.2.03i) under Linux x86_64
From: rickman <gnuarm@gmail.com>
Date: Wed, 21 Nov 2007 06:03:56 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 20, 6:22 pm, <steve.l...@xilinx.com> wrote:
> A substantial amount of work is required for each appication when we
> move away from Wind/U. We have decided not to do that for FPGA
> Editor. Instead, we are creating a new application that is a combination
> of PACE, Floorplanner, FPI, FPE and FPGA Editor. That will be
> available in 11.1 (March 2009).
>
> Steve

I read that correctly as a year and a half from now, right?  That
seems like a loooooong way off.  I remember once being told that
supporting partial reconfiguration on the Spartan devices was a few
months off and that Xilinx was committed to it. I don't think that has
ever materialized.  How serious is Xilinx about this new tool, PACE?
Anything more committal than just "committed"?


Article: 126407
Subject: Re: Xilinx XST 8.2, Error on multi-source, bug?
From: Gabor <gabor@alacron.com>
Date: Wed, 21 Nov 2007 06:21:49 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 21, 6:32 am, John McCaskill <jhmccask...@gmail.com> wrote:
> On Nov 21, 5:09 am, Timo Gerber <tim...@web.de> wrote:
>
> > Hi,
> > I'm using Xilinx 8.2.03i and I get an Error Xst:528 "Multi-source in
> > Unit ..."
> > It's a wire in a submodule and i checked the code:
> > The signal is an output to module A and an input to module B.
> > There is no other assignment to this signal. Inside module B the signal
> > is only on the right-side of any "=" assignments.
>
> > Could there be a bug in Xst when using a design containig both VHDL and
> > verilog files?
>
> > Timo
>
> We use EDK, ISE, and ModelSim with mixed VHDL and Verilog designs, and
> it works. We have instances of VHDL instantiating Verilog modules, and
> Verilog instantiating VHDL. We are currently using 8.1 and 8.2.
>
> The biggest problem that we have encountered is when passing generics
> from VHDL to Verilog.  For example, if we are passing a generic from
> VHDL to Verilog, and Verilog considers it an integer, ISE wants it
> done one way, and ModelSim wants it done a different way.
>
> The rest of the error message should tell you what it thinks the
> multiple sources are, track that down to see if they really exit.
>
> Regards,
>
> John McCaskillwww.fastertechnology.com


Are module A and B in this instance different languages?  If so make
sure that the port connections are all properly matched.  I've seen
cases where the error message doesn't necessarily give useful
information when you cross language boundaries, so it may not really
be a multi-source issue.

Also make sure that the sourcing module doesn't report a multi-
source if you build it alone.  If you use Verilog, XST will complain
of multi-source if you assign a register in more than one always
block.

Regards,
Gabor

Article: 126408
Subject: Re: Problem using xilinx usb download cable in linux
From: Ken Ryan <newsryan@leesburg-geeks.org>
Date: Wed, 21 Nov 2007 14:36:15 GMT
Links: << >>  << T >>  << A >>
roger wrote:
> On Nov 10, 1:07 pm, Michael Gernoth <m...@gernoth.net> wrote:
>> Hi,
>>
>> On Sat, 03 Nov 2007 22:04:14 -0000, roger wrote:
>>> I have installed the usb-driver fromhttp://www.rmdir.de/~michael/xilinx
>>> and I have managed to light up the green led to the usb download cable
>>> on the spartan 3e starter kit. The green led is going black every 6-8
>>> second and then green again.
>> I have not heard of this behaviour previously. For me this seems to
>> indicate that the cable gets dis- and reconnected all the time.
>> Do you see reoccuring dis-/reconnects in "dmesg".
>>
>>> I don't manage to get a connection to the board using Impact. lsusb
>>> gives me the following:
>>> Bus 005 Device 012: ID 03fd:0008 Xilinx, Inc.
>>> [...]
>>> can't get device qualifier: Operation not permitted
>> What are the permissions on /dev/bus/usb/005/012 (or the current
>> location of the cable)? This error might show there is a permission
>> problem. You did add the MODE-line to an udev rules-file?
>>
>>> and Impact says:
>>> Connecting to cable (Usb Port - USB21).
>>> Checking cable driver.
>>> File version of /usr/share/xusbdfwu.hex = 1025(dec), 0401.
>>>  libusb-driver.so version: 2007-10-08 15:43:55.
>>> Cable connection failed.
>> If you preload libusb-driver-DEBUG.so instead of libusb-driver.so you
>> get a much more detailed output, which could tell why impact does not
>> find the device (which according to your lsusb-output has the correct
>> firmware loaded).
>>
>> Regards,
>>   Michael
> 
> Hi Michael,
> 
> The permissions on /dev/bus/usb/005/016 is:
> 
> crw-rw-r-- 1 root root 189, 512 2007-11-12 18:37 001
> crw-rw-rw- 1 root root 189, 527 2007-11-12 21:45 016
> 
> from the dmesg output you can see that the cable jumps around between
> different buses:
> 
> [14746.456000] usb 5-2: new high speed USB device using ehci_hcd and
> address 14
> [14746.588000] usb 5-2: configuration #1 chosen from 1 choice
> [14746.972000] usb 5-2: USB disconnect, address 14
> [14748.984000] usb 1-2: new full speed USB device using uhci_hcd and
> address 10
> [14749.124000] usb 1-2: not running at top speed; connect to a high
> speed hub
> [14749.148000] usb 1-2: configuration #3 chosen from 1 choice
> [14778.480000] usb 1-2: USB disconnect, address 10
> [14780.092000] usb 5-2: new high speed USB device using ehci_hcd and
> address 16
> [14780.224000] usb 5-2: configuration #2 chosen from 1 choice
> 
> Any idea why I get this behaviour?
> 
> Thanks!
> 
> /Roger
> 

Where are you plugged in?  It sounds as if you are on a port that isn't 
giving enough power (not that the cable needs much).

If you aren't already, try plugging into the USB ports on the back of 
the machine that are directly part of the mainboard or I/O board.  Often 
the front-panel ports are underpowered, and hubs just make it worse.

Plugging into a hub with an AC adapter would help if this is the case also.

	ken

Article: 126409
Subject: Re: did i miss edk 9.2
From: Ken Ryan <newsryan@leesburg-geeks.org>
Date: Wed, 21 Nov 2007 14:40:05 GMT
Links: << >>  << T >>  << A >>
satih82@gmail.com wrote:
> Hi,
> 
> Does someone has the serial number for EDK 9.2i?

Yes.

I'm sure any of Xilinx's distributors (Avnet, NuHorizons, etc)
would be happy to provide one to you as well. :-)


	ken

Article: 126410
Subject: Re: VHDL language is out of date! Why? I will explain.
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: Wed, 21 Nov 2007 15:55:46 +0100
Links: << >>  << T >>  << A >>
On Sat, 17 Nov 2007, Filip Miletic wrote:

|--------------------------------------------|
|"To the rest: please don't feed the trolls."|
|--------------------------------------------|

Refuting can be useful.

I apologize for provoking the original poster of this thread without
being able to remain to participate in future parts of the thread. Some
contributors to these newsgroups who had emailed me before this season
had been aware of circumstances which deprive me of much opportunity 
to contribute to Usenet often. Hopefully I will be more active on Usenet
late in Spring 2008, but I can not be sure now what the circumstances
shall be at that time.

I quote from an article of the ACCU UK Python Users Group entitled
""The sound of one coconut shell clopping"" by Paul Brian in the
August 2002, Volume 14, Number 4 issue of "CVu" ( WWW.ACCU.org ) on
Page 28:
"[..]
   Where are the type declarations? Well, Python discovers type at run-time,
[..]
[..]"

I quote from "Using Python's Dynamic Features to Encapsulate Relational
Database Queries" by Richard Taylor in the December 2002 issue of "CVu"
from Page 27:
"[..]
[..] Python's dynamic type system means that you can be unsure of the type
of the variable [..]
[..]"

One of the main goals of static strong typing such as in VHDL and Ada
is to detect mistakes early, especially when attempting to compile
instead of when running (and hence crashing). Instead, in a dynamic,
object-oriented language such as Lisp, mistakes which are trivial for
a VHDL compiler to find crash a program at runtime. E.g. perform the
following experiment: compile the Common Lisp program for theorem
proving called Prototype Verification System (PVS) (e.g. if I recall
correctly, in 2007 it took a CMU CL compiler approximately 40 minutes).
To satisfy yourself that it is how it should be, run PVS and invoke one of
the functions for pretty printing. Quit PVS and change only one lexical
token in PVS's source code: change something in one of the functions for
pretty printing such that a typing error occurs. Recompile (if I recall
correctly, it took approximately 10 minutes for me). Run your modified
PVS and do some things with it. Note how the error has not been detected
yet. Invoke the function you changed, then it crashes. This is an extremely
good advertisement against dynamic typing. I remember someone boasted
on news:comp.lang.lisp that the advanced debugging features provided
by a Lisp implementation in a fielded application were retained which
made on-site debugging easy. For work of interest to me, being able
to maintain a deployed system is of importance, but that is not a
valid excuse for allowing errors to be present when launching
a system into the field. I quote from "Using Python's Dynamic Features
to Encapsulate Relational Database Queries" by Richard Taylor in the
December 2002 issue of "CVu" from Page 29:
"[..]
This article has demonstrated how features such as dynamic attribute
lookup and class definitions as first class objects can be used to build
flexible abstractions in Python. I have used such techniques extensively in
the applications on which I have worked. However, I have also learned
through bitter experience that such techniques can cause faults that, because
Python has little compile time checking, only become apparent at run time
and can prove very hard to find. These problems can be alleviated with
judicious use of pre- and post-conditions on methods along with careful
use of exception handlers to recover from runtime errors.
   [..] tripped
up by a built-in method that you have overloaded by accident. [..]"

For Python; Eiffel; and Lisp, whitespace is significant which can
cause trouble if a text editor which forces a particular layout (e.g.
Pico; Nano; some of the modes of Emacs; Microsoft Edit.com; Vim if
ai (autoindent) is set; and a text editor for VMS Notes) is used and
a change forced by a text editor goes unnoticed.

Python with the Stratus hardware description language has not
displaced VHDL yet. Nor has Python with MyHDL.

The following have been claimed to be terser than VHDL for a
number of hardware uses: C++; Verilog; Verischemelog (I may
have misspelt that name earlier in this thread); APL; Lava;
Confluence; and HDCaml. How could Python even possibly
compete with APL for terseness?

I do not agree that conciseness is a good thing. If one sees
an asterisk, which of Kleene closure; multiplication;
convolution; footnote; and adjoint is denoted by the * in
this instance? How would one check? Adobe Acrobat's search
function can be extraordinarily slow when searching through
a strict subset of Synopsys's documentation on a quadcore
workstation; grep can also accept an asterisk but many
search engines will ignore an asterisk (and just about
every other character which is not alphanumeric). Can you
remember which of the intervals [1,5) and (1,5] includes the
number five? The command
Copy Source.txt Dest.txt
will behave differently on VMS if a file named Dest.txt
already exists than the lexically identical command on
MS DOS. Please find someone who knows neither MS DOS nor
VMS and tell me if this person will correctly say without
prompting all the possible outcomes of entering
Copy Source.txt Dest.txt. Are you fond of the way numbers
instead of words spelt with letters are used to select
different integration methods in SPICE? Would you risk
adjusting this setting without checking which numbers
correspond to which methods?

Please search for an old post by myself in news:comp.arch.embedded
in which I asked a Lint user how he would prevent accidentally
adding a value of a datatype for counting apples to a value of a
datatype for counting oranges. How should these situations be
handled in a better HDL to replace VHDL?

Article: 126411
Subject: Re: Measuring setup and hold time in Lab
From: MikeShepherd564@btinternet.com
Date: Wed, 21 Nov 2007 15:00:05 +0000
Links: << >>  << T >>  << A >>
>How can we measure setup and hold time of a flip-flop on FPGA in lab ?

Short of sawing the top off the chip, you'll have to do it via the
pins, so you'll need to take into account propagation delays between
those pins and the logic element.  Beyond that, the method is the
same.  I assume you know how to do it for a "raw" flip-flop (like a
7474).  There are integrated circuit devices designed to support such
measurements.

This is another "mystery" enquiry, which raises first the question
"Why would you want to do it anyway?"  Do you want to measure "pin to
pin" behaviour or are you trying to measure the "real" behaviour
(whatever that means) of a logic element (whatever that means, given
that there may be no atomic component of the particular device which
could be described as a "flip-flop" until it's configured as part of
such a component by the design software).

For normal use of the device, you should just comply with the limits
shown in the data sheet.  What you find may not apply to other devices
or under other operating conditions.

Article: 126412
Subject: Re: Measuring setup and hold time in Lab
From: John_H <newsgroup@johnhandwork.com>
Date: Wed, 21 Nov 2007 15:16:57 GMT
Links: << >>  << T >>  << A >>
Ved wrote:
> Hi all,
> How can we measure setup and hold time of a flip-flop on FPGA in lab ?
> 
> Regards,
> Ved

Modern FPGAs don't have a setup *and* hold time for a single register. 
The sample window for the FPGA is sub-picosecond.

Any measurements you try to make will be swamped by the system jitter of 
your measurement setup leaving you with a statistical center and a wide 
area around that center representing your system jitter.

Use the values provided by the manufacturer!

- John_H

Article: 126413
Subject: Re: Measuring setup and hold time in Lab
From: "David Spencer" <davidmspencer@verizon.net>
Date: Wed, 21 Nov 2007 16:27:53 GMT
Links: << >>  << T >>  << A >>

"Ved" <vedpsingh@gmail.com> wrote in message 
news:bb827301-846a-415d-b04d-5a0aecb3ab89@y43g2000hsy.googlegroups.com...
> Hi all,
> How can we measure setup and hold time of a flip-flop on FPGA in lab ?
>
> Regards,
> Ved

As others have suggested, the timing model of an FPGA is too complex for the 
setup and hold requirements of a single flip-flop to have any significance 
(or be measurable). The correct way to design an FPGA is define timing 
constraints and then let the place and route tools achieve these. This way, 
you are making the FPGA fit your requirements rather than making your design 
work around the FPGA. All place and route tools also produce data-sheet type 
reports that give pin-related timings.

If, for some academic reason, you did want to measure the characteristics of 
a single flip-flop as seen at the device pins, who would need a trivial 
design with clock and data inputs and a Q output. You drive the inputs from 
a pulse generator that allows fine tuning of the delay between rising edges 
and look at the output on a scope set to infinite persistence and triggered 
by the clock input. You slide the data input edge with respect to the clock 
until you start seeing the output stay low after the clock. (The clock 
frequency needs to be twice the data frequency so that the flip-flop returns 
low before the edge you are looking at.) 



Article: 126414
Subject: Re: partial dynamic reconfiguration on Virtex-4 SX35
From: austin <austin@xilinx.com>
Date: Wed, 21 Nov 2007 08:45:25 -0800
Links: << >>  << T >>  << A >>
G_Abg,

Yes, all V4 (and V5) parts are supported through the PlanAhead(tm)
software tool for partial reconfiguration.

I suggest you ask your professor to request the PlanAhead software so
that you may do what you need to.

http://www.xilinx.com/ise/optional_prod/planahead.htm

The partial reconfiguration flow still has some "bumps" in it (even with
the latest tools), but it now comes down to a steady improvement as we
find and fix bugs, and add features (as we discover what customers
really need).

http://www.xilinx.com/prs_rls/ip/02165sdr_forum.htm

Austin

Article: 126415
Subject: Re: partial dynamic reconfiguration on Virtex-4 SX35
From: G_Abg <Gael.Abgrall@gmail.com>
Date: Wed, 21 Nov 2007 09:43:03 -0800 (PST)
Links: << >>  << T >>  << A >>
On 21 nov, 14:54, rickman <gnu...@gmail.com> wrote:
> On Nov 21, 3:30 am, G_Abg <Gael.Abgr...@gmail.com> wrote:
>
> > Hi,
>
> > I have just begin my PhD on SDR and I will have to use a FPGA with
> > partial dynamic reconfiguration. The system which interest me have a
> > Xilinx Virtex-4 SX35 integrated on it and I'm not sure this FPGA can
> > do it.
>
> > If someone could answer me, it'll be great.
>
> I haven't looked at the Virtex-4 devices in detail, but Xilinx has
> included partial dynamic reconfiguration in their parts for several
> generations now.   The trick is that they don't support this in
> software... at least very well.  PDC sounds good on paper, but seems
> to be hard to implement and clearly there is not much demand for it.
>
> I'm curious, what is SDR and why are you working on it?

SDR is for Software Defined Radio. I'm sorry but I'm not enough good
in english to explain you what it consists of, I let you find it by
yourself. (Perhaps one day my english will be sufficient to do that
^^)

About why I am working on it, it's very simple, I find this subject
very interesting and mostly because I think it will open me good job
opportunities after my PhD.

If you want more information about this subject, I could find some
articles for you.

Article: 126416
Subject: Re: partial dynamic reconfiguration on Virtex-4 SX35
From: G_Abg <Gael.Abgrall@gmail.com>
Date: Wed, 21 Nov 2007 09:49:08 -0800 (PST)
Links: << >>  << T >>  << A >>
On 21 nov, 17:45, austin <aus...@xilinx.com> wrote:
> G_Abg,
>
> Yes, all V4 (and V5) parts are supported through the PlanAhead(tm)
> software tool for partial reconfiguration.
>
> I suggest you ask your professor to request the PlanAhead software so
> that you may do what you need to.
>
> http://www.xilinx.com/ise/optional_prod/planahead.htm
>
> The partial reconfiguration flow still has some "bumps" in it (even with
> the latest tools), but it now comes down to a steady improvement as we
> find and fix bugs, and add features (as we discover what customers
> really need).
>
> http://www.xilinx.com/prs_rls/ip/02165sdr_forum.htm
>
> Austin

Thank you for your answer and for the links. I will look at it rigth
now.

Article: 126417
Subject: EDK + Modelsim simulation : Memory allocation failure
From: Pasacco <pasacco@gmail.com>
Date: Wed, 21 Nov 2007 10:00:49 -0800 (PST)
Links: << >>  << T >>  << A >>
Dear

When I simulate one EDK project (with multi-processors), Modelsim
reports an error "Memory allocation failure".

I tested the EDK project with 6 microblazes and it was okay.

Now I am trying to simulate the EDK project with 12 Microblaze.

What I did was
1. Implement the system using EDK.

In Modelsim,
2. compile "system.vhd" and "system_init.vhd"
3. compile "testbench"
4. Load "testbench" (configuration with BRAM initialization) with SDF
file.

In step 4, following error occurred:

----------------------------------------------------------------------------
# ** Error: system.vhd(681006): (vopt-4) ****** Memory allocation
failure. *****
# Please check your system for available memory and swap space.
# ** Error: system.vhd(681006): (vopt-4) ****** Memory allocation
failure. *****
# Please check your system for available memory and swap space.

voptk.exe - application error
The exception unknown software exception (0xc00000fd) occurred in the
application at location 0x77c3011e
-----------------------------------------------------------------------------

My windows machine has 4GB RAM. I think 4GB is more than enough.

Does anyone have this experience?

Article: 126418
Subject: Re: VHDL language is out of date! Why? I will explain.
From: "RCIngham" <robert.ingham@gmail.com>
Date: Wed, 21 Nov 2007 12:06:34 -0600
Links: << >>  << T >>  << A >>
>
>Refuting can be useful.
>

<snip />

Well refuted sir!

A great advantage of VHDL's strong (compile-time) type checking is that it
much reduces the need for a linting-type tool. Reading some styles of code,
however, indicates that it does not eliminate it, however!
;-)


Article: 126419
Subject: Re: partial dynamic reconfiguration on Virtex-4 SX35
From: rickman <gnuarm@gmail.com>
Date: Wed, 21 Nov 2007 10:27:18 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 21, 12:43 pm, G_Abg <Gael.Abgr...@gmail.com> wrote:
> On 21 nov, 14:54, rickman <gnu...@gmail.com> wrote:
>
>
>
> > On Nov 21, 3:30 am, G_Abg <Gael.Abgr...@gmail.com> wrote:
>
> > > Hi,
>
> > > I have just begin my PhD on SDR and I will have to use a FPGA with
> > > partial dynamic reconfiguration. The system which interest me have a
> > > Xilinx Virtex-4 SX35 integrated on it and I'm not sure this FPGA can
> > > do it.
>
> > > If someone could answer me, it'll be great.
>
> > I haven't looked at the Virtex-4 devices in detail, but Xilinx has
> > included partial dynamic reconfiguration in their parts for several
> > generations now.   The trick is that they don't support this in
> > software... at least very well.  PDC sounds good on paper, but seems
> > to be hard to implement and clearly there is not much demand for it.
>
> > I'm curious, what is SDR and why are you working on it?
>
> SDR is for Software Defined Radio. I'm sorry but I'm not enough good
> in english to explain you what it consists of, I let you find it by
> yourself. (Perhaps one day my english will be sufficient to do that
> ^^)

It is not an English problem, it is an abbreviation problem.  We use
so many of them that they become context dependent jargon that even
people who work in the field don't always know what you are talking
about.

I am very familiar with SDR, both the generic usage and the version
defined by the US government which is a particular implementation.


> About why I am working on it, it's very simple, I find this subject
> very interesting and mostly because I think it will open me good job
> opportunities after my PhD.
>
> If you want more information about this subject, I could find some
> articles for you.

Thanks, but I have been up to my ears in the topic.  Yes, it should
provide you with good job opportunities over a long span as more and
more SDR related application open up constantly.

Article: 126420
Subject: Re: Measuring setup and hold time in Lab
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Thu, 22 Nov 2007 08:00:38 +1300
Links: << >>  << T >>  << A >>
Ved wrote:
> Hi all,
> How can we measure setup and hold time of a flip-flop on FPGA in lab ?
> 
> Regards,
> Ved

  Because those are design limits, you cannot actually measure them
on a real device.
  What you could derive in the lab, is the point in between these
values, where the actual sampling aperture sits.
  Before that point, the FF captures the value, after that point
and it misses it.

  It could be good educationally, to do this on (say) 8 FF's all
at the same time. ( 8 LEDS, or 16 leds to show two time-stamps ?)

  I have thought that a sliding-contact on a stripline system
with CLK and DATA lines, could demonstrate well, as well as allow
very fine time adjustments.

  Also provide fine adjustment on Vcc, and a can of Freeze,
and ask the students what happens then.

  If you can vary very precisely in the time-domain, you could even
start to demonstrate meta-stable operation, but just showing the
variation in aperture times between those 8 FF's is enough of
a warning to students.

-jg


Article: 126421
Subject: Re: Measuring setup and hold time in Lab
From: "David Spencer" <davidmspencer@verizon.net>
Date: Wed, 21 Nov 2007 20:21:58 GMT
Links: << >>  << T >>  << A >>

"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message 
news:47447ff6$1@clear.net.nz...
>  Because those are design limits, you cannot actually measure them
> on a real device.
>  What you could derive in the lab, is the point in between these
> values, where the actual sampling aperture sits.
>  Before that point, the FF captures the value, after that point
> and it misses it.
>
>  It could be good educationally, to do this on (say) 8 FF's all
> at the same time. ( 8 LEDS, or 16 leds to show two time-stamps ?)
>
>  I have thought that a sliding-contact on a stripline system
> with CLK and DATA lines, could demonstrate well, as well as allow
> very fine time adjustments.
>
>  Also provide fine adjustment on Vcc, and a can of Freeze,
> and ask the students what happens then.
>
>  If you can vary very precisely in the time-domain, you could even
> start to demonstrate meta-stable operation, but just showing the
> variation in aperture times between those 8 FF's is enough of
> a warning to students.
>
> -jg
>
Howard Johnson has a setup that he uses at his high-speed design lectures to 
demonstrate metastability. There are some details at: 
http://www.sigcon.com/Pubs/news/4_4.htm, and more information in his first 
book. 



Article: 126422
Subject: Re: Measuring setup and hold time in Lab
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Thu, 22 Nov 2007 09:38:58 +1300
Links: << >>  << T >>  << A >>
David Spencer wrote:
> 
> Howard Johnson has a setup that he uses at his high-speed design lectures to 
> demonstrate metastability. There are some details at: 
> http://www.sigcon.com/Pubs/news/4_4.htm, and more information in his first 
> book. 

Yes, that is good, tho I see he is missing a R2 from the SCH, that is
referenced in the text. SCH as drawn would not work :)

-jg


Article: 126423
Subject: Re: VHDL language is out of date! Why? I will explain.
From: Paul Taylor <ptaylor_ng@tiscali.co.uk>
Date: 21 Nov 2007 20:53:05 GMT
Links: << >>  << T >>  << A >>
On Wed, 21 Nov 2007 15:55:46 +0100, Colin Paul Gloster wrote:

> One of the main goals of static strong typing such as in VHDL and Ada
> is to detect mistakes early... <snip>

Compiling a small program that you want to change/run is a pain, so
dynamic/scripting languages are great here. But then for larger programs,
scripting languages are a pain for the reasons you state. Others
like/advocate them for writing large programs but I can't understand that.
So I'm with you here.

> Python with the Stratus hardware description language has not
> displaced VHDL yet. Nor has Python with MyHDL. 

Probably nothing will displace vhdl/verilog. Just like nothing has
and probably won't replace C for embedded programming, for example. That's
been around for years as well. 

> I do not agree that conciseness is a good thing ... <snip>

Of course clarity is more important than terseness - e.g some perl, yuk. A
state machine in my other post in this thread I like - it's terse and it's
clear and it's easy to maintain. Lets say I want to change it by adding a
state or two, I don't need to mess around adding constants to an
enumeration type, and changing constants around in a case statement.

Also I don't explicitly connect clocks to registers/modules - that's done
automatically for me, if there is a clk node in the module. I can override
this but mostly that's what I want. 

Conciseness can be very good (if clarity and the ability to scale are not
compromised), the language can be easier to use, and so allowing you to
concentrate more on the problem you're trying to solve.

> Please search for an old post by myself in news:comp.arch.embedded
> in which I asked a Lint user how he would prevent accidentally
> adding a value of a datatype for counting apples to a value of a
> datatype for counting oranges. 

orangesDb.add(anApple) ? 

Ok, I know that's a contrived example, and nobody would write a line of
code like that. But Java didn't have generics until version 5. Before
version 5 I don't recall having an issue with the sort of problem you are
describing. I now use generics, but not because I'm particularly concerned
about storing the wrong type (I use sensible variable names :-)), it's
just that it's easier to use generics than not because otherwise you end
up doing a lot of casting. 

I'm not against putting safeguards in a language. You have to ask what it
is you are protecting yourself against, and consider what the cost is (too
much red tape is bad). When writing vhdl I find the most common error I
make is that when assigning to a bit vector, I sometimes get the length
wrong, especially when slices and concatenations are involved.  VHDL finds
that problem of coarse, which is great. The language that I am developing
has that safeguard too. I also have a marked keyword, which is a safeguard
because sometimes I stupidly use the wrong variable, e.g. an
unsynchronised signal instead of one that I have synchronised for use
(especially when I come back to change some code). I also have asserts on
compile-time config, so when I instantiate a module I find config
parameter errors too. A contrived example:

module ACounter(DIR = UP; SIZE = 16) {
  assert DIR {UP, DOWN, UPDOWN};
  assert SIZE > 0;

  inport clk, rst;
  outport count[%SIZE];

  reg cnt[%SIZE];
  count = cnt;		

  config DIR == UP {
    inport inc;
    cnt = {0 when rst; next when inc;}
  }
  config DIR == DOWN {
    inport dec;
    cnt = {0 when rst; prev when dec;}
  }
  config DIR == UPDOWN {
    inport inc, dec;
    cnt = {0 when rst; next when inc; prev when dec;}
  }	
}

I would be interested to know what mistakes others commonly make, that are
found by the VHDL compiler.

Regards,

Paul Taylor.

Article: 126424
Subject: Re: EDK + Modelsim simulation : Memory allocation failure
From: John McCaskill <jhmccaskill@gmail.com>
Date: Wed, 21 Nov 2007 14:20:37 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 21, 12:00 pm, Pasacco <pasa...@gmail.com> wrote:
> Dear
>
> When I simulate one EDK project (with multi-processors), Modelsim
> reports an error "Memory allocation failure".
>
> I tested the EDK project with 6 microblazes and it was okay.
>
> Now I am trying to simulate the EDK project with 12 Microblaze.
>
> What I did was
> 1. Implement the system using EDK.
>
> In Modelsim,
> 2. compile "system.vhd" and "system_init.vhd"
> 3. compile "testbench"
> 4. Load "testbench" (configuration with BRAM initialization) with SDF
> file.
>
> In step 4, following error occurred:
>
> ----------------------------------------------------------------------------
> # ** Error: system.vhd(681006): (vopt-4) ****** Memory allocation
> failure. *****
> # Please check your system for available memory and swap space.
> # ** Error: system.vhd(681006): (vopt-4) ****** Memory allocation
> failure. *****
> # Please check your system for available memory and swap space.
>
> voptk.exe - application error
> The exception unknown software exception (0xc00000fd) occurred in the
> application at location 0x77c3011e
> -----------------------------------------------------------------------------
>
> My windows machine has 4GB RAM. I think 4GB is more than enough.
>
> Does anyone have this experience?



Are you using a 32 or 64 bit version of Windows? If you are using a 32
bit version, you are not going to get to use all 4GB. By default, 32
bit Windows will only give a program up to 2GB. There is a setting
that you can put in the boot.ini file that will let a program use up
to 3 GB in Windows XP Pro. Search the Xilinx answers database for
"Windows 3 GB" and you will get instructions on how to set it.

Regards,

John McCaskill



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