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Messages from 125975

Article: 125975
Subject: Xilinx USB cable in Fedora 7
From: Duane Clark <junkmail@junkmail.com>
Date: Sat, 10 Nov 2007 13:24:05 -0800
Links: << >>  << T >>  << A >>
I was wondering about peoples success/failure getting the USB cable 
working in Fedora 7? I am running 64 bit F7 but am running 32 bit ISE. I 
am trying to use Michael's driver.
http://www.rmdir.de/~michael/xilinx/
The USB cable is the DLC9G.

The driver seemed to compile fine with the lib32 flag. I did need to 
install fxload. After that, I get a green light on the cable (without 
fxload there was no light), and lsusb shows that the device ID changed to:
Bus 007 Device 020: ID 03fd:0008 Xilinx, Inc.

Running impact shows:

Connecting to cable (Usb Port - USB21).
Checking cable driver.
File version of /opt/Xilinx9.2/bin/lin/xusbdfwu.hex = 1030.
File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1021.
  libusb-driver.so version: 2007-10-08 06:43:55.
Please run `source ./setup_pcusb` from the /opt/Xilinx9.2/bin/lin 
directory with root privilege to update the firmware. Disconnect and 
then reconnect the cable from the USB port to complete the driver update.
Cable connection failed.

So it does seem to find the driver, and the xusbdfwu.hex file (and I did 
run setup_pcusb from Xilinx9.2).

So just curious if others got this working in F7, and were there any 
special steps needed?

Article: 125976
Subject: Re: Why dynamic partial reconfiguration is still not there?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sat, 10 Nov 2007 15:24:26 -0800
Links: << >>  << T >>  << A >>
Adam Megacz wrote:
> Mike Treseler <mike_treseler@comcast.net> writes:
>>> My opinion is that the proprietary closed nature of FPGA hardware
>>> and software tools is the big obstacle in this way.

Hmm. I don't remember saying that.

>> If I had a great idea in this area, I would demonstrate it in
>> simulation and then ring up a venture capitalist.
> 
> If every beneficial technology were commercially exploitable by a
> small startup company I think the computing world would be quite a
> different place.

Not every idea is a great one,
and it is not up to the FPGA makers
to make hardware the way I happen to
prefer it.

   -- Mike Treseler

Article: 125977
Subject: Re: newbie to 16v8
From: Peter Alfke <alfke@sbcglobal.net>
Date: Sat, 10 Nov 2007 16:43:12 -0800
Links: << >>  << T >>  << A >>
On Nov 10, 11:00 am, Amit <amit.ko...@gmail.com> wrote:
> On Nov 10, 10:49 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
> wrote:
>
>
>
> > On Sat, 10 Nov 2007 18:25:35 -0000, Amit <amit.ko...@gmail.com> wrote:
>
> > >Hello group,
>
> > >I'm new to this field and currently learning how 16v8 architecture is
> > >designed. Of course, pretty confused but as my first experiement I
> > >need to implement a logical function and also design multiplier using
> > >61v8.
>
> > >does anybody know where I can get some information to be able to
> > >complete this?
>
> > A GAL16V8, which I guess is what you mean, has only...
> > - 8 bits of storage
> > - 18 user I/O pins, of which one must be taken as a clock
> >   in most cases
> > so your multiplier surely cannot be very big! You could make
> > a multiplier with two 4-bit inputs and an 8-bit result...
> > probably.  If you have *lots* of 16V8s on a board, you
> > could make a bigger multiplier.
>
> > When I did a Google search for GAL16V8, the first hit I found
> > was the Lattice data sheet.  (I used to know those devices
> > inside-out, but I haven't used one for so long that I thought
> > I'd better remind myself of the details.)  Not a bad place to start.
> > --
> > Jonathan Bromley, Consultant
>
> > DOULOS - Developing Design Know-how
> > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
Amit,
you will not fnd a multiplier, nor even an adder. The chip has lots of
wide AND gates that can be ORed together, and that's the (very low)
level of abstraction you should use to design. Back to basics (or is
it forward to basics for you ?).
Good exercise in logic design, and in logical thinking.
Greetings to your teacher or prof.
Peter Alfke

> > The contents of this message may contain personal views which
> > are not the views of Doulos Ltd., unless specifically stated.
>
> Hello Jonathan,
>
> Thanks for your response. you are right,  I did download it but one
> thing that I need to know how can I find a right flow? and associate
> it with a multiplier 4 by 4?
> it seems there are other controlling inputs such as Vcc (or maybe I'm
> wrong) but is there any example of an adder for instance?
>
> Once again thanks.
> amit



Article: 125978
Subject: Re: ROM (altsyncram) corruption
From: Allan Herriman <allanherriman@hotmail.com>
Date: Sun, 11 Nov 2007 12:26:51 +1100
Links: << >>  << T >>  << A >>
On Fri, 09 Nov 2007 22:43:51 -0800, Peter Alfke <alfke@sbcglobal.net>
wrote:

>On Nov 9, 10:34 pm, Peter Alfke <al...@sbcglobal.net> wrote:
>> On Nov 9, 10:05 pm, Eric Smith <e...@brouhaha.com> wrote:
>>
>> > Peter Alfke wrote:
>> > > If the RAM is selected, even if WE is inactive, a violation of the
>> > > address set-up time CAN occasionally corrupt the RAM=ROM content.
>>
>> > Thanks for psting about the problem and the cause.  Is this true of
>> > all Xilinx parts with BRAM?  Is there any plan to "fix" it in future
>> > FPGAs?
>>
>> > Can I assume that the ISE post-P&R static timing analysis will generate
>> > an error if the BRAM address setup time will not be met?  I"m not sure
>> > of the limitations of the static timing analysis, but I've never seen
>> > any such error reported, so maybe my designs are OK.
>>
>> > Eric
>>
>The problem may have been around for many years and several device
>generations. It obviously was a "sleeper", since nobody detected it,
>or was bothered by it, in hundreds of millions of working systems.

I detected it and was bothered by it.  I eventually found what seemed
to be an effective workaround, and moved on.
This never got back to Xilinx however, since the local FAEs assumed it
was a problem in my design and not in the silicon.

The workaround I discovered was to use a BUFGMUX to disable the clock
to the fabric until a certain time after configuration.  The DCMs
would produce clock glitches during initial lock, and this was killing
the ROMs.
I also had an ROM integrity check that would cause the entire FPGA to
be reconfigured for another attempt if an error was found.

Years later I found out what the problem really was.  Now I would just
use the enable line instead of the bufgmux.


Regards,
Allan

Article: 125979
Subject: Re: ROM (altsyncram) corruption
From: Peter Alfke <alfke@sbcglobal.net>
Date: Sat, 10 Nov 2007 17:59:40 -0800
Links: << >>  << T >>  << A >>
On Nov 10, 5:26 pm, Allan Herriman <allanherri...@hotmail.com> wrote:
> On Fri, 09 Nov 2007 22:43:51 -0800, Peter Alfke <al...@sbcglobal.net>
> wrote:
>
>
>
> >On Nov 9, 10:34 pm, Peter Alfke <al...@sbcglobal.net> wrote:
> >> On Nov 9, 10:05 pm, Eric Smith <e...@brouhaha.com> wrote:
>
> >> > Peter Alfke wrote:
> >> > > If the RAM is selected, even if WE is inactive, a violation of the
> >> > > address set-up time CAN occasionally corrupt the RAM=ROM content.
>
> >> > Thanks for psting about the problem and the cause.  Is this true of
> >> > all Xilinx parts with BRAM?  Is there any plan to "fix" it in future
> >> > FPGAs?
>
> >> > Can I assume that the ISE post-P&R static timing analysis will generate
> >> > an error if the BRAM address setup time will not be met?  I"m not sure
> >> > of the limitations of the static timing analysis, but I've never seen
> >> > any such error reported, so maybe my designs are OK.
>
> >> > Eric
>
> >The problem may have been around for many years and several device
> >generations. It obviously was a "sleeper", since nobody detected it,
> >or was bothered by it, in hundreds of millions of working systems.
>
> I detected it and was bothered by it.  I eventually found what seemed
> to be an effective workaround, and moved on.
> This never got back to Xilinx however, since the local FAEs assumed it
> was a problem in my design and not in the silicon.
>
> The workaround I discovered was to use a BUFGMUX to disable the clock
> to the fabric until a certain time after configuration.  The DCMs
> would produce clock glitches during initial lock, and this was killing
> the ROMs.
> I also had an ROM integrity check that would cause the entire FPGA to
> be reconfigured for another attempt if an error was found.
>
> Years later I found out what the problem really was.  Now I would just
> use the enable line instead of the bufgmux.
>
> Regards,
> Allan

Allan, the clock glitches alone should not corrupt the ROM content. It
also takes address changes coincident with the clock glitches, and
moreover the BRAM must be clock-enabled to cause this bad action. So
there are several ways around it, and disabling the RAM seems to be
the most practical one.
I put a warning into the Virtex-5 data book, but I assume it applies
to many RAM generations and apparently also of more than one
manufacturer, as evidenced by the original posting.
This has to be fixed with a warning, for a cure would be worse than
the disease...
Peter Alfke


Article: 125980
Subject: Re: ROM (altsyncram) corruption
From: Allan Herriman <allanherriman@hotmail.com>
Date: Sun, 11 Nov 2007 13:26:02 +1100
Links: << >>  << T >>  << A >>
On Sat, 10 Nov 2007 17:59:40 -0800, Peter Alfke <alfke@sbcglobal.net>
wrote:

>On Nov 10, 5:26 pm, Allan Herriman <allanherri...@hotmail.com> wrote:
>> On Fri, 09 Nov 2007 22:43:51 -0800, Peter Alfke <al...@sbcglobal.net>
>> wrote:
>>
>>
>>
>> >On Nov 9, 10:34 pm, Peter Alfke <al...@sbcglobal.net> wrote:
>> >> On Nov 9, 10:05 pm, Eric Smith <e...@brouhaha.com> wrote:
>>
>> >> > Peter Alfke wrote:
>> >> > > If the RAM is selected, even if WE is inactive, a violation of the
>> >> > > address set-up time CAN occasionally corrupt the RAM=ROM content.
>>
>> >> > Thanks for psting about the problem and the cause.  Is this true of
>> >> > all Xilinx parts with BRAM?  Is there any plan to "fix" it in future
>> >> > FPGAs?
>>
>> >> > Can I assume that the ISE post-P&R static timing analysis will generate
>> >> > an error if the BRAM address setup time will not be met?  I"m not sure
>> >> > of the limitations of the static timing analysis, but I've never seen
>> >> > any such error reported, so maybe my designs are OK.
>>
>> >> > Eric
>>
>> >The problem may have been around for many years and several device
>> >generations. It obviously was a "sleeper", since nobody detected it,
>> >or was bothered by it, in hundreds of millions of working systems.
>>
>> I detected it and was bothered by it.  I eventually found what seemed
>> to be an effective workaround, and moved on.
>> This never got back to Xilinx however, since the local FAEs assumed it
>> was a problem in my design and not in the silicon.
>>
>> The workaround I discovered was to use a BUFGMUX to disable the clock
>> to the fabric until a certain time after configuration.  The DCMs
>> would produce clock glitches during initial lock, and this was killing
>> the ROMs.
>> I also had an ROM integrity check that would cause the entire FPGA to
>> be reconfigured for another attempt if an error was found.
>>
>> Years later I found out what the problem really was.  Now I would just
>> use the enable line instead of the bufgmux.
>>
>> Regards,
>> Allan
>
>Allan, the clock glitches alone should not corrupt the ROM content. It
>also takes address changes coincident with the clock glitches, and
>moreover the BRAM must be clock-enabled to cause this bad action.

I had the enable permanently on, and the addresses were coming from a
FSM triggered by the same clock.  Clock glitches due to DCM locking
can change the ROM contents in that case.

> So
>there are several ways around it, and disabling the RAM seems to be
>the most practical one.
>I put a warning into the Virtex-5 data book, but I assume it applies
>to many RAM generations and apparently also of more than one
>manufacturer, as evidenced by the original posting.
>This has to be fixed with a warning, for a cure would be worse than
>the disease...

I agree.  It's simple enough to deal with once the root cause of the
problem is understood.

My part was a V2P, btw.

Regards,
Allan

Article: 125981
Subject: Re: newbie to 16v8
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Sun, 11 Nov 2007 18:48:54 +1300
Links: << >>  << T >>  << A >>
Amit wrote:
> Hello group,
> 
> I'm new to this field and currently learning how 16v8 architecture is
> designed. Of course, pretty confused but as my first experiement I
> need to implement a logical function 

That should be easy.
Which logical function has your tutor asked for ?
What examples has he given ?

> and also design multiplier using 16v8.

How many bits wide ? - did the tutor say ?
One obvious ceiling is you only have 8 outputs, but there are other
lower ones.
One simple Multipler expression is a ROM, and a 2b x 2b multipler,
can fit in a 16x4 ROM - and that will likely fit into a 16V8.
The 22V10 will fit a larger multiplier.

-jg


Article: 125982
Subject: Re: Xilinx Parallel Cable IV, API spec
From: Eric Smith <eric@brouhaha.com>
Date: Sat, 10 Nov 2007 23:08:56 -0800
Links: << >>  << T >>  << A >>
cs_posting@hotmail.com writes:
> But why would you want to use an expensive proprietary cable?

Because I actually *want* to be able to use the Xilinx tools,
especially Chipscope Pro.

Article: 125983
Subject: Re: Xilinx USB cable in Fedora 7
From: svenand <svenand@comhem.se>
Date: Sun, 11 Nov 2007 00:05:38 -0800
Links: << >>  << T >>  << A >>
On Nov 10, 10:24 pm, Duane Clark <junkm...@junkmail.com> wrote:
> I was wondering about peoples success/failure getting the USB cable
> working in Fedora 7? I am running 64 bit F7 but am running 32 bit ISE. I
> am trying to use Michael's driver.http://www.rmdir.de/~michael/xilinx/
> The USB cable is the DLC9G.
>
> The driver seemed to compile fine with the lib32 flag. I did need to
> install fxload. After that, I get a green light on the cable (without
> fxload there was no light), and lsusb shows that the device ID changed to:
> Bus 007 Device 020: ID 03fd:0008 Xilinx, Inc.
>
> Running impact shows:
>
> Connecting to cable (Usb Port - USB21).
> Checking cable driver.
> File version of /opt/Xilinx9.2/bin/lin/xusbdfwu.hex = 1030.
> File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1021.
>   libusb-driver.so version: 2007-10-08 06:43:55.
> Please run `source ./setup_pcusb` from the /opt/Xilinx9.2/bin/lin
> directory with root privilege to update the firmware. Disconnect and
> then reconnect the cable from the USB port to complete the driver update.
> Cable connection failed.
>
> So it does seem to find the driver, and the xusbdfwu.hex file (and I did
> run setup_pcusb from Xilinx9.2).
>
> So just curious if others got this working in F7, and were there any
> special steps needed?

Here is a description on how I got it working in Ubuntu 7.04:
http://svenand.blogdrive.com/archive/55.html
Maybe it can be of some help.

Sven


Article: 125984
Subject: Re: Non-volatile FPGA in a small package
From: Thomas Stanka <usenet_nospam_valid@stanka-web.de>
Date: Sun, 11 Nov 2007 05:04:56 -0800
Links: << >>  << T >>  << A >>
Hi,

On 10 Nov., 03:39, cs_post...@hotmail.com wrote:
> It also seems that you can't get pullups on inputs, and instead of
> merely being cautioned against using non-clock inputs as clocks, you
> literally can't do it - meaning board designs with stupid mistakes
> that might be programmed away with other devices are more likely to
> require modifications with these.

You can't use clk input buffer on non clock input pads, but you can
use any input as feed for the internal clock buffer (GLint) to drive
the clocks from any input you like. The perfomance may be much better,
when using the clock pads, but you are not limited.

> On the other hand, if you prefer to do everything in simulation and
> not make incremental trials in hardware, and you value synopsis over X
> or A's tools enough to habitually use it anyway, then maybe these
> parts are just your thing.

You can use Synopsys for synthesis of any fpga, but I guess, you get
not very good results when using it for ram or flash based Fpgas. Even
for Actel fuse based fpgas you need to check, wheter you get better
results with Synopsy or Synplify. I used both synthesis tools for
serveral flash based designs and learned, that  I gained sometimes 10%
with the one and sometimes with the other tool (depending on the
design).

bye Thomas


Article: 125985
Subject: Re: Non-volatile FPGA in a small package
From: cs_posting@hotmail.com
Date: Sun, 11 Nov 2007 08:05:53 -0800
Links: << >>  << T >>  << A >>
On Nov 11, 8:04 am, Thomas Stanka <usenet_nospam_va...@stanka-web.de>
wrote:

> You can't use clk input buffer on non clock input pads, but you can
> use any input as feed for the internal clock buffer (GLint) to drive
> the clocks from any input you like. The perfomance may be much better,
> when using the clock pads, but you are not limited.

Maybe if you tell it exactly what primitives you want you can do it.

But the obvious case of simply writing HDL code that uses a non-clock
input as a clock, fails.  Wheras it works on X or A - albeit with
warnings.


Article: 125986
Subject: Re: Problem using xilinx usb download cable in linux
From: roger <roger.jons@gmail.com>
Date: Sun, 11 Nov 2007 16:23:17 -0000
Links: << >>  << T >>  << A >>
On Nov 10, 1:07 pm, Michael Gernoth <m...@gernoth.net> wrote:
> Hi,
>
> On Sat, 03 Nov 2007 22:04:14 -0000, roger wrote:
> > I have installed the usb-driver fromhttp://www.rmdir.de/~michael/xilinx
> > and I have managed to light up the green led to the usb download cable
> > on the spartan 3e starter kit. The green led is going black every 6-8
> > second and then green again.
>
> I have not heard of this behaviour previously. For me this seems to
> indicate that the cable gets dis- and reconnected all the time.
> Do you see reoccuring dis-/reconnects in "dmesg".
>
> > I don't manage to get a connection to the board using Impact. lsusb
> > gives me the following:
>
> > Bus 005 Device 012: ID 03fd:0008 Xilinx, Inc.
> > [...]
> > can't get device qualifier: Operation not permitted
>
> What are the permissions on /dev/bus/usb/005/012 (or the current
> location of the cable)? This error might show there is a permission
> problem. You did add the MODE-line to an udev rules-file?
>
> > and Impact says:
>
> > Connecting to cable (Usb Port - USB21).
> > Checking cable driver.
> > File version of /usr/share/xusbdfwu.hex = 1025(dec), 0401.
> >  libusb-driver.so version: 2007-10-08 15:43:55.
> > Cable connection failed.
>
> If you preload libusb-driver-DEBUG.so instead of libusb-driver.so you
> get a much more detailed output, which could tell why impact does not
> find the device (which according to your lsusb-output has the correct
> firmware loaded).
>
> Regards,
>   Michael

Thanks for the tips! I'll try that out soon.

/Roger


Article: 125987
Subject: Re: newbie to 16v8
From: "David Spencer" <davidmspencer@verizon.net>
Date: Sun, 11 Nov 2007 16:56:32 GMT
Links: << >>  << T >>  << A >>

"Amit" <amit.kohan@gmail.com> wrote in message 
news:1194719135.535112.238400@e9g2000prf.googlegroups.com...
>
> Hello group,
>
> I'm new to this field and currently learning how 16v8 architecture is
> designed. Of course, pretty confused but as my first experiement I
> need to implement a logical function and also design multiplier using
> 61v8.
>
>
> does anybody know where I can get some information to be able to
> complete this?
>
> Regards,
> amit
>

Your best starting point would be to ask your tutor why he thinks you need 
to work with a technology that nobody has used for at least ten years. You 
might be able to catch him after his lecture on valves (vacuum tubes) and 
germanium transistors. 



Article: 125988
Subject: Re: newbie to 16v8
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Mon, 12 Nov 2007 07:48:43 +1300
Links: << >>  << T >>  << A >>
David Spencer wrote:
> "Amit" <amit.kohan@gmail.com> wrote in message 
> news:1194719135.535112.238400@e9g2000prf.googlegroups.com...
> 
>>Hello group,
>>
>>I'm new to this field and currently learning how 16v8 architecture is
>>designed. Of course, pretty confused but as my first experiement I
>>need to implement a logical function and also design multiplier using
>>61v8.
>>
>>
>>does anybody know where I can get some information to be able to
>>complete this?
>>
>>Regards,
>>amit
>>
> 
> 
> Your best starting point would be to ask your tutor why he thinks you need 
> to work with a technology that nobody has used for at least ten years. You 
> might be able to catch him after his lecture on valves (vacuum tubes) and 
> germanium transistors. 

Quite a few introductory courses are taught using a SPLD/CPLD
- after all, AND/OR/XOR Logic and D-FF have not changed :)

The student learns using Boolean equation entry, which teaches them
how the logic actually maps, and is also a common language in report files.

The devices come in DIP packages, and can also be easily vector
tested on device programmers, which brings the silicon inside
the design loop.

The 16V8 may not be seen much in new designs, but it is still active
in production [ We still buy ATF16V8BQL for production :) ]
and the modern 32 macrocell CPLD's are a pretty easy step from
the 16V8. Some courses could include both -depends on the hours allocated.

-jg







Article: 125989
Subject: Re: Xilinx Parallel Cable IV, API spec
From: cs_posting@hotmail.com
Date: Sun, 11 Nov 2007 14:42:56 -0800
Links: << >>  << T >>  << A >>
On Nov 11, 2:08 am, Eric Smith <e...@brouhaha.com> wrote:
> cs_post...@hotmail.com writes:
> > But why would you want to use an expensive proprietary cable?
>
> Because I actually *want* to be able to use the Xilinx tools,
> especially Chipscope Pro.

If you are intending to use the xilinx tools, then why can't you use
the xilinx tools to program the parts?  ie, why do you need to talk to
the cable yourself??


Article: 125990
Subject: Re: newbie to 16v8
From: nico@puntnl.niks (Nico Coesel)
Date: Sun, 11 Nov 2007 23:31:06 GMT
Links: << >>  << T >>  << A >>
"David Spencer" <davidmspencer@verizon.net> wrote:

>
>"Amit" <amit.kohan@gmail.com> wrote in message 
>news:1194719135.535112.238400@e9g2000prf.googlegroups.com...
>>
>> Hello group,
>>
>> I'm new to this field and currently learning how 16v8 architecture is
>> designed. Of course, pretty confused but as my first experiement I
>> need to implement a logical function and also design multiplier using
>> 61v8.
>>
>>
>> does anybody know where I can get some information to be able to
>> complete this?
>>
>> Regards,
>> amit
>>
>
>Your best starting point would be to ask your tutor why he thinks you need 
>to work with a technology that nobody has used for at least ten years. You 
>might be able to catch him after his lecture on valves (vacuum tubes) and 
>germanium transistors. 

Are you sure modern fpga's work differently? The latest processors
still use the same base technology invented decades ago. I've learned
how processors / small computers work from books describing the 8080
while the 486 was readily available. The theory behind it however
still holds true for today (and probably many tomorows). In fact, old
technology is usually much simpler and easier to understand and the
documentation contains a lot more background information which is held
for granted nowadays. For instance try to find a datasheet from an
EPROM which lists the wavelength it needs to get erased... I had to
dig up a datasheet from 1982.

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Article: 125991
Subject: Re: newbie to 16v8
From: Peter Alfke <alfke@sbcglobal.net>
Date: Sun, 11 Nov 2007 16:12:30 -0800
Links: << >>  << T >>  << A >>
On Nov 11, 3:31 pm, n...@puntnl.niks (Nico Coesel) wrote:
> "David Spencer" <davidmspen...@verizon.net> wrote:
>
> >"Amit" <amit.ko...@gmail.com> wrote in message
> >news:1194719135.535112.238400@e9g2000prf.googlegroups.com...
>
> >> Hello group,
>
> >> I'm new to this field and currently learning how 16v8 architecture is
> >> designed. Of course, pretty confused but as my first experiement I
> >> need to implement a logical function and also design multiplier using
> >> 61v8.
>
> >> does anybody know where I can get some information to be able to
> >> complete this?
>
> >> Regards,
> >> amit
>
> >Your best starting point would be to ask your tutor why he thinks you need
> >to work with a technology that nobody has used for at least ten years. You
> >might be able to catch him after his lecture on valves (vacuum tubes) and
> >germanium transistors.
>
> Are you sure modern fpga's work differently? The latest processors
> still use the same base technology invented decades ago. I've learned
> how processors / small computers work from books describing the 8080
> while the 486 was readily available. The theory behind it however
> still holds true for today (and probably many tomorows). In fact, old
> technology is usually much simpler and easier to understand and the
> documentation contains a lot more background information which is held
> for granted nowadays. For instance try to find a datasheet from an
> EPROM which lists the wavelength it needs to get erased... I had to
> dig up a datasheet from 1982.
>
> --
> Reply to nico@nctdevpuntnl (punt=.)
> Bedrijven en winkels vindt U opwww.adresboekje.nl
That goes for many things. On an old car you could adjust the breaker
points and the carburator, on an old radio you could change the tubes,
and on even a new bike you can still change the chain and the bowden
wires,
Good as a tutorial, but how much time do you want to spend there?
Who needs to know the EPROM erasure wavelength of light when everybody
is using Flash, and no light?
On th other hand...
I get annoyed when designers blindly think that chips can add,
multiply, and perform a Fourier Transform, without any understanding
or appreciation of the underlying physics.
We need some balance...
Peter Alfke


Article: 125992
Subject: Re: newbie to 16v8
From: "David Spencer" <davidmspencer@verizon.net>
Date: Mon, 12 Nov 2007 00:44:29 GMT
Links: << >>  << T >>  << A >>

"Peter Alfke" <alfke@sbcglobal.net> wrote in message 
news:1194826350.291056.94690@e9g2000prf.googlegroups.com...
> Good as a tutorial, but how much time do you want to spend there?
> Peter Alfke
>

That was the point I was trying to make. Whilst understanding the concept of 
implementing arbitrary logic functions using a sum of products architecture, 
I can see little point in making someone develop a design to go in an 
obsolescent part. Although most modern CPLDs still use sum-of-products 
architecture, it is very unlikely that you would ever need to code a design 
directly into such an architecture in this day and age. It would be akin to 
getting someone to program a processor directly in machine code, ignoring 
the perfectly good (and probably free) assembler that is available. 



Article: 125993
Subject: Re: newbie to 16v8
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Mon, 12 Nov 2007 14:35:28 +1300
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> That goes for many things. On an old car you could adjust the breaker
> points and the carburator, on an old radio you could change the tubes,
> and on even a new bike you can still change the chain and the bowden
> wires,
> Good as a tutorial, but how much time do you want to spend there?
> Who needs to know the EPROM erasure wavelength of light when everybody
> is using Flash, and no light?
> On th other hand...
> I get annoyed when designers blindly think that chips can add,
> multiply, and perform a Fourier Transform, without any understanding
> or appreciation of the underlying physics.
> We need some balance...

Yes, knowing what you can't do, is important.
I suspect the tutor threw in the Multiplier question for exactly that
reason : To impress on the students what cannot fit into a device :)
You can fit a Multiplier into a 16V8, the question is up to what size!

-jg


Article: 125994
Subject: Re: newbie to 16v8
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Mon, 12 Nov 2007 14:41:12 +1300
Links: << >>  << T >>  << A >>
David Spencer wrote:

> "Peter Alfke" <alfke@sbcglobal.net> wrote in message 
> news:1194826350.291056.94690@e9g2000prf.googlegroups.com...
> 
>>Good as a tutorial, but how much time do you want to spend there?
>>Peter Alfke
>>
> 
> 
> That was the point I was trying to make. Whilst understanding the concept of 
> implementing arbitrary logic functions using a sum of products architecture, 
> I can see little point in making someone develop a design to go in an 
> obsolescent part. Although most modern CPLDs still use sum-of-products 
> architecture, it is very unlikely that you would ever need to code a design 
> directly into such an architecture in this day and age. It would be akin to 
> getting someone to program a processor directly in machine code, ignoring 
> the perfectly good (and probably free) assembler that is available. 
> 

You've lost me a little here ?

You write for SPLD in HDL - Boolean Equation Entry languages like
CUPL, ABEL, or others.

You can also write in Table form, or State engine form, all of
which port quite easily to higher end HDLs

It is all Text Editor / named variables / and comments in source code
stuff.

You never work at the JED fuse-file level ?

-jg




Article: 125995
Subject: Programming connection
From: m <martin.usenet@gmail.com>
Date: Sun, 11 Nov 2007 21:18:22 -0800
Links: << >>  << T >>  << A >>
Looking for ideas to eliminate the programming connector and replace
it with pads/contacts on the board.  This is both for cost and size
reduction as well as simplifying programming during manufacturing and
testing.

One idea is to build a programming jig for each candidate board
containing a connector like this:

http://www.samtec.com/technical_specifications/overview.aspx?series=OPP&menu=STANDARD_PRODUCTS


Any ideas?

Thanks,

-Martin


Article: 125996
Subject: Re: Programming connection
From: m <martin.usenet@gmail.com>
Date: Sun, 11 Nov 2007 21:22:57 -0800
Links: << >>  << T >>  << A >>
Here's another option:

http://www.yokowo.com/springpinconnectors/applications.html

-Martin



Article: 125997
Subject: Re: Xilinx Parallel Cable IV, API spec
From: Antti <Antti.Lukats@googlemail.com>
Date: Mon, 12 Nov 2007 08:30:37 -0000
Links: << >>  << T >>  << A >>
On 11 Nov., 23:42, cs_post...@hotmail.com wrote:
> On Nov 11, 2:08 am, Eric Smith <e...@brouhaha.com> wrote:
>
> > cs_post...@hotmail.com writes:
> > > But why would you want to use an expensive proprietary cable?
>
> > Because I actually *want* to be able to use the Xilinx tools,
> > especially Chipscope Pro.
>
> If you are intending to use the xilinx tools, then why can't you use
> the xilinx tools to program the parts?  ie, why do you need to talk to
> the cable yourself??

REASON 1:

tools provided by xilinx for Cable IV fail on most PC to work in high
speed Cable IV mode and fall back to Cable III compatible mode

REASON 2:

xilinx tools are not sufficient for many tasks :(
like if you want to program SPI flash on S3E over platform USB cable..
you can not, so need to RE the platform cable todo it, just one
example

Antti












Article: 125998
Subject: Re: Programming connection
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: 12 Nov 2007 10:01:03 +0100
Links: << >>  << T >>  << A >>
m <martin.usenet@gmail.com> writes:

> Looking for ideas to eliminate the programming connector and replace
> it with pads/contacts on the board.  This is both for cost and size
> reduction as well as simplifying programming during manufacturing and
> testing.

I've been looking into this too. I want to add a 1x PCI-Express edge
connector on my board for programming. Programming and JTAG testing
will be done by inserting the board into a PCI-Express 1x slot on my
test bench. Anybody else doing this? 

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 125999
Subject: [EDK tool] simulation setup
From: Pasacco <pasacco@gmail.com>
Date: Mon, 12 Nov 2007 04:16:32 -0800
Links: << >>  << T >>  << A >>
Dear

I need to simulate  my EDK (8.2) project.

Simulator is Modelsim SE 6.1c.

I did following steps:

-------------------------------------------
In order to compile COMPXLIB,

I used the EDK simulation library compilation wizard

Project -> Project options -> HDL and Simulation -> Simulation library
path

EDK library = C:/EDK/EDK_LIB
Xilinx library = C:/Xilinx/Xilinx_LIB
-------------------------------------------

However, I could not proceed, because of the message "Modelsim is not
found. Please ensure that the simulator is correctly installed and/or
necessary environment settings are available".

Could anyone tell me "how to set up the environment" (or, how to
points to the location of the simulator)? in EDK 8.2 ?

Thank you in advance




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