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On 12 Dez., 16:34, Paul <P...@yahoo.co.uk> wrote: > I have a simple question. I have a design where the RTL simulation is > working. Now I would like to see if the design also works then on the > FPGA. The obvious way would be to use the JTAG interface and see what is > going on in the CHIP. Anyway, is there somehow another way this could be > achieved? For example is there somehow a way that a file could be > written to which I can get them someway access? Or is the JTAG the only > option I have? I think you ask for a Hardwaretester (or do you really think, a file could be created inside the fpga). Google for them and ask yourself, if you could life with lowcost or need a more expensive unit above the 100k. Most other solutions use jtag, some are direct from fpga vendors like chipscope pro from Xilinx or silicon explorer from Actel other sollutions like tementor claim to be vendor independend. bye ThomasArticle: 127151
On Dec 12, 12:24 pm, kislo <kisl...@student.sdu.dk> wrote: > I have a question regarding the T9 pin of the FT256 footprint of the > spartan 3e .. GCLK0 shares pin with the RDWR_B pin which is a > configuration pin whitch according to the datasheet (p.97) has to be > low during configuration .. how is it possible to use GLCK0 as input > for my primary fpga clock source? (im am using SPI for configuration). If you're using SPI for configuration, you should be fine. According to the Spartan-3 Generation Configuration User Guide http://www.xilinx.com/support/documentation/user_guides/ug332.pdf the RDWR_B is only used for BPI and Slave Serial modes (table 2-15, p54 and table 2-16, p. 57). Also keep in mind that you can use other GCLK signals as alternatives to GCLK0. Just because it's "0" doesn't mean it has to be used first. Note with the BPI mode on page 160 in the User Guide that many, many GCLK lines are taken up by that configuration mode. You should be clean with SPI configuration; do you have functional results that suggest the data isn't accurate or was it just a matter of incompletely communicated information in the myriad of guides and tables that led you to believe you were in trouble? Hope the configuration is a breeze, - John_HArticle: 127152
On Dec 12, 2:42 pm, John Adair <g...@enterpoint.co.uk> wrote: > Your are entering a very big subject area that most people make the > classic mistake that "it's just drawing lines on the screen". We > entered the manufacturing market 4 years ago with some substantial > practical experience being involved in customer designs but it was > still a very big jump to doing it all yourself. I know, from many > years helping customers out of problems, that our own hit rate in > delivering perfect boards is exceptional. Some our boards are still > effectively in their first revision. Even now after our having design > something like 100 major designs in the last 4 years we still are > learning things about the process and even new tricks. Some companies > that we see actually think they are doing well if they get it right in > 3 revisions of a particular board. I have seen some customer designed > projects go to 7+ revisions before they called us in. > > That all said it can be a very pleasant task to layout boards somthing > like tacking a jigsaw pauzzle. Whether you find doing boards yourself > good fun, or frustrating and expensive when you make mistakes, you > might want to start doing a simple design on a cheap package like > Eagle and then going through the manufacturing process. Having learned > some of the ropes you can then make better judgements on what tools to > buy and even if the own layout process works for you. > > John Adair > Enterpoint Ltd. - Home of CR1 the J1962 solution. > > On 12 Dec, 18:45, Poonam <poonam.mur...@gmail.com> wrote: > > > > > On Dec 12, 1:26 pm, John_H <newsgr...@johnhandwork.com> wrote: > > > > On Dec 12, 7:13 am, Poonam <poonam.mur...@gmail.com> wrote: > > > > > Hi, > > > > > I have been developing applications in Xilinx FPGAs using VHDL for the > > > > past 3 years for a small company in Virginia. As our designs are > > > > getting larger and more complex, the off-the-shelf boards we have been > > > > using are proving to be insufficient. I am interested in learning > > > > about designing boards myself with FPGAs, ADCs, DACs etc. I am new to > > > > board design and am wondering where to start. Any suggestions would be > > > > greatly appreciated. > > > > > Thanks, > > > > Poonam > > > > Without communicating the level of engineer you are, it's hard to > > > communicate what it takes to succeed in board design. Are you even a > > > hardware engineer? Do you prototype hardware with flying wires, a > > > soldering iron, and cheap plastic cases? Do you know anything about > > > power regulators, amplifiers, transmission line theory, or PCB > > > manufacturing issues? > > > > Please tell us a little more about what you bring to the table. > > > You are right.. I should've mentioned before that I don't have any > > hardware experience, but do have some theoretical knowledge about > > amplifiers, transmission line theory etc. I am a complete newbie in > > PCB design.. > > > Poonam- Hide quoted text - > > > - Show quoted text -- Hide quoted text - > > - Show quoted text - Thank you Gabor and John. I know I am entering a whole new area and that it will take a lot of time (years...) and effort to get good at it. But I will try out the suggestions you guys have posted. I will start out with some cheap CAD package and see how it goes. Thanks again for the replies.Article: 127153
John Stein wrote:
> [RocketIO]
>
>> Are you trying to implement your own protocol? If you are just
>> transferring data between the devices, why not use the Aurora protocol?
>> It is simple and already debugged, and works quite well.
>
> As a matter of fact, I have to write a conduit for a special application
> protocol already established. I do have the source code for that
> protocol and I basically followed each step which is done, but had no
> success. It seems so strange, that the parallel loopback works, but the
> serial does not. As a matter of fact this is my first high speed
> protocol experience and as far as I understand the synchronization
> (apart from bit alignment) is done by the RocketIO controller. I still
> find no explanation why the bits are changed in that drastic matter
> (input doesn't seem to match output in any way)
> I also had a look at the Aurora protocol, but I am not sure if that is
> really going to help me (even though I'm still looking through it).
> At this point pretty much every idea is welcome.
I have 2 guesses as to what is likely wrong.
1) You didn't wait long enough for the MGT PLL and CDR to be fully
functional and if you run it another 10K+ words things might be OK.
2) Your special application protocol is not properly aligned as you
either haven't set the 8B10B comma alignment sequences to the values
defined in your protocol (along with the correct initialization
control) or if you have a scrambled protocol you haven't implemented
an aligner in the fabric.
When you start something new and foreign, IMHO, it is best to start from
a known working solution that is close to what you are attempting to do.
Then you can verify that your setup is correct, understand how it works,
tweak it, and eventually build your own unique version. In this case
starting with the Aurora 8B10B example designs for Virtex-II Pro would
be a very good first step.
Ed McGettigan
--
Xilinx Inc.
Article: 127154How come in the pdf of the vq100 diagram, it shows something with 64 pins. This is odd because the spartan 3e sure doesn't come in a vq64, it comes in a vq100. Maybe they mean the vq100 has 64 pins but that doesn't make sense because the pinout spreadsheet has 100 entries. And how would you divide 100 by 4 to fill up 4 sides of a square chip? You cant do that with 100 unless its a 5 sided chip. Thanks.Article: 127155
On Dec 12, 4:45 pm, Josh.OuterSp...@gmail.com wrote: > How come in the pdf of the vq100 diagram, it shows something with 64 > pins. This is odd because the spartan 3e sure doesn't come in a vq64, > it comes in a vq100. Maybe they mean the vq100 has 64 pins but that > doesn't make sense because the pinout spreadsheet has 100 entries. > And how would you divide 100 by 4 to fill up 4 sides of a square > chip? You cant do that with 100 unless its a 5 sided chip. > > Thanks. This is the link the datasheet sends you to. http://www.xilinx.com/bvdocs/packages/vq100.pdfArticle: 127156
Hi, I am a bit new to VHDL. Can some one please point me to component labeling (image processing) code in VHDL if there is any. Regards RkArticle: 127157
In comp.arch.fpga, Josh.OuterSpace@gmail.com <Josh.OuterSpace@gmail.com> wrote: > On Dec 12, 4:45 pm, Josh.OuterSp...@gmail.com wrote: >> How come in the pdf of the vq100 diagram, it shows something with 64 >> pins. This is odd because the spartan 3e sure doesn't come in a vq64, >> it comes in a vq100. Maybe they mean the vq100 has 64 pins but that >> doesn't make sense because the pinout spreadsheet has 100 entries. >> And how would you divide 100 by 4 to fill up 4 sides of a square >> chip? You cant do that with 100 unless its a 5 sided chip. >> >> Thanks. > > This is the link the datasheet sends you to. > http://www.xilinx.com/bvdocs/packages/vq100.pdf This is the mechanical drawing for the xilinx VQ44, VQ64 and VQ100 packages, not limited to spartan 3e. The pins drawn are just an indication and there happen to be 64 of them on the drawing, but that could have been 4 or 16 or 44... Just use the sizes from the table for the VQ100 package. There are 25 pins on each side, symetrical around the center of the package, 0.5mm pin pitch. But with any luck there will be a suitable shape in your pcb package library. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)Article: 127158
Rk wrote: > Can some one please point me to component > labeling (image processing) code in VHDL if there is any. http://www.google.com/search?q=vhdl+examples+image+processingArticle: 127159
Hello, I'm having problems with XIlinx ISE 9.1. My design works fine on behavioral simulation but when I want to implement i, I get an error in bitgen stage. I get a warning message in PAR stage: "WARNING:Par:289 - The signal GSS/emu_gss/emul_sm/B_haz has no driver. PAR will not attempt to route this signal. The error message is: "ERROR:PhysDesignRules:10 - The network <GSS/emu_gss/B_haz> is completely unrouted." They seem to be related. How can I avoid PAR to eliminate the signal B_haz?. Everything looks fine in the simulation (every line has a defined value), what can be wrong?. Thanks, Daniel.Article: 127160
Poonam wrote: > > Thank you Gabor and John. I know I am entering a whole new area and > that it will take a lot of time (years...) and effort to get good at > it. But I will try out the suggestions you guys have posted. I will > start out with some cheap CAD package and see how it goes. Thanks > again for the replies. After designing a simple board, a very handy thing to do is to submit the design files to http://www.freedfm.com/ It will tell you quickly about a number of ordinary board design problems you might have. There is no obligation to purchase boards, though for simple boards the price is decent.Article: 127161
I have performed the simulation by sample project generated after core gen. By the way, the sample project Is application on an actual FPGA board possible? Jim Wu $B$N%a%C%;!<%8(B: > On Dec 12, 1:29 am, dream_life_0102 <yosh...@jp.fujitsu.com> wrote: > > hello > > > > I will be trying to [Tri-Mode Embedded EMAC] except EDK tool. > > > > Can I implement only by ISE 9.1i tool ? > > > > Does anyone have a sample project? > > You can generate one from CoreGen. > > Cheers, > Jim > http://home.comcast.net/%7Ejimwu88/toolsArticle: 127162
On Dec 12, 6:22 pm, Duane Clark <junkm...@junkmail.com> wrote: > Poonam wrote: > > > Thank you Gabor and John. I know I am entering a whole new area and > > that it will take a lot of time (years...) and effort to get good at > > it. But I will try out the suggestions you guys have posted. I will > > start out with some cheap CAD package and see how it goes. Thanks > > again for the replies. > > After designing a simple board, a very handy thing to do is to submit > the design files tohttp://www.freedfm.com/ > It will tell you quickly about a number of ordinary board design > problems you might have. There is no obligation to purchase boards, > though for simple boards the price is decent. Can anybody suggest some books I could start with? Thanks, PoonamArticle: 127163
> Can anybody suggest some books I could start with? It's probably a bit dated, but when I was working on PCB design, I found the following book to be quite useful ... http://www.amazon.com/High-Speed-Digital-Design-Semiconductor/dp/0133957241 (I worked for a company that brought the author in for an afternoon to give a talk & answer questions. It was pretty interesting.) K.Article: 127164
On Wed, 12 Dec 2007 13:45:47 -0800 (PST), Josh.OuterSpace@gmail.com wrote: >How come in the pdf of the vq100 diagram, it shows something with 64 >pins. This is odd because the spartan 3e sure doesn't come in a vq64, >it comes in a vq100. Maybe they mean the vq100 has 64 pins but that >doesn't make sense because the pinout spreadsheet has 100 entries. >And how would you divide 100 by 4 to fill up 4 sides of a square >chip? You cant do that with 100 unless its a 5 sided chip. > >Thanks. I couldn't swear to it, but I think that 100 divided by 4 is close to 25. JohnArticle: 127165
On Dec 12, 8:21 am, John Stein <slime...@fragmasters.net> wrote: > Hi. > I am trying to establish a communication between two RocketIO driven > Virtex2P FPGAs. I am currently simulating the design running into the > following problem: When I set the RocketIO Transmitters (Xilinx > GT_CUSTOM) into parallel loopback mode everything is fine (received data > = sent data). Whenever I set it into serial loopback mode (or try to > communicate with another RocketIO receiver) I seem to receive strange > data (which doesn't seem to be connected to sent data in any way). I am > completely running out of ideas what I might do wrong, even though I am > just a starter with RocketIO. An yes, I did read the RocketIO Users > Guide, but I didn't find it very helpful for my problem. Howdy John, At the risk of pointing out the obvious, it's pretty much gotta be one of the following: 1. MGT power (LDO fed, right?) 2. MGT ref clock (tried renting a differential scope probe? Coming from an XO [not a PLL]? Low jitter?) 3. chip-to-chip problem (board-level signal integrity through traces, connectors, ac-coupling, etc) 4. Protocol (anything in the digital domain - like byte alignment that others have hinted at, or not crossing clock domains correctly) One item to be aware of: the analog loopback (looping TX data to RX data) is exactly that - analog. While I wouldn't call it useless, it is VERY sensitive because you end up with a great big stub hanging off due to the trace to your other FPGA. If you happened to have connected power to a spare MGT, you might try looping back there. Good luck, MarcArticle: 127166
On Dec 12, 10:47 pm, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > On Wed, 12 Dec 2007 13:45:47 -0800 (PST), Josh.OuterSp...@gmail.com > wrote: > > >How come in the pdf of the vq100 diagram, it shows something with 64 > >pins. This is odd because the spartan 3e sure doesn't come in a vq64, > >it comes in a vq100. Maybe they mean the vq100 has 64 pins but that > >doesn't make sense because the pinout spreadsheet has 100 entries. > >And how would you divide 100 by 4 to fill up 4 sides of a square > >chip? You cant do that with 100 unless its a 5 sided chip. > > >Thanks. > > I couldn't swear to it, but I think that 100 divided by 4 is close to > 25. > > John It makes more sense to me to have 5 sides than an odd number of pins one sideArticle: 127167
Josh.OuterSpace@gmail.com wrote: >On Dec 12, 10:47 pm, John Larkin ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> On Wed, 12 Dec 2007 13:45:47 -0800 (PST), Josh.OuterSp...@gmail.com >> wrote: >> >> >How come in the pdf of the vq100 diagram, it shows something with 64 >> >pins. This is odd because the spartan 3e sure doesn't come in a vq64, >> >it comes in a vq100. Maybe they mean the vq100 has 64 pins but that >> >doesn't make sense because the pinout spreadsheet has 100 entries. >> >And how would you divide 100 by 4 to fill up 4 sides of a square >> >chip? You cant do that with 100 unless its a 5 sided chip. >> >> >Thanks. >> >> I couldn't swear to it, but I think that 100 divided by 4 is close to >> 25. >> >> John > >It makes more sense to me to have 5 sides than an odd number of pins >one side Hmm, why not make chip packages round? Would make soldering a bit more easy since the pin spacing would be maximal at the end of the leads. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 127168
I'm trying to use the Xilinx ISOCM memory in a Virtex-II Pro. I can't seem to get it to actually write to the ISOCM BRAMs. In .mhs file I have: BEGIN ppc405 PARAMETER INSTANCE = ppc405_0 PARAMETER HW_VER = 2.00.c PARAMETER C_ISOCM_DCR_BASEADDR = 0b0100000000 PARAMETER C_DSOCM_DCR_BASEADDR = 0b1000000000 PARAMETER C_DCR_RESYNC = 2 BUS_INTERFACE ISOCM = iocm BUS_INTERFACE DSOCM = docm PORT BRAMISOCMCLK = sys_clk_s PORT BRAMDSOCMCLK = sys_clk_s PORT DCRCLK = sys_clk_s . . . END BEGIN isocm_v10 PARAMETER INSTANCE = iocm PARAMETER HW_VER = 2.00.a PARAMETER C_ISCNTLVALUE = 0x83 // Note ppc_clk_s is 2 times sys_clk_s PORT ISOCM_Clk = sys_clk_s PORT sys_rst = sys_bus_reset END BEGIN isbram_if_cntlr PARAMETER INSTANCE = iocm_cntlr PARAMETER HW_VER = 3.00.a PARAMETER C_BASEADDR = 0x01000000 PARAMETER C_HIGHADDR = 0x01003FFF BUS_INTERFACE ISOCM = iocm BUS_INTERFACE DCR_WRITE_PORT = isocm_porta BUS_INTERFACE INSTRN_READ_PORT = isocm_portb END BEGIN bram_block PARAMETER INSTANCE = isocm_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = isocm_porta BUS_INTERFACE PORTB = isocm_portb END In .mss I have: BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = iocm_cntlr END Then in my C code, I do the following: // Initialize ISINIT register to starting address. // This works when I read it back. mtdcr(0x100, 0x01000000); I'm using 0x100 for the DCRN address above since I set the base address of the IOCM DCR to 0x100 in the MHS, and the offset of the ISINIT from that base is 0. // Write a value to ISFILL register. mtdcr(0x101, 0xFFFFFFFF); The write to the ISFILL works and increments ISINIT as it should. Reading back the value in ISFILL gives 0xFFFFFFFF as it should, but this is just the register, not what is in BRAM itself. However, when I go to read the IOCM memory itself using: long *p = (long *) 0x01000000; long x = *p; I still get 0. So it seems the like everything is working except the value in ISFILL is not being transferred to the actual BRAM. What am I missing? Do I need to create a DCR bus to the IOCM? Do I need to somehow enable DCR writes? Any help would be appreciated.Article: 127169
Nico Coesel wrote: > Josh.OuterSpace@gmail.com wrote: > > >On Dec 12, 10:47 pm, John Larkin > ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > >> On Wed, 12 Dec 2007 13:45:47 -0800 (PST), Josh.OuterSp...@gmail.com > >> wrote: > >> > >> >How come in the pdf of the vq100 diagram, it shows something with 64 > >> >pins. This is odd because the spartan 3e sure doesn't come in a vq64, > >> >it comes in a vq100. Maybe they mean the vq100 has 64 pins but that > >> >doesn't make sense because the pinout spreadsheet has 100 entries. > >> >And how would you divide 100 by 4 to fill up 4 sides of a square > >> >chip? You cant do that with 100 unless its a 5 sided chip. > >> > >> >Thanks. > >> > >> I couldn't swear to it, but I think that 100 divided by 4 is close to > >> 25. > >> > >> John > > > >It makes more sense to me to have 5 sides than an odd number of pins > >one side > > Hmm, why not make chip packages round? Would make soldering a bit more > easy since the pin spacing would be maximal at the end of the leads. > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U op www.adresboekje.nl Why do we have to be locked into the concept of a flat chip that has to rest on a flat board? I want spherical chips that snap together like playing legos.Article: 127170
On Dec 13, 3:58 am, dte...@gmail.com wrote: > Hello, > I'm having problems with XIlinx ISE 9.1. My design works fine on > behavioral simulation but when I want to implement i, I get an error > in bitgen stage. > > I get a warning message in PAR stage: > "WARNING:Par:289 - The signal GSS/emu_gss/emul_sm/B_haz has no driver. > PAR will not attempt to route this signal. > > The error message is: > "ERROR:PhysDesignRules:10 - The network <GSS/emu_gss/B_haz> is > completely unrouted." > > They seem to be related. How can I avoid PAR to eliminate the signal > B_haz?. Everything looks fine in the simulation (every line has a > defined value), what can be wrong?. > > Thanks, > Daniel. Daniel, Apparently the logic has been removed in the synthesis process. Recheck your driving logic for the signal. When I face similar problem, I usually bind these signals to an used I/ O of FPGA. You may try that as well. (Definitely not a recommended practice). Hope this helps. /MHArticle: 127171
HI everyone, I have purchased ML505 virtex5 based kit for PCIe testing. It has one pre-loaded compact flash with some in-built testing environment. My uses is PCIe testing which this compact flash doesn't have the testing utility nor Xilinx having any utility for the same. I have contacted Xilinx but didn't get any proper answer. As per user guide it requires external CF reader for copying .ace file to compact flash after executing using core gen for PCIe. Does any body know how to read/write compact flash on-board(ML505), any utility to copy any file to compact flash, anybody having?? I don't have CF reader. I want to copy generated .ace file to CF using on-board ML505. Your early reply is highly appreciated. Thanks, SachinArticle: 127172
Hi, Can you show the system.mhs file and the system_map.mrp contents? You can't have 31 BRAMs in a device with 16 BRAMs. There is no extra magic inside the FPGA, just the usual magic. Göran "ratemonotonic" <niladri1979@gmail.com> wrote in message news:2a8577bd-197c-4d03-8bfc-3f37ed87cfef@e25g2000prg.googlegroups.com... > Hi All , > > I am new to FPGA development and have learned VHDL using text books. > NOW! that doesn't teach practical aspects! > I am extremely confused with the following discovery - > > I am using Spartan 3 400k device and it has 16 block rams. > I have configured a microblaze system to use block ram as follows - > > 1) Local memory - 16 Kbytes > 2) OPB Block Ram 1 - 8Kbytes > 3) OPB Block Ran 2 - 8Kbytes > > That means that it has used up all the block Rams. > > Now the confusing part - I have designed an IP which consumes 15 > Block Rams , and when I include the IP in my microblaze system , the > bitstream gets generated! The synthesis report shows that my IP is > using up 15 Block Rams and that microblaze momories are using up 16 > Block Rams! That means that the system is using up 31 Block Rams! > > How is that Possilbe? > > Any help would be greatly appreciated. > > BR > RateArticle: 127173
First cut of the Darnaw1 user manual is now available here http://www.enterpoint.co.uk/moelbryn/Darnaw1_User_Manual_Issue_1_00.pdf. John Adair Enterpoint Ltd. - Home of Darnaw1. The PGA FPGA solution.Article: 127174
Hi > What FPGA you are using? What kind of interfaces are already available > on your design? How much data do you want to capture? How fast? I am using a Xilinx Virtex II XC2V6000 board, and I have a simple processor running on it. So the simulation in Modelsim is working fine, and I have to check wether the register content or the memory content on the FPGA are the same as in the simulation! So either I have a way to see what is written in the registers in the end or I need a way to have access to the data written into the RAM. How fast doesnt matter, I just need to know now for a start, that at the end of the computation I have the correct result! > Typically, I already have some sort of interface that goes to a > computer, allowing me to capture data to a file. I commonly include some > debugging circuitry within my designs that allow me to steer > intermediate data to the output, so that I can verify the operation of > different stages in the data path. That sounds interesting, maybe also useful for me. Are there some webresources that tells me the basics whats the best way to achieve this? > I kind of infer from the way you phrased the question the you don't want > to use Chipscope? If that assumption is wrong, and you have a Xilinx > FPGA, then how about Chipscope? It does exactly what you are asking > about, though it does use the JTAG port. Yes I have chipscope and JTAG, so maybe thats then my only chance if there is no other way to do that!
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