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Threads Starting Jun 2004

70059: 04/06/01: Kelvin: Is this a bug in ISE 6.1?
    70063: 04/06/01: lee news: Re: Is this a bug in ISE 6.1?
70062: 04/06/01: arvind: Configration............problem..............
70065: 04/06/01: Iker Pryszo: Testing a lot of FPGA
70067: 04/06/01: George: NIOS 2 memory limitations
    70069: 04/06/01: David Brown: Re: NIOS 2 memory limitations
        70073: 04/06/01: George: Re: NIOS 2 memory limitations
            70077: 04/06/01: Ken Land: Re: NIOS 2 memory limitations
            70080: 04/06/01: Jesse Kempa: Re: NIOS 2 memory limitations
                70148: 04/06/05: Stifler: Re: NIOS 2 memory limitations
70068: 04/06/01: yvan.eustache1@etud.univ-ubs.fr: Problem with carry reusing RPM with ISE 6.2i and VirtexE
    70071: 04/06/01: Symon: Re: Problem with carry reusing RPM with ISE 6.2i and VirtexE
70074: 04/06/01: Matthew E Rosenthal: converting design from ise 6.1 to 6.2 problems
    70076: 04/06/01: Symon: Re: converting design from ise 6.1 to 6.2 problems
70075: 04/06/01: George: NIOS I memory usage
70078: 04/06/01: Michael S: Seven leading PC processors benchmarked on Quartus-II Web Ed place&route
    70081: 04/06/02: Tommy Thorn: Re: Seven leading PC processors benchmarked on Quartus-II Web Ed
70079: 04/06/01: Mark Holland: Problems with PLAmap (part of RASP package) from UCLA
70082: 04/06/01: digari: tri-state in altera
    70092: 04/06/02: rickman: Re: tri-state in altera
        70093: 04/06/02: Austin Lesea: Re: tri-state in altera
            70118: 04/06/03: qlyus: Re: tri-state in altera
                70119: 04/06/03: Symon: Re: tri-state in altera
                    70130: 04/06/03: Marc Randolph: Re: tri-state in altera
                70120: 04/06/03: Ray Andraka: Re: tri-state in altera
            70127: 04/06/03: Jeff Cunningham: Re: tri-state in altera
                70128: 04/06/03: Austin Lesea: Re: tri-state in altera and xilinx
                    70131: 04/06/04: Jan Gray: Re: tri-state in altera and xilinx
                        70132: 04/06/04: Jan Gray: Re: tri-state in altera and xilinx
                        70135: 04/06/04: Ray Andraka: Re: tri-state in altera and xilinx
                            70136: 04/06/04: Ray Andraka: Re: tri-state in altera and xilinx
                            70138: 04/06/04: Jan Gray: Re: tri-state in altera and xilinx
                                70142: 04/06/04: Ray Andraka: Re: tri-state in altera and xilinx
                            70139: 04/06/04: Hal Murray: Re: tri-state in altera and xilinx
                                70140: 04/06/04: rickman: Re: tri-state in altera and xilinx
                                    70141: 04/06/04: Ray Andraka: Re: tri-state in altera and xilinx
                                    70271: 04/06/10: Hal Murray: Re: tri-state in altera and xilinx
                                        70273: 04/06/11: Phil Hays: Re: tri-state in altera and xilinx
                                            70305: 04/06/11: Peter Alfke: Re: tri-state in altera and xilinx
    70114: 04/06/03: Vaughn Betz: Re: tri-state in altera
        70116: 04/06/03: Austin Lesea: Re: tri-state in altera and xilinx
            70124: 04/06/03: qlyus: Re: tri-state in altera and xilinx
                70126: 04/06/03: Eric Crabill: Re: tri-state in altera and xilinx
70086: 04/06/02: chris: How can I get an output clock phased align with the input clock.
    70087: 04/06/02: Luc Braeckman: Re: How can I get an output clock phased align with the input clock.
        70107: 04/06/03: chris: Re: How can I get an output clock phased align with the input clock.
            70111: 04/06/03: Luc Braeckman: Re: How can I get an output clock phased align with the input clock.
    70089: 04/06/02: Dave Vanden Bout: Re: How can I get an output clock phased align with the input clock.
    70105: 04/06/03: John Retta: Re: How can I get an output clock phased align with the input clock.
    70209: 04/06/09: Luc Braeckman: Re: How can I get an output clock phased align with the input clock.
70090: 04/06/02: Srikanth Anumalla: FPGA + A/D converter
    70091: 04/06/02: Ray Andraka: Re: FPGA + A/D converter
    70096: 04/06/03: Jim Granville: Re: FPGA + A/D converter
        70100: 04/06/02: Ulf Samuelsson: Re: FPGA + A/D converter
70097: 04/06/02: Matt Cohen: 5 V inputs to 3.3 V CPLD
    70098: 04/06/02: rickman: Re: 5 V inputs to 3.3 V CPLD
        70117: 04/06/03: Matt Cohen: Re: 5 V inputs to 3.3 V CPLD
    70099: 04/06/02: Ray Andraka: Re: 5 V inputs to 3.3 V CPLD
    70113: 04/06/03: James Alston: Re: 5 V inputs to 3.3 V CPLD
70102: 04/06/03: Richard B. Katz: MAPLD 2004: Registration Open and Program Announced
70103: 04/06/02: Adam Megacz: FPPTA?
    70104: 04/06/03: Jim Granville: Re: FPPTA?
    70108: 04/06/03: Philip Freidin: Re: FPPTA?
70106: 04/06/03: Giuseppeł: Three-phase PWM generator in VHDL
    70109: 04/06/03: Rene Tschaggelar: Re: Three-phase PWM generator in VHDL
        70112: 04/06/03: Giuseppeł: Re: Three-phase PWM generator in VHDL
    70156: 04/06/06: Mike: Re: Three-phase PWM generator in VHDL
70110: 04/06/03: Florian: Partial Reconfiguration clock enable problem
    156685: 14/06/04: <hiluckydr@gmail.com>: Re: Partial Reconfiguration clock enable problem
        156686: 14/06/04: KJ: Re: Partial Reconfiguration clock enable problem
        156688: 14/06/04: Mike Perkins: Re: Partial Reconfiguration clock enable problem
            156690: 14/06/04: glen herrmannsfeldt: Re: Partial Reconfiguration clock enable problem
                156717: 14/06/07: rickman: Re: Partial Reconfiguration clock enable problem
70121: 04/06/03: John Providenza: Virtex-II Pro slave serial configuration problem....
    70213: 04/06/09: John Providenza: Re: Virtex-II Pro slave serial configuration problem....
        70270: 04/06/10: Hal Murray: Re: Virtex-II Pro slave serial configuration problem....
            70354: 04/06/14: John Providenza: Re: Virtex-II Pro slave serial configuration problem....
70123: 04/06/03: rickman: USB OTG high speed
    70133: 04/06/03: db: Re: USB OTG high speed
    70153: 04/06/05: Antti Lukats: Re: USB OTG high speed
70125: 04/06/03: qlyus: where is ISE 6.2 SP#3 ?
    70134: 04/06/04: Peng Cong: Re: where is ISE 6.2 SP#3 ?
        70272: 04/06/10: Hendra Gunawan: Re: where is ISE 6.2 SP#3 ?
70129: 04/06/03: Chris Cheung: PAR runtime error
70137: 04/06/04: Holger Baxmann: IDE/ATA _device_ core availablility
    70147: 04/06/05: Dave Vanden Bout: Re: IDE/ATA _device_ core availablility
        70151: 04/06/05: Holger Baxmann: Re: IDE/ATA _device_ core availablility
70145: 04/06/04: Sumit Gupta: Book on SPARK: parallelizing high-level synthesis tool
70152: 04/06/05: Charles Zheng: parameter feature of AHDL in Xilinx
    70160: 04/06/07: Anders Hellerup Madsen: Re: parameter feature of AHDL in Xilinx
70154: 04/06/05: Jason Berringer: Quick question
    70164: 04/06/07: john jakson: Re: Quick question
    70167: 04/06/07: John_H: Re: Quick question
        70197: 04/06/08: Jason Berringer: Re: Quick question
            70215: 04/06/09: John_H: Re: Quick question
                70237: 04/06/09: Jason Berringer: Re: Quick question
    70327: 04/06/12: Ken McElvain: Re: Quick question
70155: 04/06/06: GaRY: Variable Frequency and Voltage Supply
    70168: 04/06/07: Peter Alfke: Re: Variable Frequency and Voltage Supply
        70181: 04/06/08: GaRY: Re: Variable Frequency and Voltage Supply
70157: 04/06/06: David Joseph Bonnici: Where is my Digital Up Convertor in Logicore ??!! :)
70158: 04/06/07: Scott Mahlke: CFP: Workshop on Application Specific Processors (WASP 2004)
70159: 04/06/07: Adarsh Kumar Jain: Rocket IO Timing Problem : sometimes miss Half Word
70161: 04/06/07: Adarsh Kumar Jain: Rocket IO : Sensitivity to RefClk Phase
70162: 04/06/07: pop: comp.arch.fpga: reset strategy
    70172: 04/06/07: Hendra Gunawan: Re: comp.arch.fpga: reset strategy
    70173: 04/06/08: John Retta: Re: comp.arch.fpga: reset strategy
        70190: 04/06/08: Thomas Stanka: Re: comp.arch.fpga: reset strategy
            70203: 04/06/09: rickman: Re: comp.arch.fpga: reset strategy
        70194: 04/06/08: glen herrmannsfeldt: Re: comp.arch.fpga: reset strategy
            70210: 04/06/09: Rajeev: Re: comp.arch.fpga: reset strategy
                70311: 04/06/11: glen herrmannsfeldt: Re: comp.arch.fpga: reset strategy
    70238: 04/06/10: roller: design guidelines, was: comp.arch.fpga: reset strategy
70163: 04/06/07: yvan.eustache1@etud.univ-ubs.fr: Problem with the "Write RPM to UCF" command (floorplanner 6)
70165: 04/06/07: Peter Sommerfeld: Good SDRAM Controller
    70166: 04/06/07: Dave Vanden Bout: Re: Good SDRAM Controller
    70169: 04/06/07: Roger Larsson: Re: Good SDRAM Controller
        70189: 04/06/08: Peter Sommerfeld: Re: Good SDRAM Controller
            70202: 04/06/09: rickman: Re: Good SDRAM Controller
    70175: 04/06/08: Nicolas Matringe: Re: Good SDRAM Controller
        70188: 04/06/08: Peter Sommerfeld: Re: Good SDRAM Controller
        70201: 04/06/09: rickman: Re: Good SDRAM Controller
            70214: 04/06/09: Peter Sommerfeld: Re: Good SDRAM Controller
                70235: 04/06/09: john jakson: Re: Good SDRAM Controller
70170: 04/06/07: Hendra Gunawan: ISE 4.2i Impact and Windows XP not working
    70219: 04/06/09: Neil Glenn Jacobson: Re: ISE 4.2i Impact and Windows XP not working
70171: 04/06/07: charles: DCM in Xilinx
    70200: 04/06/09: charles: Re: DCM in Xilinx
    70451: 04/06/17: john: Re: DCM in Xilinx
70174: 04/06/08: Allan Herriman: Virtex-4 FX transceiver jitter
    70180: 04/06/08: John Adair: Re: Virtex-4 FX transceiver jitter
70176: 04/06/08: Heiko: Hardware implementation of the Xilinx configuration CRC generator
    70177: 04/06/08: Philip Freidin: Re: Hardware implementation of the Xilinx configuration CRC generator
        70179: 04/06/08: Allan Herriman: Re: Hardware implementation of the Xilinx configuration CRC generator
            70196: 04/06/08: Philip Freidin: Re: Hardware implementation of the Xilinx configuration CRC generator
            70198: 04/06/08: Heiko: Re: Hardware implementation of the Xilinx configuration CRC generator
            70236: 04/06/09: Eric Smith: Re: Hardware implementation of the Xilinx configuration CRC generator
70178: 04/06/08: Julien Chevalier: SOPC BUILDER - SOFTWARE GENERATION
    70182: 04/06/08: Petter Gustad: Re: SOPC BUILDER - SOFTWARE GENERATION
    70268: 04/06/10: Jerry: Re: SOPC BUILDER - SOFTWARE GENERATION
70183: 04/06/08: Petter Gustad: Virtex-4 availability?
    70184: 04/06/08: Uwe Bonnes: Re: Virtex-4 availability?
70185: 04/06/08: Clark Pope: IR_CAPTURE fail on Virtex2
    70218: 04/06/09: Neil Glenn Jacobson: Re: IR_CAPTURE fail on Virtex2
        70229: 04/06/09: Clark Pope: Re: IR_CAPTURE fail on Virtex2
70186: 04/06/08: geoffrey brown: Nios II really available ?
    70239: 04/06/09: Bob Garrett: Re: Nios II really available ?
        70242: 04/06/10: Tommy Thorn: Re: Nios II really available ?
            70267: 04/06/10: Dave Greenfield: Re: Nios II really available ?
                70278: 04/06/10: Stifler: Re: Nios II really available ?
                    70279: 04/06/11: David Brown: Re: Nios II really available ?
70187: 04/06/08: charles: slice # change from .syr to map report
    70193: 04/06/08: Ray Andraka: Re: slice # change from .syr to map report
70191: 04/06/08: Jan Gray: V4 teaser
    70192: 04/06/08: Jan Gray: Re: V4 teaser, correction
        70204: 04/06/09: rickman: Re: V4 teaser, correction
            70211: 04/06/09: Marc Randolph: Re: V4 teaser, correction
                70222: 04/06/09: Steven K. Knapp: Re: V4 teaser, correction
                    70227: 04/06/09: rickman: Re: V4 teaser, correction
                    70233: 04/06/09: Hul Tytus: Re: V4 teaser, correction
70195: 04/06/08: sabine: Where is my Digital Up Convertor in Logicore ??!!
70199: 04/06/08: Raven76: handel-c library file
    70732: 04/06/25: Alan Fitch: Re: handel-c library file
70205: 04/06/09: Matthew E Rosenthal: xilinx gigabit MAC core full vs half duplex
    70212: 04/06/09: Marc Randolph: Re: xilinx gigabit MAC core full vs half duplex
70206: 04/06/09: Lawrence Nospam: Question about Xilinx packages and CLB ordering
    70217: 04/06/09: Symon: Re: Question about Xilinx packages and CLB ordering
70207: 04/06/09: San San: lancelot VGA daughter board for altera nios dev board
    70208: 04/06/09: David Brown: Re: lancelot VGA daughter board for altera nios dev board
    70241: 04/06/10: Tommy Thorn: Re: lancelot VGA daughter board for altera nios dev board
        70277: 04/06/11: San San: Re: lancelot VGA daughter board for altera nios dev board
70216: 04/06/09: Pszemol: Altera Instructor-led course on Designing with NIOS II
70220: 04/06/09: David Joseph Bonnici: Digital Clock Manager (DCM) Question
    70223: 04/06/09: Peter Alfke: Re: Digital Clock Manager (DCM) Question
        70224: 04/06/09: Symon: Re: Digital Clock Manager (DCM) Question
            70225: 04/06/09: Austin Lesea: Re: Digital Clock Manager (DCM) Question
                70226: 04/06/09: Symon: Re: Digital Clock Manager (DCM) Question
                    70230: 04/06/09: Austin Lesea: Re: Digital Clock Manager (DCM) Question
        70228: 04/06/09: Peter Alfke: Re: Digital Clock Manager (DCM) Question
            70232: 04/06/09: Austin Lesea: Re: Digital Clock Manager (DCM) Question
70221: 04/06/09: Rudi Grave: Xilinx 6.2 - - WARNING:NetListWriters:303
70234: 04/06/09: vadim: LPM Megafunction : LPM_SHIFTREG timing
70240: 04/06/10: Phil Hays: Xilinx Co-Founder Bernard 'Bernie' Vonderschmitt Passes Away
70243: 04/06/10: Valeri Serebrianski: Is Virtex-4 LX succesor for Spatan-3?
70244: 04/06/10: Andrew Greensted: Stupid Xilinx Rubbish
    70248: 04/06/10: Andrew Greensted: Re: Not so Stupid Xilinx Rubbish
    70280: 04/06/11: Gammaburst: Re: Stupid Xilinx Rubbish
70245: 04/06/10: sebastian: delayed clocks on timesim simulation?
70246: 04/06/10: Allan Herriman: Virtex-4 suggestion: TSMCCCS change
70247: 04/06/10: Andrew Greensted: Help For Linux ISE users (DLC5, impact)
70249: 04/06/10: Julien Chevalier: can't trap custom ITon NIOS
    70250: 04/06/10: Kenneth Land: Re: can't trap custom ITon NIOS
    70259: 04/06/10: Ben Twijnstra: Re: can't trap custom ITon NIOS
70251: 04/06/10: chris: Frequency synthesizer.
    70579: 04/06/21: Tarmo Palm: Re: Frequency synthesizer.
        70588: 04/06/21: Peter Alfke: Re: Frequency synthesizer.
70252: 04/06/10: Brannon King: Virtex4: I don't understand their thinking....
    70254: 04/06/10: Peter Alfke: Re: Virtex4: I don't understand their thinking....
    70255: 04/06/10: Symon: Re: Virtex4: I don't understand their thinking....
        70258: 04/06/10: Austin Lesea: Re: Virtex4: I don't understand their thinking....
        70281: 04/06/11: Adam Megacz: Re: Virtex4: I don't understand their thinking....
            70296: 04/06/11: Symon: Re: Virtex4: I don't understand their thinking....
        70295: 04/06/11: rickman: Re: Virtex4: I don't understand their thinking....
            70299: 04/06/11: Symon: Re: Virtex4: I don't understand their thinking....
                70302: 04/06/11: rickman: Re: Virtex4: I don't understand their thinking....
                70322: 04/06/12: Simon Peacock: Re: Virtex4: I don't understand their thinking....
    70256: 04/06/10: Austin Lesea: Re: Virtex4: I don't understand their thinking....
    70257: 04/06/10: Phil Hays: Re: Virtex4: I don't understand their thinking....
    70276: 04/06/10: Stifler: Re: Virtex4: I don't understand their thinking....
        70293: 04/06/11: John_H: Re: Virtex4: I don't understand their thinking....
70253: 04/06/10: raj: Reading Back Configuration of Slice/LUT
70260: 04/06/10: Arturo Rios: Cores into fpga
    70261: 04/06/10: Symon: Re: Cores into fpga
    70266: 04/06/11: Michal HUSEJKO: Re: Cores into fpga
    70323: 04/06/12: Pete: Re: Cores into fpga
    70340: 04/06/13: INS122595: Re: Cores into fpga
70262: 04/06/10: Chao: How to obtain original input/output signal name from SDF Timing Simulation within Modelsim?
    70300: 04/06/11: Mike Treseler: Re: How to obtain original input/output signal name from SDF Timing Simulation within Modelsim?
        70348: 04/06/14: ALuPin: Re: How to obtain original input/output signal name from SDF Timing Simulation within Modelsim?
        70353: 04/06/14: Chao: Re: How to obtain original input/output signal name from SDF Timing Simulation within Modelsim?
            70358: 04/06/14: Mike Treseler: Re: How to obtain original input/output signal name from SDF Timing
70263: 04/06/10: Christopher Red: run-time management of logic resources
70264: 04/06/11: Martin Maurer: Avoid action on very short peak on input signal (Xilinx Spartan 2)
    70265: 04/06/11: =?iso-8859-1?Q?Michael_Sch=F6berl?=: Re: Avoid action on very short peak on input signal (Xilinx Spartan 2)
    70274: 04/06/10: Mike Treseler: Re: Avoid action on very short peak on input signal (Xilinx Spartan 2)
    70275: 04/06/11: Jim Granville: Re: Avoid action on very short peak on input signal (Xilinx Spartan
    70307: 04/06/11: Eric Crabill: Re: Avoid action on very short peak on input signal (Xilinx Spartan 2)
70269: 04/06/10: Raven76: Xilinx Floorplanner
70282: 04/06/11: Timo Dammes: example designs for Xilinx System Generator ?
    70298: 04/06/11: Elliot Schei: Re: example designs for Xilinx System Generator ?
70283: 04/06/11: sebastian: Xilinx: infering dual port ROM in VHDL
    70285: 04/06/11: John Adair: Re: Xilinx: infering dual port ROM in VHDL
    70287: 04/06/11: Ray Andraka: Re: Xilinx: infering dual port ROM in VHDL
70284: 04/06/11: gvaglia: Xilinx Coregen
70286: 04/06/11: Edward: Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5
    70303: 04/06/11: Mike Treseler: Re: Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5
    70304: 04/06/11: Jesse Kempa: Re: Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5
        70338: 04/06/13: Edward: Re: Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5
            70432: 04/06/16: Jesse Kempa: Re: Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5
70288: 04/06/11: Yang-Tzu: Problems about Using Xilinx Command Line !
    70308: 04/06/11: Eric Crabill: Re: Problems about Using Xilinx Command Line !
        70334: 04/06/12: Yang-Tzu: Re: Problems about Using Xilinx Command Line !
70289: 04/06/11: Andrea Sabatini: Microblaze asm and C shared variables
    70344: 04/06/13: Matthew Ouellette: Re: Microblaze asm and C shared variables
        70351: 04/06/14: Andrea Sabatini: Re: Microblaze asm and C shared variables
            70367: 04/06/14: roller: Re: Microblaze asm and C shared variables
70290: 04/06/11: Yttrium: Xilinx System Generator problem: ERROR:NgdBuild:604
    70301: 04/06/11: Chris Arndt: Re: Xilinx System Generator problem: ERROR:NgdBuild:604
70306: 04/06/11: Stephen Williams: Xilinx ParallelCable IV vs. Linux
    70309: 04/06/11: Neil Glenn Jacobson: Re: Xilinx Parallel Cable IV vs. Linux
        70310: 04/06/11: Stephen Williams: Re: Xilinx Parallel Cable IV vs. Linux
            70312: 04/06/11: Neil Glenn Jacobson: Re: Xilinx Parallel Cable IV vs. Linux
            70313: 04/06/11: Neil Glenn Jacobson: Re: Xilinx Parallel Cable IV vs. Linux
                70315: 04/06/11: Stephen Williams: Re: Xilinx Parallel Cable IV vs. Linux
                    70365: 04/06/14: Neil Glenn Jacobson: Re: Xilinx Parallel Cable IV vs. Linux
                        70374: 04/06/14: Stephen Williams: Re: Xilinx Parallel Cable IV vs. Linux
                            70408: 04/06/15: Neil Glenn Jacobson: Re: Xilinx Parallel Cable IV vs. Linux
                                70434: 04/06/16: Stephen Williams: Re: Xilinx Parallel Cable IV vs. Linux
                                    70593: 04/06/21: Neil Glenn Jacobson: Re: Xilinx Parallel Cable IV vs. Linux
                                    70596: 04/06/21: Neil Glenn Jacobson: Re: Xilinx Parallel Cable IV vs. Linux
                                        70699: 04/06/23: Sietse Achterop: Re: Xilinx Parallel Cable IV vs. Linux
    70319: 04/06/11: General Schvantzkoph: Re: Xilinx ParallelCable IV vs. Linux
        70326: 04/06/12: Stephen Williams: Re: Xilinx ParallelCable IV vs. Linux
    70443: 04/06/17: Rudolf Usselmann: Re: Xilinx ParallelCable IV vs. Linux
        70460: 04/06/17: Jan Panteltje: Re: Xilinx ParallelCable IV vs. Linux
            70470: 04/06/17: Uwe Bonnes: Re: Xilinx ParallelCable IV vs. Linux
                70473: 04/06/17: Jan Panteltje: Re: Xilinx ParallelCable IV vs. Linux
        72212: 04/08/11: Phil Tomson: Re: Xilinx ParallelCable IV vs. Linux
            72224: 04/08/11: Sietse Achterop: Re: Xilinx ParallelCable IV vs. Linux
    70444: 04/06/17: Philip Freidin: Re: Xilinx ParallelCable IV vs. Linux
        70463: 04/06/17: Jan Panteltje: Re: Xilinx ParallelCable IV vs. Linux
70314: 04/06/11: makmorbi: Low Power FPGA Design Seminar
70316: 04/06/12: Frank Benoit: Costs of IPs
    70317: 04/06/11: Symon: Re: Costs of IPs
        70318: 04/06/12: Frank Benoit: Re: Costs of IPs
            70324: 04/06/12: Jon Beniston: Re: Costs of IPs
                70331: 04/06/13: Frank Benoit: Re: Costs of IPs
                    70343: 04/06/13: Antti Lukats: Re: Costs of IPs
    70328: 04/06/12: Antti Lukats: Re: Costs of IPs
        70350: 04/06/14: Martin Thompson: Re: Costs of IPs
    70330: 04/06/12: Rene Tschaggelar: Re: Costs of IPs
70325: 04/06/12: Edward: Megawizard Plugin and SDRAM controller
70329: 04/06/12: rickman: RAM in Altera EABs and Xilinx Block Rams
    70363: 04/06/14: Rajeev: Re: RAM in Altera EABs and Xilinx Block Rams
        70445: 04/06/17: rickman: Re: RAM in Altera EABs and Xilinx Block Rams
    70366: 04/06/14: roller: Re: RAM in Altera EABs and Xilinx Block Rams
        70368: 04/06/14: Peter Alfke: Re: RAM in Altera EABs and Xilinx Block Rams
            70447: 04/06/17: rickman: Re: RAM in Altera EABs and Xilinx Block Rams
                70724: 04/06/24: Ray Andraka: Re: RAM in Altera EABs and Xilinx Block Rams
                    70729: 04/06/24: rickman: Re: RAM in Altera EABs and Xilinx Block Rams
        70446: 04/06/17: rickman: Re: RAM in Altera EABs and Xilinx Block Rams
    70369: 04/06/14: Symon: Re: RAM in Altera EABs and Xilinx Block Rams
        70370: 04/06/14: Peter Alfke: Re: RAM in Altera EABs and Xilinx Block Rams
            70372: 04/06/14: John_H: Re: RAM in Altera EABs and Xilinx Block Rams
                70449: 04/06/17: rickman: Re: RAM in Altera EABs and Xilinx Block Rams
                    70469: 04/06/17: Peter Alfke: Re: RAM in Altera EABs and Xilinx Block Rams
                        70598: 04/06/21: rickman: Re: RAM in Altera EABs and Xilinx Block Rams
                            70600: 04/06/21: John_H: Re: RAM in Altera EABs and Xilinx Block Rams
                                70603: 04/06/21: rickman: Re: RAM in Altera EABs and Xilinx Block Rams
                                    70642: 04/06/22: Symon: Re: RAM in Altera EABs and Xilinx Block Rams
                            70632: 04/06/22: Peter Alfke: Re: RAM in Altera EABs and Xilinx Block Rams
                                70641: 04/06/22: rickman: Re: RAM in Altera EABs and Xilinx Block Rams
                                    70646: 04/06/22: Peter Alfke: Re: RAM in Altera EABs and Xilinx Block Rams
        70448: 04/06/17: rickman: Re: RAM in Altera EABs and Xilinx Block Rams
    70371: 04/06/15: roller: Re: RAM in Altera EABs and Xilinx Block Rams
70335: 04/06/13: charles: a newbie question
    70337: 04/06/13: Jon Beniston: Re: a newbie question
        70339: 04/06/13: charles: Re: a newbie question
            70346: 04/06/14: Kelvin @ SG: Re: a newbie question
            70347: 04/06/13: Mike Treseler: Re: a newbie question
                70414: 04/06/16: charles: Re: a newbie question
                    70426: 04/06/16: Symon: Re: a newbie question
                    70758: 04/06/26: Mike Treseler: Re: a newbie question
            72905: 04/09/07: glen herrmannsfeldt: Re: a newbie question
70336: 04/06/13: Yang-Tzu: Xilinx .bit to .svf...
    70341: 04/06/13: Shalin Sheth: Re: Xilinx .bit to .svf...
    70342: 04/06/13: ram: Re: Xilinx .bit to .svf...
    70360: 04/06/14: Neil Glenn Jacobson: Re: Xilinx .bit to .svf...
        70455: 04/06/17: Yang-Tzu: Re: Xilinx .bit to .svf...
70345: 04/06/14: Kelvin @ SG: Design Compiler, how do I use a derating library...
70352: 04/06/14: Thierry Gschwind: Several Problems with Spartan2 Configuration
    70362: 04/06/14: Thierry Gschwind: Re: Several Problems with Spartan2 Configuration
        70379: 04/06/15: Simon Peacock: Re: Several Problems with Spartan2 Configuration
            70382: 04/06/15: Jens Hildebrandt: Re: Several Problems with Spartan2 Configuration
        70456: 04/06/17: Nial Stewart: Re: Several Problems with Spartan2 Configuration
            70471: 04/06/17: Thierry Gschwind: Re: Several Problems with Spartan2 Configuration
70357: 04/06/14: John Adair: Free Seminar
    72298: 04/08/13: pippo: Re: Free Seminar
70359: 04/06/14: Jan Panteltje: 90nm Xilinx FPGA?
70361: 04/06/14: Brijesh: FPGA serial programming troubles. (Virtex II)
    70364: 04/06/14: Peter Alfke: Re: FPGA serial programming troubles. (Virtex II)
        70397: 04/06/15: Brijesh: Re: FPGA serial programming troubles. (Virtex II)
            70401: 04/06/15: Peter Alfke: Re: FPGA serial programming troubles. (Virtex II)
70373: 04/06/14: Rajeev: Stratix DSP Block: Choosing which FFs are enabled
    70404: 04/06/15: Subroto Datta: Re: Stratix DSP Block: Choosing which FFs are enabled
        70422: 04/06/16: Rajeev: Re: Stratix DSP Block: Choosing which FFs are enabled
70375: 04/06/14: Paul K: Atmel WinCupl
    70377: 04/06/15: Jim Granville: Re: Atmel WinCupl
    70385: 04/06/15: Mike Harrison: Re: Atmel WinCupl
        70406: 04/06/15: Paul K: Re: Atmel WinCupl
            70499: 04/06/17: Paul K: Re: Atmel WinCupl
70376: 04/06/15: <user@domain.invalid>: >Math Skills = >Engineer ?
    70378: 04/06/15: Simon Peacock: Re: >Math Skills = >Engineer ?
    70380: 04/06/15: Nicolas Matringe: Re: >Math Skills = >Engineer ?
    70381: 04/06/15: Kelvin: Re: >Math Skills = >Engineer ?
        70383: 04/06/15: David Brown: Re: >Math Skills = >Engineer ?
            70387: 04/06/15: Kelvin: Re: >Math Skills = >Engineer ?
                70391: 04/06/15: David Brown: Re: >Math Skills = >Engineer ?
                70398: 04/06/15: Uwe Bonnes: Re: >Math Skills = >Engineer ?
            70411: 04/06/15: Hendra Gunawan: Re: >Math Skills = >Engineer ?
                70419: 04/06/16: Simon Peacock: Re: >Math Skills = >Engineer ?
                    70428: 04/06/16: glen herrmannsfeldt: Re: >Math Skills = >Engineer ?
                70507: 04/06/18: jtw: Re: >Math Skills = >Engineer ?
                70565: 04/06/20: Thomas Stanka: Re: >Math Skills = >Engineer ?
    70396: 04/06/15: thangkho: Re: >Math Skills = >Engineer ?
    70427: 04/06/16: Brannon King: Re: >Math Skills = >Engineer ?
        70581: 04/06/21: john jakson: Re: >Math Skills = >Engineer ?
    70534: 04/06/19: Victor Schutte: Re: >Math Skills = >Engineer ?
70384: 04/06/15: ALuPin: Content of RAM
70386: 04/06/15: Paulo Valentim: Altera CLKLK_FB use when OPERATION_MODE=NORMAL
    70425: 04/06/16: Paulo Valentim: Re: Altera CLKLK_FB use when OPERATION_MODE=NORMAL
70388: 04/06/15: ALuPin: Library Mapping
70389: 04/06/15: Frank Benoit: Starter Kit for Linux in Virtex?
70390: 04/06/15: krebs: how to connect my IP-Core to Microblaze in EDK and ISE with IPIF
    90748: 05/10/20: moleo: Re: how to connect my IP-Core to Microblaze in EDK and ISE with IPIF
70392: 04/06/15: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: pulse generation using SRL16E on a Virtex-II
    70393: 04/06/15: Michael Rhotert: Re: pulse generation using SRL16E on a Virtex-II
    70394: 04/06/15: Goran Bilski: Re: pulse generation using SRL16E on a Virtex-II
    70395: 04/06/15: Goran Bilski: Re: pulse generation using SRL16E on a Virtex-II
        70402: 04/06/15: Antonio Pasini: Re: pulse generation using SRL16E on a Virtex-II
            70403: 04/06/15: Goran Bilski: Re: pulse generation using SRL16E on a Virtex-II
                70405: 04/06/15: Symon: Re: pulse generation using SRL16E on a Virtex-II
                    70409: 04/06/16: Jim Granville: Re: pulse generation using SRL16E on a Virtex-II
                    70413: 04/06/16: Philip Freidin: Re: pulse generation using SRL16E on a Virtex-II
                    70418: 04/06/16: Goran Bilski: Re: pulse generation using SRL16E on a Virtex-II
                    70572: 04/06/21: Yttrium: Re: pulse generation using SRL16E on a Virtex-II
    70585: 04/06/21: Brian Philofsky: Re: pulse generation using SRL16E on a Virtex-II
70399: 04/06/15: Justin: Using Altera libraries for Nios Dev Board
    70400: 04/06/15: Hal Murray: Re: Using Altera libraries for Nios Dev Board
    70429: 04/06/16: Jesse Kempa: Re: Using Altera libraries for Nios Dev Board
70407: 04/06/16: Jim Granville: Progress in FPGA static Icc timeline degrade
70410: 04/06/15: Matthew E Rosenthal: length of parallel cable attached to P IV xilinx jtag cable
    70412: 04/06/15: Matthew E Rosenthal: Re: length of parallel cable attached to P IV xilinx jtag cable
70415: 04/06/16: charles: importing a design from maxplus2 to quartus II ver 3
    70417: 04/06/16: Subroto Datta: Re: importing a design from maxplus2 to quartus II ver 3
70416: 04/06/15: Ted: C Header files for User Design Logic in the Nios.
    70430: 04/06/16: Jesse Kempa: Re: C Header files for User Design Logic in the Nios.
        70453: 04/06/17: Hal Murray: Re: C Header files for User Design Logic in the Nios.
            70476: 04/06/17: Ted: Re: C Header files for User Design Logic in the Nios.
            70477: 04/06/17: Ted: Re: C Header files for User Design Logic in the Nios.
                70527: 04/06/18: Ted: Re: C Header files for User Design Logic in the Nios.
    70586: 04/06/21: Aaron Ferrucci: Re: C Header files for User Design Logic in the Nios.
        70672: 04/06/23: Ted: Re: C Header files for User Design Logic in the Nios.
            70700: 04/06/23: Aaron Ferrucci: Re: C Header files for User Design Logic in the Nios.
70420: 04/06/16: prav: MGT pin details(Xilinx Virtex 2 PRO)
    70421: 04/06/16: Allan Herriman: Re: MGT pin details(Xilinx Virtex 2 PRO)
        70442: 04/06/17: Andrew Dyer: Re: MGT pin details(Xilinx Virtex 2 PRO)
70423: 04/06/16: salman sheikh: Suse 9.1 Linux and Xilinx ISE 6.2i
    70437: 04/06/16: Stephen Williams: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
    70478: 04/06/17: Duane Clark: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
        70484: 04/06/17: Marc Kelly: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
            70504: 04/06/17: Hal Murray: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
            70518: 04/06/18: Uwe Bonnes: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
                70587: 04/06/21: Brian Philofsky: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
                    70611: 04/06/22: Hal Murray: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
                        70627: 04/06/22: Brian Philofsky: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
                    70623: 04/06/22: Martin Thompson: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
                        70647: 04/06/22: Brian Philofsky: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
                            70671: 04/06/23: Martin Thompson: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
                                70673: 04/06/23: Allan Herriman: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
                                    70708: 04/06/24: Martin Thompson: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
                                        70710: 04/06/24: Allan Herriman: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
                                70689: 04/06/23: Brian Philofsky: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
                                    70709: 04/06/24: Martin Thompson: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
    70482: 04/06/17: Jon Elson: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
    70500: 04/06/17: General Schvantzkoph: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
        70506: 04/06/18: Tom Dillon: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
            70594: 04/06/21: Duane Clark: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
    70961: 04/07/02: Victor Atkinson: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
        70964: 04/07/02: Brian Philofsky: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70424: 04/06/16: zhangdidi: example for excalibur epxa1
70431: 04/06/16: (beta-) Frank Nitzsche: XCS10-84PC: How JTAG-Pins as I/O ?
    70435: 04/06/16: Steven K. Knapp: Re: XCS10-84PC: How JTAG-Pins as I/O ?
    70436: 04/06/16: Philip Freidin: Re: XCS10-84PC: How JTAG-Pins as I/O ?
70433: 04/06/16: Pszemol: Many UARTs on Avalon bus with NIOS cpu
70438: 04/06/16: tom: help for finding a company which can provide FPGA based PCI board with ethernet port
    70441: 04/06/17: Philip Freidin: Re: help for finding a company which can provide FPGA based PCI board with ethernet port
    70452: 04/06/17: buli: Re: help for finding a company which can provide FPGA based PCI board with ethernet port
    70454: 04/06/17: John Adair: Re: help for finding a company which can provide FPGA based PCI board with ethernet port
70439: 04/06/17: Doug Miller: Xilinx RAM64x1D simulation problems
    70440: 04/06/17: Doug Miller: Re: Xilinx RAM64x1D simulation problems
70450: 04/06/17: Ravi Sankar K.: Synplify_pro
    70468: 04/06/17: John_H: Re: Synplify_pro
70457: 04/06/17: <sanpab@eis.uva.es>: Is there a verilog version of PicoBlaze?
    70458: 04/06/17: Allan Herriman: Re: Is there a verilog version of PicoBlaze?
        70462: 04/06/17: INS122595: Re: Is there a verilog version of PicoBlaze?
            70465: 04/06/18: Allan Herriman: Re: Is there a verilog version of PicoBlaze?
                70466: 04/06/17: Shalin Sheth: Re: Is there a verilog version of PicoBlaze?
                    70467: 04/06/18: Allan Herriman: Re: Is there a verilog version of PicoBlaze?
                        70497: 04/06/17: Steven K. Knapp: Re: Is there a verilog version of PicoBlaze?
                            70503: 04/06/18: Allan Herriman: Re: Is there a verilog version of PicoBlaze?
                                70514: 04/06/18: Henk van Kampen: Re: Is there a verilog version of PicoBlaze?
                                    70515: 04/06/18: Allan Herriman: Re: Is there a verilog version of PicoBlaze?
                                        70526: 04/06/18: Henk van Kampen: Re: Is there a verilog version of PicoBlaze?
                                            70561: 04/06/21: Allan Herriman: Re: Is there a verilog version of PicoBlaze?
                                                70590: 04/06/21: Brian Philofsky: Re: Is there a verilog version of PicoBlaze?
                                                70602: 04/06/21: Ray Andraka: Re: Is there a verilog version of PicoBlaze?
    70464: 04/06/17: Steven K. Knapp: Re: Is there a verilog version of PicoBlaze?
70459: 04/06/17: ALuPin: Altera unable to respond
70461: 04/06/17: vadim: Quartus II - Disabling the Optimizer to use gate delay
    70479: 04/06/17: Subroto Datta: Re: Quartus II - Disabling the Optimizer to use gate delay
    70486: 04/06/17: Peter Sommerfeld: Re: Quartus II - Disabling the Optimizer to use gate delay
    70487: 04/06/17: Peter Sommerfeld: Re: Quartus II - Disabling the Optimizer to use gate delay
70472: 04/06/17: Spartan Ray: VHDL code for EPP parallel port with xc2s200-pq208
70474: 04/06/17: <sanpab@eis.uva.es>: How to create an EDIF file from ISE Foundation?
    70512: 04/06/18: Michael Rhotert: Re: How to create an EDIF file from ISE Foundation?
        70521: 04/06/18: Brannon King: Re: How to create an EDIF file from ISE Foundation?
        70570: 04/06/21: <sanpab@eis.uva.es>: Re: How to create an EDIF file from ISE Foundation?
70475: 04/06/17: Amontec, Laurent Gauch: SPARTAN-IIE -> LVCMOS18
    70480: 04/06/17: Mark Ng: Re: SPARTAN-IIE -> LVCMOS18
        70481: 04/06/17: Amontec, Laurent Gauch: Re: SPARTAN-IIE -> LVCMOS18
70483: 04/06/17: Matt Dykes: Xilinx XST synthesis removes input pin even though it's LOCed
    70510: 04/06/18: John Adair: Re: Xilinx XST synthesis removes input pin even though it's LOCed
    70519: 04/06/18: Alvin Andries: Re: Xilinx XST synthesis removes input pin even though it's LOCed
        70541: 04/06/19: Frank Benoit: Re: Xilinx XST synthesis removes input pin even though it's LOCed
            70576: 04/06/21: Matt Dykes: Re: Xilinx XST synthesis removes input pin even though it's LOCed
                70615: 04/06/22: John Adair: Re: Xilinx XST synthesis removes input pin even though it's LOCed
70485: 04/06/17: John Larkin: compressing Xilinx bitstreams
    70488: 04/06/18: Jim Granville: Re: compressing Xilinx bitstreams
        70511: 04/06/18: Kolja Sulimma: Re: compressing Xilinx bitstreams
            70513: 04/06/18: Jim Granville: Re: compressing Xilinx bitstreams
    70489: 04/06/17: Clark Pope: Re: compressing Xilinx bitstreams
        70505: 04/06/18: Allan Herriman: Re: compressing Xilinx bitstreams
    70490: 04/06/17: Austin Lesea: Re: compressing Xilinx bitstreams
        70492: 04/06/18: Jim Granville: Re: compressing Xilinx bitstreams
    70491: 04/06/17: John_H: Re: compressing Xilinx bitstreams
        70495: 04/06/17: John Larkin: Re: compressing Xilinx bitstreams
    70493: 04/06/17: Steve Casselman: Re: compressing Xilinx bitstreams
    70494: 04/06/17: Tim Wescott: Re: compressing Xilinx bitstreams
    70496: 04/06/17: Greg Neff: Re: compressing Xilinx bitstreams
    70501: 04/06/18: Paul Leventis (at home): Re: compressing Xilinx bitstreams
        70502: 04/06/18: Jim Granville: Re: compressing Xilinx bitstreams
    70529: 04/06/18: Neil Glenn Jacobson: Re: compressing Xilinx bitstreams
        70531: 04/06/19: Antonio Pasini: Re: compressing Xilinx bitstreams, some test data
            70540: 04/06/19: Frank Benoit: Re: compressing Xilinx bitstreams, some test data
    70533: 04/06/19: roller: Re: compressing Xilinx bitstreams
    70535: 04/06/19: Nico Coesel: Re: compressing Xilinx bitstreams
        70536: 04/06/19: John Larkin: Re: compressing Xilinx bitstreams
            70537: 04/06/19: Nico Coesel: Re: compressing Xilinx bitstreams
                70538: 04/06/19: Tim: Re: compressing Xilinx bitstreams
                    70542: 04/06/19: Nico Coesel: Re: compressing Xilinx bitstreams
                70546: 04/06/20: Zak: Re: compressing Xilinx bitstreams
                    70557: 04/06/20: Nico Coesel: Re: compressing Xilinx bitstreams
                70550: 04/06/20: John Larkin: Re: compressing Xilinx bitstreams
                70574: 04/06/21: Kolja Sulimma: Re: compressing Xilinx bitstreams
    70599: 04/06/21: rickman: Re: compressing Xilinx bitstreams
70498: 04/06/17: Jake Janovetz: IOBs in NGC - problem with OBUFT
    70522: 04/06/18: Brannon King: Re: IOBs in NGC - problem with OBUFT
        70548: 04/06/20: Jake Janovetz: Re: IOBs in NGC - problem with OBUFT
            70597: 04/06/21: Paulo Dutra: Re: IOBs in NGC - problem with OBUFT
                70635: 04/06/22: Jake Janovetz: Re: IOBs in NGC - problem with OBUFT
    71666: 04/07/27: Joko: Re: IOBs in NGC - problem with OBUFT
        71677: 04/07/27: Brian Philofsky: Re: IOBs in NGC - problem with OBUFT
70508: 04/06/18: Peter Monta: Linux on Xilinx v2pro: OCM access?
    70520: 04/06/18: Peter Ryser: Re: Linux on Xilinx v2pro: OCM access?
        70528: 04/06/18: Peter Monta: Re: Linux on Xilinx v2pro: OCM access?
70509: 04/06/18: qianeasy: Re: TCP/IP in Virtex II Pro
    70525: 04/06/18: Matthew Ouellette: Re: TCP/IP in Virtex II Pro
70516: 04/06/18: David Brown: Nios II and eCos
    70664: 04/06/23: Andrew Dyer: Re: Nios II and eCos
    70883: 04/06/30: Mustafa: Re: Nios II and eCos
70517: 04/06/18: lc: CPLD mistery. Help.
    70532: 04/06/19: Fabio G.: Re: CPLD mistery. Help.
    70544: 04/06/20: Jim Granville: Re: CPLD mistery. Help.
    70545: 04/06/19: Ashish Kapoor: Re: CPLD mistery. Help.
    70573: 04/06/21: lc: Re: CPLD mistery. Help.... reHelp.
        70608: 04/06/21: Hal Murray: Re: CPLD mistery. Help.... reHelp.
        70620: 04/06/22: Peter Hermansson: Re: CPLD mistery. Help.... reHelp.
    70575: 04/06/21: lc: Re: CPLD mistery. Help. The resulting equations.
    70621: 04/06/22: lc: Re: CPLD mistery. Problem Found... and is an interesting one !
        70651: 04/06/23: Jim Granville: Re: CPLD mistery. Problem Found... and is an interesting one !
70523: 04/06/18: Sohaib Majzoub: Virtex II : partial reconf, bus macro
70524: 04/06/18: rajendra: Programming FPGA in Xilinx Virtex 2 pro board
70530: 04/06/18: prav: scatter gather DMA in OPB MAC core
    70539: 04/06/19: Stan Lackey: Re: scatter gather DMA in OPB MAC core
70543: 04/06/20: (beta-) Frank Nitzsche: Newbie: Spartan XCS10
70547: 04/06/20: Miika Pekkarinen: Altera Quartus II on Linux
    70552: 04/06/20: Subroto Datta: Re: Altera Quartus II on Linux
    70637: 04/06/22: Uwe Bonnes: Re: Altera Quartus II on Linux
70549: 04/06/20: Gregg C Levine: Is the Xilinix XC3020 atill supported?
    70551: 04/06/20: General Schvantzkoph: Re: Is the Xilinix XC3020 atill supported?
        70555: 04/06/20: Gregg C Levine: Re: Is the Xilinix XC3020 atill supported?
            71222: 04/07/12: Tom Seim: Re: Is the Xilinix XC3020 atill supported?
                71223: 04/07/12: Peter Alfke: Re: Is the Xilinix XC3020 atill supported?
                    71418: 04/07/18: glen herrmannsfeldt: Re: Is the Xilinix XC3020 atill supported?
        70589: 04/06/21: Peter Alfke: Re: Is the Xilinix XC3020 atill supported?
        70654: 04/06/22: Marlboro: Re: Is the Xilinix XC3020 atill supported?
            71194: 04/07/11: Thales Belchior: Re: Is the Xilinix XC3020 atill supported?
                71214: 04/07/12: Austin Lesea: Re: Is the Xilinix XC3020 atill supported?
70553: 04/06/20: Acciduzzu: XST: Inferring dual-port RAM from VHDL with BlockRAM
    70560: 04/06/21: Phil Hays: Re: XST: Inferring dual-port RAM from VHDL with BlockRAM
        70566: 04/06/21: Acciduzzu: Re: XST: Inferring dual-port RAM from VHDL with BlockRAM
            70592: 04/06/21: Brian Philofsky: Re: XST: Inferring dual-port RAM from VHDL with BlockRAM
                70612: 04/06/22: Acciduzzu: Re: XST: Inferring dual-port RAM from VHDL with BlockRAM
    70584: 04/06/21: John_H: Re: Inferring dual-port RAM from VHDL with BlockRAM
    70591: 04/06/21: Peter Alfke: Re: XST: Inferring dual-port RAM from VHDL with BlockRAM
70554: 04/06/20: anon: Atmel / Synplicity built-in macros
70556: 04/06/20: Richard Cooke: 8 ch countdown timer - doable in a CPLD?
    70558: 04/06/21: John Retta: Re: 8 ch countdown timer - doable in a CPLD?
70559: 04/06/20: flo: XC4010XL : parallel port access through data pin
70562: 04/06/21: Jimmy: VDHL implementation of RAM with serial input and parallel outpout ? thx
    70563: 04/06/21: Jerome: Re: VDHL implementation of RAM with serial input and parallel outpout ? thx
    70564: 04/06/21: =?iso-8859-15?Q?Michael_Sch=F6berl?=: Re: VDHL implementation of RAM with serial input and parallel outpout ? thx
70567: 04/06/21: wei ming: readback on Virtex2 , anybody help me!
70568: 04/06/21: Naimesh: Spartan: How to select device as Spartan/SpartanXL
70569: 04/06/21: karthik: Interface Bidir IO datalines to dualport RAM within FPGA - URGENT
    70601: 04/06/21: Paulo Dutra: Re: Interface Bidir IO datalines to dualport RAM within FPGA - URGENT
70571: 04/06/21: Naimesh: Spartan/SpartanXL Device Selection
    70578: 04/06/21: Greg Neff: Re: Spartan/SpartanXL Device Selection
        70595: 04/06/21: Brian Philofsky: Re: Spartan/SpartanXL Device Selection
    70582: 04/06/21: John_H: Re: Spartan/SpartanXL Device Selection
        70607: 04/06/21: Naimesh: Re: Spartan/SpartanXL Device Selection
            70628: 04/06/22: John_H: Re: Spartan/SpartanXL Device Selection
                70810: 04/06/28: Naimesh: Re: Spartan/SpartanXL Device Selection
70577: 04/06/21: andrew<AT>rogerstech<DOT>co<DOT>uk: Linux.
    70580: 04/06/21: David Brown: Re: Linux.
    70624: 04/06/22: Larry Doolittle: Re: Linux.
        71011: 04/07/05: Edwin Bland: Re: Linux.
            71012: 04/07/05: Uwe Bonnes: Re: Linux.
70583: 04/06/21: John_H: Re: 8 ch countdown timer - doable in a CPLD?
70604: 04/06/21: Phil Moore: New: read/write to D2SB fpga
    70618: 04/06/22: Joerg Ritter: Re: New: read/write to D2SB fpga
        70650: 04/06/22: Phil Moore: Re: New: read/write to D2SB fpga
            70683: 04/06/23: Joerg Ritter: Re: New: read/write to D2SB fpga
70605: 04/06/21: Phil Moore: Exponential Function
    70701: 04/06/23: Ray Andraka: Re: Exponential Function
70606: 04/06/21: Phil Moore: Neural Network on fpga
70609: 04/06/22: rickman: Initializing data in EAB ram
    70649: 04/06/22: Rajeev: Re: Initializing data in EAB ram
70610: 04/06/21: mamtachalana: system verilog
    70626: 04/06/22: john jakson: Re: system verilog
70613: 04/06/22: Oleg Slonsky: JTAG - XC2S200E-PQ208
    70617: 04/06/22: Amontec Team: Re: JTAG - XC2S200E-PQ208
    70619: 04/06/22: Jan Panteltje: Re: JTAG - XC2S200E-PQ208
    70629: 04/06/22: Shalin Sheth: Re: JTAG - XC2S200E-PQ208
    70645: 04/06/22: Antti Lukats: Re: JTAG - XC2S200E-PQ208
70614: 04/06/22: ALuPin: Unused signals in Modelsim
    70622: 04/06/22: jtw: Re: Unused signals in Modelsim
    70634: 04/06/22: Jon Beniston: Re: Unused signals in Modelsim
70616: 04/06/22: ALuPin: Synthesis of loops
    70625: 04/06/22: Thierry Gschwind: Re: Synthesis of loops
70630: 04/06/22: D: ROM instantiation question
    70633: 04/06/22: Brian Philofsky: Re: ROM instantiation question
        70655: 04/06/22: D: Re: ROM instantiation question
70631: 04/06/22: chuk: VIRTEX v Spartan 3
    70636: 04/06/22: Austin Lesea: Family Photo Album
        70639: 04/06/22: Symon: Re: Family Photo Album
            70644: 04/06/22: Austin Lesea: Re: Family Photo Album
                70652: 04/06/23: Jim Granville: Re: Family Photo Album
                    70657: 04/06/22: Austin Lesea: Re: Family Photo Album
                        70658: 04/06/23: Jim Granville: Re: Family Photo Album
                            70669: 04/06/23: Uwe Bonnes: Re: Family Photo Album
                            70685: 04/06/23: Austin Lesea: Re: Family Photo Album
                                70693: 04/06/23: Symon: Re: Family Photo Album
                                70793: 04/06/28: rickman: Re: Family Photo Album
                                    70797: 04/06/28: Austin Lesea: Re: Family Photo Album
                                        70800: 04/06/28: Austin Lesea: Re: Family Photo Album
                                            70803: 04/06/28: Symon: Re: Family Photo Album
                                                70820: 04/06/29: Austin Lesea: Re: Family Photo Album
                                                70823: 04/06/29: Steven K. Knapp: Re: Family Photo Album
                                            70807: 04/06/29: Jim Granville: Re: Family Photo Album
                                                70821: 04/06/29: Austin Lesea: Re: Family Photo Album
                                                70824: 04/06/29: Steven K. Knapp: Re: Family Photo Album
                                        70830: 04/06/29: glen herrmannsfeldt: Re: Family Photo Album
                                            70831: 04/06/29: Austin Lesea: Re: Family Photo Album
                70761: 04/06/26: Finn S. Nielsen: Re: Family Photo Album
                    70788: 04/06/28: Austin Lesea: Re: Family Photo Album
        70648: 04/06/22: Ray Andraka: Re: Family Photo Album
    70638: 04/06/22: Ray Andraka: Re: VIRTEX v Spartan 3
70640: 04/06/22: Repzak: Newbie Q
    70643: 04/06/22: Repzak: Re: Newbie Q
    70662: 04/06/22: Ashish Kapoor: Re: Newbie Q
    70899: 04/07/01: Jose Antonio: Re: Newbie Q
70653: 04/06/22: rickman: Trying to remember how to use Quartus
    70674: 04/06/23: Rajeev: Re: Trying to remember how to use Quartus
    70679: 04/06/23: Subroto Datta: Re: Trying to remember how to use Quartus
        70686: 04/06/23: rickman: Re: Trying to remember how to use Quartus
            70703: 04/06/23: Mike Treseler: Re: Trying to remember how to use Quartus
                70712: 04/06/24: Subroto Datta: Re: Trying to remember how to use Quartus
                70721: 04/06/24: rickman: Re: Trying to remember how to use Quartus
70656: 04/06/23: www.amontec.com: ANN: Low cost & high speed JTAG interface
70659: 04/06/23: MikeJ: Asteroids Deluxe in an FPGA
    70665: 04/06/23: phil: Re: Asteroids Deluxe in an FPGA
    70666: 04/06/23: Mark (UK): Re: Asteroids Deluxe in an FPGA
        70705: 04/06/24: Ulrich Kloidt: Re: Asteroids Deluxe in an FPGA
            70717: 04/06/24: Mark (UK): Re: Asteroids Deluxe in an FPGA
70660: 04/06/22: Paulo Dutra: Re: EDK 6.2 ISE verilog toplevel possible ?
    70692: 04/06/23: Antti Lukats: Re: EDK 6.2 ISE verilog toplevel possible ?
        70697: 04/06/23: Amit Kasat: Re: EDK 6.2 ISE verilog toplevel possible ?
            70702: 04/06/23: Antti Lukats: Re: EDK 6.2 ISE verilog toplevel possible ?
    70838: 04/06/29: Antti Lukats: Re: EDK 6.2 ISE verilog toplevel possible ?
70661: 04/06/22: Antti Lukats: EDK 6.2 ISE verilog toplevel possible ?
70663: 04/06/22: Andy: Division in Xilinx
    70680: 04/06/23: Jon Beniston: Re: Division in Xilinx
        70698: 04/06/23: Symon: Re: Division in Xilinx
            70783: 04/06/28: Jonas Floden: Re: Division in Xilinx
    70690: 04/06/23: John_H: Re: Division in Xilinx
    71102: 04/07/08: Kelvin: Re: Division in Xilinx
70667: 04/06/23: Jonas Floden: Problems with a Virtex-II Engineering Sample
    70670: 04/06/23: Goran Bilski: Re: Problems with a Virtex-II Engineering Sample
        70675: 04/06/23: Jonas Floden: Re: Problems with a Virtex-II Engineering Sample
        70676: 04/06/23: wa11: Virtex II slave selectMap config mode
    70696: 04/06/23: Amit Kasat: Re: Problems with a Virtex-II Engineering Sample
        70706: 04/06/24: Jonas Floden: Re: Problems with a Virtex-II Engineering Sample
    70962: 04/07/02: Zach Pfeffer: Re: Problems with a Virtex-II Engineering Sample
        70999: 04/07/05: Jonas Floden: Re: Problems with a Virtex-II Engineering Sample
            71030: 04/07/06: Jonas Floden: Re: Problems with a Virtex-II Engineering Sample
                71405: 04/07/17: Zach Pfeffer: Re: Problems with a Virtex-II Engineering Sample
    71840: 04/08/02: Jonas Floden: Re: Problems with a Virtex-II Engineering Sample
70668: 04/06/23: marco p.: 5V board in a 3.3V PCI slot
    70677: 04/06/23: Paul Fulghum: Re: 5V board in a 3.3V PCI slot
        70681: 04/06/23: Amontec Team: Re: 5V board in a 3.3V PCI slot
            70684: 04/06/23: Paul Fulghum: Re: 5V board in a 3.3V PCI slot
                70691: 04/06/23: Amontec Team: Re: 5V board in a 3.3V PCI slot
        70695: 04/06/23: Dwayne Surdu-Miller: Re: 5V board in a 3.3V PCI slot
            70713: 04/06/24: marco p.: Re: 5V board in a 3.3V PCI slot
                70743: 04/06/25: Dwayne Surdu-Miller: Re: 5V board in a 3.3V PCI slot
                    70749: 04/06/26: Uwe Bonnes: Re: 5V board in a 3.3V PCI slot
                        70790: 04/06/28: Dwayne Surdu-Miller: Re: 5V board in a 3.3V PCI slot
                        70896: 04/07/01: Sylvain Munaut: Re: 5V board in a 3.3V PCI slot
70678: 04/06/23: brian hubeau: Communication FPGA & MII
    70808: 04/06/28: MS: Re: Communication FPGA & MII
70682: 04/06/23: Varun: -mapstyle option in BATCH mode operation of XST
70687: 04/06/23: Varun Jindal: -mapstyle option in BATCH mode operation of XST
70688: 04/06/23: Aleco31: Xilinx Sparta-3 configuration
70694: 04/06/23: Sushmita: Readback Problems
70704: 04/06/24: =?ISO-8859-1?Q?Tobias_M=FCller?=: booting fpga and xscale
    70715: 04/06/24: Mike Treseler: Re: booting fpga and xscale
70707: 04/06/24: Jim: DPLL in CPLD
    70726: 04/06/25: Jim Granville: Re: DPLL in CPLD
        70731: 04/06/25: Leon Heller: Re: DPLL in CPLD
        70753: 04/06/26: Jim: Re: DPLL in CPLD
            70757: 04/06/26: Hal Murray: Re: DPLL in CPLD
            70759: 04/06/27: Jim Granville: Re: DPLL in CPLD
70711: 04/06/24: Jimmy: Divided by 11 in VHDL
    70716: 04/06/24: Kevin Neilson: Re: Divided by 11 in VHDL
        70734: 04/06/25: Kolja Sulimma: Re: Divided by 11 in VHDL
    70718: 04/06/24: John_H: Re: Divided by 11 in VHDL
        70771: 04/06/27: Stan Lackey: Re: Divided by 11 in VHDL
70714: 04/06/24: javid: synchronizer and Reset question?
    70741: 04/06/25: Mike Treseler: Re: synchronizer and Reset question?
70719: 04/06/24: Brannon King: Xilinx's interp on EDIF properties
    70720: 04/06/24: Symon: Re: Xilinx's interp on EDIF properties
    70722: 04/06/24: Tim: Re: Xilinx's interp on EDIF properties
    70733: 04/06/25: Petter Gustad: Re: Xilinx's interp on EDIF properties
    70748: 04/06/26: jtw: Re: Xilinx's interp on EDIF properties
70723: 04/06/24: Amy: Looking for Fax software
    71047: 04/07/06: Jim-Green: Re: Looking for Fax software
70725: 04/06/24: David Rogoff: Why does Quartus take 4 hours for a pin I/O change?
    70727: 04/06/25: Jeroen: Re: Why does Quartus take 4 hours for a pin I/O change?
    70744: 04/06/25: Subroto Datta: Re: Why does Quartus take 4 hours for a pin I/O change?
70728: 04/06/24: Scott Mahlke: CFP - WASP 2004 - Abstracts due July 1
70730: 04/06/25: rickman: Forget the RAMs, I can't get Quartus to use the cascade chains!
70735: 04/06/25: Sasa Bremec: open source FPGA tools
    70736: 04/06/25: Allan Herriman: Re: open source FPGA tools
70738: 04/06/25: Morten Leikvoll: Large fast FIFO?
    70739: 04/06/25: Dwayne Surdu-Miller: Re: Large fast FIFO?
        70740: 04/06/25: Dwayne Surdu-Miller: Re: Large fast FIFO?
70742: 04/06/25: Arnaud: Using a BlockRam in an async FIFO for bus width conversion ?
    70746: 04/06/25: Peter Alfke: Re: Using a BlockRam in an async FIFO for bus width conversion ?
        70750: 04/06/26: Arnaud: Re: Using a BlockRam in an async FIFO for bus width conversion ?
            70791: 04/06/28: Peter Alfke: Re: Using a BlockRam in an async FIFO for bus width conversion ?
70745: 04/06/25: Kavitha: Post-Map Simulation
    70768: 04/06/27: Arnaud: Re: Post-Map Simulation
70747: 04/06/26: Alex: RocketIO transmission error
70751: 04/06/26: vivek: Newbie question -fanout of iopins in fpga
    70752: 04/06/26: Hal Murray: Re: Newbie question -fanout of iopins in fpga
        70781: 04/06/28: Mario Trams: Re: Newbie question -fanout of iopins in fpga
70754: 04/06/26: news.optimum-online.com: Xilinx ML310 Experience?
    70765: 04/06/27: Thomas Womack: Re: Xilinx ML310 Experience?
70755: 04/06/26: Repzak: GCK0 Problem
70756: 04/06/26: tns1: Nios stops responding to interrupts
    70782: 04/06/28: Peter Sommerfeld: Re: Nios stops responding to interrupts
    70784: 04/06/28: Peter Sommerfeld: Re: Nios stops responding to interrupts
        70787: 04/06/28: tns1: Re: Nios stops responding to interrupts
            70814: 04/06/29: Hal Murray: Re: Nios stops responding to interrupts
            70834: 04/06/29: Peter Sommerfeld: Re: Nios stops responding to interrupts
                70846: 04/06/29: tns1: Re: Nios stops responding to interrupts
70760: 04/06/26: Chao: simprim X_FF component
    70776: 04/06/28: Niv: Re: simprim X_FF component
        70826: 04/06/29: Chao: Re: simprim X_FF component
            70828: 04/06/29: Barry Brown: Re: simprim X_FF component
                70839: 04/06/29: Brian Philofsky: Re: simprim X_FF component
                    70848: 04/06/30: Tim: Re: simprim X_FF component
                        70860: 04/06/30: Brian Philofsky: Re: simprim X_FF component
                        70862: 04/06/30: Hal Murray: Re: simprim X_FF component
        70827: 04/06/29: Gary Michels: Re: simprim X_FF component
70762: 04/06/26: Brad Smallridge: Simulation Tool with Video Display
    70774: 04/06/28: Allan Herriman: Re: Simulation Tool with Video Display
70763: 04/06/26: Pino: How to Connect User-Defined Master Peripheral to SDRAM Slave Peripheral in SOPC Builder
70764: 04/06/27: Abbes Amira: Short Course by Dr. Abbes Amira:Accelerating Matrix Algorithms on Reconfigurable Hardware for Image and Signal Processing Applications
70766: 04/06/27: Sushmita: Spartan 2
70767: 04/06/27: Repzak: PROTEL DXP 2004 / NANOBOARD / 3rd Part board
70769: 04/06/27: chuk: clk inputs, are they all same?
    70770: 04/06/27: Repzak: Re: clk inputs, are they all same?
70772: 04/06/27: General Schvantzkoph: Running precision on Mandrake 10
    70951: 04/07/02: Hans: Re: Running precision on Mandrake 10
70773: 04/06/28: rat: How to add clock delay in CPLD?
    70775: 04/06/28: Repzak: Re: How to add clock delay in CPLD?
    70777: 04/06/28: Jim Granville: Re: How to add clock delay in CPLD?
        70778: 04/06/28: Uwe Bonnes: Re: How to add clock delay in CPLD?
            70786: 04/06/28: rat: Re: How to add clock delay in CPLD?
                70789: 04/06/28: Uwe Bonnes: Re: How to add clock delay in CPLD?
            70813: 04/06/29: Hal Murray: Re: How to add clock delay in CPLD?
    70973: 04/07/03: John Adair: Re: How to add clock delay in CPLD?
        71089: 04/07/07: pablo aimar: Re: How to add clock delay in CPLD?
70779: 04/06/28: Seyior: XILINX GMAC Core 4.0 - HALF Duplex
70780: 04/06/28: Petter Gustad: GT10_PCI_EXPRESS_n
    70792: 04/06/28: Eric Crabill: Re: GT10_PCI_EXPRESS_n
        70817: 04/06/29: Petter Gustad: Re: GT10_PCI_EXPRESS_n
70785: 04/06/28: ALuPin: Programming Altera Devices
    70884: 04/06/30: xyz: Re: Programming Altera Devices
        70905: 04/07/01: ALuPin: Re: Programming Altera Devices
70794: 04/06/28: Thomas Womack: Battle of the Vapours
    70796: 04/06/28: Peter Alfke: Re: Battle of the Vapours
        70798: 04/06/28: Thomas Womack: Re: Battle of the Vapours
            70801: 04/06/28: Peter Alfke: Re: Battle of the Vapours
            70802: 04/06/28: Symon: Re: Battle of the Vapours
            70806: 04/06/28: rickman: Re: Battle of the Vapours
        70805: 04/06/28: rickman: Re: Battle of the Vapours
        70809: 04/06/29: Jim Granville: Re: Battle of the Vapours
            70822: 04/06/29: Austin Lesea: Re: Battle of the Vapours
    70799: 04/06/29: Jim Granville: Re: Battle of the Vapours
70795: 04/06/28: lenz: FPGA jobs in Germany
    70812: 04/06/29: Guenter Dannoritzer: Re: FPGA jobs in Germany
        70819: 04/06/29: john jakson: Re: FPGA jobs in Germany
    70833: 04/06/29: Rene Tschaggelar: Re: FPGA jobs in Germany
70804: 04/06/28: Alan Calac: Download Nios II evaluation version today
70811: 04/06/28: John Craven: Answer Record # 18857 compiling modelsim library
    70840: 04/06/29: Brian Philofsky: Re: Answer Record # 18857 compiling modelsim library
70815: 04/06/29: Colin: Programming Nios Ethernet Development Kit
    70872: 04/06/30: Vaughn Betz: Re: Programming Nios Ethernet Development Kit
70816: 04/06/29: Sean Durkin: Where are the EDK3.x service packs?
    70818: 04/06/29: Sean Durkin: Re: Where are the EDK3.x service packs?
70825: 04/06/29: Markus Koechy: File format *.eqn in Altera IDE
    70853: 04/06/30: Peter Sommerfeld: Re: File format *.eqn in Altera IDE
    70858: 04/06/30: Vaughn Betz: Re: File format *.eqn in Altera IDE
70829: 04/06/29: Steven K. Knapp: ANN: Xilinx Delivers Lowest Cost, Easy-to-use $99 Spartan-3 FPGA Starter Kit
70832: 04/06/29: Pino: Altera SOPC Master Peripheral Design?
    70865: 04/06/30: Jesse Kempa: Re: Altera SOPC Master Peripheral Design?
        70925: 04/07/01: Pino: Re: Altera SOPC Master Peripheral Design?
            71260: 04/07/13: Pino: Re: Altera SOPC Master Peripheral Design?
        70926: 04/07/01: Pino: Re: Altera SOPC Master Peripheral Design?
70835: 04/06/29: Chris Carlen: Trouble with $readmemh in ModelSim
    70836: 04/06/29: Duane Clark: Re: Trouble with $readmemh in ModelSim
        70842: 04/06/29: Brian Philofsky: Re: Trouble with $readmemh in ModelSim
        70843: 04/06/29: Chris Carlen: Re: Trouble with $readmemh in ModelSim
    70837: 04/06/29: Kevin Neilson: Re: Trouble with $readmemh in ModelSim
        70844: 04/06/29: Chris Carlen: Re: Trouble with $readmemh in ModelSim
            70857: 04/06/30: Kevin Neilson: Re: Trouble with $readmemh in ModelSim
                70863: 04/06/30: Brian Philofsky: Re: Trouble with $readmemh in ModelSim
                    70930: 04/07/01: Chris Carlen: Re: Trouble with $readmemh in ModelSim
70841: 04/06/29: Colin: Altera Nios Ethernet Development Kit: "spurious interrupt number: 0000 001C"
    70850: 04/06/30: Peter Sommerfeld: Re: Altera Nios Ethernet Development Kit: "spurious interrupt number: 0000 001C"
    70870: 04/06/30: Jesse Kempa: Re: Altera Nios Ethernet Development Kit: "spurious interrupt number: 0000 001C"
70845: 04/06/30: rat: a question in the pci interface design
    70847: 04/06/30: Luc Braeckman: Re: a question in the pci interface design
    70868: 04/06/30: Vaughn Betz: Re: a question in the pci interface design
    70873: 04/06/30: www.amontec.com: Re: a question in the pci interface design
        70882: 04/07/01: rat: Re: a question in the pci interface design
70849: 04/06/30: Michael Dales: Problems with custom IP in Xilinx Project Navigator
70851: 04/06/30: Mark Schellhorn: PCI-X DMA problem w/ Xeon?
    70919: 04/07/01: Brannon King: Re: PCI-X DMA problem w/ Xeon?
70852: 04/06/30: Fuchs Gottfried: FPGA with fully asynchronous RAM
    70854: 04/06/30: John_H: Re: FPGA with fully asynchronous RAM
    70859: 04/06/30: Peter Alfke: Re: FPGA with fully asynchronous RAM
    70866: 04/06/30: Symon: Re: FPGA with fully asynchronous RAM
        70889: 04/07/01: Fuchs Gottfried: Re: FPGA with fully asynchronous RAM
            70911: 04/07/01: Symon: Re: FPGA with fully asynchronous RAM
                70912: 04/07/01: Peter Alfke: Re: FPGA with fully asynchronous RAM
            70913: 04/07/01: Nicholas Weaver: Re: FPGA with fully asynchronous RAM
                71372: 04/07/15: Ray Andraka: Re: FPGA with fully asynchronous RAM
                    71375: 04/07/16: E. Backhus: Re: FPGA with fully asynchronous RAM
                        71385: 04/07/16: john jakson: Re: FPGA with fully asynchronous RAM
                            71453: 04/07/19: E. Backhus: Re: FPGA with fully asynchronous RAM
                                71461: 04/07/19: john jakson: Re: FPGA with fully asynchronous RAM
                                    71465: 04/07/19: rickman: Re: FPGA with fully asynchronous RAM
                                    71493: 04/07/20: E. Backhus: Re: FPGA with fully asynchronous RAM
                                        71542: 04/07/21: john jakson: Re: FPGA with fully asynchronous RAM
70855: 04/06/30: Leon Heller: Xilinx $99 Spartan-3 kit
    70861: 04/06/30: Symon: Re: Xilinx $99 Spartan-3 kit
        70864: 04/06/30: Steven K. Knapp: Re: Xilinx $99 Spartan-3 kit
            70867: 04/06/30: Lukasz Salwinski: Re: Xilinx $99 Spartan-3 kit
                70871: 04/06/30: Symon: Re: Xilinx $99 Spartan-3 kit
                    70874: 04/06/30: Thomas Womack: Re: Xilinx $99 Spartan-3 kit
                70894: 04/07/01: Jon Beniston: Re: Xilinx $99 Spartan-3 kit
            70869: 04/06/30: Tim: Re: Xilinx $99 Spartan-3 kit
                70910: 04/07/01: Georgi Beloev: Re: Xilinx $99 Spartan-3 kit
                    70937: 04/07/01: Tom Seim: Re: Xilinx $99 Spartan-3 kit
                    70946: 04/07/02: Nial Stewart: Re: Xilinx $99 Spartan-3 kit
                    71392: 04/07/16: Ray Andraka: Would Tom buy from Nu Horizons?
                        71400: 04/07/16: Tom Seim: Re: Would Tom buy from Nu Horizons?
    70875: 04/06/30: Phil Tomson: Re: Xilinx $99 Spartan-3 kit
        70876: 04/06/30: Uwe Bonnes: Re: Xilinx $99 Spartan-3 kit
            70878: 04/06/30: Phil Tomson: Re: Xilinx $99 Spartan-3 kit
                70880: 04/06/30: Uwe Bonnes: Re: Xilinx $99 Spartan-3 kit
        70877: 04/06/30: Steven K. Knapp: Re: Xilinx $99 Spartan-3 kit [Windows Only]
            70879: 04/06/30: Phil Tomson: Re: Xilinx $99 Spartan-3 kit [Windows Only]
    70936: 04/07/02: Bob Perlman: Re: Xilinx $99 Spartan-3 kit
        70955: 04/07/02: Phil Tomson: Re: Xilinx $99 Spartan-3 kit
            70957: 04/07/02: Bob Perlman: Re: Xilinx $99 Spartan-3 kit
            70959: 04/07/02: Rich Webb: Re: Xilinx $99 Spartan-3 kit
                70963: 04/07/02: Phil Tomson: Re: Xilinx $99 Spartan-3 kit
                    70968: 04/07/03: Rich Webb: Re: Xilinx $99 Spartan-3 kit
        70976: 04/07/03: Brian Davis: Re: Xilinx $99 Spartan-3 kit
70856: 04/06/30: Tom Becker: GAL22V10D vs GAL22V10A
70881: 04/06/30: Gary Pace: Cyclone 5V Tolerance
    70907: 04/07/01: Nial Stewart: Re: Cyclone 5V Tolerance
70886: 04/06/30: tns1: Quartus web editions vs licenced compatibility problems
    71111: 04/07/08: tns1: Re: Quartus web editions vs licenced compatibility problems
70887: 04/06/30: Daragoth: Compact FPGA Board?
    70895: 04/07/01: Leon Heller: Re: Compact FPGA Board?
        70900: 04/07/01: Fredrik: Re: Compact FPGA Board?
            70927: 04/07/01: Tim: Re: Compact FPGA Board?
                71401: 04/07/16: Daragoth: Re: Compact FPGA Board?
                    71403: 04/07/17: Leon Heller: Re: Compact FPGA Board?
                71470: 04/07/19: Kolja Sulimma: Re: Compact FPGA Board?
                    71607: 04/07/24: Daragoth: Re: Compact FPGA Board?
            70987: 04/07/05: valentin tihomirov: Re: Compact FPGA Board?
    70897: 04/07/01: www.amontec.com: Re: Compact FPGA Board?
        70917: 04/07/01: Daragoth: Re: Compact FPGA Board?
    70908: 04/07/01: john jakson: Re: Compact FPGA Board?
        71274: 04/07/13: Daragoth: Re: Compact FPGA Board?
            71858: 04/08/02: Daragoth: Re: Compact FPGA Board?
                71860: 04/08/02: Peter Alfke: Re: Compact FPGA Board?
                    71965: 04/08/04: Daragoth: Re: Compact FPGA Board?
                        71983: 04/08/04: Tom Seim: Re: Compact FPGA Board?
                71861: 04/08/03: Jim Granville: Re: Compact FPGA Board?
                    72066: 04/08/06: Daragoth: Re: Compact FPGA Board?
                        72067: 04/08/07: Jim Granville: Re: Compact FPGA Board?
                            72316: 04/08/14: Daragoth: Re: Compact FPGA Board?
                71863: 04/08/03: Philip Freidin: Re: Compact FPGA Board?
                    72140: 04/08/09: Daragoth: Re: Compact FPGA Board?
    70923: 04/07/01: Jacek Wawrzaszek: Re: Compact FPGA Board?
        71189: 04/07/11: Daragoth: Re: Compact FPGA Board?
    70974: 04/07/03: John Adair: Re: Compact FPGA Board?


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