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Messages from 71475

Article: 71475
Subject: Re: fpga board with audio in/out (xilinx fpga) ?
From: Dave Vanden Bout <devb@xess.com>
Date: Mon, 19 Jul 2004 21:50:50 GMT
Links: << >>  << T >>  << A >>
"Timo Dammes" <timo.dammes@gmx.de> wrote in
news:cdghf4$1gq$1@nx6.HRZ.Uni-Dortmund.DE: 

> Hello
> 
> I'm searching for a FPGA board for about $500 with an "audio in" and
> "audio out" port... adequate for audio processing applications. I
> thought of a Virtex II fpga, but can be another one from XILINX....
> Can anyone recommend a board like this ?

We offer the XST-2 Board that has an AK4551 stereo audio codec:
http://www.xess.com/prod033.php3

You combine it with one of our XSA-50 or XSA-100 Boards:
http://www.xess.com/prod026.php3


Or look at the XSB-300E Board with an AK4565 stereo audio codec:
http://www.xess.com/prod032.php3



> 
> Regards,
> Timo Dammes
> 
> 



-- 
----------------------------------------------------------------
Dr. Dave Van den Bout
XESS Corp.
PO Box 33091
Raleigh NC 27636
Phn: (919) 363-4695
Fax: (801) 749-6501
devb@xess.com
http://www.xess.com


Article: 71476
Subject: Xilinx XC9500 CPLD internal pull-up??
From: "Bruno Cardeira" <bmscc@netcabo.pt>
Date: Mon, 19 Jul 2004 22:54:14 +0100
Links: << >>  << T >>  << A >>
Hello!
Does anyone know if the Xilinx XC9500 has internal pull-ups (or
pull-downs...) when in normal mode (programmable)?
If not, how can I solve this problem...
-> I have a input pin of the CPLD connected to a output pin of  a IC that
normally is tri-stated. The device gets very hot when the output of the IC
is in tri-state (so I think...). Is this possible? how can I solve this
without an external pull-up (or pull-down)?
The programming language that i'm using is ABEL.

Thanks in advance
Best Regards

Bruno



Article: 71477
Subject: Re: IDE or ATA controler on a Fpga
From: =?iso-8859-1?Q?Michael_Sch=F6berl?= <MSchoeberl@ratnet.stw.uni-erlangen.de>
Date: Tue, 20 Jul 2004 00:03:24 +0200
Links: << >>  << T >>  << A >>
> > I would like to know if someone has already build a IDE or ATA controler
> >     on a FPGA (any kind Xilinx or Altera) ? The contoler has to been
> > fully compliant at least with the with the ATA 4 normalisation.

fully compliant? but only ATA-4 ? (http://www.t13.org/project/d1153r18.pdf)
thats a lot of work for only 33 MByte/sec ...


> opencores.net
> Never tried it myself though

this one suppports only PIO Modes ...


a few years ago I've written something to read/write with
UDMA/100 but this was far from beeing fully compliant ...


bye,
Michael


Article: 71478
Subject: Re: twos to ones and ones to twos compliments
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Mon, 19 Jul 2004 22:08:51 GMT
Links: << >>  << T >>  << A >>
rickman wrote:

(snip)

>>>chuk wrote:

>>>>Any one know of the most efficient method (seed and space wise) of
>>>>implementing conversion of ones to twos and twos to ones compliment???

(snip)

> I don't think this method is really a short cut other than if you are
> doing it using paper and pencil.  This is the same calculation that the
> inverters and adder does.  

> The OP is really just trying to find a way to not have to do the
> addition, but in reality there is no way around it.  

Note that while in many ways twos complement seems simpler
than ones complement this example shows a case where it isn't.

There are some advantages to ones complement, though not quite
as many.

-- glen


Article: 71479
Subject: Re: IDE or ATA controler on a Fpga
From: "Steve Casselman" <sc@vcc.com>
Date: Mon, 19 Jul 2004 22:32:05 GMT
Links: << >>  << T >>  << A >>
Try www.opencores.org

"Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> wrote in message
news:40fbec7e$0$6422$ba620e4c@news.skynet.be...
> David wrote:
> > Hi everybody,
> >
> > I would like to know if someone has already build a IDE or ATA controler
> >     on a FPGA (any kind Xilinx or Altera) ? The contoler has to been
> > fully compliant at least with the with the ATA 4 normalisation.
> >
> > If yes what are the conditions to access to the code ?
> >
> > Thanks
> >
>
> opencores.net
>
> Never tried it myself though



Article: 71480
Subject: Re: How Bidirectional (AHDL) or INOUT (VHDL) are displayed in the Waveform Simulation?
From: pinod01@sympatico.ca (Pino)
Date: 19 Jul 2004 16:54:54 -0700
Links: << >>  << T >>  << A >>
dhruvish@gmail.com (Drew) wrote in message news:<ad2011c0.0407191058.44dad230@posting.google.com>...
> Thanks a lot Subroto,
> 
> I am having one more doubt now. If I place an Oscilloscope on the
> Bidirectional Pin, what would I see? Will it be any form of
> combination of A and A~result or it will be A~result only. Can I use
> MAX3000 family EPLD for this sort of application?
> 
> Thanks,
> Dhruvish

Dhruvish,

    My understanding is that the bidirectional pin will only have one
set of values on it and therefore on the oscilloscope you will measure
what is present.  The diagram should explain this.  If OE = '1' for
example then whatever the value of A is should be present otherwise,
it should be whatever some other entity placed on that pin.

            _____ OE
           |
           |/|
        ___/ |___ A
       |   \ |
       |    \|
   Z --|
       |   |\
       |___| \___ Y
           | /
           |/

Article: 71481
Subject: 32-channel PC-based logic analyzers
From: ernielin@gmail.com (ernie)
Date: 19 Jul 2004 17:38:03 -0700
Links: << >>  << T >>  << A >>
Hi,

Can anyone recommend any good (and cheap) 32-channel analyzers?  By
cheap I mean less than or approximately $1000.  It would be nice if
the software supported complex triggering and the analyzer had
decently fast sampling rates.  Sample depth is not really a critical
issue but more is obviously better.

Thank you!

Article: 71482
Subject: Re: 32-channel PC-based logic analyzers
From: "Kevin Neilson" <kevin_neilson@removethiscomcast.net>
Date: Tue, 20 Jul 2004 02:35:15 GMT
Links: << >>  << T >>  << A >>
It's starting to look like ChipScope is a pretty decent logic analyzer.  You
could get a Xilinx eval board with headers on it and use it and ChipScope as
a logic analyzer.  The depth will be limited by the number of blockRAMs on
the part.
-Kevin

"ernie" <ernielin@gmail.com> wrote in message
news:d7fe9825.0407191638.58b29e0c@posting.google.com...
> Hi,
>
> Can anyone recommend any good (and cheap) 32-channel analyzers?  By
> cheap I mean less than or approximately $1000.  It would be nice if
> the software supported complex triggering and the analyzer had
> decently fast sampling rates.  Sample depth is not really a critical
> issue but more is obviously better.
>
> Thank you!



Article: 71483
Subject: Re: 32-channel PC-based logic analyzers
From: Michael Dombrowski <legodudenein@hammycorp.com>
Date: Mon, 19 Jul 2004 23:57:33 -0400
Links: << >>  << T >>  << A >>
ernie wrote:
> Hi,
> 
> Can anyone recommend any good (and cheap) 32-channel analyzers?  By
> cheap I mean less than or approximately $1000.  It would be nice if
> the software supported complex triggering and the analyzer had
> decently fast sampling rates.  Sample depth is not really a critical
> issue but more is obviously better.
> 
> Thank you!

HP/Aligent Logicwaves show up on Ebay occasionally. I don't know 
anything about them but you might want to take a look.

Mike

Article: 71484
Subject: Re: PLL phase after compensation
From: vbetz@altera.com (Vaughn Betz)
Date: 19 Jul 2004 22:20:14 -0700
Links: << >>  << T >>  << A >>
> I have the following question concerning PLL use in Altera Cyclone
> devices:
> 
> In normal mode it said  that the PLL phase aligns the input reference
> clock with the clock signal at the ports
> of the registers that is clock used for FPGA internal registers.
> 
> Functional simulation shows that PLL input clock (30MHz) and PLL
> output clock (90MHz) (which is
> NOT used for I/O pin!) are phase aligned that is three clock periods
> of Clock_out fit into the period of Clock_in.
> 
> But when doing timing simulation Clock_out is not phase aligned with
> the input clock but there is a delay.
> But why? I have compensated the PLL for the Clock_out so why is there
> a delay at all in the simulation?
> 
> I would appreciate your help.
> 
> Kind regards

Hi,

Exactly where you are measuring your 90 MHz clock signal?

The 90 MHz clock measured at the output of the PLL (but before the
global clock network) will have a phase that is ahead of the 30 MHz
clock.  That is because the the 90 MHz clock should be phase-aligned
with the 30 MHz clock at the logic cell register inputs, and there is
a global clock delay between them and the PLL output.

If you bring the 90 MHz clock to an output pin, and monitor that point
in the Quartus timing simulation, you will see its phase being behind
the 30 MHz clock.  That is because the 90 MHz clock at this point has
both a global clock network delay *and* an IO output pad delay.

Unfortunately, there is no way to look at the clock at the input to a
register in the Quartus simulator. You can only enter the names of
signals that are the output of blocks, and that really limits you to
the two possibilities I mention above.

In functional simulation, routing and block delays (such as the GCLK
network delay and IO pad delays) are not included in the simulation,
so you could bring the 90 MHz clock to an IO pad and see it phase
aligned with the 30 MHz clock.

Another thing to remember is that the compensation for global clock
network delays (normal compensation) is not quite perfect.  There is
some clock skew even on the dedicated global clock networks, so it is
not possible to perfectly align the output clock of a PLL with the
input clock phase at all destination registers.  This skew is small
though, so this is a small effect (at most a few hundred picoseconds).

Hope this helps,

Vaughn
Altera

Article: 71485
Subject: Re: Using Verilog to embed the synthesis date and time
From: hmurray@suespammers.org (Hal Murray)
Date: Tue, 20 Jul 2004 00:24:31 -0500
Links: << >>  << T >>  << A >>
>No, I've always done this with Perl. I've also used Perl & Data2MEM to
>include the P&R time into the download bitstream. The times are loaded into
>a BlockRAM which is the character storage for my debug VGA driver. Very
>useful when working with those (sometimes forgetful, bless 'em) software
>guys!

You can also use cpp for hacks like this.

It's the c pre-processor that processes #include and #ifdef
and #define and such.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 71486
Subject: Re: Problem with LogicLock and register packing
From: vbetz@altera.com (Vaughn Betz)
Date: 19 Jul 2004 22:35:39 -0700
Links: << >>  << T >>  << A >>
> Hi folks,
> 
> I'm having a problem where I back-annotated the nodes of a
> LogicLock'ed SDRAM controller. The design was compiled with Auto
> Packed Registers = MINIMIZE on Quartus 3.0 SP1. When I recompile the
> design, it fails, sometimes with as little as 2 nodes not being able
> to fit. This problem does not occur if I compile Reg Packing = NORMAL,
> so I assume register packing is causing problems.
> 
> I need to pack the registers to stay within the resource constraints
> of the project and I need to LogicLock to maintain timing. Is there a
> way to LogicLock a register-packed design and not have problems in
> subsequent compiles?
> 
> -- Pete

Hi Peter,

This does occasionally happen when Quartus' register packing
heuristics can't find a register packing that matches your
back-annotated logic lock constraints, even though clearly a packing
solution exists (since it was found on the first compile).

Three things to try:

1.  Back-annotate this logic-lock region to the logic cell (rather
than LAB) level.  Generally it is best to back-annotate to the LAB
level to give the compiler more flexibility.  In this case though, by
back-annotating to the logic cell level you will make the correct
register packing very explicit (this LUT goes with that register), and
that should make Quartus reproduce the register packing you need and
get you a fit.

2. Upgrade to Quartus 4.1.  I can't guarantee that will fix this, but
it probably will, since we improved the handling of back-annotated
designs with area-minimizing register packing in Quartus II 4.0 and
4.1.

3. Send me the problem design (vbetz@altera.com).  If you can send two
Quartus archives -- one with the non-back-annotated design that fits,
and one with the back-annotated one that doesn't fit -- that would be
ideal.  I'll get someone in my group to confirm that the problem does
not exist in Quartus II 4.1 (or fix it if it does still exist).

Regards,

Vaughn
Altera

Article: 71487
Subject: Re: Using Verilog to embed the synthesis date and time
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Tue, 20 Jul 2004 15:54:08 +1000
Links: << >>  << T >>  << A >>
On 19 Jul 2004 08:27:08 -0700, johnp3+nospam@probo.com (John
Providenza) wrote:

>Does anyone have a simple way to embed the date and time
>that a module is compiled into a wire or register in Verilog?
>
>I could use a Perl script to create an `include file with the
>proper `define statements, but I'm wondering if anyone has
>a cute way to do this purely in Verilog.
>
>FYI - I'm using Xilinx XST for synthesis.

Another solution that you may not have considered is to put the
timestamp and version information in a header prepended to the
download image.  This is trivial to do as part of your build process,
and avoids the need to have any extra information inside the FPGA
itself.

(Obviously this only works if the FPGA is downloaded from a cpu - the
cpu will read and strip the version and timestamp info before
downloading it into the fpga.)

I (and others) developed something similar when I was at Agilent.  We
ended up with a lot of information in the headers, including:
- An ID that was unique for each download.
- The name of the person who generated the download file (which came
from the username on the computer).
- The part number of the FPGA (extracted from the EDIF file).
- Date stamps for synthesis and PAR (extracted from the EDIF and the
PAR report file).
- The version number of the synthesiser and PAR tools (extracted from
the respective report files).

All of this was done automatically by the build script, which meant
that all fpga download image files had complete traceability back to
the exact source files and tool versions.  This made bug finding much
easier (particularly tool bugs).

Regards,
Allan.

Article: 71488
Subject: Re: Xilinx XC9500 CPLD internal pull-up??
From: Falser Klaus <kfalser@durst.it>
Date: Tue, 20 Jul 2004 08:48:45 +0200
Links: << >>  << T >>  << A >>
In article <40fc41ee$0$18591$a729d347@news.telepac.pt>, bmscc@netcabo.pt 
says...
> Hello!
> Does anyone know if the Xilinx XC9500 has internal pull-ups (or
> pull-downs...) when in normal mode (programmable)?
> If not, how can I solve this problem...
> -> I have a input pin of the CPLD connected to a output pin of  a IC that
> normally is tri-stated. The device gets very hot when the output of the IC
> is in tri-state (so I think...). Is this possible? how can I solve this
> without an external pull-up (or pull-down)?
> The programming language that i'm using is ABEL.
> 
> Thanks in advance
> Best Regards
> 
> Bruno
> 
> 
> 
The XC9500 family has a pullup, but is active only during
programming and can not be used during normal operation.
Please, read the data sheet!
You have to connect an external resistor.

Best regards 
-- 
Klaus Falser
Durst Phototechnik AG
kfalser@IHATESPAMdurst.it

Article: 71489
Subject: Re: Memory width on Spartan-3 boards
From: Simon <news@gornall.net>
Date: Tue, 20 Jul 2004 09:01:06 GMT
Links: << >>  << T >>  << A >>
John Adair wrote:
> Cost isn't set yet but likely to be 299 / E499 / $ 499. We have not set 
> a specific production date for these yet. We would like to put a few 
> XC3S1500 specific enhancements into the design over and above the larger 
> chip size. However if there is enough demand we will accelerate the 
> production cycle but this may be limited by delivery times on XC3S1500 
> silicon. We now have a rolling delivery of XC3S400 so once we are past 
> the initial demand Broaddown2-400 will be a stock item. Broaddown2-1500 
> should be become a stock item in about 3-4 months on the current 
> schedule. If you need a solution earlier contact me offline and I will 
> see what can be done.

Actually that timescale sort of suits me. I've got to persuade myself 
that the $2500 (probably = 1800 after import duty etc.) for Foundation 
is worth the outlay, just to use the larger part. I work in the 
video/film industry, and I have an idea which might make it worthwhile, 
but a few months will give me some time to explore that :-)

What specific enhancements are you proposing ? If you want to take this 
to private email, that's fine - the same address will do (news@gornall.net).

Simon

Article: 71490
Subject: Re: Spartan 3 termination question (DCI)
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 20 Jul 2004 10:09:49 GMT
Links: << >>  << T >>  << A >>
Austin Lesea wrote:

> LVDCI_33 is 60 mA for the reference resistors.  For the whole bank.

> Wow.  Sooooo much current!  Face it:  setting the reference for the 
> entire bank does take some power (in this case 3.3V X 60 mA or 200 
> milliwatts.  I am pretty sure this is not going to "break the bank."

(snip)

See:

http://www.world-academy-of-science.org/IMCSE2004/ws/keynote

He has a challenge to build computers using one millionth of
the power of current systems, so maybe 100 microwatts.

On that scale, 200mW does break the bank.

There are people interested in micropower logic.

-- glen



Article: 71491
Subject: Re: fpga board with audio in/out (xilinx fpga) ?
From: "John Adair" <removethisjea@replacewithcompanyname.co.uk>
Date: Tue, 20 Jul 2004 03:30:36 -0700
Links: << >>  << T >>  << A >>
Not quite off the shelf but our Broaddown2 will accept 3.3V DIL packaged codecs etc or stripboard based interfaces. 

Broaddown2 is Spartan-3 based. Broaddown2 details are here 
  http://www.enterpoint.co.uk/moelbryn/broaddown2.html 

-- 
John Adair 
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board. 
http://www.enterpoint.co.uk 



Article: 71492
Subject: Re: PLL phase after compensation
From: ALuPin@web.de (ALuPin)
Date: 20 Jul 2004 03:51:17 -0700
Links: << >>  << T >>  << A >>
Hi,

thank you very much for your answer.
 
> Unfortunately, there is no way to look at the clock at the input to a
> register in the Quartus simulator. You can only enter the names of
> signals that are the output of blocks, and that really limits you to
> the two possibilities I mention above.
> 

I have used the following testbench for my gate-level-simulation:
The clock "C1" is not in phase with InClk0 (shwon in the plot is
"t_c1_sys".
Does that mean that I look at an IO pin and not at the clock at the input
to a register?
Would the second testbench be the solution ? But what is then t_c1_sys ?
Is it the pll output before an input register or is the clock at an input register?


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity tb_pll1 is
end tb_pll1;

architecture testbench of tb_pll1 is

component pll1
port ( Inclk0 : in  std_logic := '0';
       Areset : in  std_logic := '0';
       C0     : out std_logic;
       C1     : out std_logic;            
       Locked : out std_logic
     );
end component;

signal t_Clk_30   : std_logic;
signal t_Reset    : std_logic;
signal t_c0_sys   : std_logic;
signal t_c1_sys   : std_logic;
signal t_Locked   : std_logic;

begin
u1 : pll1
     port map ( Inclk0 => t_Clk_30,
                Areset => t_Reset,
                C0     => t_c0_sys,
                C1     => t_c1_sys,            
                Locked => t_Locked
              );
---------------------------------------------
---------------------------------------------
 process
 begin
   t_Reset <= '1', '0' after 150 ns;
 wait;
 end process;
---------------------------------------------
---------------------------------------------
 process
 begin
   t_Clk_30 <= '1'; wait for 16.665 ns;      -- 30MHz
   t_Clk_30 <= '0'; wait for 16.665 ns;
 end process;
---------------------------------------------
---------------------------------------------
end testbench;


Second testbench: The additional module "reg_help" does use the clocks C0 and
C1 as clocks for registers


library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity tb_pll1 is
end tb_pll1;

architecture testbench of tb_pll1 is

component pll1
port ( Inclk0 : in  std_logic := '0';
       Areset : in  std_logic := '0';
       C0     : out std_logic;
       C1     : out std_logic;            
       Locked : out std_logic
     );
end component;

component reg_help 
port ( Clk0     : in  std_logic;
       Clk1     : in  std_logic;
       Out_help : out std_logic
     );
end component;

signal t_Clk_30   : std_logic;
signal t_Reset    : std_logic;
signal t_c0_sys   : std_logic;
signal t_c1_sys   : std_logic;
signal t_Locked   : std_logic;
signal t_Out_help : std_logic;

begin


u1 : pll1
     port map ( Inclk0 => t_Clk_30,
                Areset => t_Reset,
                C0     => t_c0_sys,
                C1     => t_c1_sys,            
                Locked => t_Locked
              );

u2 : reg_help
     port map ( Clk0 => t_c0_sys,
                Clk1 => t_c1_sys,
                Out_help => t_Out_help
              );

---------------------------------------------
---------------------------------------------
 process
 begin
   t_Reset <= '1', '0' after 150 ns;
 wait;
 end process;
---------------------------------------------
---------------------------------------------
 process
 begin
   t_Clk_30 <= '1'; wait for 16.665 ns;      -- 30MHz
   t_Clk_30 <= '0'; wait for 16.665 ns;
 end process;
---------------------------------------------
---------------------------------------------


end testbench;

Article: 71493
Subject: Re: FPGA with fully asynchronous RAM
From: ibis@tiscalinet.de (E. Backhus)
Date: 20 Jul 2004 04:43:18 -0700
Links: << >>  << T >>  << A >>
johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0407190711.45a7a53a@posting.google.com>...
> ibis@tiscalinet.de (E. Backhus) wrote in message news:<e5e7ca2e.0407182337.570d1070@posting.google.com>...
> > johnjakson@yahoo.com (john jakson) wrote in message 



> 
> My family is all too aware of AthlonXP heat output, looking to kill it
> one day with a Transputer or 2, but 1 should suffice. After all it
> only surfs & plays net TV.

I just didn't dare to mention Transputers :-)
 


> > 
> > I wonder, besides any asynchronous stuff, if the same space could hold
> > a bunch of (slow) low power SoC microcomputers, working together as
> > known from grid computers.
> 
> Yes, thats what I am working on, Inmos did this 20yrs ago, probably
> 20yrs too early. I keep doing the same engineering calculation, Intel
> ups the freq of x86 by 30x and gets 30x perf over the p100. BUT
> transister count also went up (big no) and heat,noise,space too. That
> used to be called bad engineering. Notice that bridge builders today
> build lighter bridges today than IKB did many yrs ago.
> 
> The intel supporters will pooh pooh that analysis but if you have
> distributed cpus & local memory and know how to use them (Transputer
> people do), you also get far more total memory b/w than pushing it all
> up 1 pipe. Also no reason to be limited to std DRAM, theres RLDRAM
> available with 20n RAS times. And with MTA architecture, branching &
> memory delays are better hidden than single threaded cpus with ever
> bigger caches.

There are lots of pro's and con's about transputer technology, but
what really broke their neck was the high price of the CPU alone
compared to a whole PC with (then) cheap Network cards. The parallel
processing people started grid computing and the controller people
were just happy with their (then) fast controllers(ARM etc.)

Today there is a possibility for the return of integrated parallel
processing architectures. The IEEE1355 and Spacewire Interfaces
(successors of the Transputer links) are available as FPGA-cores, and
combined with a CPU-core and other fancy stuff (e.g. hardware
scheduler) we get powerful Transputer-Substitutes on cool and cheap(?)
FPGA-Silicon.



regards
 Eilert Backhus

Article: 71494
Subject: Re: Using Verilog to embed the synthesis date and time
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 20 Jul 2004 13:03:35 +0100
Links: << >>  << T >>  << A >>
johnp3+nospam@probo.com (John Providenza) writes:

> Does anyone have a simple way to embed the date and time
> that a module is compiled into a wire or register in Verilog?
> 
> I could use a Perl script to create an `include file with the
> proper `define statements, but I'm wondering if anyone has
> a cute way to do this purely in Verilog.
> 
> FYI - I'm using Xilinx XST for synthesis.
> 

I've embedded the place and route time (year, month, day, hour) in the
bitstream in the past as the USERCODE 0xyymmddhh

And embedded the synthesis time in the "HDL" by overriding a top-level
generic with a synplify TCL script, which is an idea I saw mentioned
somewhere in this NG, or maybe in comp.arch.vhdl.

Cheers,
Martin


-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 71495
Subject: Re: Problem with LogicLock and register packing
From: petersommerfeld@hotmail.com (Peter Sommerfeld)
Date: 20 Jul 2004 08:13:45 -0700
Links: << >>  << T >>  << A >>
Hi Vaughn,

Thanks for the reply.

I erroneously stated that I am using QII 3.0. I am actually using QII 4.0 SP1.19.

I will discuss further through email.

-- Pete

vbetz@altera.com (Vaughn Betz) wrote in message news:<48761f7f.0407192135.4594c112@posting.google.com>...
> > Hi folks,
> > 
> > I'm having a problem where I back-annotated the nodes of a
> > LogicLock'ed SDRAM controller. The design was compiled with Auto
> > Packed Registers = MINIMIZE on Quartus 3.0 SP1. When I recompile the
> > design, it fails, sometimes with as little as 2 nodes not being able
> > to fit. This problem does not occur if I compile Reg Packing = NORMAL,
> > so I assume register packing is causing problems.
> > 
> > I need to pack the registers to stay within the resource constraints
> > of the project and I need to LogicLock to maintain timing. Is there a
> > way to LogicLock a register-packed design and not have problems in
> > subsequent compiles?
> > 
> > -- Pete
> 
> Hi Peter,
> 
> This does occasionally happen when Quartus' register packing
> heuristics can't find a register packing that matches your
> back-annotated logic lock constraints, even though clearly a packing
> solution exists (since it was found on the first compile).
> 
> Three things to try:
> 
> 1.  Back-annotate this logic-lock region to the logic cell (rather
> than LAB) level.  Generally it is best to back-annotate to the LAB
> level to give the compiler more flexibility.  In this case though, by
> back-annotating to the logic cell level you will make the correct
> register packing very explicit (this LUT goes with that register), and
> that should make Quartus reproduce the register packing you need and
> get you a fit.
> 
> 2. Upgrade to Quartus 4.1.  I can't guarantee that will fix this, but
> it probably will, since we improved the handling of back-annotated
> designs with area-minimizing register packing in Quartus II 4.0 and
> 4.1.
> 
> 3. Send me the problem design (vbetz@altera.com).  If you can send two
> Quartus archives -- one with the non-back-annotated design that fits,
> and one with the back-annotated one that doesn't fit -- that would be
> ideal.  I'll get someone in my group to confirm that the problem does
> not exist in Quartus II 4.1 (or fix it if it does still exist).
> 
> Regards,
> 
> Vaughn
> Altera

Article: 71496
Subject: Re: Spartan 3 termination question (DCI)
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 20 Jul 2004 08:17:31 -0700
Links: << >>  << T >>  << A >>
Glen,

I'm impressed.  A million to one reduction in current?

Did anyone hear how he accomplished this miracle?

Austin


> 
> He has a challenge to build computers using one millionth of
> the power of current systems, so maybe 100 microwatts.
> 
> On that scale, 200mW does break the bank.
> 
> There are people interested in micropower logic.
> 
> -- glen
> 
> 

Article: 71497
Subject: Re: FPGA in a Compact Flash format.
From: Phil James-Roxby <Phil.James-Roxby@xilinx.com>
Date: Tue, 20 Jul 2004 10:07:12 -0600
Links: << >>  << T >>  << A >>
Whilst its neither a PDA or compact flash, there's that XPort thing that 
plugs in to a Gameboy Advance.

http://www.charmedlabs.com/

Phil

John Carter wrote:

> Does anyone know of a supplier of FPGA's in compact flash format?
> 
> (Yes, I know of FPGA development boards that have slots for compact
> flash storage devices.)
> 
> Compact Flash is a flexible standard that extends way beyond just
> flash storage devices. You can get GPS's, wireless LAN's, ADC/DAC's
> etc. etc. in Compact Flash format.
> 
> What I want is to be able to plug an FPGA into my Sharp Zaurus PDA
> (which has a Compact Flash slot and embedded Linux) and use the PDA as
> the user interface to the FPGA.


Article: 71498
Subject: Open Collector Circuit - How to Simulate?
From: dhruvish@gmail.com (Drew)
Date: 20 Jul 2004 09:13:40 -0700
Links: << >>  << T >>  << A >>
Hi all,

I need Open Collector Active-Low analog circuit's logical
representation. I am having pretty hard time putting it togather. I
used bidirectional tristated bus, but it doesnt solve my problem.
There are some contentions as I have to read what I write to the Bidir
Pin (always) and at some point the Bidir Pin works as an output too.

Please help,
Drew

Article: 71499
Subject: Re: Spartan 3 termination question (DCI)
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 20 Jul 2004 09:41:26 -0700
Links: << >>  << T >>  << A >>
Modern high-performance sub-150 nm conventional CMOS technology has leakage
currents that make that goal unattainable (by a long shot).
Such a  requirement is not mainstream...
Peter Alfke
============================
>
> 
> See:
> 
> http://www.world-academy-of-science.org/IMCSE2004/ws/keynote
> 
> He has a challenge to build computers using one millionth of
> the power of current systems, so maybe 100 microwatts.
> 
> On that scale, 200mW does break the bank.
> 
> There are people interested in micropower logic.
> 
> -- glen
> 
> 




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