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> It also has the problem of leaving your board in a broken > state if you drop power in the middle of the update. Or something else goes wrong, plus the cost of the PROM is comparable to the cost of a PCI bridge... /MikhailArticle: 71226
"Adarsh Kumar Jain" <adarsh.jain@cern.ch> wrote in message news:<cctf2s$hd7$1@sunnews.cern.ch>... > Hi All, > This may be a strange question .. > I program 9 Xilinx Devices with the same bitstream file. > But some of them behave differently from the others. > Can anyone give me any suggestions on why this could be happening ? > Is the problem internal to Xilinx (if i am on the edge of timing on some > signals) > or it is outside in the signals coming to them ? > Any pointers will be really appreciated, > Thanks, > Adarsh I had the same experience due to a bug (mine) crossing clock domains between 1x and 2x clocks. IIRC the problem was not a source code issue, rather a missing or incorrect timing constraint. Some devices happened to be fast enough where the unconstrained path was OK, others failed. This was in Altera/Quartus. Hope this helps, -rajeev-Article: 71227
Hello, I did a lot of work since the begining of NIOS(1) to put some libraries toghether with stuff that wasn't supported those days. Now with Nios2 it seems to be impossible to make your own library? Or do I miss something. I can generate syslibs and other things I dont'really need, but not an ordenary archive (that is of course linked in before the standard C (or is it newlib now)). Is Altera planning to change over the whole system again for NIOS 3 ? I tried also the 'legacy' way of doing it, but then the linker generates an error on cpp files (something with the destructors?), even with the simples example where I putted a class in. Something else about interrupt latency, has anyone already found a way to reduce it further than 2 to 4 microseconds running from external SRAM and 50Mc? I think jumping to a single interrupt-service address is somewhere the most stupid thing to do? It's just a question, but is the battle for the smallest core between Xilinx and Altera so overwhelming, that a decent interrupt controller was not allowed in NIOS2? For someones interest, if you are using the uart with NIOS2. Look at the signals and see that the promised 'fast printf' is sitting waiting till all characters are sent out. The nice thing about the bug is that the printf is OK, but all possible cycles are eaten up by the interrupt service routine that is not doing the correct things. To correct, change : copy altera_avalon_uart.c to your project dir, change TMT (line 613) to TRDY and recompile. Hope this can be a usefull help for someone. StefaanArticle: 71228
Oleg wrote:
> Yes, the option keep_hierarchy = 'yes' did realy help to solve this,
> but the area occupation increases because of this and i have no idea
> how to overcome this, or at least reduce it...???
In general, with a well thought out design hierarchy,
KEEP_HIERARCHY=TRUE generally does not have much effect on area. There
are three reasons that come to mind as to why you could see an increased
area due to KEEP_HIERARCHY. The first happens only when you do not
register the boundaries of your hierarchy (particularly the outputs).
If you have a data path that transverses several levels of hierarchy
from start to finish, it is possible when you use KEEP_HIERARCHY that
that path would not be as optimized as it could be and in order to
retain the proper footprint and logic within the hierarchy that it would
need more logic levels (LUTs) to build that data. Again, if you
register the outputs of each module hierarchy, this can not happen. The
next place that you may see in increase in logic used has to do with
resource sharing. Synthesis tools can identify arithmetic operators
(and other logic) and restructure it to use less logic. For instance:
if (SELECT)
C = A+B;
else
C = C+D;
The following logic can use one adder with two MUXes on the inputs or
use two adders with one MUX on the output. Both implementations yield
the same result but would have different logic utilization. If however
it was coded so that one adder is in one hierarchy and one is in
another, that opportunity to combine the two adders could not happen.
Again, with registered outputs at the hierarchy boundaries, this becomes
a less likely scenario but can happen if you do not. Finally, synthesis
tools do some optimizations like removal of duplicate registers that can
be obstructed with the use of KEEP_HIERARCHY. In general this should
not account to a large increase in design size and is somewhat rare but
can certainly happen.
The other thing that can happen with hierarchy retention is a
performance degradation. This too generally only has a significant
effect on designs with poorly chosen hierarchy boundaries. The biggest
cause of performance degradation with this methodology is the same as I
mentioned above where added logic levels (LUTs) are needed to form a
function in which the data path spans several hierarchy layers. This
not only adds to the resources necessary but also adds to the time it
takes to get from one point to another. Another time performance can be
hindered by KEEP_HIERARCHY is with register duplication. If an input or
output signal at a hierarchy boundary has several sources or loads (a
high fan-in/fan-out) it can limit the synthesis and back-end tools
ability to do register or logic duplication to ease timing. Since you
are trying to keep the original boundaries to the interface, the tools
can not add ports to the interface in order to do this duplication.
Keeping hierarchy for a design has many benefits for improved constraint
entry, floorplanning and verification and sometimes can improve
performance and reduce runtimes but you must be careful in how the
original design hierarchy is laid out in order to not get the opposite
effects. So what should you do. As mentioned before, register the
hierarchy boundaries where possible (especially the outputs). This is a
good design practice to follow in general. Understand where resource
sharing opportunities exist in your design and change the hierarchy to
take advantage of this to save resources and can also improve timing.
Also, be alert to where you feel critical timing paths may exist in the
design (i.e. paths with lots of logic level, high fan-outs, etc.) Try
to either keep those contained within a level of hierarchy, do manual
duplication or other design practices to ensure this methodology will
not hurt you more than it will help you. And finally, be selective in
where you keep your hierarchy. rarely is it advantageous to keep
everything in the design. On retain the hierarchy that will help you
with constraint entry, floorplanning and/or verification and let it
flatten elsewhere. In general, the most benefits are seen when you do
not take a global approach of keeping or flattening a design and instead
are selective in what hierarchy should stay and what should go.
A fairly good document on this topic is the Synthesis and Verification
Design Guide
(http://toolbox.xilinx.com/docsan/xilinx6/books/docs/sim/sim.pdf). In
Chapter 6 there is a section called Design hierarchy and Simulation that
explains most of the concepts I mention above. Also there is a section
in the "General HDL Coding Styles" chapter on resource sharing if you
are interested.
Hope this helps.
-- Brian
Article: 71229Look at the bd option on bitgen. Also, you should be able to use an exact guide file for the map/par if all else fails.Article: 71230
I've posted below a cut from my .par file. I'm attempting to use an "exact"
guide file. You'll note it has about 25% of the nets fall under "Rejected
Implicit/Internal." This seems to be a trend; can someone explain that to
me? Perhaps you could explain this report in general? (i.e., why it lists
things twice, why it was unable to route all the signals that had the names
matching, etc.)
Xilinx Place and Route Guide Results File
=========================================
Guide Summary Report:
Design Totals:
Components:
Name matched: 2363 out of 2964 79%
Total guided: 2363 out of 2363 100%
Signals:
Rejected Implicit/Internal: 2046 out of 8166
LOGIC0/LOGIC1 nets ignored: 2 out of 6120
Name matched: 6118 out of 6118 100%
Total guided: 3331 out of 6118 54%
Total connections guided: 12000
Guide file: ".\last\HWHW_Elements_C_PEn_RPEn_R_R.ncd" Guide mode:
"exact"
Components:
Name matched: 2363 out of 2964 79%
Total guided: 2363 out of 2363 100%
Signals:
LOGIC0/LOGIC1 nets ignored: 2 out of 8166
Name matched: 6118 out of 8164 74%
Total guided: 3331 out of 6118 54%
Total connections guided: 12000
For a detailed guide report refer to the "HWHW_Elements_C_PEn_RPEn_R_R.grf"
file.
Device utilization summary:
Number of External IOBs 96 out of 824 11%
Number of LOCed External IOBs 96 out of 96 100%
Number of RAMB16s 4 out of 144 2%
Number of SLICEs 2858 out of 33792 8%
Number of BUFGMUXs 5 out of 16 31%
Number of DCMs 1 out of 12 8%
--
Prepend a 'b' to email me. Thanks.
Article: 71231thanks for the help john_H and Jim Granville! It's working! Bruno "Jim Granville" <no.spam@designtools.co.nz> escreveu na mensagem news:W_0Hc.6873$NA1.634567@news02.tsnz.net... > Bruno Cardeira wrote: > > Hello everyone! > > Can anyone tell me or suggest a way to capture a RC servo PWM signal with a > > Xilinx CPLD in ABEL?. When the pulse duration is 1ms the digital value is > > logic 0, when is 2 ms the digital output is a logic 1. > > In building block terms, this is a monostable and a D register. > In a CPLD a monostable is built as an edge-reset-counter-compare. > You could consider hysteresis on the time threshold, as the 1-2ms > windows are usually linear. > > If it is multichannel RC, there is a frame signal to consider too. > > -jg >Article: 71232
Your better off using Webpack 6.2 (free download ) See http://www.xilinx.com/products/design_resources/design_tool/index.htm Anna Acevedo - Manager Xilinx University Program onyx wrote: > I am currently using Cypress programmable logic but > they have announced some that some products will be > discontinued. I am looking at the Xilinx 4.2i > (obtained via Wakerly's book) > I am wondering how the Xilinx chips supported > by 4.2i are programmed. I am using the JTAG stuff > from Cypress right now. > > Also, how extensive is the product support in 4.2i. > Can "reasonably" big chips be programmed, etc. > > DaveArticle: 71233
Fred Ma <fma@doe.carleton.ca> wrote in message news:<40EF0407.8F0A430E@doe.carleton.ca>... > I've been reading papers about routing in island-style FPGAs. Most > cite Xilinx architectures, though I've looked at a few papers about > H-tree networks. Often, there is a simplified model being used. > There is mention (kind of dated) that commercial routers use > derivatives of maze routing, with some more recent mention of channel > routing. Is there some papers that can give a good idea of how the > real industry software does global and detailed routing, what > algorithms are actually used? What is the typical lag time between > the advent of certain approaches in conference/journal papers versus > uptake in commercial routers? I'm kind of curious how much I can > should trust the papers as an indication of actual practice. As well, > I am still in rummaging mode, and have yet to rummage into a paper > that shows how the switches in the switch boxes are actually explored > to get detailed routing, given a non-full crossbar. I've looked at > > Wu &Tsukiyama et al.: Graph analysis of 2D FPGA routing > > but I'm hoping to rummage into something more applied. 1 On optimum switch box designs for 2-D FPGAs Hongbing Fan; Jiping Liu; Yu-Liang Wu; Chak-Chung Cheung; Design Automation Conference, 2001. Proceedings , 18-22 June 2001 Pages:203 - 208 2 General models and a reduction design technique for FPGA switch box designs Hongbing Fan; Jiping Liu; Yu-Liang Wu; Computers, IEEE Transactions on , Volume: 52 , Issue: 1 , Jan. 2003 Pages:21 - 30 3 Not necessarily more switches more routability [sic.] Yu-Liang Wu; Chang, D.; Marek-Sadowska, M.; Tsukiyama, S.; Design Automation Conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific , 28-31 Jan. 1997 Pages:579 - 584 4 The effect of switch box flexibility on routability of field programmable gate arrays Rose, J.; Brown, S.; Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990 , 13-16 May 1990 Pages:27.5/1 - 27.5/4 5 General models for optimum arbitrary-dimension FPGA switch box designs Hongbing Fan; Jiping Liu; Yu-Liang Wu; Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on , 5-9 Nov. 2000 Pages:93 - 98 6 Graph based analysis of 2-D FPGA routing Yu-Liang Wu; Tsukiyama, S.; Marek-Sadowska, M.; Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , Volume: 15 , Issue: 1 , Jan. 1996 Pages:33 - 44 7 On improving FPGA routability applying multi-level switch boxes Jiping Liu; Hongbing Fan; Yu-Liang Wu; Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific , 21-24 Jan. 2003 Pages:366 - 369 8 On computational complexity of a detailed routing problem in two dimensional FPGAs Yu-Liang Wu; Shuji Tsukiyama; Malgorzata Marek-Sadowska; VLSI, 1994. 'Design Automation of High Performance VLSI Systems'. GLSV '94, Proceedings., Fourth Great Lakes Symposium on , 4-5 March 1994 Pages:70 - 75 9 On optimal hyperuniversal and rearrangeable switch box designs Hongbing Fan; Jiping Liu; Yu-Liang Wu; Chak-Chung Cheung; Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , Volume: 22 , Issue: 12 , Dec. 2003 Pages:1637 - 1649 10 A global routing model for universal switch box design Hongbing Fan; Jiping Liu; Yu-Liang Wu; Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on , Volume: 1 , 17-20 Dec. 2000 Pages:78 - 81 vol.1Article: 71234
"ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0407120157.6cf038c1@posting.google.com... > Hi, > > does someone know links to FPGA/CPLD related sites about > VHDL design of VGA controller, hsync, vsync, composite sync in general ? > > I would appreciate your help. > > Kind regards try http://www.fpga.nl/index.html?lancelot.html which is a working VGA implementation for an Altera Cyclone, have seen it working ;)Article: 71235
I just started playing with NIOS and NIOS-II: It's interesting because I got
a taste of both worlds. I think they have made a mistake with the NIOS-II
IDE- they should have stayed with Cygwin for the SDK. I liked the NIOS-I
"Germs" bootloader, even if it wastes a RAM on the chip. I don't like the
undocumented JTAG console port- who is going to design this into their
product? It requires the IDE to use, whereas the old school console serial
port can be used with any terminal program.
At the very least, they should document the JTAG side of the console ports.
A minor point is that with NIOS-I, you can get going with the printed
quick-start guide, whereas with NIOS-II you have to run the tutorial.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 71236Phil Thank you for the dits If only one could RTFM (Read The Full Manual) - it never seems to get published these days An F* problem in its own right; but fore warned is fore armed Martin "Phil Hays" <Spampostmaster@comcast.net> wrote in message news:av25f0psef0joqr911kraedr7rbdco8q4d@4ax.com... > On Mon, 12 Jul 2004 10:26:21 +0100, "DrB" <nospam@nospam.no> wrote: > > >> There is another common issue with DCMs or DLLs that you might also be > >> having a problem with. Are you using a DCM or a DLL? > > >Your allusion to "common" DCM / DLL issues has aroused my curiosity. > > Sure. I'm not sure "common" was the correct word, but I suspected > that the original poster might have run into the following issue. > I've seen it in someone else's design. These problems are curable by > reading the fine manual (RTFM). > > RTFM # 1 "Do not use the DCM output clock signals until after > activation of the LOCKED signal. Prior to the activation of the LOCKED > signal, the DCM output clocks are not valid and can exhibit glitches, > spikes, or other spurious movement." > > You can keep the part in configuration until the DCMs are locked by a > bitgen option, or you can use the synchronized locked signal to force > reset to all state machines and all other critical logic. Better do > one of the two. The bitgen option is probably best, unless you may be > resetting the DCMs after configuration, in which case you need to do > the second. > > > I didn't think he had this issue, but I've seen it as well. In my own > design. > > RTFM # 2 "To ensure consistent locking, if a DCM is configured with > external feedback, applying a reset after configuration is strongly > recommended." > > "Strongly recommended" isn't quite correct. "Required" would be > better wording. > > > -- > Phil Hays > Phil-hays at posting domain should work for email > >Article: 71237
look up the datasheet of the video ADC/DAC in question. that should have more information than you need. it should be easy to write up state machines that do i2c programming and video sync generation/reception for the devices u use. a good place to look for is the eecs150 berkeley class http://www-inst.eecs.berkeley.edu/~cs150/sp04/ look into the docs section to get the datasheets...you might even find some verilog code...but i would encourage u to write ur own. nachiket. ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0407120157.6cf038c1@posting.google.com>... > Hi, > > does someone know links to FPGA/CPLD related sites about > VHDL design of VGA controller, hsync, vsync, composite sync in general ? > > I would appreciate your help. > > Kind regardsArticle: 71238
csim036@ec.auckland.ac.nz (Colin) wrote in message news:<eeab73c0.0407072122.3ceee0e@posting.google.com>... > Hi, > > I would like to know if the Ethernet packets sent through the Nios > Ethernet Kit, do they have a 32-bit CRC as the trailer. > > If there is a CRC trailer does the Nios software and hardware check > this automatically? And if there isn't a 32-bit CRC trailer, how can > we calculate and add this? > > Thanx Hi, In addition to the other reply on your question: end of frame CRC (sometimes called FCS) can be calculated in hardware on many Ethernet MACs; this way it is done independently of the CPU. I'm not sure if all MACs do this, but when I was messing with the opencores.org Ethernet MAC it had this capability... the software that talks to the MAC had to enable CRC generation on a frame-by-frame basis -- so given this I would highly recommend getting the data sheet of the Ethernet MAC you're using to see if it supports this feature. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 71239
fpgadev@yahoo.com (AndyAtHome) wrote in message news:<29ab33c4.0407111311.6b14f944@posting.google.com>... > Hi All, > > I'm need to interface a Xilinx Virtex to a PCI Bus. The Xilinx PCI IP > core is too costly for the volumes I will be building, so I'm looking > at PCI controller chips. > > From experience can anybody recommend a vendor, such as Quicklogic, > AMCC, Tundra, etc. I've used PLX 9030 and 9656 in different designs, and they're actually pretty easy to use. The local bus is fairly straightforward. I don't think they have Verilog or VHDL models of their local bus. I did write my own, based on the data sheets, and it matched the real hardware (always a bonus). I also did a design with the QuickLogic QL5064. The local bus (inside the FPGA) is also fairly straightforward and their simulation models are correct. It's also fast -- I set up a DMA test from one QL5064 (as a master) to another (as a slave) behind a bridge and I got damn near max PCI64/66 bandwidth. The main downside to the part (other than its expense -- $110 a pop) is that it's an OTP BGA, so you'll need to use a fairly expensive socket and be prepared to burn through a bunch of chips. My current design is based on a roll-my-own PCI interface in an FPGA, for two reasons: 1) no room on the board for a PLX (or other) controller chip), and 2) my application requires a DMA engine that I don't think maps too well to Brand A or Brand X's IP. I will also say that a PCI bus analyzer is mandatory. --aArticle: 71240
Hi all I wrote a VHDL parser as part of another larger software tool about 6 years ago. The webpage, on which the parser is, is going to be retired soon. So, if anyone is interested, here is a link to my parser: http://www.cecs.uci.edu/~iesag/oldPage/Topts/ Regards SumitArticle: 71241
Hi guys:
How fast is a 10-bit mutiplier in FPGA?
Frigile
Article: 71242Xia, Signed, or unsigned? Hard multiplier core (as in Virtex II, II Pro, Spartan III, Virtex 4), pipelined, or non-pipelined? Soft multiplier core (built from LUTs)? Constant multiplier, or one which allows both inputs to be variables? http://www.xilinx.com/ipcenter/catalog/logicore/docs/mult_gen.pdf The unsigned harware multiplier in VII Pro is 1.81 ns for a 10 bit multiply (fastest speed grade). So if you can pipeline it, and feed it fast enough that would be ~ 2ns per 10 bit X 10 bit multiply, or 500 million multiplies per second..... And with 444 multipliers in the largest part, that is one heck of a lot of multiplying action. Austin xia wrote: > Hi guys: > How fast is a 10-bit mutiplier in FPGA? > > Frigile > >Article: 71243
"Vanheesbeke Stefaan" <svhb@pandora.be> wrote in message news:<h9BIc.183520$Zg1.8783987@phobos.telenet-ops.be>... > Hello, > > I did a lot of work since the begining of NIOS(1) to put some libraries > toghether with stuff that wasn't supported those days. Now with Nios2 it > seems to be impossible to make your own library? Or do I miss something. I > can generate syslibs and other things I dont'really need, but not an > ordenary archive (that is of course linked in before the standard C (or is > it newlib now)). > > Is Altera planning to change over the whole system again for NIOS 3 ? Hopefully not - we wanted to provide a SW environment suitable for people to port more code into working with Nios. In the Nios I days our SDK, while quick/easy/efficient, was rather processor & peripheral-specific and a lot of software engineers were after the environment you see with HAL & Nios II. > > I tried also the 'legacy' way of doing it, but then the linker generates an > error on cpp files (something with the destructors?), even with the simples > example where I putted a class in. The intention of the legacy SDK mode was to support existing customers' SW flows who just wanted to replace processor cores -- if this is a big problem feel free to email me and we can discuss the destructor problem. > > Something else about interrupt latency, has anyone already found a way to > reduce it further than 2 to 4 microseconds running from external SRAM and > 50Mc? > I think jumping to a single interrupt-service address is somewhere the most > stupid thing to do? > It's just a question, but is the battle for the smallest core between Xilinx > and Altera so overwhelming, that a decent interrupt controller was not > allowed in NIOS2? > Allow me to explain how it works - hopefully that is useful to you: As with any processor there are two components to ISR latency: Hardware (IRQ assertion to exception SW start) Software (what you do to call your ISR) The "interrupt controller", in the traditional sense, isn't some big scary slow thing. Nios II operates by finishing execution of whatever is in the pipeline before launching off to service an interrupt. Most of the time this is speedy *but*, if you're doing things like repeated loads/stores from/to a slow external memory, latency can go up as those instructions need to finish. This in itself isn't different from Nios I. What is different from Nios I is that no longer have the windowed register file (something that was discussed at length earlier in this group), which has reduced the worst-case latency substantially (although for the vast majority of ISRs in Nios I, you didn't go to a new set of registers, something competitive marketing organizations would tend to skew a bit!). Next, software: so you respond to IRQ going high - you have a situation where registers need to be pushed to the stack, figure out if you have a HW or SW exception, etc. We provide a default, Altera-supported ISR funnel for your convenience, but there is no rule that says you have to use it. The code is located in the altera_nios2 component folder of your installation (nios_isr_handler.c/.s for the legacy SDK; alt_exception.S for the HAL) contain the documented source. If your application is very specialized and you only want to do the quickest possible jump upon exception handler entry, this is the place to do it. It may be advisable to place the exception handling code itself into a low-latency memory (SRAM, or preferably, on-chip), to further reduce latency. > > For someones interest, if you are using the uart with NIOS2. Look at the > signals and see that the promised 'fast printf' is sitting waiting till all > characters are sent out. The nice thing about the bug is that the printf is > OK, but all possible cycles are eaten up by the interrupt service routine > that is not doing the correct things. To correct, change : copy > altera_avalon_uart.c to your project dir, change TMT (line 613) to TRDY and > recompile. > Hope this can be a usefull help for someone. > > Stefaan I will definitely take a look at this - thank you for pointing it out. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 71244
Jesse Kempa wrote: [big snip] > I will definitely take a look at this - thank you for pointing it out. > > Jesse Kempa > Altera Corp. > jkempa at altera dot com Jesse, It is great to see you (and Altera) on the newsgroup. At my place of employment, (my alter ego is richard dot pennington at med dot ge dot com) we use a lot of Altera parts (and Nios). Great stuff. -Rich -- Richard Pennington Email: rich@pennware.com http://www.pennware.com ftp://ftp.pennware.comArticle: 71245
Just curious while running P&R in ISE during the placement part it runs through several phases, 1.1, 2.2, 3.3, 4.5, 5.8, etc usually during phase 5.8 I see several rows of text containing just dots(...), there are different numbers of dots per line. Wut do these dots mean? MattArticle: 71246
Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com> wrote in message news:<ccpkhu$9i8$1@ail.sri.ucl.ac.be>... > Hal Murray wrote: > >>What is an input for one chip of the bus is an output for another one. > >>So : > >>Why does t_val need to be min 2ns ? For the one that samples the signal, t_h must be 0ns. > >>Why max 11ns ? Since setup time is min 7ns ... > >>Also, I suppose that the output signal that must be set within 2ns->11ns will only be sampled by the receiver side at the next clock cycle. > > > > > > The differences in times from what you might quickly calculate cover > > two areas. One is clock skew between the chips. The other is the time > > for the signal to get from one chip to the other. With several chips > > on a "bus", that can be a lot longer than the simple speed of light delays. > > > > Ok, so that means that the output of my FPGA must be stable for at least 2ns after receiving the clock and then change before 11ns after clock. > How can I ensure that in my VHDL code ... > > > > Sylvain Munaut Hi Sylvain, You can't ensure that happens just by coding your VHDL in a certain way. You need to set appropriate timing constraints to ensure that synthesis, placement and routing all work on the proper paths, and achieve the desired delays. The precise syntax varies from tool to tool. For Altera's CAD suite (Quartus), you would use the assignment editor to set Tco 11 ns minTco 2 ns Tsu 7 ns Th 0 ns That would set these constraints for every IO in the design. If you want different constraints for different IOs, you make assignments to specific IOs. You should also the timing settings dialog to make a clock frequency setting of 33 MHz to your PCI clock. If you really want to set these constraints in your VHDL, you can by embedding the constraints in the Quartus Tcl command format as comments in your VHDL. See the Quartus help for the details of this format. Quartus will try to get short routes for signals on Tsu or Tco critical paths. For paths that are in danger of failing their Th or minTco constraints, Quartus will add routing delay to slow them down. You have to code your VHDL so that it is possible to meet your timing constraints. For 33 MHz PCI that isn't too hard. Make sure you don't put logic after your output registers, and make sure you don't put any more logic than you need on the Tsu-critical paths (from input IO to registers). Regards, Vaughn AlteraArticle: 71247
Hi all, Does anyone have any experience in interfacing SDRAM, SBSRAM and FLASH to MicroBlaze in Spartan-3? I am somewhat confused with the number of various memory controllers mentioned on the EDK web pages, albeit many of them don't name Spartan-3 amongst their target technologies... Can this be done with just Logicores? Thanks, /MikhailArticle: 71248
bana8@rediffmail.com (banesh) wrote in message news:<98d2c8bc.0407051155.4343fe8b@posting.google.com>... > hi, > > I want to know what is meant by clock compensation and which > clock in the design should be compensated or used as compensated clock > and advantages > of doing so in an enhanced pll. Clock compensation refers to using the PLL to align the clock at some point in your design with a reference clock edge. Typically the reference clock comes from an input IO in your design. The most common compensation is to align the clock edge that the FPGA registers receive with the clock edge of the reference clock. That means the PLL is compensating for the delay of the global clock network used to reach those registers, by generating a clock that is earlier in time by the same delay as the clock network. The enhanced PLLs in Stratix have several compensation modes: Normal mode: compensate for the delay of a clock distributed on a global network -- chip-wide global or regional (quadrant) global. Zero delay buffer: Compensate for the delay to an output IO. Generally used when you want to send out a clock to your board that is phase-aligned to the input clock (i.e. has no delay versus the input clock). External feedback: Lets you take the clock signal out to your board via an output IO, and send it back into the Stratix chip via an input IO. All the delay in this path will be compensating out by the PLL. No compensation: Don't shift the clock back in time to compensate for any delay. What compensation is best depends on what you're trying to do. Normal is the default, and if you have no reason to believe you need one of the other modes, then you should just leave the compensation at the default. See http://www.altera.com/literature/hb/stx/ch_1_vol_2.pdf for more details. Hope this helps, Vaughn AlteraArticle: 71249
"Paul Leventis (at home)" wrote: > > > I'll look more closely at Pathfinder to see if it details how the > switchbox > > settings are determined. > > I'm not quite sure what you mean by this. If you're referring to how the > topology of the switchbox is determined (an architectural decision), there > are some other papers I can point you to. > > From a routing algorithm perspective, it is really quite simple. You > represent the entire chip as a graph where each node represents a routing > resource -- a block input, block output, or routing wire. Directed edges > are placed between these nodes to represent the presence of a (programmable) > connection from one resource to another. So a swich box that is not a > complete cross-bar is encoded in this graph as edges. For each net, the > router starts at the source block output, traverses the edges from that > node, and assigns a desirability/cost to each of the nodes seen and places > them in a heap. It then removes the best node from the heap and repeats > from there until it hits the desired destination (a block input). This is > known as an a-star or best-first traversal, and clearly all the > work/intelligence lies in how you cost the nodes (including a prediction of > future cost), how you guide the router to correct congestion, etc. For a > multi-terminal net, the routing thus far is placed on the heap and the > router expands from there. There are optimizations that can be done to > reduce the amount of re-expansion of the wavefront, and other techniques for > quickly routing high-fanout nets. I sort of got lost with the heap, but don't worry, I was just getting a rough idea. If needed, I will look up A* (I have papers on it). The representation for wires/switches above matches that in Pathfinder, and I noticed that Betz's VPR also has tricks to cut down some work in restarting the wave front for multiterminal nets. The use of arcs to represent switches seems to get rid of the division between detailed and global routing. > Global routing (not worrying about precise wires and switch box settings) is > done using the same algorithm, except that rather than nodes representing > one wire, you represent a group of wires with a node of capacity = channel > width. A well-written global + detailed router does not require a global > route and performs fast enough that there really isn't any point to look at > global routing (in FPGAs) anymore. Yes, I was noticing that in recent papers. > We don't like to tell each other what we do in our tools for obvious reasons > :-) VPR served as the basis for Right Track CAD's work, and Right Track > provided Altera with enhanced place & route results for their FLEX10K > products in MaxPlus II. What the algorithms were before or what they've > become since is not a matter of public record. Aaawwww. OK. Thanks. I understanding why there is a paucity of such information. Fred -- Fred Ma Dept. of Electronics, Carleton University Ottawa, Ontario, Canada
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