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Authors (S)

S:
    124276: 07/09/17: Directing data to DDR
S . Vadlamani:
    12452: 98/10/12: FPGA info..
s cote:
    32911: 01/07/11: Re: Simulation problems with BlockRAM's INIT values !
S Embree:
    48222: 02/10/14: Spartan II: CLKDLL
    48224: 02/10/14: Re: Clk Problem
    53014: 03/02/28: IBUF : Pullup Resistors
    53023: 03/02/28: Re: IBUF : Pullup Resistors
S Gupta:
    64325: 03/12/28: Release of SPARK C-to-VHDL Parallelizing High Level Synthesis tool
    64487: 04/01/05: Release of SPARK C-to-VHDL Parallelizing High Level Synthesis tool
    64755: 04/01/12: SPARK C-to-VHDL Synthesis tool now supports Windows & Xilinx XST
S Lam:
    20790: 00/02/22: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
S Matthews:
    115796: 07/02/21: Re: Nexys from Digilent... aka, binge hacking
    115798: 07/02/21: Re: Business is not "as usual"
S P:
    47711: 02/10/02: virtex 2 -5i vs -6
    47956: 02/10/08: shared clock routing resource virtex 2 - adjacent IOB
S Ramirez:
    40385: 02/03/06: Re: Is there a ver 7.1 of Sunplify?
    40513: 02/03/08: Re: suggestion to comp.arch.fpga
    69856: 04/05/22: Re: I2C Slave
S. Bernstein:
    137951: 09/02/03: Implementation of Xilinx Aurora protocol with error correction
    138042: 09/02/04: Re: Implementation of Xilinx Aurora protocol with error correction
    138657: 09/03/03: Virtex6 Virtex4 FPGA compatibility
S. Hagenkoetter:
    96171: 06/01/31: Constraining a 50 MSPS DAC Interface
    96235: 06/02/01: Re: Constraining a 50 MSPS DAC Interface
S. Ramirez:
    24821: 00/08/20: Re: Permanently programming FPGAs
    24828: 00/08/20: Re: Permanently programming FPGAs
    24855: 00/08/20: Re: Permanently programming FPGAs
    24859: 00/08/21: Re: timing simulation vs functional one
    24876: 00/08/21: Re: Distributor attitude !!
    24896: 00/08/21: Re: Looks like Xilinx is at it again!
    24909: 00/08/22: Re: Looks like Xilinx is at it again!
    24931: 00/08/22: Re: Mealy vs Moore FSM model
    24939: 00/08/22: Re: Mealy vs Moore FSM model
    24943: 00/08/22: Re: Mealy vs Moore FSM model
    24972: 00/08/23: Re: Mealy vs Moore FSM model
    25031: 00/08/24: Re: availability of Spartan II
    25048: 00/08/24: Re: largest fpga in the industry
    25058: 00/08/25: Re: largest fpga in the industry
    25071: 00/08/25: Re: largest fpga in the industry
    25091: 00/08/25: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
    25136: 00/08/27: Re: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
    25169: 00/08/29: Spartan II vs. Virtex
    25175: 00/08/30: Re: Xilinx and CD databooks (rant)
    25194: 00/08/30: Re: Spartan II vs. Virtex
    25297: 00/09/05: Re: XC4013 available
    25377: 00/09/08: Re: VirtexE availability?
    25401: 00/09/10: Re: VirtexE availability?
    25408: 00/09/11: Re: virtex shape
    25433: 00/09/11: Re: VirtexE availability?
    25477: 00/09/12: Re: Clock skew in XILINX CPLD
    25528: 00/09/13: Re: Clock skew in XILINX CPLD
    25529: 00/09/13: Re: VirtexE availability?
    25544: 00/09/13: Re: Virtex 'shutdown' phenomenon
    25543: 00/09/13: Re: Clock skew in XILINX CPLD
    25569: 00/09/14: Re: Clock skew in XILINX CPLD
    25590: 00/09/14: Re: Simon,Floating Inputs
    25591: 00/09/14: Re: Simon,Floating Inputs
    25592: 00/09/14: Re: FPGA Express Strikes Again!
    25608: 00/09/15: Re: Simon,Floating Inputs
    25615: 00/09/15: Re: Simon,Floating Inputs
    25635: 00/09/15: Re: Simon , decoupling caps
    25680: 00/09/17: Re: Clock skew in XILINX CPLD
    25690: 00/09/17: Re: MAX PLUS 2
    25694: 00/09/17: Re: MAX PLUS 2
    25695: 00/09/17: Re: MAX PLUS 2
    25696: 00/09/18: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
    25697: 00/09/18: Re: VirtexE availability?
    25706: 00/09/18: Re: Clock skew in XILINX CPLD
    25730: 00/09/18: Re: Freelance Designer Needed: Protel & FPGA
    25741: 00/09/19: Re: Freelance Designer Needed: Protel & FPGA
    25753: 00/09/19: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
    25771: 00/09/20: Re: Freelance Designer Needed: Protel & FPGA
    25812: 00/09/21: Re: Freelance Designer Needed: Protel & FPGA
    25835: 00/09/22: Re: Announce: Free HC11 CPU Core
    25843: 00/09/22: Re: Announce: Free HC11 CPU Core
    25856: 00/09/23: Re: Announce: Free HC11 CPU Core
    25906: 00/09/26: Re: Announce: Free HC11 CPU Core
    25933: 00/09/27: Re: FPGA Express strikes again! Xilinx response
    25967: 00/09/28: Re: Synplicity vs Xilinx FPGA Express
    25969: 00/09/28: Re: atmel verses altera
    25982: 00/09/29: Re: some question about synplify tool
    26001: 00/09/30: Re: Funny Message
    26016: 00/09/30: Re: Altera FPGA experts needed
    26033: 00/10/01: Re: Altera FPGA experts needed
    26128: 00/10/05: Re: DLL unlocking
    26229: 00/10/09: Re: Analogue FPGAs ?
    26316: 00/10/11: Re: Analogue FPGAs ?
    26317: 00/10/11: Re: palasm
    26390: 00/10/14: Re: palasm
    26392: 00/10/14: Re: clk'event
    26453: 00/10/16: Re: palasm
    26551: 00/10/20: Re: Very Lucrative FPGA Jobs
    26798: 00/10/30: Re: Very Lucrative FPGA Jobs
    26799: 00/10/30: Re: Very Lucrative FPGA Jobs
    26816: 00/10/31: Re: Undergraduate PLD Studies
    26832: 00/10/31: Alliance 3.2i
    26837: 00/10/31: Re: Alliance under Linux?
    26844: 00/11/01: Re: Alliance under Linux?
    26868: 00/11/01: Re: Alliance under Linux?
    26869: 00/11/01: Re: Hardware Engineer position in Pittsburgh
    26899: 00/11/02: Re: Xilinx T-Shirt
    26955: 00/11/05: Re: ACEX1K vs FLEX10K
    26961: 00/11/05: Re: ACEX1K vs FLEX10K
    27004: 00/11/07: Re: Flex10KA RAM Inferencing with Synplify 5.1.5a
    27063: 00/11/09: Microprocessor Verilog/VHDL Models
    27071: 00/11/09: Re: Microprocessor Verilog/VHDL Models
    27081: 00/11/10: Re: Non routable design
    27098: 00/11/10: Re: Microprocessor Verilog/VHDL Models
    27227: 00/11/16: Re: Microprocessor Verilog/VHDL Models
    27278: 00/11/17: Re: Microprocessor Verilog/VHDL Models
    27337: 00/11/18: Re: Altera MAX+PlusII v.s. Xilinx Foundation
    27695: 00/12/04: Re: Hey there anybody!!
    27780: 00/12/08: Re: XC9500/9500XL CPLD Clocks
    27924: 00/12/15: Re: Verilog or VHDL
    27989: 00/12/19: Re: ActiveHDL 4.1?
    27990: 00/12/19: Re: Verilog or VHDL
    28109: 00/12/21: Re: Help with encoder/decoder
    28119: 00/12/21: Re: Help with encoder/decoder
    28330: 01/01/07: Re: which fpga architecture?
    28545: 01/01/17: Re: FPGA driving clock line
    28547: 01/01/17: Re: Looking for prototyping board
    28553: 01/01/17: Re: FPGA driving clock line
    29092: 01/02/06: Re: .ucf commands
    29134: 01/02/07: 8B/10B Encoding
    29146: 01/02/08: Re: Xilinx vs Altera
    29520: 01/02/24: Re: Is anybody using Quicklogic PCI/FPGA devices?
    29649: 01/03/03: Re: Metastability, Asynchronous Signals, & Asynchronous design
    29658: 01/03/04: Re: Metastability, Asynchronous Signals, & Asynchronous design
    29662: 01/03/04: Re: webpack ISE synthesis fails with exit code: 0002
    29664: 01/03/04: Re: Full Time - No contractors
    29674: 01/03/05: Re: Metastability, Asynchronous Signals, & Asynchronous design
    29678: 01/03/05: Re: Actel's FPGA : A54SX32A
    29739: 01/03/07: Re: Actel's FPGA : A54SX32A
    29740: 01/03/07: Re: Full Time - No contractors
    29791: 01/03/10: Re: $HOT JOBS$ ASIC / FPGA / VLSI designers needed - Canada
    30424: 01/04/07: Re: xilinx price lists
    30433: 01/04/08: Re: Handel-C
    30471: 01/04/10: Re: Handel-C
    30490: 01/04/11: Re: Handel-C
    31649: 01/06/01: Re: PowerPC?
    31700: 01/06/03: Re: one state machine
    32133: 01/06/15: Re: From EDF to VHDL?
    32189: 01/06/19: Re: Verilog or VHDL?
    32524: 01/06/29: Re: Is the Grass Greener for an Engineer in the USA?
    32670: 01/07/04: Re: Is the Grass Greener for an Engineer in the USA?
    35326: 01/09/28: Re: Active-HDL back annotated simulation and PC memory usage
    35461: 01/10/06: Synplify vs. Leonardo
    35526: 01/10/09: Synplify vs. Leonardo
    35527: 01/10/09: Synplicity/Leonardo License Agreement Information
    36989: 01/11/28: Re: What does a 'Slice' refer to in a Xilinx MAP report?
    37435: 01/12/11: Re: About special promotion of Synplicity's Synplify? FPGA synthesis solution
    37466: 01/12/11: Re: About special promotion of Synplicity's Synplify? FPGA synthesis solution
    37476: 01/12/12: Re: Initialization of RAM
    37503: 01/12/13: Re: Initialization of RAM
    37559: 01/12/14: Re: About special promotion of Synplicity's Synplify? FPGA synthesis solution
    37657: 01/12/18: Defauolt Should Be "Inputs and Outputs" For IOBs
    37724: 01/12/19: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
    37725: 01/12/19: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
    37736: 01/12/19: Re: Default Should Be "Inputs and Outputs" For IOBs
    37737: 01/12/19: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
    37774: 01/12/20: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
    37826: 01/12/21: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
    37986: 01/12/29: Re: Spartan LUT question
    37996: 01/12/29: Re: Spartan LUT question
    38047: 02/01/03: Re: A Fast counter in VHDL?
    38099: 02/01/04: Re: asic vs. fpga
    38125: 02/01/06: Re: how do i program a Spartan FPGA
    38867: 02/01/27: Re: New Risc5x cpu core on Opencores
    39403: 02/02/08: Re: Design with Triscend E5
    39724: 02/02/17: Re: FPGA choices and questions
    40225: 02/03/02: Re: share two months salary with you if you have job information
    40527: 02/03/08: Re: Sandwich board at ESC
    40627: 02/03/12: Re: Article in March Embedded Systems - "The Death of Hardware Engineering"...
    40671: 02/03/12: Re: Article in March Embedded Systems - "The Death of Hardware Engineering"...
    40722: 02/03/13: Re: Synthesis tools comparison?
    40746: 02/03/14: Re: Synthesis tools comparison?
    42595: 02/04/28: FlexLM
    45132: 02/07/13: Re: Foundation 2.1i --- does it support vertexII?
    45159: 02/07/14: Re: Foundation 2.1i --- does it support vertexII?
    45610: 02/07/29: Re: secure FPGA
    45701: 02/08/01: Re: about amplify/synplify
    45782: 02/08/05: Re: ATMEL GAL
    45888: 02/08/09: How Fast FIFOs?
    45994: 02/08/13: Re: "flip flop" and "register"
    46289: 02/08/24: Why Can't Engineers Be Like Doctors?
    48682: 02/10/22: Re: Buy fpga
    51171: 03/01/05: Re: How can you tell if your clock signals are on the clock net?
    51365: 03/01/12: Anyone Used DCI in Virtex-2?
    52196: 03/02/04: Re: Difference between : CPLD , FPGA , ASICS
    52237: 03/02/05: Re: Difference between : CPLD , FPGA , ASICS
    53364: 03/03/12: Re: Prob. with data-input of SDRAM-Controller
    58287: 03/07/19: Re: Digital Design with just one clock at one edge
S.C.Lim:
    3163: 96/04/17: Looking for FPGA Boards taking Xilinx 4000 series FPGA
s.d.:
    52062: 03/01/30: Re: Random number generator
S.G. Wood, Jr.:
    2501: 95/12/20: Bit Stream Parser
    2651: 96/01/19: PLD JDEC Files
S.Gailhard avec un h:
    8233: 97/12/02: PCI cores and PCI bus HDL models
S.H.McBader:
    41289: 02/03/25: Re: Maximum device usage for successful PAR
S.Ivanov:
    27399: 00/11/20: Spartan and XC4000 configuration
    27424: 00/11/21: Re: Spartan and XC4000 configuration
    27425: 00/11/21: Re: Spartan and XC4000 configuration
S.j:
    118430: 07/04/26: pcis3base, cesys
S.J.B.Acock:
    1245: 95/05/22: Xilinx Download
    2209: 95/11/02: Xilinx XSI FPGA User Guide
    3665: 96/07/10: FPGA - RAM interfacing
S.JULHES:
    31243: 01/05/16: help for BGA ?
S.K. Sharma:
    23768: 00/07/07: Quattus Automatic clock Selection
    23845: 00/07/12: Re: Timing Simulation for Alter FPGAs
    24579: 00/08/14: Quartus/Certify results mismatch
    28362: 01/01/10: Re: APEX
S.Perri:
    6851: 97/07/02: Re: FPGA prototype board
<s.stanislava@gmail.com>:
    123571: 07/08/30: Re: Output signals not synchronized
S.T.:
    89350: 05/09/13: Re: Followup: USB cable, Xilinx XUP, EDK/ISE 7.1, Fedora Core 3
    89443: 05/09/15: Re: Followup: USB cable, Xilinx XUP, EDK/ISE 7.1, Fedora Core 3
    89725: 05/09/23: Linux USB XUP board
    89771: 05/09/26: Re: Linux USB XUP board
    89781: 05/09/26: Xilinx XUP + Linux (firmware loading problem!)
    96717: 06/02/09: OPB busmaster device
    108079: 06/09/05: Re: linux 2.4 v 2.6 on xilinx
    108687: 06/09/15: Re: Xilinx Platform Cable USB on Linux: Impact always wants to update Firmware
    109046: 06/09/20: XUP Boad User Expansion Ports
    112926: 06/12/01: EDK 8.2 Busmaster Example
    113161: 06/12/07: Re: EDK 8.2 Busmaster Example
    115256: 07/02/05: xilinx x2pro ppc custom crt0
    115267: 07/02/05: Re: xilinx x2pro ppc custom crt0
    116097: 07/03/01: xilinx block ram synthesis
    116142: 07/03/02: Re: xilinx block ram synthesis
    116582: 07/03/13: Re: xilinx block ram synthesis
    116687: 07/03/15: Re: xilinx block ram synthesis
s.timm:
    10582: 98/06/03: Xilinx Foundation
<s1r.h3nry@gmail.com>:
    104900: 06/07/08: PPC XMK bootloader for ELF files
s2:
    48087: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
    48123: 02/10/11: Re: Intel ARM 'XScale' cores as IP blocks that can be synthesized into an FPGA/ASIC?
<s2z.domain@googlemail.com>:
    157150: 14/10/18: Re: Fast and slow clocks
<s>:
    43684: 02/05/29: DCM partial reconfiguration
<s@cotts.cluon.com>:
    6098: 97/04/11: Seeking PALASM/ABEL/CUPL/?
<s_sharma@my-deja.com>:
    26183: 00/10/07: Re: programm Xilinx FPGAs via JTAG
    26184: 00/10/07: Re: Altera Internal Error
<sa@ctrlvrmt.ca>:
    11817: 98/09/11: This Website (slocomputers) was HACKED by United Hackers HQ
saad:
    96247: 06/02/01: LDPC
    134036: 08/07/22: help needed for Virtex-4
Saad Zafar:
    155717: 13/08/21: Cascaded floating-point reduction?
saar drimer:
    145253: 10/02/03: Re: synthesizing a completely empty design for an FPGA to measure
    145647: 10/02/17: Re: Data2Mem ? BlockRAM ? Init BMM and MEM
    148988: 10/09/19: Stack Exchange site for programmable logic and FPGA design
    148995: 10/09/20: Re: Stack Exchange site for programmable logic and FPGA design
    149742: 10/11/22: Re: Debugging with a single LED
    149951: 10/12/03: FPGA project structure definition
    150015: 10/12/06: Re: FPGA project structure definition
    150023: 10/12/06: Re: FPGA project structure definition
    150203: 10/12/31: Re: I Give Up!
    150353: 11/01/11: Re: Stack Exchange site for programmable logic and FPGA design
    150960: 11/02/24: Re: XST returning error code on success?
    150961: 11/02/24: Re: XST returning error code on success?
    151695: 11/05/05: boldport
    152095: 11/07/05: Re: boldport
<saardrimer@gmail.com>:
    152671: 11/09/26: Re: comparing Xilinx XC3S500E-4CPG132C vs Altera Cyclone IV FPGA
    152693: 11/10/03: Re: How do they handle shorts during the dynamic reconfiguration?
    152724: 11/10/10: Re: high speed place and route about xilinx
<sabatini@tiscali.nl>:
    100860: 06/04/19: Xilinx FPGA status after configuration.
    100864: 06/04/19: Re: Xilinx FPGA status after configuration.
sabine:
    70195: 04/06/08: Where is my Digital Up Convertor in Logicore ??!!
Sabri Berisha:
    17519: 99/08/05: Re: Watch! [2.2di7.49n]
Sabrina:
    53720: 03/03/20: Re: Excalibur bus functional model
    65303: 04/01/23: Re: Programming and debugging the Altera Cyclone family
    67500: 04/03/12: Re: anyone using nios kit APEX?
Sachin:
    64700: 04/01/11: Error message in Mapping while using Xilinx ISE 6.1.03i
    120776: 07/06/16: Re: Virtex-4 pre-configuration pull-ups
    120777: 07/06/16: Re: Virtex-4 pre-configuration pull-ups
    120778: 07/06/16: Re: Programming Question
    153123: 11/12/07: DDR2 read interface
sachin:
    127171: 07/12/13: ML505 board Compact Flash
    127455: 07/12/27: Re: ML505 board Compact Flash
Sachin Garg:
    37972: 01/12/27: IPDS 2002 Deadline extended to January 10, 2002
Sachin Vaish:
    27926: 00/12/14: Exemplar: max_load=1 gives me fanout=75
<sachink321@gmail.com>:
    98198: 06/03/06: Internal Signals in OPB EMC In XIlinx PLatform studio
    98264: 06/03/07: Re: Internal Signals in OPB EMC In XIlinx PLatform studio
    98591: 06/03/13: PROBLEMS WITH COOLRUNNER XPLA3
    98596: 06/03/13: Re: PROBLEMS WITH COOLRUNNER XPLA3
    100343: 06/04/06: Accessing compact flash?????????
    100344: 06/04/06: C H S in a Compact flash
    100400: 06/04/07: Re: Accessing compact flash?????????
    100425: 06/04/08: Re: Accessing compact flash?????????
    100568: 06/04/12: Print FAT table in a compact flash ??????????
sadadasdsa:
    31157: 01/05/13: Re: Avnet Virtex-E Development Kit
Saddle:
    12867: 98/11/03: Re: New free FPGA CPU
    12894: 98/11/04: Re: New free FPGA CPU
    20130: 00/01/28: Re: ADC to DSP... FIFO?
sadik:
    41563: 02/04/02: floorplanning for FPGA
    52199: 03/02/04: Can't start server quartus_cmp in quartus II 1.0
sadik khan:
    34540: 01/08/28: Any body used ACEX1K series for testing the design??
Saed Aryan,13325,1100,g:
    3884: 96/08/14: Inquiry on FPGA for NN HW
Saeed Nari:
    58528: 03/07/25: GL85 synthesizable code
    59162: 03/08/11: Re: GL85 synthesizable code
SAF:
    32991: 01/07/14: Which Chip Family?
    33002: 01/07/14: Re: Which Chip Family?
    33003: 01/07/14: WebPack or Foundation?
    33010: 01/07/15: Re: Which Chip Family?
    33021: 01/07/15: Re: Which Chip Family?
    33022: 01/07/15: Re: Which Chip Family?
    33037: 01/07/16: Book Recommendation (bit different)
    33061: 01/07/16: Re: Book Recommendation (bit different)
    33076: 01/07/17: Re: Book Recommendation (bit different)
    56545: 03/06/09: Re: Xilinx FFT Core Problems
    56850: 03/06/17: Re: DCMs and CLKDV not dividing correctly
saffary:
    13563: 98/12/09: xilink Parallel cable III
    14045: 99/01/09: I2C core
    15028: 99/03/03: Re: graphic Lcd control core
    14976: 99/03/01: graphic Lcd control core
    23853: 00/07/13: SerialProm programmer
Saffary:
    49310: 02/11/08: Spartan I with ISE Webpack
    49312: 02/11/08: Spartan I with ISE Webpack
Safiri H.,13310,1100,g:
    3274: 96/05/08: Implementation of a ROM
Safiri Hamidriza,13310,1100,g:
    3716: 96/07/20: Re: Hardware sort?
Sagaert Johan:
    14768: 99/02/16: Any FREE soft for XC5000 series ?
<sagarmemane4@gmail.com>:
    156486: 14/04/09: Re: MapLib:93 - Illegal LOC on symbol "clk.PAD" (pad signal=clk) or
    156487: 14/04/09: ERROR:MapLib:93 - Illegal LOC on IPAD symbol "autman" or BUFGP symbol
sagarvetal:
    150950: 11/02/24: image processing on SPARTAN-3 DSP TRAINER MODEL : MXS3FK-DSP
Saghir A. Shaikh:
    824: 95/03/08: Cost of FPGA
sahar:
    151648: 11/04/30: question about vtr
SaHiD:
    97354: 06/02/21: DSP
SAHITHI:
sai:
    112539: 06/11/24: Re: What's Nonpipelined bus mean?
    124501: 07/09/25: DRAM modules - RIMM, SODIMM,UDIMM..etc
sai a:
    63543: 03/11/25: Soft-core processor construction
Sai Sanda:
    85237: 05/06/06: FPGA I/O pin current sink
Saied Benyamin:
    1100: 95/04/27: Viewlogic VHDL for Xilinx
saijayram:
    144160: 09/11/15: Interconnecting 3v3 LVDS transmitter to 2V5 Receiver
<saira.samar@gmail.com>:
    135627: 08/10/10: ddr2 sdram xilin mig controller, mig v1.72 issue
Sajan:
    65593: 04/02/03: Re: asynchronous counter an Xilinx FPGA for a newbie
    65642: 04/02/03: Re: 4 bit divisor with flip-flop ?
    68999: 04/04/24: Re: reading files in vhdl
sajjad:
    41714: 02/04/05: Vertex 2 DCM problem
<saju@wipinfo.soft.net>:
    12082: 98/09/28: Metastability
SAKAKIHARA Kazuya:
    47107: 02/09/18: Using CVS with Quartus
<salah.kazi@gmail.com>:
    94247: 06/01/09: Study material for logic design
<salary_guide@hitechsalary.com>:
    30342: 01/04/03: salary info for FPGA/HardwareEng's
Salil Raje:
    100322: 06/04/06: Re: Xilinx java application freeze
    104400: 06/06/26: Re: Achieving timing in Xilinx EDK designs
    112836: 06/11/29: Re: modular design / PlanAhead
    119940: 07/05/29: Re: IOSTANDARD user constrain
salimbaba:
    148309: 10/07/06: spartan 3xc3s4000 daisy chain help required
    148314: 10/07/07: Re: spartan 3xc3s4000 daisy chain help required
    148335: 10/07/08: Programming individual FPGAs in a daisy chain
    148339: 10/07/08: Re: Programming individual FPGAs in a daisy chain
    148355: 10/07/15: help regarding daisy chained fpgas
    148372: 10/07/16: Re: help regarding daisy chained fpgas
    148375: 10/07/16: Re: help regarding daisy chained fpgas
    148588: 10/08/04: Logic implementation probelm
    148601: 10/08/05: Re: Logic implementation probelm
    148876: 10/09/06: Problems with timing constraints
    149100: 10/10/01: FPGA design not working!
    149103: 10/10/01: Re: FPGA design not working!
    149120: 10/10/03: Re: FPGA design not working!
    149121: 10/10/03: Re: FPGA design not working!
    149124: 10/10/04: Re: FPGA design not working!
    149125: 10/10/04: Re: FPGA design not working!
    149131: 10/10/04: Re: FPGA design not working!
    149139: 10/10/04: Re: FPGA design not working!
    149159: 10/10/05: Re: FPGA design not working!
    149220: 10/10/09: Need help with partitioning.
    149222: 10/10/09: Re: Need help with partitioning.
    149232: 10/10/11: Re: FPGA design not working!
    149248: 10/10/11: JTAG stops working!
    149251: 10/10/12: Re: JTAG stops working!
    149255: 10/10/12: Re: JTAG stops working!
    149262: 10/10/12: Re: JTAG stops working!
    149413: 10/10/22: Need help with powering FPGA
    149418: 10/10/23: Re: Need help with powering FPGA
    149471: 10/10/27: FPGA and ethernet phy problem
    149478: 10/10/28: Re: FPGA and ethernet phy problem
    149594: 10/11/09: INIT_B stays low
    150119: 10/12/15: spartan 3 xc3s4000 JTAG pins not pulled up
    150171: 10/12/24: jtag pin showing weird behavior
    150267: 11/01/07: spartan 3 xc3s1000 not getting programmed
    150290: 11/01/08: Re: spartan 3 xc3s1000 not getting programmed
    150343: 11/01/11: Re: spartan 3 xc3s1000 not getting programmed
    150360: 11/01/12: Re: spartan 3 xc3s1000 not getting programmed
    150542: 11/01/26: strange problem with RTL
    150548: 11/01/26: Re: strange problem with RTL
    150586: 11/01/27: MAXIM DS33Z44 configration issue
    150604: 11/01/27: Re: strange problem with RTL
    150904: 11/02/20: timing issues at high speed
    150907: 11/02/21: Re: timing issues at high speed
    150911: 11/02/21: Re: timing issues at high speed
    150912: 11/02/21: Re: timing issues at high speed
    150916: 11/02/21: Re: timing issues at high speed
    150921: 11/02/22: Re: timing issues at high speed
    150927: 11/02/22: Re: timing issues at high speed
    150933: 11/02/23: Re: timing issues at high speed
    150942: 11/02/24: Re: timing issues at high speed
    150962: 11/02/24: Re: timing issues at high speed
    151185: 11/03/14: ping pong buffer overflow issue
    151212: 11/03/15: Re: ping pong buffer overflow issue
    151525: 11/04/17: same RTL on two same boards giving different behaviour
    151602: 11/04/25: Re: same RTL on two same boards giving different behaviour
    151632: 11/04/27: Re: same RTL on two same boards giving different behaviour
    151636: 11/04/27: Re: same RTL on two same boards giving different behaviour
    151638: 11/04/28: Re: same RTL on two same boards giving different behaviour
    151646: 11/04/30: Re: same RTL on two same boards giving different behaviour
    151768: 11/05/15: Random behavior of xilinx simple dual port block ram
    151815: 11/05/20: Problem with xilinx 12.3 Timing Analyzer
    151839: 11/05/23: comparator fast implementation
    151840: 11/05/23: Re: comparator fast implementation
    151844: 11/05/24: Re: comparator fast implementation
    152008: 11/06/21: Re: ucf file for 32 bit counter spartan 3e S500E -4
    152077: 11/06/30: Ericsson Eurocom D1
    152085: 11/07/03: Re: Help with bidirectional interface of a FPGA with a uC
    152156: 11/07/14: FPGA not getting programmed
    152172: 11/07/15: Re: FPGA not getting programmed
    152173: 11/07/15: RTL timing issue
    152178: 11/07/15: Re: RTL timing issue
    152184: 11/07/16: Re: RTL timing issue
    152192: 11/07/18: Re: FPGA not getting programmed
    152194: 11/07/18: Re: FPGA not getting programmed
    152197: 11/07/18: Re: FPGA not getting programmed
    152499: 11/08/29: Boundary scan
    152531: 11/09/06: interfacing Xilinx platform usb jtag with other vendor devices
    152585: 11/09/15: LFSR in xilinx 13.2
    152648: 11/09/22: gigabit ethernet problem
    153284: 12/01/26: FPGA not working after programming from EEPROM
    153286: 12/01/26: Re: FPGA not working after programming from EEPROM
    153290: 12/01/26: Re: FPGA not working after programming from EEPROM
    153443: 12/02/25: Re: gigabit ethernet problem
    153452: 12/02/27: Re: gigabit ethernet problem
    153641: 12/04/09: RPMs in xilinx 13.2
    153695: 12/04/25: FPGA circuit simulator
    153701: 12/04/26: Re: RPMs in xilinx 13.2
SALIX Technologies - Dan Simpkins:
    6760: 97/06/25: Are Xilinx 4000XL I/O's truly 5V tolerant?
Sally Verkaik:
    28992: 01/02/01: Short Course Announcement
    29434: 01/02/21: Short Course Announcement
salman:
    144755: 09/12/30: Re: XILINX license model restricts longtime availability
Salman:
    7858: 97/10/23: Re: Upgrade to Alliance 3.0 CAD VLSI software
Salman Sheikh:
    39682: 02/02/15: Re: Xilinx Virtex XCV300
    39765: 02/02/19: Virtex II prototype/development boards
    40451: 02/03/07: Xilinx ISE 4.1
    40982: 02/03/19: Re: DDS in an FPGA
    43539: 02/05/23: Altera 10K30A240C-1
    44843: 02/07/02: altera 10K30A synthesis
    52259: 03/02/05: Nallatech Ballynuey 3
    52553: 03/02/13: Designware Components and Modelsim
    54097: 03/04/02: Xilinx Divider Core
    55203: 03/04/30: Modelsim startup directory
    56560: 03/06/09: Fixed point divider cores?
    56628: 03/06/10: Re: Fixed point divider cores?
    59736: 03/08/27: fixed point divider help
salman sheikh:
    66490: 04/02/20: Re: ANN: Graphical Testbench Tool Download
    67102: 04/03/05: Modelsim glitches
    67115: 04/03/05: Re: Testing a Verilog design after synthesis in Xilinx ISE
    67191: 04/03/08: Re: strange error
    68013: 04/03/24: Mandrake 10 and Xilinx
    70115: 04/06/03: Re: VHDL test bench in Quartus
    70423: 04/06/16: Suse 9.1 Linux and Xilinx ISE 6.2i
    76040: 04/11/23: Re: VLSI professional at NASA
    76235: 04/11/29: Connecting a PLL output internally and externally simultaneously
salorankatu:
    114926: 07/01/26: Re: Forcing a LUT to not be optimized
    116117: 07/03/01: Re: Help with Partial Reconfiguration on Spartan3
salquraish:
    144872: 10/01/11: Programming Failed
salu:
    113961: 06/12/30: hi......
sam:
    13619: 98/12/14: Atmel's PLD
    30300: 01/04/02: XCV1000BG560: onchip ram
    77216: 04/12/30: Re: Need help with CUPL
    79431: 05/02/18: synthesizable vhdl coding style
    79440: 05/02/18: Re: synthesizable vhdl coding style
    80089: 05/03/01: Xilinx *.rbt file into AMD flash
    80226: 05/03/02: Re: Fault Tolerant FPGA design
    80246: 05/03/02: Re: Fault Tolerant FPGA design
    80294: 05/03/03: Re: Fault Tolerant FPGA design
    80663: 05/03/09: Re: Differences among the FPGA development tools.
    81107: 05/03/17: Re: Newbie: Slow FPGAs
    101634: 06/05/04: Re: ISE8.1 inout, tristate Problem?Please help!
    150947: 11/02/24: Difficulty in programming from PROM
Sam:
    4147: 96/09/18: Cypress FPGA/Warp2--Any Good?
    77165: 04/12/27: CIC filter implementation using FPGA
    77201: 04/12/29: Multipliers implementation (xilinx)
    77242: 05/01/01: Re: CIC filter implementation using FPGA
    77287: 05/01/03: Re: Multipliers implementation (xilinx)
    81702: 05/03/30: Re: Driving two DCM with same clock input pad.
    81754: 05/03/30: Re: Driving two DCM with same clock input pad.
    145201: 10/02/01: How can I convert size requirements from Altera devices to Xilinx
Sam (rép. sans -no-sp-am):
    67963: 04/03/23: Bus width between registers in IIR
    68019: 04/03/24: Re: Bus width between registers in IIR
sam catalpatechnology com:
    128563: 08/01/30: Xilinx prom programming problem
Sam Collinson:
    153027: 11/11/16: Re: Xilinx PCI Express - Am I starting too low?
    153042: 11/11/20: Re: Xilinx PCI Express - Am I starting too low?
Sam Duncan:
    51757: 03/01/21: Virtex II embedded multipliers
    51758: 03/01/21: Re: Virtex II embedded multipliers
    53004: 03/02/28: Virtex II - Driving more than one global clock net from one incoming clock pin
    53124: 03/03/04: Re: Virtex II - Driving more than one global clock net from one incoming clock pin
    54750: 03/04/17: Distributing clock to external devices
    54914: 03/04/22: Re: Distributing clock to external devices
    62365: 03/10/28: Re: Input pins that are driven but not used
    63751: 03/12/03: OFFSET OUT with phase shift in DCM
Sam Estess:
    9947: 98/04/15: Dynachip DL6035
Sam Falaki:
    7061: 97/07/28: Design Protection in FPGAs
    7060: 97/07/28: Re: free FPGA software from actel
    7476: 97/09/15: Re: HELP: FIFO's on an FPGA
    8851: 98/02/01: Re: FPGA/ASIC - same difference?
    8945: 98/02/08: Re: Free FPGA tools???
    8953: 98/02/09: Re: Free FPGA tools???
    8985: 98/02/12: Re: Devices and Prices
    9043: 98/02/17: Re: Devices and Prices
    9139: 98/02/24: Re: MPEG video tutorial
    9632: 98/03/27: Re: XactStep6 - The cure for a dongle
    9651: 98/03/27: Re: XactStep6 - The cure for a dongle
    9774: 98/04/04: Re: Rees-Solomon
    9839: 98/04/08: Re: Effects of IC production
Sam Goldwasser:
    8266: 97/12/04: Re: what is metastability time of a flip_flop
    8283: 97/12/05: Re: what is metastability time of a flip_flop
    8290: 97/12/05: Re: what is metastability time of a flip_flop
    8322: 97/12/08: Re: what is metastability time of a flip_flop
    8345: 97/12/10: Re: what is metastability time of a flip_flop
Sam Kaan:
    60709: 03/09/19: ORCA fpga?
    60896: 03/09/24: Re: ORCA fpga?
Sam Kerr:
    143896: 09/11/02: Need some help creating a ring oscillator on a Spartan-3AN
    143970: 09/11/05: Re: Need some help creating a ring oscillator on a Spartan-3AN
    144234: 09/11/21: Stop ISE from trimming signals for a ring oscillator?
    144240: 09/11/22: Re: Stop ISE from trimming signals for a ring oscillator?
Sam Kung:
    11964: 98/09/21: Verilog newsgroup
Sam Walton:
    54006: 03/03/31: Re: Anyone have difficulty downloading this core?
Sam Worth:
    132575: 08/06/01: Combinatorial logic delay plus routing delay exceeds clock period
    132579: 08/06/01: Re: Combinatorial logic delay plus routing delay exceeds clock period
    132586: 08/06/02: Re: Combinatorial logic delay plus routing delay exceeds clock period
    132601: 08/06/02: Re: Combinatorial logic delay plus routing delay exceeds clock period
    132607: 08/06/02: Re: Combinatorial logic delay plus routing delay exceeds clock period
    132627: 08/06/03: Re: Combinatorial logic delay plus routing delay exceeds clock period
sam@catalpatechnology.com:
    115370: 07/02/08: Virtex 4 SATA redux
<sam@palmnet.net>:
    11892: 98/09/17: Onboard reprogramming of config EEPROM
    11909: 98/09/18: Re: Onboard reprogramming of config EEPROM
    14145: 99/01/15: Re: FPGA/core PCI interface system
samar:
    137396: 09/01/14: effect of channel capacity on hamming code
sambad20:
    148031: 10/06/15: DLC9G problem
samece:
    139304: 09/03/25: Dynamic reconfiguration in Spartan 3
    139684: 09/04/09: reconfiguration in spartan 3
    139685: 09/04/09: Programming in Microblaze
sameer:
    69886: 04/05/23: strange behaviour of the design
Sameer D. Sahasrabuddhe:
    47153: 02/09/19: Re: C\C++ to VHDL Converter
    52261: 03/02/05: Re: Writing and Reading into RC100 Flash RAM
Samer EL HAJJ:
    14059: 99/01/11: DES Hardware Implementation!!
    14481: 99/02/01: FPGA Express Evaluation...
    19206: 99/12/06: Re: Help with ROM in Xilinx Virtex
    19207: 99/12/06: Re: Help with ROM in Xilinx Virtex
<samg@codenet.net>:
    43157: 02/05/15: Re: Architecture for high-level reconfigurable computing
    43158: 02/05/15: Re: Architecture for high-level reconfigurable computing
    44219: 02/06/14: Re: 20,000 gates?
    45982: 02/08/13: Re: Synthesis Verilog to ASIC
    46023: 02/08/15: Re: Reed-Solomon polynom transform....
    46058: 02/08/15: Re: Reed-Solomon polynom transform....
sami:
    129639: 08/03/01: HELP > Face/Edge detection on FPGA
Sami Sallinen:
    798: 95/03/03: Re: Limits on on-chip FPGA virtual computing
    797: 95/03/03: Re: Lattice ispLSI starter kit
    1224: 95/05/18: Re: Altera Flex Logic & Other Problems
samiam:
    100737: 06/04/17: PLD610
    100744: 06/04/17: Re: PLD610
    100753: 06/04/17: Re: PLD610
    100754: 06/04/17: Re: PLD610
    100820: 06/04/18: Re: PLD610
    110594: 06/10/18: Cheapest FPGA board to study VHDL on
    110602: 06/10/18: Re: Cheapest FPGA board to study VHDL on
    110603: 06/10/18: Re: Cheapest FPGA board to study VHDL on
    110679: 06/10/19: Re: Cheapest FPGA board to study VHDL on
    114429: 07/01/15: Re: Will FPGAs suit my need?
SAMIR KHERICHA:
    9716: 98/04/01: fifo
    9840: 98/04/08: fmap and timespec
    10772: 98/06/17: books on vhdl
Samir Marc Falaki:
    5684: 97/03/07: DEVICE SELECTION
    5864: 97/03/21: FPGA CLB USAGE
    5865: 97/03/21: RENOIR DEMO CD
    5866: 97/03/21: BIT SERIAL MULTIPLY
    6551: 97/06/02: Re: Best way to learn VHDL?
samlin:
    43644: 02/05/29: How to add delay in fpga(spartan)?
samliu:
    135747: 08/10/14: About the jitter of Xilinx Virtex-5's DCM output
    135992: 08/10/26: "Out of Order" problem in Xilinx V5 used as a PCI Express Endpoint
Sammo Spud:
    25260: 00/09/03: OverClockers Direct
<samonestopva@gmail.com>:
    129681: 08/03/03: Re: Xilinx DCM for frequency synthesis -- newbie question
    129692: 08/03/03: Re: Xilinx DCM for frequency synthesis -- newbie question
samplify:
    79064: 05/02/13: Announcing Samplify for Windows: high-speed sampled data compression
    79321: 05/02/17: Re: Announcing Samplify for Windows: high-speed sampled data compression
samtee:
    101579: 06/05/03: ISE8.1 inout, tristate Problem?Please help!
    101617: 06/05/04: Re: ISE8.1 inout, tristate Problem?Please help!
Samuel Bogale:
    36483: 01/11/09: ideas
    36711: 01/11/16: Re: CAM
Samuel Lee:
    1623: 95/08/04: Double side surface mount PCBs
    1624: 95/08/04: Double side SMT
samuel nobs:
    65152: 04/01/21: microblaze reg_addr and new_reg_value outputs
Samuel Paik:
    13613: 98/12/13: Re: FPGA Data compression
Samuel Richard:
    35083: 01/09/20: Asking advice on a choise of platform
Samuel Stammbach:
    4558: 96/11/13: Looking for a multiplier
Samuel Thomas Kerr:
    138921: 09/03/14: Getting started with FPGA
    140358: 09/05/10: Getting started with FPGA
san:
    77095: 04/12/22: AHB master related
San San:
    70207: 04/06/09: lancelot VGA daughter board for altera nios dev board
    70277: 04/06/11: Re: lancelot VGA daughter board for altera nios dev board
sanchana:
    142254: 09/07/30: can anybody suggest me..
Sandb:
    54389: 03/04/09: Cheap(er) FPGA configuration?
sandbender:
    143871: 09/10/30: Re: Chipscope with Verilog
<sandcl@my-dejanews.com>:
    13191: 98/11/19: Need VLSI usenet group
sandcreek:
sandeep:
    33100: 01/07/17: regarding the constraints while writing VHDL code
    43690: 02/05/29: Re: State machine synthesis
    102217: 06/05/11: Re: simulation works fine but the actual chip doesnt work
    102218: 06/05/11: Re: simulation works fine but the actual chip doesnt work
    102350: 06/05/15: Re: simulation works fine but the actual chip doesnt work
    136043: 08/10/28: Re: ISE 9.2.03i problem - work-around
    147964: 10/06/05: Calling different modules of a project from another main file
Sandeep:
    55625: 03/05/14: Re: Xilinx Coregen FFT64
    56961: 03/06/19: Re: Tristate
    58845: 03/08/02: beginner
    59070: 03/08/07: Re: Error Generate Statement
    59394: 03/08/18: Xilinx's library associations
    61656: 03/10/08: Re: use of radix-2 ffts
    65243: 04/01/22: Synthesizing pipelined multipliers in Synplify Pro
    65297: 04/01/23: Re: Synthesizing pipelined multipliers in Synplify Pro
Sandeep Dutta:
    74639: 04/10/15: ANN: Introducing MANIK - a 32 bit Soft-Core RISC Processor
    74748: 04/10/18: Re: ANN: Introducing MANIK - a 32 bit Soft-Core RISC Processor
    74783: 04/10/18: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
    108620: 06/09/13: Re: FIFO with EBR
    108640: 06/09/14: Re: FIFO with EBR
    109629: 06/10/01: Re: DDR RAM
    134354: 08/08/07: Re: RTL Schematic as EDIF
Sandeep Grover:
    45752: 02/08/04: newbie ..
Sandeep Kulkarni:
    57457: 03/07/01: Re: Creating interface with NAND flash
    57538: 03/07/02: Re: MapLib:93 - Illegal LOC on symbol "clk.PAD" (pad signal=clk) or BUFGP symbol "u1" (output signal=u1), IPAD-IBUFG should only be LOC'd to GCLKIOB site."
    57627: 03/07/03: Re: post-PAR simulation model
    61856: 03/10/14: Re: problem with XC18v01 and Spartan XCS20XL
    62643: 03/11/04: Re: Xilinx - Multi Volt Interfacing
    62644: 03/11/04: Re: Defect and Fault Tolerance Material
    64088: 03/12/16: Re: PIN naming confusion xilinx spartan 2E XC2S200E
    77050: 04/12/21: Re: PLCC84
    77051: 04/12/21: Re: Memory Controller
    77053: 04/12/21: Re: Programming Virtex II in slave select MAP mode?
    77127: 04/12/24: Re: Virtex II Pro Memory Questions
Sandeep Mukthavaram:
    16199: 99/05/09: Re: Configuring Xilinx FPGAs
Sandeep Pagey:
    77: 94/08/11: Wanted: Literature on Reconfigurable Systems..
Sandeep Unni:
    44751: 02/06/28: Altera equivalent for GAL 16V8
    44766: 02/06/29: Re: Altera equivalent for GAL 16V8
    44813: 02/07/02: VHDL Compliation Problem in Synario
<sandeepbabel@gmail.com>:
    102046: 06/05/09: simulation works fine but the actual chip doesnt work
    102199: 06/05/11: Re: simulation works fine but the actual chip doesnt work
Sander & Stieneke Odekerken:
    100545: 06/04/11: Altera Nios II & PCI Compiler 4.1.0 Question
    100575: 06/04/12: Re: Altera Nios II & PCI Compiler 4.1.0 Question
Sander Odekerken:
    65720: 04/02/05: Fast Fourier Transform
    68498: 04/04/06: VGA Contoller
    69699: 04/05/18: Meaning of output value?
Sander Vesik:
    14798: 99/02/17: Re: Free circuit design
    14810: 99/02/18: Re: Free circuit design
    19823: 00/01/13: Re: HW resources increased
    19829: 00/01/13: Re: HW resources increased
    37705: 01/12/19: Re: MIPS or MOPS?
    52256: 03/02/05: Re: clock ditribution tree
    56416: 03/06/04: cyclone on pci?
    56421: 03/06/04: Re: cyclone on pci?
    57139: 03/06/24: Re: MIPS instruction set?
    57342: 03/06/27: Re: MIPS instruction set?
    57369: 03/06/28: Re: MIPS instruction set?
    57449: 03/06/30: Re: MIPS instruction set?
    57725: 03/07/04: Re: cyclone on pci?
    57874: 03/07/09: Re: QuartusII software licencing
    59022: 03/08/06: Re: opencores.org - Question on project licensing?
    59069: 03/08/07: Re: Offshore engineering
    60240: 03/09/09: Re: CMOS camera w/ USB2 -- crazy?
    61094: 03/09/28: Re: Graphics rendering
    66354: 04/02/18: Re: Dual-stack (Forth) processors
    66423: 04/02/19: Re: Dual-stack (Forth) processors
    66511: 04/02/20: Re: Dual-stack (Forth) processors
    66516: 04/02/21: Re: GZIP algorithm in FPGA
    66544: 04/02/22: Re: GZIP algorithm in FPGA
    66642: 04/02/24: Re: Free PCI-bridge in VHDL for Spartan-IIE
    66721: 04/02/25: Re: Free PCI-bridge in VHDL for Spartan-IIE
    66722: 04/02/25: Re: Free PCI-bridge in VHDL for Spartan-IIE
    66792: 04/02/26: Re: Free PCI-bridge in VHDL for Spartan-IIE
    67098: 04/03/05: Re: Spec VPR Results for various processors...
    67099: 04/03/05: Re: Spec VPR Results for various processors...
    67109: 04/03/05: Re: mersenne twister
    67129: 04/03/06: Re: mersenne twister
    67496: 04/03/13: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
    68545: 04/04/07: Re: Apples to Apples? Starrix Two <> Virtex II Pro
    68588: 04/04/08: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
    70928: 04/07/01: Re: *RANT* Ridiculous EDA software "user license agreements"?
    71549: 04/07/21: Re: FSM in illegal state (conclusion)
    80131: 05/03/02: Re: Is Altera Cyclone a good choice ?
    80133: 05/03/02: Re: Multiple additions
    80134: 05/03/02: Re: Multiple additions
    80135: 05/03/02: Re: Multiple addition(2)
    80169: 05/03/02: Re: publishing IP
    81242: 05/03/20: Re: Spartan 3E vs. Cyclone2
    81243: 05/03/20: Re: Altera free web FPGA software license question
    82036: 05/04/06: Re: ISA vs. patent/trademark
    82070: 05/04/06: Re: Open PowerPC Core?
    95560: 06/01/24: Re: OT:Shooting Ourselves in the Foot
    106256: 06/08/10: Re: LISP Workshop at ECOOP06
Sander Zuidema:
    86971: 05/07/11: Bazix introduce FPGA based One Chip computer system
    86973: 05/07/11: Re: Bazix introduce FPGA based One Chip computer system
    86998: 05/07/12: Re: Bazix introduce FPGA based One Chip computer system
<sanders@accessone.com>:
    7653: 97/10/01: Re: Xilinx licensie idiocy
<sandesh.bharadwaj@gmail.com>:
    108289: 06/09/07: Certify partition tool for FPGAs
Sandhya:
    72109: 04/08/09: synchronous FSM
<sandhya.mathur08@gmail.com>:
    153821: 12/05/28: Re: Xilinx ISE 12.3 : library simprim problem
sandi:
    96296: 06/02/01: don't care condition
Sandi Posl:
    67673: 04/03/17: Re: Difficulties fitting a design into a Xinlinx Virtex-II XC2V6000
Sandip:
    111642: 06/11/07: How to generate a PROM file and then burn it on FPGA
    111685: 06/11/08: Re: How to generate a PROM file and then burn it on FPGA
    111783: 06/11/09: Re: How to generate a PROM file and then burn it on FPGA
    115846: 07/02/21: VHDL code for Generating registers
    116133: 07/03/01: How to connect an IP to OPB bus??
    117117: 07/03/23: Custom IP ports to be used as GPIOs
    120086: 07/06/01: After PAR simulation, should I assume that it will work on FPGA board?
    120103: 07/06/01: Re: After PAR simulation, should I assume that it will work on FPGA board?
Sandip Dasgupta:
    6910: 97/07/08: SPICE tutorial
Sandor Jager:
    64047: 03/12/14: datasheet needed!
Sandra:
    31615: 01/05/31: Place and Route Tools for Virtex FPGAs
Sandra Dominikus:
    17225: 99/07/12: Xilinx On-Chip-Oscillator
    17531: 99/08/06: XILINX Implementation Problem
Sandra Hillel:
    1524: 95/07/07: ** Computer Buying Guide **
Sandra Nielsen:
    32713: 01/07/05: AMS Wildstar Board
    32737: 01/07/06: Re: AMS Wildstar Board
<sandrayshaw@hotmail.com>:
Sandro:
    81656: 05/03/29: Re: What type of IO to use
    84482: 05/05/19: Re: Spartan 3 CPI
    85160: 05/06/06: Re: Spartan 3 Starter kit group formed
    85163: 05/06/06: Re: Spartan 3 Starter kit group formed
    90039: 05/10/03: Re: Antti is back
    90262: 05/10/07: Re: Xilinx WebPack and command line
    90306: 05/10/10: Re: Xilinx WebPack and command line
    90360: 05/10/11: Re: Using the BSCAN primitives
    92484: 05/11/30: Re: ISE Simulator not present in Linux?
    97264: 06/02/20: multiphase data extraction question
    97269: 06/02/20: Re: multiphase data extraction question
    97271: 06/02/20: Re: multiphase data extraction question
    97429: 06/02/22: Re: DIFF_OUT buffer example
    99609: 06/03/27: Re: OpenSPARC released
    103807: 06/06/12: Re: xc3sprog -- any updates?
    104213: 06/06/21: Re: xc3sprog -- any updates?
    104267: 06/06/22: Re: xc3sprog -- any updates?
    104275: 06/06/22: Re: xc3sprog -- any updates?
    105181: 06/07/17: Re: OpenFire - public domain MicroBlaze clone in verilog
    106695: 06/08/17: DCM and Maximum Frequency implied by XST
    106742: 06/08/18: Re: DCM and Maximum Frequency implied by XST
    106847: 06/08/21: Re: S3 starter kit, command-line
    106978: 06/08/23: virtex4fx board and ethernet
    106983: 06/08/23: Re: virtex4fx board and ethernet
    107004: 06/08/23: Re: virtex4fx board and ethernet
    107062: 06/08/24: Block RAM vs Flip Flop
    107065: 06/08/24: Re: Block RAM vs Flip Flop
    107069: 06/08/24: Re: Block RAM vs Flip Flop
    110144: 06/10/11: OT: sun vs xilinx
    110199: 06/10/12: Re: VGA timing
    110280: 06/10/13: Re: VGA timing
    110844: 06/10/24: Re: microblaze uclinux ping delay
    115316: 07/02/07: Re: or1k on spartan 3, 400K gate version
    115317: 07/02/07: Re: : Is Digilent still in business ???
    119980: 07/05/30: Spartan-3E DIG-3E1600 Development Board Kit
    120014: 07/05/31: Re: Spartan-3E DIG-3E1600 Development Board Kit
    120321: 07/06/05: Re: ARM in FPGA's?
    120327: 07/06/05: Re: ARM in FPGA's?
    120910: 07/06/20: Re: Spartan-3E DIG-3E1600 Development Board Kit
    121742: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
    121829: 07/07/13: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
    122049: 07/07/18: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
    125129: 07/10/16: Re: MIG for Linux?
    133229: 08/06/21: Re: Xilinx Clock Doubler
    140341: 09/05/09: Re: Dual Port RAM Inference
    140344: 09/05/09: Re: Dual Port RAM Inference
    140346: 09/05/10: Re: Dual Port RAM Inference
    140374: 09/05/11: Re: Dual Port RAM Inference
    140408: 09/05/12: Re: 100 Mbps on 1000/100/10 Mbps PHY
    140713: 09/05/22: Re: DCM Jitter
    140796: 09/05/26: Re: 11.1 & USB cable drivers
    141115: 09/06/06: Re: digital RGB Video to Analog VGA triple DAC question
    141212: 09/06/11: Re: opencores shut down?
    141438: 09/06/24: Re: True dual-port RAM in VHDL: XST question
    141653: 09/07/02: Re: I/O Pads in ASIC
    141715: 09/07/04: Re: 50 000 registered users at OpenCores.org
    141720: 09/07/04: Re: 50 000 registered users at OpenCores.org
    142159: 09/07/27: ISE 11 and symbolic links with linux - just a tip
    142166: 09/07/28: Re: ISE 11 and symbolic links with linux - just a tip
    142170: 09/07/28: Re: ISE 11 and symbolic links with linux - just a tip
    142765: 09/08/31: Re: Virtex 5 HDMI
    146797: 10/03/29: Re: Which is the most beautiful and memorable hardware structure in a
    148037: 10/06/15: Re: How to detect a sync and start of a frame in an optimal way
    148047: 10/06/16: Re: How to detect a sync and start of a frame in an optimal way
    148121: 10/06/22: Re: Why is Google so F****** dense about SPAM?
    148128: 10/06/22: Re: Why is Google so F****** dense about SPAM?
    148202: 10/06/27: Re: Free bitmap font
Sandro Pastore:
    7832: 97/10/20: help on xc4005a Boundary Scan
Sandro Wefel:
    16880: 99/06/16: Recursive Structures under Aldec AVHDL3.3
    16921: 99/06/17: Re: aobut analog
Sandy:
    79930: 05/02/25: pci x core on virtex II
sandy:
    68303: 04/03/31: REGISTER as a COUNTER in hardware
    149346: 10/10/18: ZIGBEE with FPGA
    149360: 10/10/18: Re: ZIGBEE with FPGA
Sandy Harris:
    5488: 97/02/20: Re: Q: Search Engines for Electronic Parts?
    12421: 98/10/12: Re: Software tool
    12463: 98/10/12: Re: DES in FPGA
Sandy Jeffers:
    15854: 99/04/16: Industry Network?
<sandypure@yahoo.com>:
    98234: 06/03/07: Questions about counter in VHDL
saned:
    88258: 05/08/13: re:Xilinx ISE 6.3i on Gentoo Linux
Sanford Hayes:
    8450: 97/12/16: Xilinx Stock
Sang-hee Lee:
    29299: 01/02/13: The usage of 'Guide files' in Xilinx foundation 2.1i
    29430: 01/02/21: Xilinx CoreGen problem.
Sang-Kwon Lee:
    12683: 98/10/23: How can I estimate number of Xilinx CLB?
SangchulJung@gmail.com:
    122180: 07/07/23: Could you explain the procedure about system simulation?
sanika:
    141531: 09/06/26: Error while downloading prodram on CPLD
    141545: 09/06/27: Re: Error while downloading prodram on CPLD
sanjay:
    52876: 03/02/25: Decoupling Capacitor for CPLD
    53906: 03/03/27: Re: Differential LVPECL Inteface of Spartan IIE
    53907: 03/03/27: Re: Translating 2 CLKDLLs for SpartanII architecture
    53979: 03/03/29: Re: Spartan vs. Cyclone for arithmetic functions
    59685: 03/08/26: Re: Which Adder?
Sanjay Balasubramanian:
    473: 94/11/29: XC3090 PERFROMANCE...
Sanjay Kumar Sharma:
    34730: 01/09/05: Re: Interfacing Verilog and VHDL
Sanjay Maniku:
    34355: 01/08/22: Re: I NEED TO BUY A FPGA BOARD
sanjay parekh:
    42898: 02/05/06: virtex2: clk via clk buf to BRAM
    42964: 02/05/08: trace report
Sanjay Parekh:
    36809: 01/11/20: Re: Hex numbers in VHDL
    155242: 13/06/17: Re: Modelsim ought to be cheaper
    155261: 13/06/19: Re: Modelsim ought to be cheaper
    155266: 13/06/20: Re: Modelsim ought to be cheaper
    155367: 13/06/24: Re: Modelsim ought to be cheaper
Sanjay Patil:
    48197: 02/10/14: Clk Problem
    48415: 02/10/17: Re: Clk Problem
    48704: 02/10/23: Serial PROM Configuration
    49262: 02/11/07: LUT Consumption in Virtex-2
    49269: 02/11/07: Re: LUT Consumption in Virtex-2
    49430: 02/11/12: Re: EDIF generation from XST of ISE 5.1i
    49482: 02/11/13: Simulation Modes
    49520: 02/11/14: Re: question about booth multipliers
    50004: 02/11/28: Xilinx ISE/XST Problem or FFT Designer can help me.
    50321: 02/12/09: Re: vlsi implementation of multipliers
    50816: 02/12/20: Xilinx 1024 Pt FFT
Sanjay Srivastava:
    8535: 98/01/06: Re: SDRAM model
Sanjay Vishin:
    279: 94/10/12: Memory bus based FPGA's
<sanjay.gajendra@gmail.com>:
    89232: 05/09/08: Quartus II - Timing Analyzer
<sanjay@edadirect.com>:
    6013: 97/04/04: Re: verilog to VHDL tools needed!
Sanjeev:
    14626: 99/02/06: Board for XC4085XL
    14634: 99/02/07: Board for XC4085XL?
Sanjeev Gunawardena:
    17766: 99/09/01: Dissolve hierarchy or not?
Sanjeev Kwatra:
    15946: 99/04/22: Free Xilinx CPLD design software on the web
    15973: 99/04/23: Re: Free Xilinx CPLD design software on the web
sanju:
    120382: 07/06/06: asynchronous circuit design
Sanka Piyaratna:
    100821: 06/04/19: driving high speed ADC using an FPGA
    100848: 06/04/19: Re: driving high speed ADC using an FPGA
    101992: 06/05/09: Xilinx ISE 8.1 Makefile
    102841: 06/05/22: incremental chip building in ISE
    107073: 06/08/25: high level languages for synthesis
    124468: 07/09/23: Xilinx GTP based serial link
    124590: 07/09/27: FPDP to PCIe
sankalp.singhal:
    84436: 05/05/18: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
    84438: 05/05/18: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
    84441: 05/05/19: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
    84442: 05/05/19: how to debug a C/C++ application in NIOS II IDE
    84534: 05/05/20: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
Sanket Bandyopadhyay:
    39257: 02/02/05: Re: Xilinx synthesis tools
    39259: 02/02/05: Re: chipscope "disable JTAG clock BUFG insertion"
Sanket Xilinx FAE Insight:
    47125: 02/09/18: Re: Any Virtex 2 pro development boards yet?
sanketinsight.memec.co.in:
    39261: 02/02/05: Re: When is Xilinx going to have multi-gigabit serial PHY?
<sanpab@eis.uva.es>:
    68262: 04/03/31: Re: AHDL, VERILOG or VHDL??
    68483: 04/04/06: Re: iMPACT "Programming Failed"
    70022: 04/05/27: Re: Driving fpga pin out over long cable
    70095: 04/06/02: Re: how to random generate packet for Ethernet MAC(802.3) with verilog in testbench ?
    70457: 04/06/17: Is there a verilog version of PicoBlaze?
    70474: 04/06/17: How to create an EDIF file from ISE Foundation?
    70570: 04/06/21: Re: How to create an EDIF file from ISE Foundation?
Santa:
    53449: 03/03/13: What is the diff between FPGA and CPLD?
<Santa@TheNorthPole.Org>:
    19487: 99/12/25: * * * M E R R Y C H R I S T M A S * * *
SantaBarbara350Z@gmail.com:
    87538: 05/07/25: Re: Problems installing windrvr.o in Red Hat EL3...
<SantaBarbara350Z@gmail.com>:
    87459: 05/07/24: Problems installing windrvr.o in Red Hat EL3...
santanu:
    106209: 06/08/09: A Newbie question
    106275: 06/08/10: Re: A Newbie question
santhosh:
    79699: 05/02/23: FPGA : file generation
<santhosh_h_98@yahoo.com>:
    99222: 06/03/21: How to get eps file from XST RTL viewer for LATEX
    99243: 06/03/21: Re: How to get eps file from XST RTL viewer for LATEX
    137102: 08/12/23: DFFR using DFF (only, may be extra gates)
Santi:
    57239: 03/06/26: CoreGen/Ngdbuild help
    57307: 03/06/27: IP core generation
    57308: 03/06/27: Re: CoreGen/Ngdbuild help
    57536: 03/07/02: FPGA Editor and Xilinx ISE 5.1i
    57623: 03/07/03: Re: FPGA Editor and Xilinx ISE 5.1i
Santiago de Pablo:
    26500: 00/10/18: Re: Sinusoidal PWM on a Xilinx FPGA
    26824: 00/10/31: Re: WebPACK ISE V3.2i is available for immediate download!
    30561: 01/04/17: Re: Is there any free processor core for vertex series?
    32093: 01/06/13: Which FPGA for Power Electronics?
    32541: 01/06/29: Re: Xc4K still alive? (5v vs 3.3v)
    32847: 01/07/10: Re: Shift and Add Multiplier With Signed Numbers
    34622: 01/08/31: Re: WebPack Con-Game
    37188: 01/12/03: Re: Modelsim
    38262: 02/01/10: [WebPACK or ISE] Mixing Verilog and EDIF?
    38769: 02/01/24: Re: microcontroller manager question
    39144: 02/02/01: Re: Linking IP
    40521: 02/03/08: Re: FPGA or DSP in a power supply?
    44576: 02/06/24: Re: Seeking CPLD/FPGA recomendation
Santiago Felici Castell:
    1616: 95/07/31: HW VIDEO ALGORITHMS
<santner@gmail.com>:
    115364: 07/02/08: Interrupts and PPC/opb_intc
    115415: 07/02/09: Re: Interrupts and PPC/opb_intc
    115416: 07/02/09: Re: Interrupts and PPC/opb_intc
santosh:
    93379: 05/12/20: Re: More beginner's verilog questions
Santosh:
    149110: 10/10/02: External Circuit to FPGA.
    149113: 10/10/02: Re: External Circuit to FPGA.
    149129: 10/10/04: Re: External Circuit to FPGA.
    149130: 10/10/04: Re: External Circuit to FPGA.
    149181: 10/10/06: Re: External Circuit to FPGA.
    149420: 10/10/23: FPGA I/O Issues.
    149423: 10/10/24: Re: FPGA I/O Issues.
    149425: 10/10/24: Re: FPGA I/O Issues.
    149451: 10/10/26: Re: FPGA I/O Issues.
    150175: 10/12/25: some VHDL error
    150182: 10/12/29: Re: some VHDL error
    150183: 10/12/29: Error in Clock Divider!
    150243: 11/01/04: Re: Error in Clock Divider!
santosh nath:
    62575: 03/11/02: Re: Shannon Entropy for Black Holes
santosh shreinivasan:
    35275: 01/09/27: Re: Xilinx implementation problem
santukms:
    148806: 10/08/27: Xilinx RocketIO problems
Saouter Yannick:
    4517: 96/11/08: Integration, the VLSI journal
Saqib:
    22812: 00/05/25: CRC
    22810: 00/05/25: Fire Wire
    22811: 00/05/25: Fire Wire
    26683: 00/10/25: Polynomial transform based 2D-DCT
    27112: 00/11/11: Number Format in DSP implementations
    27745: 00/12/06: ADAPTIVE FILTER
    27925: 00/12/15: CSD OR DISTRIBUTED ARITHMETIC?
    28056: 00/12/20: HOT AREAS IN FPGAs
    28845: 01/01/26: CORDIC ALGORITHM
    28956: 01/01/31: CORDI C PROCESSOR!
    115308: 07/02/06: Spartan-3E starter kit : trouble with configuration from NOR Flash
    115315: 07/02/07: Re: Spartan-3E starter kit : trouble with configuration from NOR Flash
    116132: 07/03/01: Re: Spartan-3E starter kit : trouble with configuration from NOR Flash
    118921: 07/05/07: computing branch metric for viterbi decoder
saqib:
    31921: 01/06/08: VOICE CODING!
Saqib Saqi:
    156603: 14/05/11: need coding
    156606: 14/05/12: Re: need coding
    156607: 14/05/12: Re: need coding
    156613: 14/05/13: Re: need coding
    156614: 14/05/13: Re: need coding
    156618: 14/05/14: Re: need coding
    156626: 14/05/15: Re: need coding
    156628: 14/05/15: Re: need coding
    156630: 14/05/16: Re: need coding
    156632: 14/05/16: Re: need coding
    156651: 14/05/23: Re: need coding
Saqib.:
    22909: 00/05/31: Verilog Questions??
Sara Reinstein:
    11567: 98/08/24: Job opportunities for FPGA Applications Engineers
sarah:
    59263: 03/08/13: Actel Core PCI
    59374: 03/08/17: serial communication between pc and altera fpga
    59392: 03/08/18: Re: serial communication between pc and altera fpga
    62354: 03/10/27: How to import QuartusII simulation waveform (vwf) and block design file(bdf) to the Word (.doc)
    70040: 04/05/28: how to random generate packet for Ethernet MAC(802.3) with verilog in testbench ?
Sarah:
    84270: 05/05/16: Silicon Valley FPGA position
Sarah Marsden:
    6883: 97/07/06: free report
sarah shen:
    53104: 03/03/03: questions about RS232 IN Altera FPGA
    53206: 03/03/06: altera quartusII help
    59190: 03/08/11: questions about PCI implemented in Actel APA300
<sarah.stregel@gmail.com>:
    127743: 08/01/06: Viterbi Decoder
sarah_s:
    130541: 08/03/26: Simulink(matlab)/FPGA serial port communication
    130542: 08/03/26: Re: Simulink(matlab)/FPGA serial port communication
    130543: 08/03/26: Simulink(Matlab)/FPGA serial communication
    130600: 08/03/27: Re: Simulink(Matlab)/FPGA serial communication
    130601: 08/03/27: Re: Simulink(Matlab)/FPGA serial communication
SARAHTAWIL:
saran:
    58464: 03/07/23: Re: MIPS instruction set?
    129440: 08/02/24: canny edge detection
Saransh:
    132901: 08/06/10: Error while compiling uClinux image for Microblaze
    133148: 08/06/19: Error while doing 'Generate Netlist' in xilinx 9.2i
saras:
    142045: 09/07/22: DONE pin does'nt go high in SPARTAN - 3AN
    146329: 10/03/12: Question Rdging xilinx chipscope pro triggering
    146412: 10/03/16: Re: Question Rdging xilinx chipscope pro triggering
sarath:
    87607: 05/07/26: Conversion of ASIC RTL to FPGA RTL
    88134: 05/08/10: Rapid prototyping in FPGA
    88260: 05/08/13: Re: Rapid prototyping in FPGA
<sarath1111@gmail.com>:
    87243: 05/07/20: Softcore based Rapid Protyping?
Saravananj:
Sarbjit Singh:
    12178: 98/10/02: Orcad Capture error DSM0006 and DBO3203
<sarfati@netvision.net.il>:
    4259: 96/10/06: Re: QuickLogic
    5100: 97/01/23: Re: 16v8,20v8 programming
    5316: 97/02/06: Re: Duplicate PLD?
    5441: 97/02/16: Re: Mealy/Moore state machines
sarin mathen:
    18391: 99/10/21: Re: Xilinx Orientation Question
SArmitage:
    14739: 99/02/14: Lucent Orca $95 design tools
sarnaths@gmail.com:
    89662: 05/09/21: JBits query
    89974: 05/09/30: reading bits using JBits 3.0
    99009: 06/03/18: question regarding LUT and MAP
saroj rout:
    4115: 96/09/12: Need HELP!!!
Sarun:
    96539: 06/02/06: Xilinx Pci Express core and Nital board Issue
Sasa Bremec:
    40582: 02/03/11: SPI interface
    42373: 02/04/22: FPGA Express problems
    42413: 02/04/23: Re: FPGA Express problems
    42484: 02/04/25: SpartanXL libraries (OSC4 element)
    50040: 02/11/29: System Generator and 18x18 multipliers
    51216: 03/01/07: Re: ChipScope Pro not importing Inserter project
    57979: 03/07/11: DDS theory of operation
    59574: 03/08/22: DA FIR filter vs. MAC FIR filter
    59728: 03/08/27: Re: DA FIR filter vs. MAC FIR filter
    65592: 04/02/03: using IIR in DDC
    70735: 04/06/25: open source FPGA tools
    71992: 04/08/05: i2c controller and Linux driver
    72030: 04/08/06: Re: i2c controller and Linux driver
Sascha Frank:
    126003: 07/11/12: Strange VHDL Error
    126004: 07/11/12: Re: Strange VHDL Error
    126007: 07/11/12: Re: Strange VHDL Error
Sashi Obilisetty:
    1115: 95/05/01: Web/FTP site for FPGA based research
    1141: 95/05/04: ****** verilog2vhdl ONLINE DEMO Available *******
    2207: 95/11/01: **ANNOUNCEMENT: VHDL to Verilog Translator**
Sasi:
    52833: 03/02/24: Re: need help
<sasrrx888er_666@yahoo.com>:
<sasx888er_666@yahoo.com>:
    31199: 01/05/14: Important News
    31343: 01/05/20: ANNA KOURNAKOVA - NEW BEST PIX!!!
SAT:
    11328: 98/08/05: Re: Dual-edge clocking device for Rambus DRAM...
Sata Know How:
    119539: 07/05/22: Re: FPGA -> SATA?
<SaTaN0rX@googlemail.com>:
    130518: 08/03/26: How to run a block with half the clockspeed on virtex 5
    130522: 08/03/26: Re: How to run a block with half the clockspeed on virtex 5
    130561: 08/03/27: Re: How to run a block with half the clockspeed on virtex 5
satchit:
    49039: 02/10/30: 2-nios design using SOPC builder
    49254: 02/11/06: Re: 2-nios design using SOPC builder
    50220: 02/12/05: Re: 2-nios design using SOPC builder
    51426: 03/01/13: RS-232 connection with SOPC Development Kit
    56409: 03/06/04: Re: NIOS-GERMS
<sathishkumar5991@gmail.com>:
    154499: 12/11/19: Re: Error while running implementation through unix command line
    154501: 12/11/19: Re: Error while running implementation through unix command line
    154503: 12/11/19: Re: Error while running implementation through unix command line
Sathya:
    109508: 06/09/27: Re: lwip
    109661: 06/10/02: Re: lwip
Sathya Thammanur:
    60062: 03/09/04: Re: EDK problem!
    60064: 03/09/04: Re: More EDK Problems..... :-(
<satih82@gmail.com>:
    126403: 07/11/21: Re: did i miss edk 9.2
Satish K:
    48995: 02/10/29: Can we retaining EAB Data using BACK UP power SUPPLY for Vccint
    64139: 03/12/18: Help me converting Mathlab code to VHDL? DSPBuilder or SystemGenerator
    64175: 03/12/18: Re: Help me converting Mathlab code to VHDL? DSPBuilder or SystemGenerator
<satish@my-dejanews.com>:
    11208: 98/07/25: Caluclation of gates in FPGA
<satish_me@hotmail.com>:
    9393: 98/03/09: Floating point representation on FPGA
    9675: 98/03/30: Floating point representation in FPGA
    10240: 98/05/06: Re: Radix-4 CORDIC pipeline -- which chip?
    10372: 98/05/15: Re: Xilinx FGA Express
    10993: 98/07/09: Re: AHDL
    14283: 99/01/23: Worst service in India by Xilinx
    14357: 99/01/27: Re: Worst service in India by Xilinx
    14358: 99/01/27: testing
    16127: 99/05/05: Reciprocator in VHDL
    16230: 99/05/11: Re: Reciprocator in VHDL
    19817: 00/01/13: Re: Design security
Satnam Singh:
    1797: 95/09/04: Call for Papers: DCC'96
    2229: 95/11/06: Re: DCC'96 2nd Call for Papers
    17891: 99/09/15: Re: What's meaning of "Partial Evaluation"
    26865: 00/11/01: Re: death of rloc ?
    26866: 00/11/01: Re: death of rloc ?
sato:
    152710: 11/10/05: wireless module for DSP stratix III
Satoru Uzawa:
    100160: 06/04/04: Re: spartan FPGA with PLCC package
    115829: 07/02/21: Re: audio low pass filtering in FPGA
<satpreetsingh@gmail.com>:
    92040: 05/11/21: FFT on an FPGA
Satwant Singh:
    115: 94/08/17: Re: Proprietary Configuration Data
    131: 94/08/18: Re: Self-Programming Devices (was Re: Proprietary Configuration Data)
    283: 94/10/12: Re: Multipliers in FPGA's
    676: 95/02/03: Re: "on-fly" reprogrammable devices/research
    814: 95/03/06: Re: Power gain when moving from FPGA to Gate Array
Satya:
    49425: 02/11/12: Re: Altera MAX7000E (EPM7128ELC84) - programmer?
    72068: 04/08/07: Synchronizing Reset De-assertion
satya:
    38029: 02/01/01: Virtex-II FPGA Chips Availability
    38149: 02/01/07: Regarding frequency achieving in fpga design
    38219: 02/01/09: Xilinx XC2000, XC3000, XC4000 families
    39072: 02/01/30: JTAG Emulator Tutorial
    40269: 02/03/04: Asynchronous boundaries in FPGA
    40376: 02/03/06: Re: Asynchronous boundaries in FPGA
    41119: 02/03/21: doubt on GDSII file integration
    43007: 02/05/09: Reconfigurable FPGAs
satyam:
    129939: 08/03/11: Matlab, RS-232, Ethernet
Satyan Namdhari:
    6233: 97/04/30: Re: Laptop
Saul Bernstein:
    135605: 08/10/09: Virtex-5 clocking
    135628: 08/10/10: Re: Virtex-5 clocking
    136368: 08/11/13: Virtex5 XC5VFX70T
    136370: 08/11/13: Re: Virtex5 XC5VFX70T
Saul Cozens:
    1537: 95/07/11: FPGAs for video coding
Saumil Merchant:
    120850: 07/06/18: XPower: Can't change activity rates
<saumyajit_tech@yahoo.co.in>:
    103446: 06/06/02: Re: Using ChipScope with EDK flow?
    104716: 06/07/05: Re: stable reset in fpga
    104778: 06/07/05: Re: stable reset in fpga
    104784: 06/07/06: Re: Weird timing failure
    104833: 06/07/06: Re: DDR Controller problems
saungmun:
    5978: 97/04/01: semiconductor selling
    5979: 97/04/01: semiconductor selling
    5980: 97/04/01: semiconductor selling
Saurabh:
    55196: 03/04/30: Implementing FPGA based network packet filtering
Saurabh Chhabra:
    74395: 04/10/10: MXE post-translate simulation problem
    74716: 04/10/17: Re: simprim errors
Saurabh Pal:
    40705: 02/03/13: DES implementation in Handel C
    50334: 02/12/09: problem in Handel-C
    50389: 02/12/10: Re: problem in Handel-C
    50532: 02/12/12: Suggestions required for Handel-C code
    51937: 03/01/26: better clock speed???
saurin shah:
    318: 94/10/19: Photolithography at 313nm wavelength (Mid-UV).
SavageLiu:
    57220: 03/06/25: Re: scaling fixed point fft
<savdeep@gmail.com>:
    85070: 05/06/03: not clear about doing power estimation using xpower
Savekar Santosh:
    23675: 00/07/05: Re: MPEG audio questions...
    23804: 00/07/10: Re: calculating modulo N
savingsandloan:
    77222: 04/12/30: Newbie looking for multiported-RAM to interface to a Spartan-III
    77959: 05/01/20: Re: How does a SDRAM controller work?
savs:
    102674: 06/05/18: Error in XPS 7.1 mb_opb_wrapper
    102831: 06/05/22: Re: Error in XPS 7.1 mb_opb_wrapper
    103192: 06/05/27: Peripheral connected to multiple OPB buses
    103197: 06/05/28: Re: Peripheral connected to multiple OPB buses
    103253: 06/05/29: Re: Peripheral connected to multiple OPB buses
    103976: 06/06/16: library for lmb
    104344: 06/06/25: multisource on signal in XPS
    104345: 06/06/25: Re: multisource on signal in XPS
    104360: 06/06/26: Re: multisource on signal in XPS
    104384: 06/06/26: Re: multisource on signal in XPS
    104416: 06/06/27: Re: multisource on signal in XPS
    104417: 06/06/27: Number of bonded IOB's
    104865: 06/07/07: FATAL ERROR IN EDK 7.1i
    104884: 06/07/08: Timing Error in edk 7.1i
Say Joe:
    115487: 07/02/12: Which is your favorite FPGA language?
    115513: 07/02/12: Re: Which is your favorite FPGA language?
    115534: 07/02/13: Re: Which is your favorite FPGA language?
    115549: 07/02/13: Re: Which is your favorite FPGA language?
Saylee:
    153382: 12/02/14: MPMC simulation
<sayskimariano@yahoo.fr>:
    85848: 05/06/16: USB2.0 UTMI Free IP Core Implentation
sb:
    30416: 01/04/07: FPGA configuration from processor
<sbaker@best.com>:
    1428: 95/06/21: Re: Who was the winner on latest PREP benchmarks?
    1464: 95/06/26: PREP benchmark data access
    1748: 95/08/24: Re: Looking for Good Introductory Book on FPGAs and ELPDs
    2631: 96/01/16: FPGAs better than gate arrays??
    2751: 96/02/01: FPGAs challenging the industry
    2971: 96/03/07: PLDCon'96 Program
    3149: 96/04/15: One Week to Boston
    3150: 96/04/15: Re: One Week to Boston
    3378: 96/05/23: FCCM Report on the Web
    3455: 96/06/02: PLDCon Xtension - On the Web
    3858: 96/08/09: PLDCon'97
    4470: 96/11/02: Online Panel - Users tell Vendors
    4546: 96/11/12: Reconfig interactive report
    5004: 97/01/10: ISP Online Discussion
<sbaker@best.com[Stan Baker]>:
    4068: 96/09/06: Re-usable cores & macros report
<sbattazz@yahoo.co.jp>:
    140056: 09/04/26: Modelsim Actel Edition and Soft FIFO Controller
    140059: 09/04/26: Re: Modelsim Actel Edition and Soft FIFO Controller
    140134: 09/04/29: Re: Modelsim Actel Edition and Soft FIFO Controller
    140143: 09/04/30: Re: Modelsim Actel Edition and Soft FIFO Controller
    140607: 09/05/20: Actel Low Cost Programming Stick (IGLOO kits)
    140611: 09/05/20: Re: Actel Low Cost Programming Stick (IGLOO kits)
    140750: 09/05/25: Adders with multiple inputs?
    140752: 09/05/25: Re: Adders with multiple inputs?
    140778: 09/05/25: Re: Adders with multiple inputs?
    140779: 09/05/25: Re: Adders with multiple inputs?
    140781: 09/05/25: Re: Adders with multiple inputs?
    140822: 09/05/26: Re: Adders with multiple inputs?
sbattazzo:
    152334: 11/08/10: Re: image storing into BRAM
    152335: 11/08/10: Re: Newbie PCB
    153371: 12/02/10: Re: Dangling all pins, DIA0 through DIA31
<sbattazzo@gmail.com>:
    157324: 14/11/21: Re: Linux USB JTAG Cable Driver for Xilinx Impact
    157448: 14/12/10: Re: Which Altera to buy?
sbf:
    39240: 02/02/05: Re: Leonardo=>MaxPlus/Quartus Vs Synopsys=>MaxPlus/Quartus
<sbierly@sed.stel.com>:
    12871: 98/11/03: Re: FIR Filter Design
Sbob5757:
    32341: 01/06/23: Re: what tools run OK on windows 2000?
sboe:
    40508: 02/03/08: hash arithmetic
Sbreheny:
    127337: 07/12/18: Glitch warnings in Modelsim with Lattice ispLever 7.0
<sc01@hotmail.com>:
    61809: 03/10/13: PCMCIA FPGA Card
    61811: 03/10/13: How to select a FPGA
    62548: 03/11/01: Convert verilog to VHDL??
    62549: 03/11/01: WinCE driver for Wildcard from Annapolis Micro System?
scada:
    119394: 07/05/17: Re: Visio logic symbols
Scarex:
    77895: 05/01/20: Virtex-II bus macro doubt
    77922: 05/01/20: SystemACE and Jtag
    77993: 05/01/21: Re: SystemACE and Jtag
    78146: 05/01/25: Module and bus macro
scd:
    14328: 99/01/25: Looking for Altera 10K libraries for Protel Adv. Schematic
    48767: 02/10/24: Re: Altera FPGA and EPLD Download ByteBlaster
    48793: 02/10/24: Re: Altera FPGA and EPLD Download ByteBlaster
    48830: 02/10/25: maxplus2 on WinXP
    48861: 02/10/25: 6809 FPGA
    48894: 02/10/26: Crystal oscillator question
    48905: 02/10/26: Re: Crystal oscillator question
    49024: 02/10/30: Altera 1k100 serial EEPROM
    49027: 02/10/30: Re: Altera 1k100 serial EEPROM
    60464: 03/09/13: Looking for Atmel dataflash VHDL model
    87058: 05/07/14: Wanted Actel ProAsic RAM VHDL models
    87061: 05/07/14: Wanted: I2C RAM pre-loader VHDL module
sceloporus occidentalis:
    23155: 00/06/16: Xilinx config over parallel port ?
    23180: 00/06/16: Re: Xilinx config over parallel port ?
    23302: 00/06/21: RE: Xilinx config over parallel port ?
<scepan@serbiancafe.com>:
    51613: 03/01/17: Modelsim crashes
    51707: 03/01/19: Re: Modelsim crashes
    51708: 03/01/20: Re: Modelsim crashes
    51710: 03/01/20: Re: Modelsim crashes
Schachinger Martin:
    46148: 02/08/20: need help with the JAM-Player from ALTERA
    46225: 02/08/22: Re: need help with the JAM-Player from ALTERA
<schaltung@hotmail.com>:
    14007: 99/01/07: fpga socket
    14158: 99/01/16: Intellectual Property
    14794: 99/02/17: Digital PLL
<scheidt@gmail.com>:
    78165: 05/01/25: Re: Truncating Fixed point numbers
    78476: 05/02/01: Re: Synchronizing multibit bus - 2
    78479: 05/02/01: Re: gate/xilinx slice
schellho:
    86687: 05/07/04: Xilinx IOB flop mapping vs. -bp switch
Scherer Anton:
    11236: 98/07/29: Re: TRISTATE in FPGA
    11327: 98/08/05: fast 8x8-Multiplyer
    11881: 98/09/16: Re: Code coverage tools
    17856: 99/09/14: tools for static timing analysis with VITAL?
<schirinboy@yahoo.de>:
    124503: 07/09/25: Variable Phase Shifting for VirtexII DCM
schmitt:
    3987: 96/08/29: Viewlogic to Synopsys VHDL ?
Schneider Daniel:
    18072: 99/09/27: PowerPC <-> VME and PC/104 busses
<schneider@eng.iac.honeywell.com>:
    204: 94/09/21: Postings sent as mail ???--------------
schsym:
    114903: 07/01/25: Re: OrCAD symbol for the Xilinx V5LX50 FF676 device
    125582: 07/10/29: Re: kicad or orcad virtex5 symbol
<schulhof@aol.com>:
    4759: 96/12/11: test
<schultz@cddis.gsfc.nasa>:
    3394: 96/05/24: Re: Looking for free FPGA softw./Xilinx
    3395: 96/05/24: Re: Looking for free FPGA softw./Xilinx
schwarz@informatik:
    17658: 99/08/19: nallatech virtex pci boards
Scope:
    102435: 06/05/16: WARNING:iMPACT:923 - Can not find cable, check cable setup !
    102436: 06/05/16: I can't connect to my Spartan 3 !!! ( Digilent starter kit )
    102512: 06/05/17: Re: WARNING:iMPACT:923 - Can not find cable, check cable setup !
    102518: 06/05/17: ADC implementation on FPGA ?
    102624: 06/05/18: Re: ADC implementation on FPGA ?
    102685: 06/05/19: generate a square signal with a 3.8 ns "plate"
    102696: 06/05/19: Re: generate a square signal with a 3.8 ns
    102715: 06/05/19: Re: generate a square signal with a 3.8 ns
    102721: 06/05/19: Re: generate a square signal with a 3.8 ns
Scorpiion:
    143716: 09/10/22: CPLD/FPGA with Linux
    143784: 09/10/25: Re: CPLD/FPGA with Linux
Scot E. Wilcoxon:
    12348: 98/10/09: Re: What is an embedded IrDA (infrared) software protocol stack?
scot.willis@gmail.com:
    97991: 06/03/02: ISE WebPack and Bitstream encryption
Scott:
    23077: 00/06/13: Re: Virtex IRDY and TRDY
    23078: 00/06/13: Re: Virtex-EM and F2.1
    23144: 00/06/15: Re: CoreGenerator and VHDL
    52848: 03/02/24: Connect USB device to Spartan 2e FPGA
    52869: 03/02/24: Re: Connect USB device to Spartan 2e FPGA
    52918: 03/02/25: Re: Connect USB device to Spartan 2e FPGA
    53001: 03/02/27: Implementing Picoblaze with Xilinx Webpack 4.2
    53216: 03/03/06: How to create a top level VHDL file for given EDIF files
    54193: 03/04/04: Xilinx V2.1i Licensing
    54196: 03/04/04: Re: Xilinx V2.1i Licensing
    54201: 03/04/04: Re: Xilinx V2.1i Licensing
    54205: 03/04/04: Re: Xilinx V2.1i Licensing
    54207: 03/04/04: Re: Xilinx V2.1i Licensing
    54209: 03/04/04: Re: Xilinx V2.1i Licensing
    54439: 03/04/10: How to store data in a 2D array
Scott & Brenda Burris:
    94705: 06/01/16: Re: FPGA Journal Article
Scott A. Hauck:
    2271: 95/11/16: Thesis available: multi-FPGA systems
    2561: 96/01/02: Survey of Reprogrammable Systems
    3287: 96/05/09: FPGA'97 Call For Papers
    3492: 96/06/10: FPGA'97 Call for Papers
    3664: 96/07/10: FPGA'97: Call for Papers
    3927: 96/08/21: FPGA 97 Call for Papers: Due date about a month away!
    4018: 96/09/03: FPGA '97 CFP: Due date in less than a month
    4031: 96/09/04: Re: query: C to FPGA?
    4127: 96/09/16: FPGA'97: Papers due on 9/27/96 (11 days away)
    4135: 96/09/17: FPGA'97: New due date, papers to appear in special issue of TVLSI
    4622: 96/11/21: Re: Async with FPGA?
    4754: 96/12/11: FPGA'97 Advanced Program
    4971: 97/01/07: FPGA '97 Advanced Program
    5039: 97/01/15: Special Issue of TVLSI, Prereg deadline for FPGA'97
    5073: 97/01/20: FPGA'97: Advanced Registration deadline in 2 days
    5295: 97/02/04: Final Notice: FPGA'97 is next week
    5400: 97/02/13: Special issue of TVLSI on FPGA Technology
    6123: 97/04/14: Surveys on Reconfigurable Computing now available
    6124: 97/04/14: Tutorial on Reconfigurable Computing at DAC, June 13th, Anaheim
    6246: 97/05/02: Tutorial on Reconfigurable Computing at DAC, June 13th, Anaheim
    6525: 97/05/30: Re: FAQ's / Documentation sites wanted
    6575: 97/06/03: FPGA'98 Call For Papers
    7183: 97/08/11: FPGA'98 Call For Papers
    7320: 97/08/26: FPGA'98: Papers due in one month
    7480: 97/09/15: FPGA'98: Papers due on 9/26
Scott Alan Hauck:
    2292: 95/11/17: Re: Thesis available: multi-FPGA systems
    6131: 97/04/14: Correction: Surveys on Reconfigurable Computing now available
Scott Bedard:
    9157: 98/02/25: Questions about FPGA
Scott Bekker:
    92849: 05/12/07: Virtex 4 not meeting timing constraints
    93281: 05/12/18: Re: Get Start for XtremeDSP Developement Board -IV
    93301: 05/12/19: Re: Virtex 4 not meeting timing constraints
Scott Bierly:
    684: 95/02/06: Problem with Altera (Intel) SBFX8160-10
    817: 95/03/06: Re: Lattice ispLSI starter kit
    1221: 95/05/17: Re: Altera Flex Logic & Other Problems
    7907: 97/10/28: Re: PROM for FLEX10K
Scott Bilik:
    9079: 98/02/18: Re: Simulator & Synthesis Engine Comparisons
    9158: 98/02/25: Re: Leonardo/VHDL and pullups in FPGAs.
    12208: 98/10/05: Re: Synthesis: Exemplar or Synopsys
    23820: 00/07/11: Re: Remedies after the Fathers' Day Massacre
    23957: 00/07/18: Re: Silicon Valley Housing Nightmare?
    24578: 00/08/14: Re: Yes but I want graphics.
    47774: 02/10/03: Re: TCP/IP in FPGA
Scott Bronson:
    9583: 98/03/24: Partially reconfigurable FPGA
    9884: 98/04/10: Event counting?
    9917: 98/04/13: Re: Event counting?
    9933: 98/04/14: Re: Event counting?
    10274: 98/05/08: Re: Low power FPGA design
Scott C. Evans:
    1205: 95/05/13: Re: How to choose an FPGA vendor
Scott C. Karlin:
    13739: 98/12/21: Circa 1994 Altera 881152GC192 FPGA
Scott Campbell:
    9058: 98/02/17: Re: Free FPGA tools???
    11456: 98/08/16: entry level ASIC salary question
    11595: 98/08/25: Re: SYNTHESIS TOOLS
    21271: 00/03/14: Re: Atmel censors web access
    30997: 01/05/08: Re: Routing: Completed - errors found.
Scott Connors:
    62682: 03/11/04: Video Scan Conversion Rate - Camera Input to DVI Display Output
Scott Cutler:
    762: 95/02/24: Re: Real-time fractal gen in h/w
Scott D. Davilla:
    3264: 96/05/07: FS: Altera EPX780QC132-15
    5108: 97/01/23: Re: Altera PCI experience anyone?
Scott D. Miller:
    5847: 97/03/20: Re: A viewlogic story
Scott Dattalo:
    7207: 97/08/14: Re: 10K100 socket?
Scott Dorsey:
    152954: 11/11/04: Re: Fundamental DSP/speech processing patent for sale
Scott Evans:
    1360: 95/06/06: HELP AT6000
    1662: 95/08/12: Re: Xilinx PROMs
    1865: 95/09/12: Re: ATMEL WWW site?
    2075: 95/10/11: Re: Workview Pro-series doesn't work with windows 95.
    2412: 95/12/01: Atmel Web Site
    6080: 97/04/10: Re: viewoffice <--> viewoffice compatibility
Scott Evans 408-436-4117:
    302: 94/10/17: Re: Multipliers in FPGA's
Scott Frazer:
    10866: 98/06/26: Re: Xilinx Foundation simulator problem?
scott frye:
    87775: 05/08/01: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87776: 05/08/01: Re: Best Practices to Manage Complexity in Hardward/Software Design?
Scott Gargash:
    56: 94/08/05: Re: Intel iFX questions
    1427: 95/06/21: Re: Low cost CPLD/FPGA tools
Scott Gravenhorst:
    134111: 08/07/26: Spartan-3A DSP 1800A Dev Board JTAG Cable and Programming Software
    134120: 08/07/26: Re: Spartan-3A DSP 1800A Dev Board JTAG Cable and Programming Software
    134160: 08/07/28: Re: Spartan-3A DSP 1800A Dev Board JTAG Cable and Programming Software
    134240: 08/07/31: Re: Spartan-3A DSP 1800A Dev Board JTAG Cable and Programming Software
Scott Guest:
    10782: 98/06/18: Re: VHDL testbench in Maxplus2
Scott Guest BNR:
    3127: 96/04/08: Re: FPGA->ASIC conversion
    6864: 97/07/03: Re: Altera MaxPlus2 verilog HIERARCHICAL writer ?
Scott Hauck:
    945: 95/03/31: Overview of implementation technology
    9865: 98/04/09: Reconfigurable Computing Survey in PIEEE
    11340: 98/08/05: FPGA '99 Call for Papers
    11803: 98/09/10: FPGA'99: Papers Due October 2nd
    11978: 98/09/22: FPGA'99: Papers due in 10 days (October 2nd)
    12342: 98/10/09: Re: FCCM 99?
    13694: 98/12/18: FPGA'99 Advance Program
    17355: 99/07/22: Re: Looking for proceedings
    17359: 99/07/22: Re: Floating point on fpga, Counters?
    24563: 00/08/14: Re: state encoding in Synplify!!!
    27136: 00/11/12: Re: CRC, LFSR and scramblers
    29108: 01/02/06: Re: Xilinx XC4010
Scott I. Chase:
    19110: 99/11/29: Re: ClearLogic Vs. Altera
    20390: 00/02/08: Re: Alternate to Altera Flex family
Scott Kroeger:
    2463: 95/12/08: FPGA Synthesis/Simulation
    2479: 95/12/14: Re: Gated Clock Problem in Xilinx FPGA Implementation
    2658: 96/01/20: Re: GRRR!!! Xilinx Makebits defaults changing
    2767: 96/02/04: Re: AT&T Orca vs Xilinx
    2804: 96/02/09: Re: Help: Xilinx behavior if Power down
    2807: 96/02/10: Re: Xilinx is NOT specified MINIMUM delay -- is it right??
    2860: 96/02/17: Re: Lowest power FPGA or PLD
    2978: 96/03/07: Re: EEPROM for Xilinx
    3047: 96/03/20: Re: Low-power FPGA or EPLD
    3054: 96/03/22: Re: What bus is a Xilinx XC1736DP SPROM?
    3099: 96/04/01: Re: XACT5.2 bit file length count changes
    3175: 96/04/18: Re: Power consumption of Xilinx device
    3181: 96/04/20: Re: On FPGAs as PC coprocessors
    3258: 96/05/04: Re: Simple Xilinx board
    3334: 96/05/14: Re: Evolvable HW
    3348: 96/05/16: Re: Looking for free FPGA softw./Xilinx
    3405: 96/05/24: Re: WEIRD NOISE PROBLEM WITH XILINX XC3064 - can anyone help?
    3409: 96/05/25: Re: OTP FPGAs was WEIRD NOISE PROB
    3460: 96/06/03: Re: Xilinxs FPGAs (newbies)
    3530: 96/06/15: Re: UART for Actel FPGA
    3543: 96/06/18: Re: Simple Xilinx board
    3676: 96/07/11: Re: wireless loader for (Xilinx) FPGAs ?
    3748: 96/07/24: Re: Does XACT(ver5.2) support 4000E series?
    3822: 96/08/06: Re: Xilinx/FPGA Timing Problems
    3826: 96/08/07: Re: Xilinx/FPGA Timing Problems
    3827: 96/08/07: Re: Xilinx clock doubler?
    3882: 96/08/14: Re: Xilinx/FPGA Timing Problems
    3906: 96/08/17: Re: Xilinx: question about bitstream and parallel download
    3915: 96/08/19: Re: Xilinx: question about bitstream and parallel download
    3974: 96/08/27: USB Host Core for FPGA/Gate Array
    3980: 96/08/28: Re: DO I REALLY NEED A XCHECKER CABLE?
    3981: 96/08/28: Re: DO I REALLY NEED A XCHECKER CABLE?
    4133: 96/09/17: Re: Inaccrate Xilinx simulations ???
    4306: 96/10/12: Re: Async with FPGA?
    4344: 96/10/17: Re: (no subject)
    4347: 96/10/18: Re: What are I/O's doing prior to configuration?
    4365: 96/10/20: Re: VHDL for Xilinx designs?
    4469: 96/11/01: XACT under WinNT is very slow
    4476: 96/11/03: Re: XACT under WinNT is very slow
    4490: 96/11/05: Re: XACT under WinNT is very slow
    4723: 96/12/06: Re: XACT under WinNT is very slow
    4731: 96/12/07: Re: Memory Requirements
    4740: 96/12/10: Re: Xilinx configuration PROM
    4817: 96/12/17: Re: ASICs Vs. FPGA in Safety Critical Apps.
    4907: 96/12/28: Re: ASICs Vs. FPGA in Safety Critical Apps.
    4913: 96/12/29: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5300: 97/02/05: Re: Robust Applications with FPGAs
    5412: 97/02/14: Re: [Q].FIFO in FPGA XILINX
    5437: 97/02/15: Re: Xilinx programming...(long)
    5615: 97/02/28: Re: Xilinx or Altera?
    5723: 97/03/10: Re: A viewlogic story
Scott L. Baker:
    45661: 02/07/31: looking for : Intel .hex to Xilinx .coe conversion
    45831: 02/08/07: Looking for behavioral Xilinx RAM model
Scott L. Burris:
    36342: 01/11/07: FPGA suppliers for hobbyists?
Scott Lurndal:
    145763: 10/02/23: Re: using an FPGA to emulate a vintage computer
    145838: 10/02/25: Re: using an FPGA to emulate a vintage computer
    145848: 10/02/25: Re: using an FPGA to emulate a vintage computer
    145851: 10/02/26: Re: using an FPGA to emulate a vintage computer
    145952: 10/03/01: Re: using an FPGA to emulate a vintage computer
    146043: 10/03/04: Re: using an FPGA to emulate a vintage computer
Scott M. Kroll:
    98263: 06/03/07: Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution
    98265: 06/03/07: Re: recommendation for JTAG Boundary Scan software??
    98294: 06/03/08: Re: Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution
    98457: 06/03/10: Re: Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution
Scott Mahlke:
    70158: 04/06/07: CFP: Workshop on Application Specific Processors (WASP 2004)
    70728: 04/06/24: CFP - WASP 2004 - Abstracts due July 1
Scott McIntosh:
    5226: 97/01/31: Suggestions how wire wrap mount a Xilinx PG223
    5286: 97/02/04: Thanks for suggestions
Scott Michel:
    152598: 11/09/16: Re: The Manifest Destiny of Computer Architectures
scott moore:
    109258: 06/09/22: Help with webpack/ISE 8.2
    109322: 06/09/23: Re: Help with webpack/ISE 8.2
    109929: 06/10/08: Antifuse, lower cost?
    110093: 06/10/10: Re: Antifuse, lower cost?
    110094: 06/10/10: Re: Antifuse, lower cost?
    110180: 06/10/11: Re: Antifuse, lower cost?
    110181: 06/10/11: Re: Antifuse, lower cost?
    110182: 06/10/11: Re: Antifuse, lower cost?
    111013: 06/10/26: Re: ISE 8.2 freeze
    111287: 06/10/31: Xilinx ISE, where do the pins go?
    111525: 06/11/04: Re: Scientific Computing on FPGA
    111602: 06/11/06: Re: Scientific Computing on FPGA
    112091: 06/11/15: Re: 8080 FSGA model in an FPGA
    112450: 06/11/22: Re: 8080 FSGA model in an FPGA
    112452: 06/11/22: Re: 8080 FSGA model in an FPGA
Scott Munroe:
    49199: 02/11/04: VME Master Design
    49227: 02/11/05: Re: How to approch timing constraints...
    49387: 02/11/11: Re: new to fpga, what language is better to start with
    49436: 02/11/12: Re: FPGA Size?
Scott Murphy:
    572: 95/01/08: RFD: comp.cad.viewlogic
    1702: 95/08/17: Re: FPGAs with embedded RAM
    1765: 95/08/28: Re: Actel PCI App Note
    1783: 95/09/01: Re: VHDL Savy editors under UNIX?
    2398: 95/11/28: bus model of the 68EC000
Scott Paul Johnston:
    10735: 98/06/14: UPDATED ENGINEERING PAGE: Please visit and comment
    10927: 98/07/02: UPDATED ENGINEERING PAGE: Please Visit
    10931: 98/07/04: UPDATED ENGINEERING PAGE: Please Visit
    11382: 98/08/08: New engineering page: please visit
    11651: 98/08/28: NEW ENGINEERING PAGE: Please Visit
    11841: 98/09/12: NEW ENGINEERING PAGE: Please Visit
    12073: 98/09/27: NEW ENGINEERING PAGE: Please Visit
    12356: 98/10/09: NEW ENGINEERING PAGE: Please Visit
    13259: 98/11/22: NEW ENGINEERING PAGE: Please Visit
    13421: 98/12/02: NEW ENGINEERING PAGE: Please Visit
    13832: 98/12/29: NEW ENGINEERING PAGE: Please Visit
    14040: 99/01/08: NEW ENGINEERING PAGE: Please Visit
    14610: 99/02/06: NEW ENGINEERING PAGE: Please Visit
    21352: 00/03/18: UPDATED ENGINEERING PAGE: Please Visit
Scott Redman:
    5005: 97/01/10: Re: Altera clique
    5444: 97/02/16: Re: Altera Max Plus 2 Software bug
Scott Schlachter:
    4187: 96/09/23: Re: How to Begin with FPGA design?
    25168: 00/08/29: Re: Anyone used Spartan II XC2S200 yet?
    25250: 00/09/01: Re: Xilinx and CD databooks (rant)
    26773: 00/10/27: Re: 155Mhz DDR in a programmable logic
    27400: 00/11/20: Re: Synthesizable VHDL
    27402: 00/11/20: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
    43278: 02/05/17: Re: Reading GSR signal of Spartan-II
    100620: 06/04/13: Re: Spartan 3E Starter Kit is finally here!
    105105: 06/07/13: Re: Spartan 3E starter kit DDR SDRAM code
Scott Seidman:
    107628: 06/08/30: Re: Performance Appraisals
    109241: 06/09/22: Re: Dell Laptop for Embedded Work
Scott Taylor:
    1497: 95/07/03: Xilinx PROM, Altera FPGA
    1496: 95/07/01: Xilinx PROMs with Altera FPGAs
    28827: 01/01/25: Re: really fast counter in SpartanXL?
Scott Thibault:
    25816: 00/09/21: Announce: Free HC11 CPU Core
    25836: 00/09/22: Re: Announce: Free HC11 CPU Core
    30404: 01/04/06: Beta tester needed: VHDL Studio Solaris/Linux/Windows
    35362: 01/10/01: ANN: VHDL Studio for Solaris
    39031: 02/01/30: Java or bytecode processors??
    39088: 02/01/31: Re: Java or bytecode processors??
    47699: 02/10/02: ANN: Embedded processor for Tcl language
    47752: 02/10/03: Re: ANN: Embedded processor for Tcl language
    47753: 02/10/03: Re: ANN: Embedded processor for Tcl language
    47829: 02/10/04: Re: ANN: Embedded processor for Tcl language
    47830: 02/10/04: Re: ANN: Embedded processor for Tcl language
    48737: 02/10/23: ANN: Embedded processor for Tcl language
    66489: 04/02/20: ANN: Graphical Testbench Tool Download
    66491: 04/02/20: Re: ANN: Graphical Testbench Tool Download
Scott Thomas:
    5070: 97/01/20: AMD names programmable logic company
    5234: 97/01/31: Re: Steven K. Knapp - no such article
    6249: 97/05/02: Re: ISP CPLD from AMD or Cypress???
    6288: 97/05/09: Re: ISP CPLD from AMD or Cypress???
    8670: 98/01/19: Vantis Enters FPGA Market Unveiling New Variable-Grain-Architecture Devices With Industry Leading Performance
    8693: 98/01/20: Re: Vantis Enters FPGA Market Unveiling New Variable-Grain-Architecture Devices With Industry Leading Performance
Scott Willis:
    100585: 06/04/12: vertex II and powerpc core
    100608: 06/04/13: Re: vertex II and powerpc core
    117796: 07/04/10: EDK 8.2 MicroBlaze Tutorial
    117882: 07/04/12: Problem with EDK 8.2 MicroBlaze Tutorial
Scott Winick:
    16539: 99/05/26: Re: Dual Port mem
<scott.yuan523@gmail.com>:
    130587: 08/03/27: Dual Independent Aurora Links on One GTP Tile
<scottf3095@aol.com>:
    87725: 05/07/29: Re: Best Practices to Manage Complexity in Hardward/Software Design?
scottfrye:
    87514: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87574: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software Design?
scottie:
    75691: 04/11/12: Virtex-II Pro Dev Board for RTOS Integrity
    75735: 04/11/13: Virtex-II Pro Dev Board for RTOS Integrity
ScottNortman:
    110546: 06/10/17: Re: buying xilinx spartan 3E kit just for EDK ?
    110710: 06/10/20: Re: Microblaze uclinux Kernel panic
    110811: 06/10/23: Re: Microblaze uclinux Kernel panic
    111749: 06/11/09: Re: How to send data/program to the memory of a Spartan 3 starter kit board
    115722: 07/02/17: Xilinx ISE WebPack Simulation Problem
scotto:
    98907: 06/03/17: HWICAP with the Virtex II Pro. Anybody? Bueller?
    105360: 06/07/20: Linux on an XUP board - cant access user IP!
SCOTTY9000:
    153513: 12/03/20: Re: ways to find frequency of operation in early phase of the design without syntheis
<scottydm@aol.com>:
    5289: 97/02/04: Re: Verilog --> FPGA
scouselad:
    125291: 07/10/19: Files produced by Quartus II compiler
    125307: 07/10/19: Re: Files produced by Quartus II compiler
scraven:
    79683: 05/02/23: Open Request for Help
    79684: 05/02/23: Re: (Q) interconnections between microblazes
<ScreamingFPGA@yahoo.com>:
    88297: 05/08/14: Spartan-3 configuration -- peculiar problem
    88338: 05/08/15: Re: Spartan-3 configuration -- peculiar problem
    88343: 05/08/15: Re: Spartan-3 configuration -- peculiar problem
    88379: 05/08/16: Re: Spartan-3 configuration -- peculiar problem
    88382: 05/08/16: Re: Spartan-3 configuration -- peculiar problem
    88424: 05/08/17: Re: Spartan-3 configuration -- peculiar problem
scrts:
    150688: 11/02/03: Re: Trivia: Where are you on the HDL Map?
    150725: 11/02/07: Re: Why is the Cyclone IV so expensive?
    151097: 11/03/06: Re: IP Core Delivery Format Info
    151125: 11/03/08: Re: Finding cheap PCI-E FPGA board for a student
    151277: 11/03/20: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
    151393: 11/04/01: Re: Ideal FPGA Development Kit
    151402: 11/04/03: Re: Ideal FPGA Development Kit
    151407: 11/04/03: Re: Ideal FPGA Development Kit
    151409: 11/04/03: Re: Ideal FPGA Development Kit
    151426: 11/04/06: Re: Ethernet MAC on Virtex 4
    151432: 11/04/07: Re: Ethernet MAC on Virtex 4
    151609: 11/04/26: Re: Lattice Breakout Boards
    151625: 11/04/27: Re: Excess Stratix IV and SIII parts inventory
    151702: 11/05/07: Re: Soft Processors and Licensing
    151706: 11/05/08: Re: Soft Processors and Licensing
    151976: 11/06/16: Choosing a scope
    151988: 11/06/19: Re: Choosing a scope
    151989: 11/06/19: Re: Choosing a scope
    151991: 11/06/20: Re: Xilinx or Altera
    151998: 11/06/20: Re: Xilinx or Altera
    152152: 11/07/14: Re: Looking for a FPGA board
    152161: 11/07/15: Re: Looking for a FPGA board
    152171: 11/07/15: Re: Looking for a FPGA board
    152310: 11/08/06: Re: QuartusII Ver11.0 programmer problems?
    152377: 11/08/17: Re: 5V FCT TO Cyclone II
    152477: 11/08/28: Re: cheating Arria FPGA i/o count
    152602: 11/09/17: Re: Virtex 6 dev. board suppliers?
    152611: 11/09/18: Re: How to digitize the VGA output using FPGA?
    152637: 11/09/19: Re: Virtex 6 dev. board suppliers?
    152672: 11/09/26: Re: FPGA + TVP70025i Board
    152678: 11/09/27: Re: PCI core with expansion ROM support
    152754: 11/10/19: Re: Altera FPGA weirdness
    152973: 11/11/07: Re: PCI Express development board
    152974: 11/11/07: Re: PCI Express development board
    153012: 11/11/14: Re: PCI Express development board
    153018: 11/11/15: Re: PCI Express development board
    153022: 11/11/16: Re: PCI Express development board
    153079: 11/11/28: Re: Compatible Xilinx USB Cables: worth to bother?
    153083: 11/11/28: Re: Compatible Xilinx USB Cables: worth to bother?
    153103: 11/12/01: Re: Compatible Xilinx USB Cables: worth to bother?
    153294: 12/01/27: Re: No daily abridged emails
    153561: 12/03/28: Re: FPGA communication with a PC (Windows)
    153562: 12/03/28: Re: FPGA communication with a PC (Windows)
    153620: 12/04/05: Re: Free Seminars/Labs - Implementing PCI Express Designs in FPGAs
    153791: 12/05/22: Re: ITU656 to Mpeg4 with Fpga?
    154093: 12/08/03: Re: how much costs the Artix 7 devices?
    154200: 12/09/07: Re: Verilog file operations
    154653: 12/12/12: Re: Where to move for an embedded software engineer.
    154665: 12/12/14: Re: Where to move for an embedded software engineer.
    155109: 13/04/19: Re: FPGA board with 4 channel 500Msps ADC?
    155589: 13/07/25: Re: Nios II problem with DDR core SOPC builder
Scullen:
    30725: 01/04/26: it worked-site for salary information
Scutum612:
    132388: 08/05/25: XST 3.0 Xess Audio to Ethernet
Scylla:
    6027: 97/04/06: Re: Pentium Pro Worth it for Altera Max Plus?
    6028: 97/04/06: Re: Pentium Pro Worth it for Altera Max Plus?
SD:
    68637: 04/04/11: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
    68673: 04/04/13: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
    68912: 04/04/21: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
    74185: 04/10/05: Sine function implementation in FPGA??
    74353: 04/10/08: Sine function implementation in FPGA
    77321: 05/01/04: Algorithm to Hardware ?
    78086: 05/01/24: Truncating Fixed point numbers
    78098: 05/01/24: Re: Truncating Fixed point numbers
    78852: 05/02/08: .vho (Xilinx Core Generator) to .vhd ??
    79304: 05/02/17: binary constant divider theory
    79337: 05/02/17: Re: binary constant divider theory
    79342: 05/02/17: Re: binary constant divider theory
    79369: 05/02/17: Re: binary constant divider theory
    79619: 05/02/22: Exporting Modelsim Values?????
sd:
    72866: 04/09/06: Need assistance with an FPGA based project.
    72872: 04/09/06: I NEED HELP / MENTOR
    88564: 05/08/23: Good SystemC tutorials or books?
sdaau:
    142495: 09/08/13: JTAGkey-Tiny with Altera/Xilinx FPGA?
    142588: 09/08/19: Help with crystal oscillator (MG-7010SA replacement)?
    142647: 09/08/24: Re: Help with crystal oscillator (MG-7010SA replacement)?
    142971: 09/09/11: Behavior of crystal oscillator?
    142996: 09/09/14: Re: Behavior of crystal oscillator?
    143023: 09/09/15: Re: Behavior of crystal oscillator?
    143767: 09/10/24: ISE 9.2 - RTL Schematic problem (separating of included components)
    143771: 09/10/24: Re: ISE 9.2 - RTL Schematic problem (separating of included components)
    151176: 11/03/14: Command line for fuse (behavioral sim), for ISE WebPack 9.2/xtclsh? (dbl)
    151201: 11/03/15: Re: Command line for fuse (behavioral sim), for ISE WebPack 9.2/xtclsh? (dbl)
    151207: 11/03/15: Re: Command line for fuse (behavioral sim), for ISE WebPack 9.2/xtclsh? (dbl)
    151265: 11/03/19: Re: Command line for fuse (behavioral sim), for ISE WebPack 9.2/xtclsh? (dbl)
    151266: 11/03/19: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
    152221: 11/07/22: Post-map simulation: timing violation and delays
    152222: 11/07/22: Re: Post-map simulation: timing violation and delays
    152249: 11/07/27: Re: Post-map simulation: timing violation and delays
    152254: 11/07/28: Re: Post-map simulation: timing violation and delays
sdaq:
    78907: 05/02/09: In need of some life-changing advice
    78988: 05/02/10: Re: In need of some life-changing advice
<sdatta@altera.com>:
    76860: 04/12/14: Re: altera DDR core simulation with NCSim
<sdave@ufl.edu>:
    112352: 06/11/20: Re: Semantics or examples for Xilinx xgpio driver under Linux?
sderien@liacs.nl:
    53884: 03/03/26: Virtex II pro board design question
sdf:
    124682: 07/09/30: Re: Own soft-processor
    129514: 08/02/26: Convert some table into combinatorial circuit + optimization
    129517: 08/02/26: Re: Convert some table into combinatorial circuit + optimization
    129640: 08/03/01: Quartus 7.2sp2 memory exhaustion
    129746: 08/03/04: [Altera] How to infer some code into ROM-blocks (in automatic way),
    129747: 08/03/04: Re: How to infer some code into ROM-blocks (in automatic way), but
    129888: 08/03/08: Cyclone III and Quartus 7.2sp2
    129892: 08/03/08: Re: Cyclone III and Quartus 7.2sp2
    129903: 08/03/08: Re: Cyclone III and Quartus 7.2sp2
    129907: 08/03/09: Re: Cyclone III and Quartus 7.2sp2
    129985: 08/03/12: Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal
    130007: 08/03/12: Re: Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal
    130019: 08/03/13: Almost offtopic about HDL optimizing.
    130022: 08/03/13: Re: Almost offtopic about HDL optimizing.
sdfg:
    40434: 02/03/07: pipeline
sdfjsd:
    37217: 01/12/04: Re: I need a Xilinx Spartan PCI Development Board
    37273: 01/12/06: Re: I need a Xilinx Spartan PCI Development Board
    37274: 01/12/06: Re: where is designed FPGA for apple II computer...?
    37568: 01/12/15: Re: XESS XSV-800 Gripes
    37570: 01/12/15: newbie Xilinx Foundation ISE4.1 questions
    37571: 01/12/15: Re: PC Cache size. Was: ModelSim performance on Solaris/sparc and
SDL:
    53199: 03/03/06: Re: Only for Altera Nios users or Modelsim expert
    53207: 03/03/06: Re: altera quartusII help
    58624: 03/07/29: SRAM question in Cyclone Dev. Board
    65276: 04/01/23: Quartus doesn't work with Pentium Hypertheading!
    93511: 05/12/23: Re: Altera based Video development board
<-01982414sdl6498xxjfgskrljz939z@qubpyobj.au>:
sdrg:
    45682: 02/08/01: about amplify/synplify
sduduma:
    22160: 00/04/28: maxplus2 lpm in renoir
sduszyk:
    51947: 03/01/27: xilinx schematics conversion
<sdwbsz@who.com>:
se:
    90853: 05/10/23: FPGA Design Docs
    97364: 06/02/21: Re: FPGA - software or hardware -2-
    100076: 06/04/03: Re: ModelSim Designer
    103635: 06/06/07: Re: FlipChip BGA Conformal Coating
<se10110@yahoo.com>:
    58716: 03/07/31: Re: PLL / DPLL phase question
    60912: 03/09/24: Re: Synchronous counter enable pulse length
    62784: 03/11/07: FPGA & handling reset of a logic block while running
Sea Squid:
    81006: 05/03/16: Need recommendation on an FPGA board with a USB socket.
    81047: 05/03/17: Re: Need recommendation on an FPGA board with a USB socket.
    81048: 05/03/17: Using XC2V6000 to send/receive test vectors.
    81057: 05/03/17: Re: Need recommendation on an FPGA board with a USB socket.
    81059: 05/03/17: How much current does an LED take?
    81060: 05/03/17: Re: How much current does an LED take?
    81124: 05/03/18: Re: Using XC2V6000 to send/receive test vectors.
    81132: 05/03/18: Re: Performance evaluation of Distributed Arithmetic architectures for FIR filters
    81575: 05/03/28: What is the format of .COE file used in the Coregen's RAM generator?
    81577: 05/03/28: Re: What is the format of .COE file used in the Coregen's RAM generator?
    81579: 05/03/28: How do I fix this error?
    81580: 05/03/28: Re: looking for keyboard scancode
Sea-Hawon Choi:
    2002: 95/09/30: Info needed for courses using FPGA and VHDL
seabedj163.com:
    44993: 02/07/09: Re: Multiple constraints, same net?
<seabrench@163.com>:
    89818: 05/09/27: Image Processing Algorithm based on FPGA?
    90293: 05/10/09: Library Simprim cannot be found?
    90505: 05/10/14: Re: Library Simprim cannot be found?
    90526: 05/10/15: About with Synplify Pro?
<seamang@wmin.ac.uk>:
    15588: 99/04/01: Re: IP cores and software industry
seamus:
    20833: 00/02/23: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
    24234: 00/07/31: Virtex DLL and external clocks
    28434: 01/01/12: Re: grey code counters
Seamus McGrady:
    2345: 95/11/21: Re: Viewlogic problem
Sean:
    41992: 02/04/12: Need help with Spartan2 and ISA bus interface please.
    42136: 02/04/16: IO Standards supported in Spartan-II devices
    42345: 02/04/21: Programming Spartan2 and external clock
    42392: 02/04/22: Trouble assigning tri-stated output buffers in Spartan2 w/Foundation
    42483: 02/04/24: Re: Using 74HCT245N between Spartan-II and ISA
    42505: 02/04/25: Re: Using 74HCT245N between Spartan-II and ISA
    42506: 02/04/25: Problems creating a tristated data bus on Spartan-II
    43083: 02/05/13: Neverending ISA bus interface drama, Spartan-II
    43116: 02/05/14: Re: Neverending ISA bus interface drama, Spartan-II
    51895: 03/01/24: Using an EPC16 as ONLY flash memory (ie. no configuration) - overkill?
    51934: 03/01/26: Re: Using an EPC16 as ONLY flash memory (ie. no configuration) - overkill?
    52065: 03/01/30: How to do on-the-fly reconfiguration of a Flex10ke using an EPC16?
    53676: 03/03/19: Re: Quartus2 : assigning I/O pins
    53800: 03/03/24: Quartus-II, how to use a user package
    74974: 04/10/22: Xilinx and Altera Modelsim on the same PC?
    105190: 06/07/17: EDK PowerPC ISS : download errors?
sean:
    85774: 05/06/15: Re: Availability of Spartan3
    85805: 05/06/16: Re: Availability of Spartan3
    86872: 05/07/07: Re: fastest FPGA speed grade? Not the only measure, but ...
Sean A Laughter:
    42477: 02/04/24: Using 74HCT245N between Spartan-II and ISA
    42642: 02/04/30: SpartanII ISA interface, IDE and ISA contention??
Sean Burroughs:
    97882: 06/03/01: Re: How do I make dual-port RAM from single port RAM?
Sean Cundiff:
    6900: 97/07/07: D Algorithm
sean da:
    48831: 02/10/24: Please recommend a FPGA chip!
    48863: 02/10/25: Re: Please recommend a FPGA chip!
    48912: 02/10/26: Re: Please recommend a FPGA chip!
    51059: 02/12/28: dualport ram instantiation in Spartan IIE
Sean Durkin:
    62466: 03/10/30: VirtexII-Pro: Full Readback via ICAP/SelectMAP
    62852: 03/11/10: VirtexII-Pro: Why is ICAP slower than SelectMAP?
    62862: 03/11/10: Re: VirtexII-Pro: Why is ICAP slower than SelectMAP?
    62911: 03/11/11: Re: VirtexII-Pro: Why is ICAP slower than SelectMAP?
    63219: 03/11/18: Re: using multilinx from ISE to download a bit file
    63427: 03/11/21: Re: Undocumented units in Virtex (I assume in Spartan-II too)
    64334: 03/12/29: Re: This design contains an RPM macro bm_0 which is to be automatically
    64337: 03/12/29: Re: This design contains an RPM macro bm_0 which is to be automatically
    64355: 03/12/30: Re: This design contains an RPM macro bm_0 which is to be automaticallyplaced,
    64707: 04/01/12: V2P7 Partial reconfiguration, FATAL_ERROR in par
    65475: 04/01/30: Re: One bit Virtex BRAM.
    65685: 04/02/04: Re: How do I fix this type of errors?
    65702: 04/02/05: Re: How do I fix this type of errors?
    65922: 04/02/10: Re: Partial reconfig flow
    66082: 04/02/12: Re: getting back Xilinx ISE commands
    66096: 04/02/12: Re: Partial reconfig flow
    66098: 04/02/12: Re: Partial reconfig flow - Aaaarrrrgggghhhh! I am dead!!!
    66101: 04/02/12: Re: getting back Xilinx ISE commands
    66167: 04/02/13: Re: Partial reconfig flow
    66314: 04/02/17: Re: Xilinx Chipscope Sample rate
    66326: 04/02/17: Re: Xilinx Chipscope Sample rate
    66336: 04/02/17: Re: Xilinx Chipscope Sample rate
    66567: 04/02/23: Re: EDK 6.1 vs 3.2 and OPB Bus resets
    66570: 04/02/23: Re: Help with Xilinx EDK 6.1
    67183: 04/03/08: Re: How do I fix this type of errors?
    67193: 04/03/08: Re: inquiry on document for partial configuration
    67778: 04/03/19: Re: V2p, plb VS opb
    68101: 04/03/26: Re: Bus macro in partial reconfiguration
    68220: 04/03/30: More Chipscope JTAG Blues...
    68360: 04/04/02: Re: Bus macro in partial reconfiguration
    68269: 04/03/31: Re: XAPP134's VHDL code
    68889: 04/04/21: Re: Partial Reconfiguration
    68930: 04/04/22: Re: Microblaze Sub-Module Adventure
    69317: 04/05/06: Re: bitgen progarm in ISE
    69486: 04/05/12: Re: reading bitstream in FPGA
    69497: 04/05/12: Re: Floating Point With Xilinx EDK (PPC)?
    69530: 04/05/13: Re: virtex dev board?
    69532: 04/05/13: Re: virtex dev board?
    69542: 04/05/13: Re: Floating Point With Xilinx EDK (PPC)?
    69563: 04/05/14: Re: Updating a XILINX Project
    69737: 04/05/19: Xilinx V2P: DCM and changing input clock
    69755: 04/05/19: Re: Xilinx V2P: DCM and changing input clock
    69795: 04/05/20: Re: Xilinx EDK (PPC): Problems Porting to Memec 2VP4LC Board
    69825: 04/05/21: XIlinx V2P7: DCM won't lock
    69862: 04/05/22: Re: XIlinx V2P7: DCM won't lock
    69863: 04/05/22: Re: XIlinx V2P7: DCM won't lock
    69908: 04/05/24: Re: XIlinx V2P7: DCM won't lock
    70816: 04/06/29: Where are the EDK3.x service packs?
    70818: 04/06/29: Re: Where are the EDK3.x service packs?
    71670: 04/07/27: Re: How to set Microblaze frequence?
    72269: 04/08/12: Re: Can PPC in V2P reconfig the FPGA slices?
    72287: 04/08/13: Re: Do you know how to reconfig the DFS of Spartan DCM at runtime
    72346: 04/08/16: Re: Can PPC in V2P reconfig the FPGA slices?
    72370: 04/08/17: Re: Can PPC in V2P reconfig the FPGA slices?
    72374: 04/08/17: Re: Can PPC in V2P reconfig the FPGA slices?
    72406: 04/08/18: Re: Can PPC in V2P reconfig the FPGA slices?
    72879: 04/09/07: DDR2 SDRAM and Virtex2Pro
    75178: 04/10/28: Re: OPB versus PLB
    74235: 04/10/06: Re: DCM and CLKFX - is this allowed?
    74837: 04/10/20: Re: Question for XST expert
    76386: 04/12/01: Re: block ram and bmm files
    76462: 04/12/03: Xilinx Memory Interface Generator
    76534: 04/12/06: Re: Xilinx 6.2 to 6.3 upgrade brakes soc
    76650: 04/12/08: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO
    76845: 04/12/14: Linking FPGAs with RocketIOs
    76873: 04/12/15: Re: Linking FPGAs with RocketIOs
    76874: 04/12/15: Re: Linking FPGAs with RocketIOs
    76882: 04/12/15: Re: Linking FPGAs with RocketIOs
    78081: 05/01/24: LVPECL and SelectIO banking rules in V2P
    78114: 05/01/25: Platform Cable USB on WinXP with SP2
    78367: 05/01/31: Re: LVPECL and SelectIO banking rules in V2P
    78812: 05/02/08: Re: opb_ddr connection to DDR chips
    78846: 05/02/08: Re: opb_ddr connection to DDR chips
    78895: 05/02/09: Re: Newbie: add opb_ddr to a project
    81275: 05/03/21: Re: Xilinx - ucf file parsing errors
    82644: 05/04/15: Re: different I/O buffers available inXilinx FPGA
    82805: 05/04/18: Re: Missing post
    83752: 05/05/06: Parallel Cable IV opened in "Compatibility Mode"
    83861: 05/05/08: Re: Parallel Cable IV opened in "Compatibility Mode"
    83951: 05/05/10: Re: Parallel Cable IV opened in "Compatibility Mode"
    84676: 05/05/24: Re: Mapping problem due to invalid pins in UCF file
    84712: 05/05/25: Re: Xilinx Answer Record 21127
    84856: 05/05/31: Magical Mystery Tour of ISE environment variables
    84858: 05/05/31: Re: Magical Mystery Tour of ISE environment variables
    85031: 05/06/03: Re: Basics FPGA
    85691: 05/06/14: Re: generating 90, 180 and 270 shifts
    85738: 05/06/15: Re: EDK 7.1 installation error: Missing libPortability.dll file
    85780: 05/06/16: Re: EDK 7.1 installation error: Missing libPortability.dll file
    86209: 05/06/23: Re: FPGAs: Where will they go?
    86212: 05/06/23: Virtex-4 FX devices availablity issues
    86442: 05/06/28: Re: Control IPIF signals
    86519: 05/06/29: Re: synthesis problem
    86578: 05/06/30: Re: read & write on SDRAM speed with PPC 300 MHz
    86967: 05/07/11: Re: output-value isn't stored
    87036: 05/07/13: Re: output-value isn't stored
    87847: 05/08/02: Re: fpga- DDR or DDR2
    87878: 05/08/03: Re: How to import EDIF netlist into ISE webpack 7.1
    87981: 05/08/04: Re: Xilinx Impact order
    87983: 05/08/04: Re: How to import EDIF netlist into ISE webpack 7.1
    88008: 05/08/05: Re: RocketIO connexion to an optical transceiver
    88102: 05/08/09: Re: Xilinx Impact order
    88403: 05/08/17: Re: Xilinx ISE on remtoe Display
    88444: 05/08/18: Re: State Machine and BUFG
    88572: 05/08/23: Re: Stdin / stdout through RS232
    89299: 05/09/12: Re: Fatal errror in ISE 6.3 i
    89313: 05/09/12: Re: modelsim simulation problem
    89504: 05/09/16: Re: problem with programming avnet edk board over LPT
    89638: 05/09/21: Re: JTAG USB Circuit
    89852: 05/09/28: Re: IPIF interface not fast enough
    90084: 05/10/04: Re: Xilinx IMPACT Problem... detects 101 unknown devices
    90674: 05/10/18: Re: Xilinx USB cable
    91012: 05/10/27: Re: Xilinx ISERDES
    92052: 05/11/21: Re: Sounds or other means to indicate end of compilation in Xilinx
    93695: 05/12/28: Re: Xilinx V4 LVDS
    93697: 05/12/28: Re: Xilinx V4 LVDS
    94153: 06/01/06: Re: Ethernet Encoding scheme
    94474: 06/01/12: Re: UCF-File problem
    94666: 06/01/16: Re: Don't even get me started on lead,
    95990: 06/01/27: Virtex-4 ISERDES and ADS527X ADCs
    96026: 06/01/28: Re: Virtex-4 ISERDES and ADS527X ADCs
    96083: 06/01/30: Re: Virtex-4 ISERDES and ADS527X ADCs
    96023: 06/01/28: Re: Virtex-4 ISERDES and ADS527X ADCs
    96053: 06/01/29: Re: Virtex-4 ISERDES and ADS527X ADCs
    96082: 06/01/30: Re: Virtex-4 ISERDES and ADS527X ADCs
    96027: 06/01/28: Re: Virtex-4 ISERDES and ADS527X ADCs
    96057: 06/01/29: Re: Virtex-4 ISERDES and ADS527X ADCs
    96081: 06/01/30: Re: Virtex-4 ISERDES and ADS527X ADCs
    96055: 06/01/29: Re: Virtex-4 ISERDES and ADS527X ADCs
    96245: 06/02/01: Re: Parallel Cable IV does not work with parallel to usb cable
    96661: 06/02/08: Virtex4 Powerdown, Vcco questions
    96698: 06/02/09: Re: Virtex4 Powerdown, Vcco questions
    97942: 06/03/02: Re: Xilinx MIG
    97948: 06/03/02: Re: Xilinx MIG
    97957: 06/03/02: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98037: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98217: 06/03/07: Re: Simulation of Xilinx Rocket IO
    99439: 06/03/24: Re: Xilinx hi-speed interconnect/routing question
    101040: 06/04/24: Re: comp.arch.reconfig
    102005: 06/05/09: Re: Xilinx ISE 8.1 Makefile
    103574: 06/06/06: ISE8.1 on OpenSUSE 64bit
    103604: 06/06/06: Re: ISE8.1 on OpenSUSE 64bit
    103625: 06/06/07: Re: ISE8.1 on OpenSUSE 64bit
    104243: 06/06/21: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
    104371: 06/06/26: Re: VHDL model for Micron SDRAM simulation ?
    104396: 06/06/26: Re: multisource on signal in XPS
    105018: 06/07/12: Re: ISE8.1 on OpenSUSE 64bit => ISE8.2 works
    105029: 06/07/12: Diffenrential I/Os in Virtex-4
    105054: 06/07/12: Re: Diffenrential I/Os in Virtex-4
    105066: 06/07/12: Re: Diffenrential I/Os in Virtex-4
    105461: 06/07/24: Re: version control of ISE+EDK projects with CVS and/or SVN
    107771: 06/09/01: Re: V2PRO30 Check
    109795: 06/10/05: Re: Are you ready for Virtex-5? We are...
    110517: 06/10/17: Re: ISE On Intel Mac
    110782: 06/10/23: Re: cross-post: newsgroup servers
    110970: 06/10/26: Re: Xilinx MIG 1.6 doesn't launch
    111961: 06/11/13: Re: Xilinx platform cable USB
    112362: 06/11/21: Re: Simple questions on IDELAYCTRL
    112642: 06/11/27: Re: vccaux and vccint
    112670: 06/11/27: Re: vccaux and vccint
    112796: 06/11/29: Re: DVI clock generation
    112812: 06/11/29: Re: DVI clock generation
    112814: 06/11/29: Re: FPGA workstation - should I wait for Window Vista?
    113088: 06/12/06: Re: Virtex-4 ML403 16x2 LCD
    113628: 06/12/18: Re: FX12 ethernet resource usage
    113975: 06/12/31: Re: Help with ISE (multi-source in unit error)
    114187: 07/01/06: Re: email protection in the list
    114445: 07/01/16: Re: small, free simple state machine processor suggestions?
    114450: 07/01/16: Re: Setup time path on V4 SX w/ IDELAY
    114700: 07/01/23: Re: iMPACT dont shows erase write options with fpga
    114765: 07/01/24: Re: R: iMPACT dont shows erase write options with fpga
    114766: 07/01/24: Re: Xilinx ISE 8.2
    114768: 07/01/24: Re: Xilinx ISE 8.2
    114784: 07/01/24: Re: Xilinx ISE 8.2
    114846: 07/01/25: Re: Xilinx ISE 8.2
    115083: 07/01/30: Re: Differential pairs per Bank
    115164: 07/02/01: Re: Webpack 9.1 problems with Impact on parallel cable
    115313: 07/02/07: Re: Question about programming a FPGA using Modelsim Designer instead
    115322: 07/02/07: Re: Question about programming a FPGA using Modelsim Designer instead
    115464: 07/02/12: Re: NGDBuild error
    115465: 07/02/12: Re: Problem with floating inputs on LVDS ports
    115748: 07/02/19: Re: Do you like Virtex-5 ?
    115855: 07/02/22: Re: porting virtex2-pro into virtex4. Performance!!
    115875: 07/02/22: Re: porting virtex2-pro into virtex4. Performance!!
    115990: 07/02/27: Re: Spartan-3AN
    116174: 07/03/03: Re: Instance Name Being Removed?
    116420: 07/03/08: Re: Xilinx CoreGen fifo - ngdbuild error
    116531: 07/03/12: Re: Xilinx CoreGen fifo - ngdbuild error
    117116: 07/03/23: Re: Xilinx Platform cable USB and impact on linux without windrvr
    117276: 07/03/27: Re: Help with Xilinx Parallel Cable IV.
    117709: 07/04/08: Re: Xilinx ISE constanly asking to regenerate a core file.
    118131: 07/04/18: Re: ISE Smart Ident
    118373: 07/04/25: Re: Virtex-5 FX when ? (II)
    118718: 07/05/02: Re: Xilinx Spartan 3 XC3S200 and Xilinx Foundation Series 3.1i beginner
    118875: 07/05/05: Re: lwIP RAW mode support for V4 temac
    119199: 07/05/15: Re: Digital gain and offset correction
    119221: 07/05/15: Re: How low DDR2 Clock Frequency can be? To make it work on FPGA.
    119225: 07/05/15: Re: How low DDR2 Clock Frequency can be? To make it work on FPGA.
    119233: 07/05/15: Re: How low DDR2 Clock Frequency can be? To make it work on FPGA.
    119926: 07/05/29: Re: PacoBlaze 2.2
    120166: 07/06/02: Re: 180 differential inputs each 800Mbps using V5
    120237: 07/06/04: Re: Lattice XP2 finally announced
    120263: 07/06/04: Re: Microcontrollers have a better predictable time behaviour than
    120271: 07/06/04: Re: ngdbuild error : multiple drivers and driving non buffer primitives
    120272: 07/06/04: Re: TBUF and modular design flow on spartan
    120520: 07/06/08: Re: FPGA with ARM+CAN+USB+ethernet+ADC
    120545: 07/06/09: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
    120759: 07/06/15: Re: Xilinx FPGA Pinout spreadsheets
    121051: 07/06/24: Re: IBIS Model V5 GTP output
    121061: 07/06/24: Re: IBIS Model V5 GTP output
    121073: 07/06/25: Re: IBIS Model V5 GTP output
    121272: 07/06/29: Re: Xilinx ngdbuild question
    121625: 07/07/10: Re: DDR SDRAM simulation model, ML300, Infineon
    122023: 07/07/17: Re: Which embedded O/S for a 32-bit RISC microcontroller?
    122326: 07/07/25: Re: Virtex-5 and powerpc...its alive....
    122393: 07/07/26: Re: DCM with Xilinx Spartan 3E and Precision
    123370: 07/08/25: Re: DDR2 controller V4 vs V5 differences ?
    123421: 07/08/28: Re: tricking bitgen into creating rom-like behavior
    123458: 07/08/28: Re: Partial reconfiguration using ICAP
    123685: 07/09/01: Re: Partial reconfiguration using ICAP
    123706: 07/09/02: V5 Configuration via SPI
    123737: 07/09/03: Re: V5 Configuration via SPI
    123746: 07/09/03: Re: V5 Configuration via SPI
    124633: 07/09/28: Re: Programming the ARM7 used to download our Xilinx FPGA
    125251: 07/10/18: Re: FPGA pin swapping utility
    125338: 07/10/22: Re: Alter RBF Compression
    125339: 07/10/22: Re: ISE or EDK?
    125415: 07/10/25: Re: Changing refresh rate for DRAM while in operation?
    125848: 07/11/06: Re: not totally repulsive
    125889: 07/11/08: Re: P160 Communication Module 3
    125892: 07/11/08: Re: P160 Communication Module 3
    126670: 07/11/29: Drawing timing-diagrams for documentation
    126770: 07/12/01: Re: Drawing timing-diagrams for documentation
    126818: 07/12/03: Re: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same
    126998: 07/12/08: Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
    127325: 07/12/18: Re: sampling error between 2 clocks
    128391: 08/01/24: Re: How to choose an FPGA for High speed applications
    128460: 08/01/27: Virtex4: LVDS-Inputs in banks with VCCO!=2.5V (again)
    128502: 08/01/29: Re: Virtex4: LVDS-Inputs in banks with VCCO!=2.5V (again)
    129720: 08/03/03: Re: my Spartan-4 wishlist
    129801: 08/03/05: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
    129898: 08/03/08: Re: Datasheet on Micron's secure products
    130642: 08/03/29: Re: need help.....how do i download an image onto a virtex 4 fpga
    130714: 08/03/31: Using USB programming cables from Xilinx and Lattice on one Windows
    130734: 08/03/31: Re: Using USB programming cables from Xilinx and Lattice on one Windows
    130750: 08/03/31: Re: Using USB programming cables from Xilinx and Lattice on one Windows
    130884: 08/04/04: Re: ModelSim XE problems with a VHDL coregen in a Virtex 5
    131842: 08/05/03: Re: Using SRL16
    133479: 08/07/01: Re: Translate problem
    133916: 08/07/19: Re: Virtex-5, DDR2 SRAM, and ISERDES
    134923: 08/09/07: Re: Are Xilinx tools that bad, or am I missing something?
    135212: 08/09/20: Re: Altera and DDR3
    136129: 08/11/03: Re: requesting solution for error:HDLParsers:810
    136342: 08/11/12: Re: clock problem
    136344: 08/11/12: Re: clock problem
    136356: 08/11/12: Re: clock problem
    136617: 08/11/26: Re: IDELAYCTRL for Xilinx virtex 5
    136702: 08/12/02: Re: reading registers
    136824: 08/12/07: Re: Invalid devices when initialising scan chain with Nexys2
    137500: 09/01/21: Re: virtex5 / configuration logic
    137511: 09/01/21: Re: Translate error
    137513: 09/01/21: Re: Translate error
    137519: 09/01/21: Re: Translate error
    137624: 09/01/24: Re: how to define global clock in UCF of PR
    138662: 09/03/03: Re: Re-synthesizing with minor changes
    138669: 09/03/03: Re: Virtex6 Virtex4 FPGA compatibility
    139317: 09/03/26: Re: virtex-5 lvds termination issue?
    140187: 09/05/02: Re: ISE/EDK/SDK 11.1 licensing
    140188: 09/05/02: Re: ISE/EDK/SDK 11.1 licensing
    140208: 09/05/04: Re: ISE/EDK/SDK 11.1 licensing
    140210: 09/05/04: Re: ISE/EDK/SDK 11.1 licensing
    140270: 09/05/07: Re: Environmental variables to point at libraries with Modelsim?
    140608: 09/05/20: Re: Port assignment question
    141580: 09/06/28: Re: 6/6 infos
    142895: 09/09/06: Re: Virtex5 DDR2 ref design failed at JTAG programming with CRC error
    142958: 09/09/10: ieee.math_real-support in Synplify for Lattice
    142960: 09/09/10: Re: ieee.math_real-support in Synplify for Lattice
    142963: 09/09/10: Re: ieee.math_real-support in Synplify for Lattice
    143071: 09/09/18: Re: To Xilinx: Regarding the download manager
    144588: 09/12/17: Re: Actel Igloo Partial Reconfiguration
    144912: 10/01/14: Re: Virtex-5 with DDR3 running @ 50Mhz
    145284: 10/02/04: DONE_cycle:6 setting neccessary in bitgen
    145299: 10/02/05: Re: DONE_cycle:6 setting neccessary in bitgen
    145330: 10/02/05: Re: DONE_cycle:6 setting neccessary in bitgen
    145331: 10/02/05: Re: DONE_cycle:6 setting neccessary in bitgen
    145433: 10/02/09: Re: DONE_cycle:6 setting neccessary in bitgen
    145451: 10/02/10: Re: DONE_cycle:6 setting neccessary in bitgen
    145481: 10/02/11: Re: DONE_cycle:6 setting neccessary in bitgen
    146406: 10/03/16: Re: ISE speed determined by console output?
    147399: 10/04/26: Re: Virtex 4 ICAP partial reconfiguration
    147852: 10/05/27: Xilinx' partition flow in ISE12.1
    149575: 10/11/06: Re: PCI Parallel port detection in XILINX
    150602: 11/01/27: Re: Wow! No TestbenchWow!
    154668: 12/12/14: Re: Where to move for an embedded software engineer.
    154706: 12/12/21: Re: Xilinx FIFO usage
    155174: 13/05/22: Re: XILINX Artix-7 DDR2-RAM-Controller
    155196: 13/05/27: Re: XILINX Artix-7 DDR2-RAM-Controller
    155361: 13/06/24: Re: VHDL syntheses timestamp
    155545: 13/07/17: Re: Xilinx "Ultrascale" announcement leaves out low-cost devices
    155914: 13/10/16: Re: Xilinx tools for XC3020???
    155923: 13/10/16: Re: Xilinx tools for XC3020???
    156319: 14/03/04: Re: New Lattice FPGAs on 40nm ?
    156321: 14/03/05: Re: New Lattice FPGAs on 40nm ?
    156352: 14/03/16: Re: cloud design flow
    156396: 14/03/28: Re: [cross-post][long] svn workflow for fpga development
    157080: 14/09/24: Re: Some newbe questions.
    157186: 14/10/29: Re: XILINX PCIe read of slow device
Sean Garnett:
    6018: 97/04/05: Re: Pentium Pro Worth it for Altera Max Plus?
Sean Murphy:
    1047: 95/04/20: Design Automation Conference WWW Site at http://www.dac.com/dac.html
    1167: 95/05/10: Design Automation Conference WWW site is http://www.dac.com/dac.html
    1675: 95/08/14: E2W3 Hotlist at http://www.e2w3.com/ points to 250+ EE WWW sites
    1804: 95/09/05: ICCAD-95 Program and Forms Available at http://www.e2w3.com/iccad/
    1837: 95/09/07: VHDL International (VI) Home Page on-line at http://www.e2w3.com/
    2688: 96/01/24: IVC-96 Hotel/Conference Registration Deadlines Fast Approaching
Sean Williams:
    35359: 01/10/01: Re: Fastest way to become a Verilog samurai?
<seannstifler69@hotmail.com>:
    84142: 05/05/13: Re: Altera Excalibur EBI problem
    87364: 05/07/21: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    90005: 05/10/01: Re: I, Wish: I had an Spartan-3e NOW!
Search for knowledge:
    43535: 02/05/23: Re: timing violations in fpgas
    44808: 02/07/01: Converting Altera Block Ram to Xilinx Block Ram
Seb:
    35453: 01/10/05: Re: Xilinx: JTAG parallel connection problem
    35757: 01/10/16: pci-card with Virtex2?
    35794: 01/10/18: Re: pci-card with Virtex2?
    35798: 01/10/18: Re: pci-card with Virtex2?
    36485: 01/11/09: speed of HW JPEG implementations
    36761: 01/11/19: modelsim: free, evaluation or full !?
    37197: 01/12/03: Re: Modelsim
    38438: 02/01/14: Insight eval board: i/o problem
    39726: 02/02/17: Re: Handel-C, System-C, Formal verification ???
    39780: 02/02/19: Re: Virtex II prototype/development boards
    39781: 02/02/19: Re: Whether an FPGA & CPLD device has been spoiled.
    39782: 02/02/19: Re: Multipliers in Altera FPGAs
    39825: 02/02/20: Re: Virtex II multiplier pipeline
    39924: 02/02/22: init RAM in VirtexII
    40009: 02/02/24: Re: init RAM in VirtexII
seb:
    71456: 04/07/19: Re: Xilinx EDK PCI
    71664: 04/07/27: Re: Xilinx EDK PCI
Seb C:
    21260: 00/03/14: DCT using FPGA
    22710: 00/05/19: DCT and FPGA !!!!
    22793: 00/05/24: Implementation in FPGA
    22817: 00/05/25: Implementation using FPGA
    24133: 00/07/27: Implementation
    25298: 00/09/05: DCT implementation using FpgA
    25299: 00/09/05: DCT implementation using FPGA
    26509: 00/10/18: two complement multiplier
    28857: 01/01/26: mutiplier !!
    29498: 01/02/23: ERROR on Xilinx fundation
    29751: 01/03/07: ERROR in Xilinx softaware !
    32412: 01/06/26: FPGA manufacturers
Seb K:
    62576: 03/11/02: Xilinx Weback 6.1i - Java Exception
    62584: 03/11/02: Re: Xilinx Weback 6.1i - Java Exception
    62603: 03/11/03: Re: Xilinx Weback 6.1i - Java Exception
<seb30@my-deja.com>:
    24038: 00/07/24: Re: Routing Resources for Xilinx BlockRAM
    24039: 00/07/24: CLKDLLE using VirtexE device.
seb_tech_fr:
    89381: 05/09/13: XilinX MAC FIR
    89548: 05/09/19: re:XilinX MAC FIR
    89830: 05/09/27: re:chipscope pro
    89898: 05/09/29: re:FPGA : Decimation Filter
    90046: 05/10/03: re:FPGA : Decimation Filter
    91257: 05/11/02: clock detection
    91351: 05/11/03: Re: clock detection
    91594: 05/11/09: re:how to implement Fast Fourier Transform on virtex pro
    91942: 05/11/17: DCM corner issue
    91971: 05/11/18: Re: DCM corner issue
    92041: 05/11/21: Re: DCM corner issue
    92438: 05/11/29: re:DCM Wizard
Seba:
    59840: 03/08/29: Xilinx Foundation Series F2.1i + win2k
    59846: 03/08/29: Re: Xilinx Foundation Series F2.1i + win2k
    59853: 03/08/29: Re: Xilinx Foundation Series F2.1i + win2k
    60355: 03/09/11: implementation error
sebas:
    150017: 10/12/06: Interconnection of multiple cores
    150021: 10/12/06: Re: Interconnection of multiple cores
    150661: 11/02/01: PCI Express Transfer
    150671: 11/02/02: Re: PCI Express Transfer
    151211: 11/03/15: Regfile access
Sebastia A. Bota:
    15336: 99/03/19: Placement control in ALtera devices
sebastian:
    67682: 04/03/17: newbie question about fpga internals
    70245: 04/06/10: delayed clocks on timesim simulation?
    70283: 04/06/11: Xilinx: infering dual port ROM in VHDL
    73866: 04/09/30: Re: Enabling clock generation
    73174: 04/09/15: altera quartus II handbook is wrong??
    73365: 04/09/20: Re: altera quartus II handbook is wrong??
    73606: 04/09/25: Re: altera quartus II handbook is wrong??
Sebastian:
    34971: 01/09/17: how to simulate virtex components?
    34973: 01/09/17: Re: how to simulate virtex components?
    35423: 01/10/04: Xilinx: JTAG parallel connection problem
    35514: 01/10/09: microblaze?
    37488: 01/12/12: ROM prog problem Virtex2 eval board
    46178: 02/08/21: Strathnuey xc2v1000
    67804: 04/03/19: reading from a XSA-50
Sebastian Goller:
    121085: 07/06/25: Trouble using DCMs in EDK 8.2
    121118: 07/06/26: Re: Trouble using DCMs in EDK 8.2
    121440: 07/07/04: Re: Trouble using DCMs in EDK 8.2
    121441: 07/07/04: Rocket IO clocking
    122592: 07/08/01: Re: DDR Simulation Model
    122594: 07/08/01: Re: DDR Simulation Model
    122595: 07/08/01: Re: DDR Simulation Model
    122605: 07/08/01: Re: DDR Simulation Model
    122606: 07/08/01: Re: DDR Simulation Model
    123108: 07/08/16: Re: DDR Simulation Model
    123579: 07/08/30: Reconfiguration of a XUP Board
Sebastian Gruber:
    45141: 02/07/13: Re: FPGA CPU?
Sebastian H Ziesler:
    4290: 96/10/10: help: max+ edif input problems
Sebastian Lange:
    60765: 03/09/22: FPGA implementation in (V)HDL
Sebastian Schmidt:
    77910: 05/01/20: Problem with Signal Tap II Logic Analyzer in Altera Quartus II 4.1 and Microtronix Stratix development board
    78074: 05/01/24: Re: Problem with Signal Tap II Logic Analyzer in Altera Quartus II 4.1 and Microtronix Stratix development board
    89089: 05/09/05: False values in Quartus In-System Memory Editor
    89093: 05/09/05: Re: False values in Quartus In-System Memory Editor
    89124: 05/09/06: Re: False values in Quartus In-System Memory Editor
    89133: 05/09/06: Re: False values in Quartus In-System Memory Editor
Sebastian Schüppel:
    115064: 07/01/30: help with Design Compiler -> Quartus
    115253: 07/02/05: Re: help with Design Compiler -> Quartus
    115298: 07/02/06: Re: help with Design Compiler -> Quartus
Sebastian Urban:
    151293: 11/03/21: Re: Finding cheap PCI-E FPGA board for a student
Sebastian Weiser:
    82243: 05/04/09: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
    82388: 05/04/12: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
    82473: 05/04/13: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
    82967: 05/04/20: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
    82968: 05/04/20: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
    82969: 05/04/20: Re: Ambigous operator '&'
sebastian.schueppel@gmail.com:
    135881: 08/10/20: external differential clock inputs
    136324: 08/11/11: Re: external differential clock inputs
Sebastien:
    32951: 01/07/12: PCI arbiter core
Sebastien @ Sundance:
    140220: 09/05/04: Re: FPGA/DSP/Video Board
    140222: 09/05/04: Re: FPGA evaluation board for SD/SDHC Host controller
    140303: 09/05/08: Re: board with 2 gigabit ethernet connectors?
    140305: 09/05/08: Re: FPGAs and Cryptography
    140364: 09/05/11: Re: Getting started with FPGA
    140381: 09/05/12: Re: which low cost fpga for space?
    140383: 09/05/12: Re: DSP + FPGA reference design?
    140501: 09/05/15: Re: FPGA/DSP system design problem
    140534: 09/05/16: Re: Cheap Ethernet PHY boards?
    141221: 09/06/11: Re: IF board for fpga?
    141465: 09/06/25: Re: 720 Mhz IF Processing
Sebastien Bourdeauducq:
    118015: 07/04/16: Safety of bidirectional lines
    118064: 07/04/17: Re: Safety of bidirectional lines
    124912: 07/10/10: Cyclone II SSTL-2 on-chip resistors
    124953: 07/10/12: Re: Cyclone II SSTL-2 on-chip resistors
    124966: 07/10/13: Re: Quartus II 7.2 web edition - Linux or not?
    124979: 07/10/14: Re: Altera devices connecting to DDR memory.
    124984: 07/10/14: Re: Newbie,the simplest way to program an FPGA at home?
    127422: 07/12/23: DQS contention with ddr_sdr from Opencores
    127431: 07/12/24: Re: DQS contention with ddr_sdr from Opencores
    135837: 08/10/17: Forcing Xilinx tools to treat two clocks as unrelated
    135838: 08/10/17: Re: Linux on Microblaze
    135846: 08/10/17: Re: Forcing Xilinx tools to treat two clocks as unrelated
    135847: 08/10/17: Re: Forcing Xilinx tools to treat two clocks as unrelated
    135869: 08/10/19: Re: Forcing Xilinx tools to treat two clocks as unrelated
    136766: 08/12/04: Preventing PAR from routing signals in closed area groups
    136792: 08/12/05: Re: Preventing PAR from routing signals in closed area groups
    147686: 10/05/15: Spartan 6 schedule
    148068: 10/06/18: Asynchronous FIFO in Spartan6
    148231: 10/06/30: Re: Xilinx BULLSHITIX-8, when?
    148980: 10/09/17: Re: Question about OC PCI Cores
    150046: 10/12/07: Re: Getting libusb-driver to work with Xilinx dev board.
    150047: 10/12/07: Re: Lattice XO2 video
    150048: 10/12/07: Re: Linux on Microblaze
    150063: 10/12/09: Re: spacewire project on opencores.org
    150141: 10/12/17: Re: spacewire project on opencores.org
    150174: 10/12/24: Re: spacewire project on opencores.org
    151100: 11/03/06: Hidden SPI_ACCESS site in Spartan-6
    151104: 11/03/06: Re: IP Core Delivery Format Info
    151108: 11/03/07: Re: IP Core Delivery Format Info
    151110: 11/03/07: Re: IP Core Delivery Format Info
Sebastien Erard:
    13110: 98/11/16: Xilinx 4k programming
    13162: 98/11/18: Re: Xilinx 4k programming, the solution
Sebastien Favard:
    22643: 00/05/16: [search] - ISA PnP specs
    22644: 00/05/16: [Part II] - Pb FPGA Xilinx config process
    22807: 00/05/25: Re: [Part II] - Pb FPGA Xilinx config process
    22809: 00/05/25: Search Spartan for small quantity
    23376: 00/06/23: lGen - Synthesis Library [Help manufacturer]
Sebastien Favard (Gordh):
    22251: 00/05/03: Search simple design
    22283: 00/05/04: Init/ line - CRC error ???
    22286: 00/05/04: Re: Init/ line - CRC error ???
    22287: 00/05/04: Re: Init/ line - CRC error ???
    22289: 00/05/04: Re: Init/ line - CRC error ???
    22295: 00/05/04: [BitGen] - pb option UserClk
    22339: 00/05/05: Re: Init/ line - CRC error ???
    22341: 00/05/05: Re: [BitGen] - pb option UserClk
    22370: 00/05/06: Re: [BitGen] - pb option UserClk
    22371: 00/05/06: Re: [BitGen] - pb option UserClk
    22373: 00/05/06: Configuration process %-(
Sebastien Matel:
    148865: 10/09/05: MPMC without MCB on Spartan-6
    148867: 10/09/05: Re: MPMC without MCB on Spartan-6
Sebastien SALAS:
    2925: 96/03/01: SYNARIO tool for CPLD and FPGA ?
sebs:
    137582: 09/01/22: XPS PowerPC accessing DCR register
    137610: 09/01/23: Re: XPS PowerPC accessing DCR register
    138469: 09/02/24: Xilinx FIFO problem
    138474: 09/02/24: Re: Xilinx FIFO problem
SECRET:
    42515: 02/04/25: Does Vertex II PRO Really work?
    42516: 02/04/25: Re: ModelSim closes for unknown reason
<secureasm@gmail.com>:
    133954: 08/07/20: Re: Change clock domain for FIFO ...
    133955: 08/07/20: Re: Change clock domain for FIFO ...
    133957: 08/07/20: Re: Change clock domain for FIFO ...
    135244: 08/09/23: OFDM band switch ...
    136564: 08/11/22: Re: Generate sample rate ...
    136928: 08/12/14: FIFO with External Memory
    136940: 08/12/15: Re: FIFO with External Memory
    137024: 08/12/19: PCR Reastamping
    137354: 09/01/10: Enterpoint Darnaw1 EDK Board Wizard Betatest ...
    137555: 09/01/22: Re: ML505 - How to read/write SRAM?
    137611: 09/01/23: Re: ML505 - How to read/write SRAM?
    137663: 09/01/27: What software do you use for PCB with FPGA ?
    137681: 09/01/27: Re: What software do you use for PCB with FPGA ?
    137707: 09/01/27: Re: What software do you use for PCB with FPGA ?
    137708: 09/01/27: Re: What software do you use for PCB with FPGA ?
    137709: 09/01/28: Re: What software do you use for PCB with FPGA ?
    137710: 09/01/28: Re: What software do you use for PCB with FPGA ?
    137711: 09/01/28: Re: What software do you use for PCB with FPGA ?
    138320: 09/02/16: Re: Capture parallel data ...
    138321: 09/02/16: Re: Capture parallel data ...
    138435: 09/02/23: Re: Problem loading my bitstream into the parallel NOR flash using
    140650: 09/05/21: No integer interpolation ...
    140671: 09/05/21: Re: No integer interpolation ...
    140699: 09/05/22: Re: No integer interpolation ...
Sedat NISANCI:
    24732: 00/08/17: Instantiation of Virtex-E Block SelectRAMs
    24787: 00/08/18: Re: Instantiation of Virtex-E Block SelectRAMs
(see below):
    145319: 10/02/05: Re: using an FPGA to emulate a vintage computer
    145397: 10/02/08: Re: using an FPGA to emulate a vintage computer
    145398: 10/02/08: Re: using an FPGA to emulate a vintage computer
    145773: 10/02/23: Re: using an FPGA to emulate a vintage computer
    145782: 10/02/23: Re: using an FPGA to emulate a vintage computer
    145783: 10/02/23: Re: using an FPGA to emulate a vintage computer
    145784: 10/02/23: Re: using an FPGA to emulate a vintage computer
    145790: 10/02/23: Re: using an FPGA to emulate a vintage computer
    145807: 10/02/24: Re: using an FPGA to emulate a vintage computer
    145810: 10/02/25: Re: using an FPGA to emulate a vintage computer
    145841: 10/02/25: Re: using an FPGA to emulate a vintage computer
    145842: 10/02/25: Re: using an FPGA to emulate a vintage computer
    145849: 10/02/25: Re: using an FPGA to emulate a vintage computer
    145887: 10/02/26: Re: using an FPGA to emulate a vintage computer
SEEdwards:
    8503: 97/12/28: Re: Xilinx Copy Protection
Seeker:
    146530: 10/03/22: Confusion in address generation for MIG generated DDR2 interface
    146577: 10/03/23: Re: Confusion in address generation for MIG generated DDR2 interface
    146619: 10/03/23: Re: Confusion in address generation for MIG generated DDR2 interface
Seftie:
    13690: 98/12/18: Re: Xilinx Foundation vs. Altera Max Plus II
<segels@home.com>:
    25239: 00/09/01: Anybody Wanna Fuck My Virgin Whiteboy Ass?
Segis:
    30856: 01/05/01: Translator from Xchecker´s files to PROM´s files.
    31000: 01/05/09: Translator from Xchecker´s files to PROM´s files.
<sego@hrz.tu-chemnitz.de>:
    122564: 07/07/31: DDR Simulation Model
Seiran:
    49871: 02/11/23: Re: programmable oscillator for Virtex-E (XCV2000E)
    50105: 02/12/02: Re: Where can I find low cost 3rd party Xilinx j-tag programmer?
    50447: 02/12/11: Some boards for designers...
    50455: 02/12/11: Re: Some boards for designers...
    50505: 02/12/11: Re: Some boards for designers...
Seiya:
    22985: 00/06/07: Xilinx foundation Student Edition problem.
    23059: 00/06/12: Xilinx Project manager 1.5
sel:
    99223: 06/03/21: need help on 16 bit risc processor code
    99353: 06/03/23: help on RISC controller developed mikej
Selenium:
    55743: 03/05/18: Altera CPLDs
Selensky:
    135576: 08/10/08: Re: How to synthesize a delay of around 10 ns in FPGA?
    140209: 09/05/04: Picoblaze C Compiler
    144730: 09/12/29: Re: Xilinx and Multi-port memories
self:
    96558: 06/02/06: Re: porting linux on ml403
    115939: 07/02/26: ML501 Platform Flash Configuration
    115952: 07/02/26: Spartan-3AN
    116037: 07/02/28: Re: ML501 Platform Flash Configuration
    119074: 07/05/10: JTAG_SIM_VIRTEX5
    127200: 07/12/13: Re: ML505 board Compact Flash
    148394: 10/07/17: Cortex-M1 in Actel in strait VHDL?
    148400: 10/07/18: Re: Xilinx License BS
    148453: 10/07/24: Re: Cortex-M1 in Actel in strait VHDL?
    148461: 10/07/25: Re: Programming the Actel Smartfusion Eval Kit in Linux
    148658: 10/08/13: CoreTimer programming in Actel SoftConsole
    148659: 10/08/13: Re: How to use VIO and core inserter at the same time.
    152845: 11/10/26: CSV pinout from Actel
    153020: 11/11/15: Xilinx PCI Express - Am I starting too low?
selva kumar:
    98222: 06/03/07: Re: A few questions about FPGAs
    121120: 07/06/26: what is speed grade in virtes1
    123512: 07/08/29: intialize memory in fpga
    123513: 07/08/29: memory in spartan 3 fpga
selvance:
    156279: 14/02/04: RE: xilinx spi example under linux
Semih Hazar:
    50034: 02/11/29: Coolrunner II Voltage levels
Sen:
    100715: 06/04/16: Re: Someone need to port LwIP to ll_temac core/wrapper?
<sendthis@gmail.com>:
    125153: 07/10/16: Re: Quartus II Web Edition License - SOPC Builder generation?
    125254: 07/10/18: Error using SOPC builder - "Custom SDRAM" with 8-bits gives error with Signal "az_be_n"
    125347: 07/10/22: Changing refresh rate for DRAM while in operation?
    125455: 07/10/25: Re: Changing refresh rate for DRAM while in operation?
    125456: 07/10/25: Re: Changing refresh rate for DRAM while in operation?
    125457: 07/10/25: Re: Changing refresh rate for DRAM while in operation?
    125473: 07/10/26: Re: Changing refresh rate for DRAM while in operation?
    125503: 07/10/26: Re: Changing refresh rate for DRAM while in operation?
    125504: 07/10/26: Re: Changing refresh rate for DRAM while in operation?
    125599: 07/10/29: Re: Changing refresh rate for DRAM while in operation?
    125650: 07/10/31: Weird behavior : Altera DE2, C++, For loops, SRAM
senget:
    18114: 99/10/01: Evaluation/Development Board with SA-11XX Processor
    18134: 99/10/02: Re: Evaluation/Development Board with SA-11XX Processor
senjed:
    59492: 03/08/20: BlockRAM in VHDL
senthil:
    66900: 04/02/29: synthesis error - left bound of range doesn't evaluate to a constant
    72880: 04/09/07: how to get the data from ADC
    73010: 04/09/10: New to FpGa ; At configuring the device error cmes
    73037: 04/09/11: Re: New to FpGa ; At configuring the device error cmes
    73051: 04/09/12: Re: New to FpGa ; At configuring the device error cmes
    73089: 04/09/13: Re: New to FpGa ; At configuring the device error cmes
    73273: 04/09/17: How can i interface Spartan-3 with PC/104.
    73342: 04/09/19: Re: How can i interface Spartan-3 with PC/104.
    74473: 04/10/12: Hve to know the pin connection between cpld and fpga in my design
Seong-Woon Kim:
    351: 94/10/27: about ALTERA
Seonil:
    54936: 03/04/22: Re: Xilinx XPower
Seonil Choi:
    9809: 98/04/06: Synthesis tool for XC6200
    9863: 98/04/09: Schematic to Place&route tool for XC6200
    9883: 98/04/10: Re: Tools for Xillinx 6200 ?
    48316: 02/10/15: Re: Power Cnsumption Benchmark
sepher:
    109584: 06/09/29: Re: ModelSim path problem as fed by Xilinx ISE ver 8.2.03i
Sepideh Miller:
    134691: 08/08/26: Xilinx Virtex 4 Newbie
    134774: 08/08/29: Re: Xilinx Virtex 4 Newbie
serdar:
    59098: 03/08/08: I am new and I want to help
    68848: 04/04/20: documents
Serebr:
    108556: 06/09/12: Re: Spartan-3: 5V -> 2.5V level shifting
<serebr@my-deja.com>:
    27341: 00/11/18: Re: Altera 768 x 16 RAM?
    27342: 00/11/18: Re: Altera 768 x 16 RAM?
    28977: 01/02/01: Re: Spartan 2 DLL
    29157: 01/02/08: Re: Xilinx vs Altera
Serg_Y:
    58760: 03/07/31: reconfiguration VirtexE via JTAG (full or partial)
    58889: 03/08/03: Re: reconfiguration VirtexE via JTAG (full or partial)
    58890: 03/08/03: Re: reconfiguration VirtexE via JTAG (full or partial)
    58891: 03/08/03: Re: reconfiguration VirtexE via JTAG (full or partial)
    59335: 03/08/15: Re: Free VHDL Simulator
Sergei Leginov:
    13953: 99/01/05: Re: 22V10 Metastability - help please
    13952: 99/01/05: HELP!!!
Sergei Skorobogatov:
    56213: 03/05/31: Re: FPGA's an Flash
Sergei Storojev:
    32137: 01/06/15: Re: Force tristate enable register into IOB
    58475: 03/07/24: Re: XST fails to recognize FSM with registered outputs
Sergej:
    62859: 03/11/10: Re: FPGA Prototyping Board
sergey:
    111544: 06/11/05: post-synthesis simulation issues with ModelSim
    111545: 06/11/05: Re: post-synthesis simulation issues with ModelSim
    111571: 06/11/06: Re: post-synthesis simulation issues with ModelSim
Sergey A. Chernyshov:
    802: 95/03/03: Needed Price List for XC3000 and XC4000 series from USA
Sergey Baranov:
    67984: 04/03/24: about trouble with attributes in Exemplar Leonardo Spectrum 20001b
Sergey Vlasov:
    19712: 00/01/09: How to upgrade Foundation 1.4 to build Spartan-XL code?
Sergey Yemets:
    63420: 03/11/21: Undocumented units in Virtex (I assume in Spartan-II too)
Sergio:
    67484: 04/03/12: LVTTL Spartan-3 pin input current...
    67798: 04/03/19: Re: LVTTL Spartan-3 pin input current...
    78560: 05/02/03: PACE error
    78630: 05/02/04: help "bank does not exist"
    148138: 10/06/22: Re: Xilinx Timing Constraings
    148151: 10/06/23: Re: altshift_taps for Xilinx?
Sergio A. Cuenca Asensi:
    9959: 98/04/17: Macros for isp6000 from Lattice
    10307: 98/05/11: Neural Network implementation
    10309: 98/05/11: Re: speed and area
    10847: 98/06/25: Re: Simple XC95xx isp - howto?
    13725: 98/12/21: Problem with Xilinx Foundation
    13770: 98/12/23: Re: Problem with Xilinx Foundation
    14669: 99/02/10: Re: Xilinx de-compiler
    14752: 99/02/15: xnf de-compiler
    14878: 99/02/22: Problem with xilinx M1
    14887: 99/02/23: Re: Problem with xilinx M1
    14901: 99/02/24: How to avoid GRS inferred in Synopsys
    14945: 99/02/26: Re: Problem with xilinx M1
    14943: 99/02/26: Re: Problem with xilinx M1
    14967: 99/03/01: Re: newbie questions
    14968: 99/03/01: Re: Problem with xilinx M1
    14997: 99/03/02: Re: Problem with xilinx M1
    20421: 00/02/09: RECONFIGURABLE board for image processign
    20678: 00/02/17: Re: Suggested prototyping boards < $200
Sergio Masci:
    35455: 01/10/05: Re: ROM based FSMs
    35464: 01/10/06: Re: ROM based FSMs
    35465: 01/10/06: Re: ROM based FSMs
    35466: 01/10/06: Re: ROM based FSMs
    35468: 01/10/06: Re: ROM based FSMs
    35475: 01/10/07: Re: ROM based FSMs
    56221: 03/05/31: Software support for experimenting with CPU core design
sergio oyaga:
    25596: 00/09/14: Boundary scan
Sergio Tassinari:
    60545: 03/09/16: Digilent board
    60592: 03/09/17: Re: Digilent board
sergio.tota:
    79689: 05/02/23: Problems with a 4-MicroBlaze Multiprocessor Architecture
    79932: 05/02/26: re:Problems with a 4-MicroBlaze Multiprocessor Architecture
    80339: 05/03/04: re:Problems with a 4-MicroBlaze Multiprocessor Architecture
    80340: 05/03/04: How to profile performances of an OPB bus
<sergiy.lukin@gmail.com>:
    155075: 13/04/05: Re: RS232 VHDL-core
Serial # 19781010:
    37038: 01/11/29: Re: Help needed in choosing the right PC for VLSI EDA
Serkan:
    141342: 09/06/19: set dont touch in Xilinx Xst
    141374: 09/06/21: Re: set dont touch in Xilinx Xst
    141499: 09/06/25: pre-initialized dpram functional simulation
    142915: 09/09/08: IMPACT-Xilinx Platform Cable USB II
    142919: 09/09/08: Re: IMPACT-Xilinx Platform Cable USB II
    142922: 09/09/08: Re: IMPACT-Xilinx Platform Cable USB II
    144898: 10/01/13: black box module integration
    144903: 10/01/14: Re: black box module integration
    144908: 10/01/14: Re: black box module integration
    144909: 10/01/14: Re: black box module integration
    145795: 10/02/23: timing constraint syntax/fpga editor info
    145796: 10/02/24: Re: timing constraint syntax/fpga editor info
    145797: 10/02/24: Re: timing constraint syntax/fpga editor info
    150086: 10/12/10: xilinx spartan 6 deserialization
    150998: 11/02/28: xilinx spartan 6
    150999: 11/02/28: Re: serial loading of image pixels????????????
    151031: 11/03/01: Re: xilinx spartan 6
Serkan Dinmez:
    41398: 02/03/27: Re: Missing Timing by 30,000 ns
Serkan Oktem (Alumni):
    152534: 11/09/08: Altera Cyclone 4 deserialization, banks, pll
sesh67:
    61994: 03/10/15: Re: Running Quartus II on ReadHat Linux 9.0
    65757: 04/02/05: Re: ByteBlaster fails on Windows 98
    65992: 04/02/10: Re: [Altera/Quartus] Tools to regenerate block schematics from .vhd files
<sesh67@yahoo.com>:
    84966: 05/06/01: Re: Incremental Compilation in Quartus 4.2
Seth:
    48757: 02/10/23: Re: FPGA XC4005E
    48802: 02/10/24: Re: FPGA XC4005E
    49922: 02/11/25: Anybody know of vendors of PCI boards with FPGAs?
    57283: 03/06/26: I need a commercial PCI FPGA board, please help
    58601: 03/07/28: Altera Stratix PCI board and Linux... Anyone try this?
    58740: 03/07/31: Question: String matching with CAM?
Seth Goodman:
    11573: 98/08/24: Re: professional autorouters
Seth Kintigh:
    33543: 01/07/30: Re: XC4010 ! help please
    47776: 02/10/03: Tough question about parallelism, data dependencies, string matching
setup:
    91173: 05/10/31: Re: Spartan-3E starter kit
Seung:
    54533: 03/04/13: Re: Help installing Altera web tools
    54540: 03/04/13: Re: Help installing Altera web tools
    59274: 03/08/13: FPGA/DSP Expert - business partner for innovative FFT
    59294: 03/08/14: Re: FPGA/DSP Expert - business partner for innovative FFT
    59328: 03/08/14: Re: FPGA/DSP Expert - business partner for innovative FFT
    59975: 03/09/02: Re: FPGA/DSP Expert - business partner for innovative FFT
    60074: 03/09/04: Re: FPGA/DSP Expert - business partner for innovative FFT
    69808: 04/05/20: shift register by block RAM
SeungHeun, Lee:
    78611: 05/02/04: Finding DDR SDRAM SODIMM(200 pin) socket.
    78612: 05/02/04: Re: Altera FLEX 8000
Sewook Wee:
    79723: 05/02/23: Re: interrupt handler problem
    85916: 05/06/17: Xil_FatFS library example.
    86275: 05/06/23: Re: Xil_FatFS library example.
    86797: 05/07/06: Cheking out Linux Kernel Source
SeXy:
Seyang Yang,:
    255: 94/10/04: Need email address of Xilinx office
Seyior:
    70779: 04/06/28: XILINX GMAC Core 4.0 - HALF Duplex
seyior:
    54528: 03/04/12: Re: Confused at Xilinx V2P OCM usage
    58755: 03/07/31: Re: AREA_GROUP constraint for Xilinx FPGAs
    68478: 04/04/06: XIL DCM Reset on XAPP462
    68479: 04/04/06: Re: signal names in modelsim
    68505: 04/04/06: Re: XIL DCM Reset on XAPP462
    73235: 04/09/16: USER RESET in XILINX FPGA
    73263: 04/09/16: Re: USER RESET in XILINX FPGA
    76645: 04/12/07: DDR Error : partial row address regardless
    76804: 04/12/12: Re: DDR Error : partial row address regardless
    77560: 05/01/11: Large SKEW kill UART?
sf:
    45710: 02/08/01: clock timing
sfaragnaus@gmail.com:
    127261: 07/12/16: Mico32 linux kernel git repository
SFCFM Volunteer:
    12345: 98/10/09: Altera embedded FIFO RAM (using EABs)
    12352: 98/10/09: Re: Altera embedded FIFO RAM (using EABs)
    12576: 98/10/16: Synthesis with Altera RAM instances
    12624: 98/10/20: Re: Synthesis with Altera RAM instances
<sfeldman@my-deja.com>:
    26180: 00/10/06: Re: programm Xilinx FPGAs via JTAG
<sfielding@base2designs.com>:
    121542: 07/07/06: Re: Choosing the EPC16 or the EPCS64 for Stratix II
    121567: 07/07/08: Re: Choosing the EPC16 or the EPCS64 for Stratix II
    121604: 07/07/09: Re: Choosing the EPC16 or the EPCS64 for Stratix II
<sfiresto@interserv.com>:
    716: 95/02/16: SAVE TAX DOLLARS!!!
sfjg:
    40706: 02/03/13: EDA tools(from front to end)
sftchs:
    154285: 12/09/23: multi-source errors
SG:
    72178: 04/08/10: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
    72179: 04/08/10: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
    72563: 04/08/24: Any experience with Actel Flash-FPGAs ?
    72581: 04/08/25: Re: Any experience with Actel Flash-FPGAs ?
    72833: 04/09/03: Is Stratix-II ALM some kind of partitionable LUT
    74252: 04/10/06: IBM Paper with answer to FPGA vs ASIC comparisons
    74255: 04/10/06: Another article that compares Re: FPGA vs ASIC area
    74302: 04/10/07: Re: IBM Paper with answer to FPGA vs ASIC comparisons
    74350: 04/10/08: Here are some references for FPGA power consumption
    74351: 04/10/08: Cost Comparison of ASIC vs FPGA vs Structured ASIC
    76668: 04/12/08: Open source FPGA EDA Tools
    76672: 04/12/08: Re: Open source FPGA EDA Tools
sg:
    68471: 04/04/05: Need help with using inout (bi-dir) in VHDL for Xilinx FPGA
    78781: 05/02/07: SATA and RocketIO
    78857: 05/02/09: Re: SATA and RocketIO
<sgfallows@gmail.com>:
    103168: 06/05/26: Xilinx EDK library size issue
    104248: 06/06/21: Linking/mapping code sections with Xilinx EDK
    104291: 06/06/22: Re: Linking/mapping code sections with Xilinx EDK
    105222: 06/07/18: Burnig flash image with Xilinx EDK flashwriter tool
<sgopalakrishnan@attotech.com>:
    16045: 99/04/29: XILINX configuration through JTAG
SH.RYU KIM HOFMANS:
    1149: 95/05/05: how to implement delay in xilinx?
    1265: 95/05/24: altera vs xilinx ???
    1350: 95/06/05: Re: FPGAs for PCI Interfaces
    1324: 95/06/01: pci-video-accell.card with Altera ?
    1413: 95/06/19: altera mail adress ?
<sh.vipin@gmail.com>:
    156175: 14/01/08: addsubs on FPGA
sh3.m4y4:
    114894: 07/01/25: Porting MontaVista Linux on ML403
    114895: 07/01/25: Porting MontaVista Linux on ML403
    114923: 07/01/26: Re: Porting MontaVista Linux on ML403
Sha Ryu Kim Hofmans:
    2747: 96/02/01: help ! pci-interface
<shabana_rizvi@yahoo.com>:
    103222: 06/05/29: XC9572 Readback
shack19@gmail.com:
    128859: 08/02/07: Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?
<shack19@gmail.com>:
    128802: 08/02/06: Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?
shadabambat1@gmail.com:
    123426: 07/08/28: XHWIF interface for Virtex II devices
    123533: 07/08/29: Difference in the JTAG instructions between Virtex and Virtex II
shadfc:
    110746: 06/10/20: Code synthesizes to one FPGA but not to another?
    128113: 08/01/15: User inputs into Spartan-3E starter board?
    128115: 08/01/15: Re: User inputs into Spartan-3E starter board?
    128347: 08/01/22: Ballistic chronograph using a Spartan 3E starter board
    128350: 08/01/22: Re: Ballistic chronograph using a Spartan 3E starter board
    128354: 08/01/22: Re: Ballistic chronograph using a Spartan 3E starter board
shadows:
    12838: 98/11/01: Re: New Evolutionary Electronics Book
Shahab:
    71694: 04/07/27: vhdl code : altera vs xilinx
Shahab47:
    72106: 04/08/09: propagation delay
    72155: 04/08/10: Re: propagation delay
    72338: 04/08/15: Re: vhdl code : altera vs xilinx
shahram:
    135531: 08/10/06: Re: CRC calculation of Virtex 4 bitstream
    135736: 08/10/14: Re: Data2Mem with CRC for Virtex FPGAs
<shahzad2512@my-deja.com>:
    22430: 00/05/09: Good books on FEC
    22564: 00/05/12: Future of FPGAs?
    22565: 00/05/12: Do you know xilinx FPGAs well?
    22566: 00/05/12: Do you know xilinx FPGAs well?
    22775: 00/05/24: 8087 in FPGA?
    22782: 00/05/24: V23 and DTMF core?
    23128: 00/06/15: Reed Solomon in Xilinx FPGA?
    25650: 00/09/16: Adders in FPGA?
    25908: 00/09/26: FEC in FPGAs?
Shai:
    86585: 05/06/30: Coverting .mcs file to .bit file
    87037: 05/07/13: Problems programing FPGAs..
Shai Gilat:
    25756: 00/09/19: An Online Course for CPLD and FPGA design
<shailbadwaik@gmail.com>:
    101062: 06/04/24: How to get divider in CRC32 , while implementatinh it in VHDL?
<shailbains007@my-dejanews.com>:
    13096: 98/11/16: CPUs: Big Endianness vs Small Endianness
    13114: 98/11/16: Re: Big-Endian vs Little-Endian
    13427: 98/12/02: Minimum clock freq reqd
Shakes:
    148831: 10/08/31: dct verilog
    153470: 12/03/06: FPGA Area
Shakith:
    75340: 04/11/02: ise and edk integration
    74952: 04/10/22: VxWorks: Java
    75471: 04/11/06: FPGA Network Encryption Engine
    76459: 04/12/02: source less connector
    84525: 05/05/20: Memec Virtex-4 LX25 LC
    88897: 05/08/30: Virtex4 : Downloading error
<shakith.fernando@gmail.com>:
    125387: 07/10/24: MGT
    125413: 07/10/25: Re: MGT
    125468: 07/10/26: Re: MGT
    127323: 07/12/18: MGT Transciever
    127329: 07/12/18: Re: MGT Transciever
    130512: 08/03/26: Serial Transmission w/o 8B/10B encoding
    130608: 08/03/28: PCI Express Switch
    131067: 08/04/09: Re: Serial Transmission w/o 8B/10B encoding
    131079: 08/04/09: Re: Serial Transmission w/o 8B/10B encoding
    131735: 08/04/30: PCI Express Switch
Shalin Sheth:
    55786: 03/05/19: verilog question
    58175: 03/07/16: Re: How to edit encrypted NGC file produced using XILINX ISE 5
    69773: 04/05/19: Re: Initialize Blockram from file
    69948: 04/05/25: Re: What can I do if my chip can't meet timing?
    70341: 04/06/13: Re: Xilinx .bit to .svf...
    70466: 04/06/17: Re: Is there a verilog version of PicoBlaze?
    70629: 04/06/22: Re: JTAG - XC2S200E-PQ208
    71167: 04/07/10: Re: xilinx spartan 3 $99 board...help
    71257: 04/07/13: Re: MicroBlaze in Spartan3, external memory interface
    71258: 04/07/13: Re: KCPSM3+vhdl+verilog
    71948: 04/08/04: Re: adding real UART to xilinx ultracontroller design.
    72003: 04/08/05: Re: What is the price of the micro-blaze, ... ?
    72264: 04/08/12: Re: Dual Microblaze System
    72330: 04/08/15: Re: Hardware/Software Communication in Virtex-2p
    72706: 04/08/29: Re: Counter counting on both clock edges.
    72724: 04/08/30: Re: Counter counting on both clock edges.
    72788: 04/09/01: Re: Spartan 3 Starter Kit and ISE WebPACK
    73758: 04/09/29: Re: Microblaze : ilmb_Cntrl
    73760: 04/09/29: Re: Co-Processor for Microblaze or PowerPC Processor
    73134: 04/09/14: Re: Xilinx S3 Serial Port Code
    74418: 04/10/11: Re: Spartan 3 Kit
    75963: 04/11/20: Re: Xilinx EDK - Unable to initialize BRAM in Simulation
    75988: 04/11/21: Re: microblaze: execute program from external memory
    76641: 04/12/07: Re: "Hello World" project for an FPGA (on a Spartan3 board)
    77168: 04/12/27: Re: interfacing DDR memory to a spartan-3
    78399: 05/01/31: Re: Init of BRAMs with ISE flow.
    78714: 05/02/06: Re: problem with xilinx platform studio 6.2i
    79217: 05/02/15: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
    82519: 05/04/13: Re: Embedded MicroBlaze solution
    84190: 05/05/13: Re: Update Picoblaze Code in Bitstream
    94967: 06/01/19: Re: data2bram and coregen
shalini:
    72741: 04/08/31: modelsim and rocketio
    72768: 04/08/31: MGT
shalom:
    136619: 08/11/26: Re: Synplicity/Synplify and Systemverilog support?
Shalom Bresticker:
    73482: 04/09/22: Re: XST vhdl adder with carry out : broken carry chain
<shalza.mittal@gmail.com>:
    105120: 06/07/14: design partition across multiple FPGAs
shamanth:
    142163: 09/07/27: how to access brams in FPGA
    142382: 09/08/07: Bram access on FPGA
Shambhu J. Upadhyaya:
    298: 94/10/14: CFP (final) -- Great Lakes Symposium on VLSI
Shamile:
    60559: 03/09/16: Re: Virtex II Pro Linux
Shane:
    42876: 02/05/05: VirtexII : Reserving IO Pins as inputs
shane:
    95994: 06/01/27: HOW CAN I USE OPB EMC
    96008: 06/01/27: Re: HOW CAN I USE OPB EMC
Shane Mincer:
    11653: 98/08/28: Embedded Systems Engineer(s) jobs from all levels (60-130K)
Shane Mulligan:
    43010: 02/05/09: Have you designed a PCI/Ethernet Adapter using a HDL?
    43542: 02/05/23: Re: Have you designed a PCI/Ethernet Adapter using a HDL?
Shane Rowell:
    36899: 01/11/23: Re: Using XC18Vxx ISP config proms with Spartan XL
Shane Tow:
    13609: 98/12/11: XESS FPGA Board?
    14292: 99/01/23: Re: Foundation V3.1 VHDL synthesis
    31527: 01/05/29: Xilinx Installation and Java Errors on Pentium 4
    31569: 01/05/30: Re: Xilinx Installation and Java Errors on Pentium 4
    33715: 01/08/02: Re: Spartan II and asynchronous memory interface
<shane.tietjen@gmail.com>:
    90371: 05/10/11: PCIXCAP
Shanjit Singh:
    154900: 13/02/09: Idea Hunt, FPGA + ARM Cortex-M3
    155186: 13/05/23: FPGA Board : Indirect SPI not working
Shankar B:
    74560: 04/10/13: Re: direct calculation of the modulus ?
Shankar Hariharan EE:
    1067: 95/04/24: fpga design advantages
Shankar Hemmady:
    1706: 95/08/18: Re: Obscuring Code For Customers (was VHDL Obfuscators)
Shankar-President-Galaxy Resources,Inc.:
<shankar.vk@gmail.com>:
    81807: 05/04/01: problem in driving I2C bus through memory-mapped register
    82314: 05/04/10: Re: problem in driving I2C bus through memory-mapped register
    82324: 05/04/11: Re: problem in driving I2C bus through memory-mapped register
    82326: 05/04/11: Re: problem in driving I2C bus through memory-mapped register
    82425: 05/04/12: Re: problem in driving I2C bus through memory-mapped register
shannon:
    147942: 10/06/03: ISE Design Suite 11 will not evaluate 2's comp
    147943: 10/06/03: ISE Design Suite 11 will not evaluate 2's comp
    147944: 10/06/03: ISE Design Suite 11 will not evaluate 2's comp
Shannon:
    124274: 07/09/17: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124281: 07/09/17: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124344: 07/09/19: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124361: 07/09/19: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    124409: 07/09/20: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    147442: 10/04/27: Virtex 4 ICAP partial reconfiguration
Shanon Fernald:
    87299: 05/07/20: Optimizing out a divide on altera cyclone fpga
    87329: 05/07/21: Re: Optimizing out a divide on altera cyclone fpga
    87349: 05/07/21: Re: Optimizing out a divide on altera cyclone fpga
    87360: 05/07/21: Re: Optimizing out a divide on altera cyclone fpga
Shanon Fernald:
    62245: 03/10/22: I Need to Generate a NTSC Signal - Help!
Shant:
    115095: 07/01/30: UNKNOWN Processor Version (0) in XMD
    115225: 07/02/03: Re: UNKNOWN Processor Version (0) in XMD
    115306: 07/02/06: Multiple MicroBlaze based Multiprocessor system
    115344: 07/02/07: Multiple Micorblaze instantion problem solved, Facing debugging related problem.
    119630: 07/05/24: Error while generating Libraries and BSPs.
    120312: 07/06/05: Build error for multiprocessor sytem.
    120433: 07/06/07: Re: Build error for multiprocessor sytem.
    145961: 10/03/01: Need support for differential 1.2V IOStandard on Virtex-6
<shant.moses@gmail.com>:
    133537: 08/07/02: Re: Timing Analyzer report for IOBs -- 1GSPS DAC interface
Shantanu Tarafdar:
    5742: 97/03/11: Fatal exception under Win95 & XACT v6.0.1
shantesh:
    140836: 09/05/27: Signal encoding for a user-defined type
    147825: 10/05/25: BRAM with output register using ram_style attribute
Shantha:
    93152: 05/12/14: Error in MAP (Xlinx Project navigator)
Shaping:
    77193: 04/12/29: Primers for Handel-C; Handel-C efficiency
<SHAR@shams.eun.eg>:
    2401: 95/11/29: subscribe
Sharad Kumar:
    18312: 99/10/13: Xilinx FPGA Programmer
Sharad Malik:
    5091: 97/01/22: Int. Workshop on Logic Synthesis: CFP
    5299: 97/02/05: CFP: Int. Workshop on Logic Synthesis, 97 (Deadline Extended)
    5413: 97/02/14: CFP: Int. Wkshp. on Logic Synthesis (IWLS) 97: Deadline Extended
    6185: 97/04/23: IWLS 97: Advance Program and Registration
    6286: 97/05/08: IWLS Registration and Program
    6416: 97/05/22: Post Doctoral Fellowship Announcement
<sharad@bisquare.com>:
    17754: 99/08/31: Xilinx Spartan Configuration Prom
<sharadm@my-dejanews.com>:
    11022: 98/07/11: 16550 UART model info req.
Sharan:
    130607: 08/03/28: CAM implementation using Dual port ram
    139493: 09/04/01: 8b10b encoding + line encoding
    139495: 09/04/01: DCM vs PLL
    139526: 09/04/02: SSO
    139591: 09/04/06: IO Type
    139804: 09/04/14: reset & analog circuits
    140465: 09/05/14: sync vs async reset
    141618: 09/06/30: pinout
    152268: 11/07/29: die's in different packages
sharan:
    55046: 03/04/25: Re: hardware implementation of viterbi decoder
sharanbr:
    152272: 11/08/01: Re: die's in different packages
Sharanbr:
    139807: 09/04/14: Re: reset & analog circuits
    140507: 09/05/15: Re: sync vs async reset
    141621: 09/07/01: Re: pinout
    141740: 09/07/05: Re: pinout
sharat babu:
    39712: 02/02/16: Re: Trivial (?) problem with Xilinx - System Generator (tristate port pin)?
sharath raghava:
    10332: 98/05/12: Your Place in the SUN!!!
Sharath Raju:
    142642: 09/08/23: Operating the Spartan 3A FPGA at maximum speed (320 MHz)
    142645: 09/08/24: Re: Operating the Spartan 3A FPGA at maximum speed (320 MHz)
    143762: 09/10/24: Generating delay using logic gates
    143773: 09/10/24: Re: Generating delay using logic gates
    146360: 10/03/14: Nu Horizons Spartan 3A DSP board
    146375: 10/03/15: Re: Nu Horizons Spartan 3A DSP board
    147634: 10/05/10: Expecting sequential output, but RTL shows concurrent implementation.
    147651: 10/05/12: Re: Expecting sequential output, but RTL shows concurrent
    147656: 10/05/13: Xilinx Synthesis Tool generates clock signals from combinatorial
    147671: 10/05/13: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
    147703: 10/05/17: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
    147865: 10/05/28: Block RAM unusually long setup time ?
    147866: 10/05/28: Re: Block RAM unusually long setup time ?
    147876: 10/05/28: Re: Block RAM unusually long setup time ?
    147899: 10/06/01: Re: Block RAM unusually long setup time ?
    147935: 10/06/03: Re: Block RAM unusually long setup time ?
    148824: 10/08/29: FPGA DAC Interface
sharath20284:
    148210: 10/06/29: Require a solution - LVDS support +RJ45 connectors
Shardendu Pandey:
    17577: 99/08/11: Clock multiplexing
Shareef:
    110881: 06/10/25: Re: Xilinx MIG 1.6 doesn't launch
Shareef Jalloq:
    29964: 01/03/19: Altera Flex10K config
    29972: 01/03/19: Re: Altera Flex10K config
    45291: 02/07/18: Xillinx functional netlist simulation
    45306: 02/07/18: Re: AMBA specyfication
    46931: 02/09/12: Re: Modelsim-Altera gate level simulation
    49182: 02/11/04: Re: Leonardo 2002d and virtex2_multipliers
    49438: 02/11/12: How to disable IOB register packing?
    49484: 02/11/13: Re: How to disable IOB register packing?
    49497: 02/11/13: Re: How to disable IOB register packing?
    49500: 02/11/13: Re: How to disable IOB register packing?
    50717: 02/12/18: Re: Strange error on Xilinx Bitgen/Netcheck DRC check
<shareef.jalloq@lightblueoptics.com>:
    113411: 06/12/13: NOR Flash Controller
Sharif:
    19240: 99/12/08: Autologic II Xilinx Library
Sharif M. Shahrier:
    7633: 97/09/29: book
<sharifs@psu.edu>:
    28376: 01/01/10: Simulation File
Sharmila:
    147595: 10/05/05: Xilinx project failed timing constraints
Sharon Okoli:
    2164: 95/10/23: Re: Comp.Arch.FPGA Reflector V1 #354
<sharono@ukefl.demon.co.uk>:
    2148: 95/10/20: subscribe
Sharp:
    22568: 00/05/12: asic vs fpga
<sharp@cadence.com>:
    88021: 05/08/05: Re: Modeling two dimensional circuits
    88070: 05/08/08: Re: Modeling two dimensional circuits
    89608: 05/09/20: Re: Modelsim XE, what's the latest version?
    96616: 06/02/07: Re: Verilog 2's Complement Shifter
    97854: 06/02/28: Re: How do I make dual-port RAM from single port RAM?
    97857: 06/02/28: Re: How do I make dual-port RAM from single port RAM?
    97893: 06/03/01: Re: How do I make dual-port RAM from single port RAM?
    97894: 06/03/01: Re: How do I make dual-port RAM from single port RAM?
    97932: 06/03/01: Re: How do I make dual-port RAM from single port RAM?
    98106: 06/03/04: Re: How do I make dual-port RAM from single port RAM?
    98107: 06/03/04: Re: How do I make dual-port RAM from single port RAM?
    99556: 06/03/26: Re: Verilog RTL and Behavioral Testbench
    100036: 06/04/01: Re: Concatenate String in Verilog?
    109669: 06/10/02: Re: Looking for HDL code for sin( a ) and x ** y Functions
    111411: 06/11/02: Re: SystemVerilog interface: virtual and ref
    111703: 06/11/08: Re: How to simulate netlist with gated clock?
    111768: 06/11/09: Re: How to simulate netlist with gated clock?
    112019: 06/11/14: Re: Compile error by Cadence NC-Sim
    112020: 06/11/14: Re: How to control the running of NC-Sim and Xilinx ISE under Unix?
    112561: 06/11/24: Re: Verilog problem: default case to set signal xxxx
    122146: 07/07/20: Re: Xilinx XST 9.2i.01 - still incomplete support for always @*
    122402: 07/07/26: Re: Best CPU platform(s) for FPGA synthesis
    143464: 09/10/12: Re: ncelab: *W,SDFINF warning when back annotating SDF
    145656: 10/02/17: Re: How a state machine is constructed using latches?
    145657: 10/02/17: Re: How a state machine is constructed using latches?
    148598: 10/08/04: Re: Differences between Verilog versions
sharpa17@gmail.com:
    91755: 05/11/11: Add files to Xilinx ISE Project w/script
Shashi:
    68867: 04/04/20: Issues on Shift Register in a Clockless UART
Shashidhar A. Thakur:
    654: 95/01/29: looking for room mate, FPGA 95 - Monterey
Shaun:503-614-9627 VoiceMail:
    521: 94/12/19: PCI HW Engr: $55-65K; Portland, OR; Verilog/Synopsis; 100 M byte/sec.
Shaw:
    58401: 03/07/22: How to deal with the interfacing problem
shaw:
    17173: 99/07/07: Can i use verilog write testbench in altera?
Shawki Areibi:
    20146: 00/01/28: Xilinx vs Altera
    30678: 01/04/23: FPGA Prototyping Kits (Platforms)
    30701: 01/04/24: SPARTAN vs VERTEX
    31417: 01/05/22: ANN Implementations (Suitable FPGA Platform)
shawn:
    135609: 08/10/09: Rebuilding harware for Petalogix Linux
    136320: 08/11/11: Re: hi all
Shawn:
    38775: 02/01/24: Synthsis Tools for Xilinx
Shawn Aker:
    29730: 01/03/06: US-AZ-Senior ASIC/FPGA Designer - 3+ years experience
    29731: 01/03/06: US-AZ-Principal ASIC Designer - 10+ years experience
shawn chen:
    37622: 01/12/17: Download byteblast circuit with byteblasterMV mode(Maxplus II baseline) :
Shawn D'Alimonte:
    20016: 00/01/24: Easy to program PLD
    20050: 00/01/25: Re: Easy to program PLD
Shawn Joel Dube:
    4440: 96/10/29: Re: PCI-compliant VHDL module
    4448: 96/10/30: Configuring FPGA before PCI accesses config regs
    5355: 97/02/10: Using FPGA for PCI interface
Shawn Lee:
    4342: 96/10/18: (no subject)
    4343: 96/10/18: (no subject)
Shawn Malhotra:
    103693: 06/06/08: Re: Incrmental Compilation in Quartus 5.1
<shawnn@gmail.com>:
    96462: 06/02/03: fpga hardware "breakpoint"
    96551: 06/02/06: Re: fpga hardware "breakpoint"
    96931: 06/02/13: "does not fanout" warnings with inouts
    100519: 06/04/10: very slow pull-up with CPLD design
    101540: 06/05/02: bizzare unexplained random errors w/ Lattice 4256V CPLD
    101662: 06/05/04: Re: bizzare unexplained random errors w/ Lattice 4256V CPLD
    101663: 06/05/04: async. load line on shift register
    101666: 06/05/04: Re: async. load line on shift register
    102308: 06/05/14: getting good deals on small qty?
    102369: 06/05/15: Re: getting good deals on small qty?
    102393: 06/05/15: Re: getting good deals on small qty?
shay:
    46042: 02/08/15: rising_edge detector?
Shay Seng:
    76410: 04/12/01: Re: microblaze using SysGen
shaz.pecobian@gmail.com:
    111697: 06/11/08: floating point arithemetic on fpga
    111785: 06/11/09: Re: floating point arithemetic on fpga
<sheakeb517@gmail.com>:
    139603: 09/04/07: pll
Sheetal:
    118341: 07/04/24: FPGA and DAC for wave generation
<sheikh.m.farhan@gmail.com>:
    114253: 07/01/08: Accessing SATA hard disk for read/write IO through FPGA in an embedded environment
    114342: 07/01/12: 16-bit DDR memory controller in EDK
    114406: 07/01/15: Re: 16-bit DDR memory controller in EDK
    114480: 07/01/17: Re: 16-bit DDR memory controller in EDK
    114483: 07/01/17: PCI Card with FPGA
    114506: 07/01/17: Re: PCI Card with FPGA
    117232: 07/03/26: FPGA board with multiple Ethernet connections (Gigabit Ethernet)
    117298: 07/03/27: FPGA board with multiple Ethernet connections (Gigabit Ethernet)
    117994: 07/04/16: OPB To Wishbone Bridge
    118122: 07/04/17: Re: OPB To Wishbone Bridge
    118123: 07/04/17: Re: OPB To Wishbone Bridge
    118136: 07/04/18: Re: OPB To Wishbone Bridge
    118365: 07/04/24: Using PCI in EDK 8.21
    118366: 07/04/24: Using OPB PCI Bridge in EDK 8.2i
Sheila Carey:
    77582: 05/01/11: Call for technical papers
Sheila Sim:
    46588: 02/09/04: choice of fpga
<sheilasu@my-deja.com>:
    17017: 99/06/24: please advise on standard cell libraries
    17018: 99/06/24: please advise on standard cell libraries
    18603: 99/11/03: software microprocessor model needed
Shekhar Bapat:
    15708: 99/04/09: Re: ZBT to Virtex Interface at +100M
Shela:
    113037: 06/12/05: Virtex-4 ML403 16x2 LCD
    117467: 07/04/01: Question about initializing the ram value in test bench
Sheldon D.:
    55733: 03/05/17: Xilinx Project Navigator in ISE 5.2i
Shen Jiakan:
    18248: 99/10/10: FYI
Shenli:
    113154: 06/12/06: Re: "|->" implicate and sequence in SVA?
    113871: 06/12/26: SystemVerilog Sequence Coverage Problem?
    113952: 06/12/29: (Improve Verilog skill) Recommend CPU core with good document and coding?
    113960: 06/12/30: Re: (Improve Verilog skill) Recommend CPU core with good document and coding?
    114906: 07/01/25: Datapath design problem?
    114908: 07/01/25: unsigned and signed data in Verilog?
Sherdyn:
    19979: 00/01/21: Biphase mark decoder
    19983: 00/01/21: Re: Biphase mark decoder
    20013: 00/01/24: Re: Biphase mark decoder
    21020: 00/03/03: Re: xilinx synthesis tool
    21276: 00/03/15: Need help on VHDL testbench
    21360: 00/03/20: Weak Pull up
    21383: 00/03/21: Open Drain and tristate buffer
    21414: 00/03/22: Re: How to solder FPGA in BGA package ?
    23010: 00/06/09: Problem with state machine
    26051: 00/10/02: Programming Cypress Graphics Clock Generator
    26080: 00/10/03: Re: Programming Cypress Graphics Clock Generator
    27783: 00/12/08: IP for De-interleaver
shereen.ahmed:
    100111: 06/04/03: why the best code are the random codes ?
    100433: 06/04/08: decoding
    100475: 06/04/10: LDPC
    100489: 06/04/10: code
    139761: 09/04/12: Irregular LDPC
    141927: 09/07/17: log likelihood ratio
    144194: 09/11/19: Shannon limit
    144196: 09/11/19: LDPC FADING
sheri:
    142047: 09/07/23: Re: DONE pin does'nt go high in SPARTAN - 3AN
sherine:
    108911: 06/09/19: E1 to ethernet conversion
<sherstuk@amsd.com>:
    10153: 98/04/30: Q: XILINX Foundation
Shervin:
    149744: 10/11/22: FPGA-based implementation of Camera Link standard
    149748: 10/11/22: Re: FPGA-based implementation of Camera Link standard
sheva25:
    143241: 09/09/28: Connect two Spartan 3E
Shi Zhong:
    37409: 01/12/10: JBits programming questions.
Shibu:
    45802: 02/08/06: Help Needed -- XESS Board question!
shidan:
    110156: 06/10/11: Functional Languages in Hardware
Shigeyuki Takano:
    30360: 01/04/04: Information about configuraiton time
<shihhsin.hu@gmail.com>:
    89762: 05/09/25: question about creating RPM
shimon001:
    148956: 10/09/15: FPGA speech recongintion system
shin:
    32337: 01/06/23: Help me !! Please! (VHDL)
Shin Woo Kyun:
    10800: 98/06/20: [Question] Xilinx Foundation FPGA Express..
    10860: 98/06/26: I need PCI2.1 Verilog source for Xilinx.
Shing-Fat Fred Ma:
    39467: 02/02/11: Re: Looking for Free EDIF/Verilog netlist - Schematic Viewer
Shiraz Kaleel:
    65514: 04/01/31: ASMBL
    66896: 04/02/28: Re: difference btw H/W & S/W implementations !!
    66898: 04/02/28: Re: difference btw H/W & S/W implementations !!
<shitsu>:
    114631: 07/01/21: When do I need reset and clear?
SHIU PUN-HANG MR:
    4904: 96/12/26: Help: Divider
shiva kumar:
    39734: 02/02/18: FPGA: JTAG CABLE
shivashankara:
    133652: 08/07/08: How to download bitstream into Cyclone III starter board
shjin:
    149695: 10/11/17: What is the meaning of 'combinatorial path crossing multiple units'?
Shlomo Kut:
    24409: 00/08/07: Drivers for Fujitso MB87Y237 USB core
shogmic:
    93651: 05/12/27: Virtex-4 CCLK termination
    93704: 05/12/28: Re: Virtex-4 CCLK termination
shoonya:
    148057: 10/06/17: Programming the Actel Smartfusion Eval Kit in Linux
    148058: 10/06/17: Re: Trouble with Altium Openbus document based UART example using TSK3000A
    148065: 10/06/18: Re: Programming the Actel Smartfusion Eval Kit in Linux
    148067: 10/06/18: Re: Programming the Actel Smartfusion Eval Kit in Linux
    148086: 10/06/20: Re: Anyone interested in customizable EDA software for FPGA?
    148113: 10/06/22: Re: Programming the Actel Smartfusion Eval Kit in Linux
Shoran:
    23440: 00/06/24: How to speed it up?
    23441: 00/06/25: How to speed it up?
<shoran@my-deja.com>:
    24381: 00/08/06: some basic rules on FPGA design
shorty:
    89722: 05/09/23: Power Management for Xilinx and Altera FPGAs
    90636: 05/10/18: re:ADC implementation on fpga? Information and procudures wante
showbiz:
    40694: 02/03/12: Re: Mutual Clock Synchronization
<shparekh@yahoo.com>:
    39455: 02/02/10: Xilinx XC2V6000 - cannot get anything out of jtag port
    43263: 02/05/17: virtex 2 block rams
    43286: 02/05/17: Re: virtex 2 block rams
    43300: 02/05/18: Re: virtex 2 block rams
Shreyas Kulkarni:
    74455: 04/10/12: newbie question
    74505: 04/10/13: Re: newbie question
    76956: 04/12/16: PCI doubt
    76981: 04/12/17: Re: PCI doubt
    76993: 04/12/18: PCB construction for PCI
    77009: 04/12/19: Re: PCI doubt
    77121: 04/12/23: Re: PCI doubt
    77132: 04/12/24: Re: PCI doubt
    77157: 04/12/26: vvp problem
    77410: 05/01/06: Queries regarding PCI with Spartan3
    77591: 05/01/11: Re: Queries regarding PCI with Spartan3
    77668: 05/01/13: Doubts in XCF01S Programming.txt
    78039: 05/01/23: Re: Queries regarding PCI with Spartan3
    83110: 05/04/23: motherboard w/o 3.3V PCI fingers
    83732: 05/05/05: Re: Xilinx Prom programming
Shridhar Patil:
    53772: 03/03/21: Altera FLEX10K100E voltage?
<shridhar@mistralsoftware.com>:
    86208: 05/06/22: DC Offset removal in FPGA
shrinivas gotur:
    156010: 13/11/08: built in adc in fpga????
    156022: 13/11/10: Re: built in adc in fpga????
shruti:
    142605: 09/08/20: FPGA to ASIC conversion
<shrutisumit@gmail.com>:
    106515: 06/08/14: Crystal input for FPGA
    106527: 06/08/14: Re: Crystal input for FPGA
    106530: 06/08/14: Re: Crystal input for FPGA
    106563: 06/08/15: Re: Crystal input for FPGA
ShtlChen:
    17674: 99/08/23: Help: Passing constriants from SYNOPSYS FPGA compiler to XILINX M1
shuaibah@gmail.com:
    99347: 06/03/23: Re: How to get eps file from XST RTL viewer for LATEX
shubhendu:
    153852: 12/06/06: MPMC does not finish initialization in simulation
shujah:
    46261: 02/08/23: optimizied decimation filter design in VHDL
<shunsl@gmail.com>:
    126762: 07/12/01: Configuration via JTAG using an Embedded Controller
<shuo.huang@fibre.com>:
    86885: 05/07/07: Possible bug in Vertex-4 Rocket-IO?
    86901: 05/07/08: Re: Possible bug in Vertex-4 Rocket-IO?
    86926: 05/07/09: Re: Possible bug in Vertex-4 Rocket-IO?
    86931: 05/07/09: Re: Possible bug in Vertex-4 Rocket-IO?
    86932: 05/07/09: Re: Possible bug in Vertex-4 Rocket-IO?
    86944: 05/07/10: Re: Possible bug in Vertex-4 Rocket-IO?
<shuss3@yahoo.com>:
    82816: 05/04/18: Declining a job offer
Shyam:
    97112: 06/02/16: User masks in HardCopy and HardCopy II
    97132: 06/02/16: Re: User masks in HardCopy and HardCopy II
    97133: 06/02/16: Re: VHDL simulation
    98607: 06/03/13: Re: FPGA Design Implementation
    99464: 06/03/24: Multithreaded NIOS II or other embedded cores
    99627: 06/03/27: Re: OpenSPARC released
    99639: 06/03/27: Re: OpenSPARC released
    99654: 06/03/27: Re: OpenSPARC released
    99736: 06/03/28: Re: OpenSPARC released
    99808: 06/03/29: Re: Multithreaded NIOS II or other embedded cores
shyam:
    151403: 11/04/02: Re: MIPI CSI-2 camera interface to parallel
    151410: 11/04/04: Re: MIPI CSI-2 camera interface to parallel
    151415: 11/04/05: Re: MIPI CSI-2 camera interface to parallel
    151456: 11/04/11: Re: Reference book on Pci-express (Hardware and software point of view)
    151473: 11/04/12: Re: Source of Dynamic Power Consumption in FPGAs
    151554: 11/04/19: Re: How to add signals to wave which is a child of the module being tested?
    151585: 11/04/22: Re: Xilinx ML605 Demo Qusstion
    151595: 11/04/23: Re: Xilinx ML605 Demo Qusstion
    151596: 11/04/23: Re: XST - timing constraints of the combinatorial logic
    151845: 11/05/24: Fall Times and Pullup
    151854: 11/05/25: Re: Fall Times and Pullup
    151855: 11/05/25: Re: Fall Times and Pullup
    151876: 11/05/27: Re: Fall Times and Pullup
    151880: 11/05/28: Re: Fall Times and Pullup
    151882: 11/05/30: Re: Instantiation of an EDF netlist within a Verilog top RTL
    152000: 11/06/21: Re: Sporadic simulation result with modelsim
    152440: 11/08/23: Re: MAXDELAY constraint
Shyam Sundar:
    131528: 08/04/24: ACTEL FPGA static timing analysis
shyweij:
    55014: 03/04/24: need help converting Verilog to VHDL
Si:
    63010: 03/11/12: System generator and Microblaze
<si007us@yahoo.com>:
    100204: 06/04/05: XAPP264 OPB slave peripherals using Syustem Generator - help
sichstre:
    75389: 04/11/04: Problem including header files in a C/C++ project using Altera's Nios II IDE
Sid:
    101676: 06/05/04: 87C52 & 87C51 core
    101756: 06/05/05: Re: 87C52 & 87C51 core
sid:
    134412: 08/08/09: eliminating individual array registers?
Sid S. Takkella:
    3843: 96/08/08: pinout of simms
Siddharth Rele:
    69420: 04/05/10: Re: Floating Point With Xilinx EDK (PPC)?
Sideway:
    109396: 06/09/26: Re: QuartusII: how to find out all the instances of a VHDL module in a design?
Sidharta:
    10275: 98/05/08: speed and area
Sidney Cadot:
    72415: 04/08/18: Announcing JOLT - Yet Another Xilinx Programming Tool
    72436: 04/08/19: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
    72437: 04/08/19: Re: Free Flash PROM programming tool for GNU/Liunx
    72438: 04/08/19: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
    72442: 04/08/19: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
    72445: 04/08/19: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
    73479: 04/09/22: Non-global location constraints in Xilinx/XST using VHDL
    75230: 04/10/30: XST: suppressing incorrect optimizations in VHDL code
    75255: 04/10/31: Re: XST: suppressing incorrect optimizations in VHDL code
    75279: 04/11/01: Re: XST: suppressing incorrect optimizations in VHDL code
    75280: 04/11/01: Re: XST: suppressing incorrect optimizations in VHDL code
    75290: 04/11/01: Re: XST: suppressing incorrect optimizations in VHDL code
    75293: 04/11/01: Re: XST: suppressing incorrect optimizations in VHDL code
    86665: 05/07/03: Xilinx: XST synchronous FIFO using BRAMs
<sidney@jigsaw.nl>:
    86668: 05/07/03: Re: Xilinx: XST synchronous FIFO using BRAMs
    86669: 05/07/03: Re: Xilinx: XST synchronous FIFO using BRAMs
    86671: 05/07/03: Re: Xilinx: XST synchronous FIFO using BRAMs
    86695: 05/07/04: Re: Xilinx: XST synchronous FIFO using BRAMs
    86696: 05/07/04: Re: Xilinx: XST synchronous FIFO using BRAMs
    86697: 05/07/04: Re: Xilinx: XST synchronous FIFO using BRAMs
    86698: 05/07/04: Re: Xilinx: XST synchronous FIFO using BRAMs
    86711: 05/07/05: Re: Xilinx: XST synchronous FIFO using BRAMs
sidsarao83@gmail.com:
    137392: 09/01/13: Re: Digilent Nexys 2 Issue
siedon:
    84789: 05/05/27: Q.Timing Simulation using ModelSim for a Xilinx Spartan 2E
SierraTech (NOSPAM):
    44034: 02/06/10: ALTERA EPC16 Configuration in MAX+PLUS II V10.1
<sierratech@my-deja.com>:
    23381: 00/06/23: Looking for old Altera Application Brief Designs ab 84?
Sietse Achterop:
    70699: 04/06/23: Re: Xilinx Parallel Cable IV vs. Linux
    72224: 04/08/11: Re: Xilinx ParallelCable IV vs. Linux
    87880: 05/08/03: Re: Xilinx 7.1, Kernel 2.6 and modules for install_driver_installscript
    104447: 06/06/27: Re: Once synthesized RAMs are vanishing in WebPACK 8.1i03
    104451: 06/06/27: Re: Once synthesized RAMs are vanishing in WebPACK 8.1i03
    104545: 06/06/29: Re: Once synthesized RAMs are vanishing in WebPACK 8.1i03
    111605: 06/11/06: Once synthesized BRAMs are still vanishing in WebPACK version 8.1
Sietze Helfferich:
    118931: 07/05/07: Re: Ubuntu and Webpack?
Sight:
signaltap:
    156899: 14/07/24: Know any good public FPGA projects to contribute to?
SIGTEK:
    16998: 99/06/22: QPSK Constellation Permutations Article in SIGTEK SOftware Radio
    17665: 99/08/21: Re: fpga board : make it or buy it?
Sigurd Urdahl:
    18068: 99/09/27: Re: Evolvable Hardware
    20023: 00/01/24: Re: Xilinx programming from a Linux PC
    21927: 00/04/07: Re: EHW
    24425: 00/08/08: Re: Circuit Drawing
    24532: 00/08/12: Re: Yes but I want graphics.
<sijo2000@googlemail.com>:
    132417: 08/05/26: Re: Downloading external data file to FPGA
Silicon Group:
    900: 95/03/24: Xilinx, FPGA and Cadence
<siliconbluetechnology@yahoo.com>:
    123595: 07/08/30: An FPGA startup is seeking testcase from potential customers
    123651: 07/08/31: Re: An FPGA startup is seeking testcase from potential customers
SiliconLinx:
    29120: 01/02/06: Re: Digital/Hardware Designer with Ericsson
siliconvenky:
    94333: 06/01/09: want to know abt companies giving internship for 6 months
Silvano Bettinzana:
    54754: 03/04/17: SpartanIII Partial Reconfiguration
    63422: 03/11/21: Virtex2Pro Internal Config. Access Port
    63871: 03/12/06: Mixing simulation of behavioral and synthesized code
Silver:
    119559: 07/05/22: JTAG FPGA Debugging
    119583: 07/05/23: Re: JTAG FPGA Debugging
    119866: 07/05/28: JTAG fundamentals question
    119932: 07/05/29: Re: JTAG fundamentals question
<silver.glimmer@gmail.com>:
    132980: 08/06/12: Re: where is the IP address assigned to the fpga in Trimode Ethernet
SilverByte:
    32222: 01/06/20: Phase Locked loop implementation on FPGA
Silvio Lauckner:
    46859: 02/09/10: Re: minimalist FPGA system
    48773: 02/10/24: Re: Altera FPGA and EPLD Download ByteBlaster
silvio.baccari:
    150879: 11/02/19: Mathematical definition of an FPGA
    150881: 11/02/19: Re: Mathematical definition of an FPGA
    150884: 11/02/19: Re: Mathematical definition of an FPGA
    150895: 11/02/20: Re: Mathematical definition of an FPGA
    150896: 11/02/20: Re: Mathematical definition of an FPGA
    150897: 11/02/20: Re: Mathematical definition of an FPGA
    150924: 11/02/22: Re: Mathematical definition of an FPGA
    150986: 11/02/27: Re: Mathematical definition of an FPGA
Silviu Chiricescu:
    6137: 97/04/15: benchmarks
Sima:
    89121: 05/09/06: Spartan 3E and Spartan 3 with GTL
simax:
    136056: 08/10/29: MPMC and DDR2 Simulation
    136066: 08/10/29: Re: MPMC and DDR2 Simulation
    136068: 08/10/29: Re: MPMC and DDR2 Simulation
    136812: 08/12/06: Xiic with low lvl interrupts
Simeon Furrer:
    17551: 99/08/10: Re: XILINX Implementation Problem
Simin:
    78043: 05/01/23: where can I find description for Synopsys library (such as and_or.ib, class.lib etc)
Simmler Harald:
    22962: 00/06/06: Re: Help with Coregen
    23753: 00/07/07: Re: HOW DO YOU MANUALLY CONFIGURE AND READ CLB's ON A RUNNING FPGA???
    23969: 00/07/19: Re: FPGA Conferences
    23970: 00/07/19: Re: FPGA Conferences
    36821: 01/11/21: Re: Elliptic Curves
simon:
    65399: 04/01/27: building macros for Virtex-II with FPGA editor...
    65414: 04/01/28: Re: building macros for Virtex-II with FPGA editor...
    65430: 04/01/29: jBits RouteClock
    66833: 04/02/27: Re: Inquiry on configuration file analysis
    66966: 04/03/02: Re: frame length, frame addressing ?
Simon:
    4086: 96/09/09: Re: DO I REALLY NEED A XCHECKER CABLE?
    4164: 96/09/20: Re: Inaccrate Xilinx simulations ???
    4484: 96/11/04: Re: Multipliers on Xilinx FPGAs
    4807: 96/12/17: Re: Anyone tried a FFT in a FPGA?
    4808: 96/12/17: Re: ASICs Vs. FPGA in Safety Critical Apps.
    4809: 96/12/17: Re: Fpga, Epld, cpld....
    13386: 98/11/30: Re: Will XILINX survive?
    14747: 99/02/14: Re: EEProm erasing?
    14884: 99/02/23: Re: Xilinx/VHDL query - two clocks in one CLB
    20962: 00/03/01: Re: AMS board simple questions
    20972: 00/03/01: Re: AMS board simple questions
    22761: 00/05/23: Re: Xilinx tools
    22780: 00/05/24: Re: Xilinx Logic Cell counts and carry chains
    23202: 00/06/17: Re: Two questions
    23317: 00/06/22: Re: Problem copying text from the Spartan II data sheet
    23572: 00/07/01: Re: Viewlogic schematic from Synplify edif output?
    23599: 00/07/02: Re: Viewlogic schematic from Synplify edif output?
    23600: 00/07/02: Re: Remedies after the Fathers' Day Massacre
    23757: 00/07/07: Re: Remedies after the Fathers' Day Massacre
    24149: 00/07/27: Re: Spartan-II power consumption
    25063: 00/08/25: Re: largest fpga in the industry
    25922: 00/09/26: Re: Global clock buffers and secondary clock buffers.
    25930: 00/09/26: Re: Global clock buffers and secondary clock buffers.
    29663: 01/03/04: Re: webpack ISE synthesis fails with exit code: 0002
    29797: 01/03/10: Re: Spartan-II Evaluation Board
    29827: 01/03/12: Re: Spartan-II Evaluation Board
    31684: 01/06/02: Re: Exact URL for ordering Webpack ISE CDROM?
    47263: 02/09/21: Re: Xilinx ISE5.1 and Windows NT
    47270: 02/09/22: Webpack and Wine (was: What software package)
    48957: 02/10/28: assigning TIG to a net in VHDL source (Xilinx)
    48968: 02/10/28: Re: assigning TIG to a net in VHDL source (Xilinx)
    48976: 02/10/28: Re: assigning TIG to a net in VHDL source (Xilinx)
    54180: 03/04/04: Re: Cyclone power up problem - Summery
    54218: 03/04/05: Re: Cyclone power up problem - 'Engineerus Emptor'
    54219: 03/04/05: Re: Spartan vs. Cyclone for arithmetic functions
    54224: 03/04/05: Re: Xilinx announces 90nm sampling today!
    54369: 03/04/09: Re: precision RTL/Synplify/LeonardoSpectrum/Quartus
    54794: 03/04/18: Cyclone Eratta
    54820: 03/04/19: Re: Cyclone power up problem - Summery
    55124: 03/04/28: Re: 4 bit Multiplier and Divider
    55125: 03/04/28: Re: Low pin count SOC
    55158: 03/04/29: Re: Low pin count SOC
    55192: 03/04/30: Re: Low pin count SOC
    55906: 03/05/23: Re: FPGA design: firmware or hardware?
    55940: 03/05/24: Re: FPGA design: firmware or hardware?
    71421: 04/07/18: Re: Xilinx 6.2i ISE WebPACK running under wine?
    71424: 04/07/18: Memory width on Spartan-3 boards
    71425: 04/07/18: Re: Xilinx 6.2i ISE WebPACK running under wine?
    71428: 04/07/18: Re: Memory width on Spartan-3 boards
    71438: 04/07/18: Re: Memory width on Spartan-3 boards
    71442: 04/07/18: Re: Memory width on Spartan-3 boards
    71443: 04/07/18: Re: Memory width on Spartan-3 boards
    71445: 04/07/18: Re: Memory width on Spartan-3 boards
    71446: 04/07/18: Re: Xilinx 6.2i ISE WebPACK running under wine?
    71489: 04/07/20: Re: Memory width on Spartan-3 boards
    71518: 04/07/20: Re: Xilinx 6.2i ISE WebPACK running under wine?
    71547: 04/07/21: Re: Cheap FPGA's
    71555: 04/07/21: Re: Memory width on Spartan-3 boards
    71777: 04/07/30: Foundation evaluation on linux
    71832: 04/08/01: Re: Foundation evaluation on linux
    71843: 04/08/02: Re: DDR or SDR ? Memory controller in FPGA
    72506: 04/08/21: XST synthesis
    72507: 04/08/21: Re: XST synthesis
    72509: 04/08/21: Floorplanning funnies
    72622: 04/08/26: Re: 6.1 vs. 6.2
    72665: 04/08/27: Re: 6.1 vs. 6.2
    72696: 04/08/29: Re: 6.1 vs. 6.2
    72697: 04/08/29: Floorplanner RPM question
    72717: 04/08/30: Re: Floorplanner RPM question
    72732: 04/08/30: Re: FPGA Floating Point Multiplier Design
    72785: 04/09/01: Re: Floorplanner RPM question
    72842: 04/09/05: more than one clock
    72846: 04/09/05: Re: more than one clock
    72893: 04/09/07: Installing BaseX
    72992: 04/09/09: Placement vs Map in 6.2i, sp3
    72995: 04/09/09: Re: Placement vs Map in 6.2i, sp3
    73003: 04/09/10: Re: Placement vs Map in 6.2i, sp3
    73025: 04/09/10: Re: Xilinx ISE vs. SuSE Linux 9.x
    73472: 04/09/22: Re: ISE 6.3 Suse 9.1 installation problem
    73571: 04/09/24: Re: Webpack 6.3 and Spartan3-1000/1500?
    80330: 05/03/03: Re: Xilinx ISE7.1
    80462: 05/03/06: adding SDRAM to the S3 starter kit
    80473: 05/03/06: Re: adding SDRAM to the S3 starter kit
    80535: 05/03/07: Version mismatch ?
    80758: 05/03/10: Xilinx eagle package (PQ208)
    81343: 05/03/21: Xilinx EDK on Linux
    82175: 05/04/07: Re: Stupid question
    82668: 05/04/15: Re: Soft CPU vs Hard CPU's
    82670: 05/04/15: Re: Hobby or job? (FPGA User's groups anyone?)
    82688: 05/04/16: Re: salary ballpark please guys
    82689: 05/04/16: Re: Hobby or job? (FPGA User's groups anyone?)
    82705: 05/04/16: Re: salary ballpark please guys
    82728: 05/04/16: Re: salary ballpark please guys
    83142: 05/04/24: Re: New FPGA Development Board
    83486: 05/04/30: current price for (small quantity) XC4VFX12/FF668
    83505: 05/05/01: Re: current price for (small quantity) XC4VFX12/FF668
    83506: 05/05/01: Re: current price for (small quantity) XC4VFX12/FF668
    84361: 05/05/17: Re: FPGA design under Mac OS X ?
    84508: 05/05/19: Re: FPGA design under Mac OS X ?
    85231: 05/06/06: Upgrading the EDK from 6.3
    85327: 05/06/07: Re: Upgrading the EDK from 6.3
    88716: 05/08/25: Re: FPGA Development Board Wish List
    92622: 05/12/02: Synthesize: Error
    92698: 05/12/05: Re: Synthesize: Error
    108044: 06/09/04: Re: Spartan 3 and 5V input
    108710: 06/09/15: USB programming cables
    108817: 06/09/17: Re: USB programming cables
    110697: 06/10/19: Re: a clueless bloke tells Xilinx to get a move on
    123483: 07/08/28: VGA controller in the EDK ?
    123487: 07/08/29: Re: VGA controller in the EDK ?
    123491: 07/08/29: Re: VGA controller in the EDK ?
    123632: 07/08/31: Memory bandwidth of the 3A kit
    123638: 07/08/31: Re: Memory bandwidth of the 3A kit
    124815: 07/10/05: Re: JPEG-LS hardware implementation
    130501: 08/03/25: Re: Chipscope analyzer GUI problem in Linux
    130931: 08/04/05: Re: Virtex-5 FXT coming soon?
    130985: 08/04/07: Re: Virtex-5 FXT coming soon?
    131882: 08/05/06: Xilinx ISE 10 in CentOS not showing in application menu list
    132593: 08/06/02: Celoxica (AgilityDS) running on Gentoo
    135506: 08/10/05: Re: Do two clock system blocks with one clock running half of other's
    135652: 08/10/11: Re: XMOS XC-1 kits are shipping
    137943: 09/02/02: Re: Spartan-6
    138040: 09/02/04: Re: Spartan-6
    141643: 09/07/02: Math Integral operation in FPGA
    141675: 09/07/03: Re: Math Integral operation in FPGA
    141676: 09/07/03: Re: Math Integral operation in FPGA
    144227: 09/11/20: Reading Altera datasheets
    144241: 09/11/22: Re: Reading Altera datasheets
    151178: 11/03/14: Re: FPGA boards
    151853: 11/05/24: Re: Verify failed between address 0x80000 and 0x8FFFF
    151861: 11/05/25: Re: Verify failed between address 0x80000 and 0x8FFFF
    151977: 11/06/16: Xilinx or Altera
    151987: 11/06/18: Re: Xilinx or Altera
    151995: 11/06/20: Re: Xilinx or Altera
    152007: 11/06/21: Re: Xilinx or Altera
    152019: 11/06/22: Re: Xilinx or Altera
    153603: 12/04/03: Very poor Xilinx experience
    153607: 12/04/03: Re: Very poor Xilinx experience
    153610: 12/04/04: Re: Very poor Xilinx experience
    153616: 12/04/04: Re: Very poor Xilinx experience
    154214: 12/09/09: Re: Looking for an extremely cheap FPGA board (in quantity, academic use)
    157654: 15/01/21: [RANT] XILINX, Are you freaking kidding me ?
    157656: 15/01/21: Re: [RANT] XILINX, Are you freaking kidding me ?
    157660: 15/01/21: Re: [RANT] XILINX, Are you freaking kidding me ?
Simon Goble:
    16502: 99/05/26: Re: Xilinx M1.5 Crash
Simon A. Young:
    30550: 01/04/15: Re: pseudo random numbers
Simon Armstrong:
    16773: 99/06/08: Re: FPGA Introduction is needed, right?
    16840: 99/06/13: comparative component pricing on www concept
Simon Bacon:
    2149: 95/10/20: Xilinx 5000 - any user feedback?
    5928: 97/03/27: Xilinx XC6200 -- any sightings?
    6444: 97/05/24: What is M1?
    6567: 97/06/03: Re: What is M1?
    6698: 97/06/16: XCHECKER Download to Xilinx 9500 CPLDs
    7443: 97/09/10: Reading Viewlogic files
    8272: 97/12/04: Xilinx ABEL releases?
    12441: 98/10/12: Processor Cores
    12700: 98/10/23: DynaText **!?!?
    13079: 98/11/15: Re: placement&routing problems
    19394: 99/12/18: Re: Dumb question springing from a discussion about chess on a chip...
    19413: 99/12/20: Re: Dumb question springing from a discussion about chess on a chip...
    19414: 99/12/20: Re: Necessary to 'synchronise' an asynchronous FSM reset?
    19503: 99/12/27: Re: Specifying Virtex CLKDLL CLKDV_DIVIDE property in VHDL
    19858: 00/01/14: Re: fastest 32 bit RISC
    20095: 00/01/26: Re: GSR in HDL on instantiated flip-flop primitives
    20096: 00/01/26: Secondary Clock Distribution in Virtex
    20118: 00/01/27: Re: GSR in HDL on instantiated flip-flop primitives
    28175: 00/12/24: Re: Question about programming xcv100
    28176: 00/12/24: Re: really fast counter in SpartanXL?
    28358: 01/01/10: Re: Alliance for Linux
    28831: 01/01/25: Re: Encryption is supported in new Virtex II but.....
    28890: 01/01/27: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
    28954: 01/01/31: Re: Advice on FPGA board.
    28972: 01/01/31: Re: Spartan 2 DLL
    28973: 01/01/31: Re: vector / edif format / LeonardoSpectrum
    29009: 01/02/01: Re: More then 4 Clocks
    29024: 01/02/02: Re: Spartan-II TBUF questions
    29104: 01/02/06: Re: Xilinx XC4010
    29168: 01/02/08: Re: initialise state machine on Altera
    29173: 01/02/08: Re: First XILINX PCI core project
    29200: 01/02/09: Re: Low skew lines in Virtex-E
    29374: 01/02/16: Re: Vertex Place & Route Time
    29376: 01/02/16: Re: Xilinx GSR in Verilog simulations
    29383: 01/02/17: Re: Vertex Place & Route Time
    29479: 01/02/23: Re: Virtex USB solution
    29480: 01/02/23: Re: Virtex E:Sample price
    29490: 01/02/23: Re: Help : Question about Synopsis
    29553: 01/02/26: Re: Spartan II power
    29569: 01/02/27: Re: Xilinx tools: RLOC hierarchy with HDL design?
    29576: 01/02/27: Re: Spartan II power
    29644: 01/03/03: Re: Xilinx tools: RLOC hierarchy with HDL design?
    29788: 01/03/09: Re: Foundation RLOC - help!
    29800: 01/03/11: Re: Questions about Xilinx Web Pack ISE
    29852: 01/03/13: Re: bonding information
    29864: 01/03/14: Re: 64 simultan A/D Converters in an SPARTAN-II
    29992: 01/03/20: Re: Packing density of Xilinx FPGAs
    29993: 01/03/20: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
    30035: 01/03/21: Re: Jobs....?
    30084: 01/03/22: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
    30182: 01/03/27: Re: Asynchronus Mashine States
    30215: 01/03/28: Re: Pinout tables
    30221: 01/03/28: Re: Pinout tables
    30259: 01/03/29: Re: FPGA V CPLD
    30269: 01/03/30: Re: HAL-15
    31969: 01/06/10: Re: [Xilinx] Spartan II Devices ..internal tristate busses ...
    31973: 01/06/10: Re: one state machine
    31992: 01/06/10: Re: Flash programming via FPGA's JTAG ????
Simon Bilodeau:
    22651: 00/05/16: Best choice between FPGA and CPLD
    22679: 00/05/17: Re: Best choice between FPGA and CPLD
    22783: 00/05/24: Why I can't place power symbols on my schematic?
    22784: 00/05/24: Re: Why I can't place power symbols on my schematic?
    22879: 00/05/29: Re: question about logic simulator from Xilinx Foundation F2.1i
    22887: 00/05/30: Re: question about logic simulator from Xilinx Foundation F2.1i
    22878: 00/05/29: question about logic simulator from Xilinx Foundation F2.1i
    23563: 00/06/30: Problem with uploading in XC95288 using ISP with HW-JTAG-PC
    23565: 00/06/30: Re: Problem with uploading in XC95288 using ISP with HW-JTAG-PC
    23660: 00/07/04: Re: Problem with uploading in XC95288 using ISP with HW-JTAG-PC
    23725: 00/07/06: Problem with XC95288 using JTAG with HW-JTAG-PC
    27048: 00/11/08: problem with XC95288 with PC-104
    27302: 00/11/17: XC95288 : Problem using 16 bits counters
Simon Bloyce:
    4402: 96/10/24: Re: VHDL for Xilinx designs?
Simon D. Wibowo:
    19747: 00/01/11: SDRAM controller ?
Simon Deeley:
    37335: 01/12/07: IP Updates and Modelsim
Simon Fielder:
    28432: 01/01/12: SRAM fpga cell
Simon Fisher:
    38522: 02/01/16: Audio time delay circuit
    38578: 02/01/18: Re: Audio time delay circuit
Simon Gauntlett:
    34818: 01/09/10: LVPECL : 75 Ohm Output Circuitry
Simon Goble:
    16504: 99/05/26: Re: Assigning pad type in Xilinx Virtex FPGA
    18883: 99/11/19: Re: Virtex: Getting flip-flops into the pads
    18884: 99/11/19: Re: Virtex: Getting flip-flops into the pads
    20593: 00/02/15: Re: Virtex DLL inoperability
Simon Gornall:
    26940: 00/11/04: Group behaviour (was: Alliance under Linux)
    26929: 00/11/03: Re: Alliance under Linux?
    26945: 00/11/04: Re: Group behaviour (was: Alliance under Linux)
    26946: 00/11/04: Spartan2 prototype boards
    26962: 00/11/05: Re: Spartan2 prototype boards
    28047: 00/12/20: Re: FPGA and Board for Microprocessor Design?
    28379: 01/01/10: Re: Alliance for Linux
    28454: 01/01/13: Re: Alliance for Linux - not a technical issue
    28808: 01/01/24: Re: Xilinx will NEVER support Linux
    32046: 01/06/11: Re: XC4005XL is it a modern chip?
    34655: 01/09/01: Re: Defending Austin Franklin
    36734: 01/11/18: Re: WebPACK 4.1 under Win95
    37170: 01/12/02: Re: Is there a full open-source synthesis path for any FPGA?
    37180: 01/12/03: Re: Is there a full open-source synthesis path for any FPGA?
    37205: 01/12/03: Re: Is there a full open-source synthesis path for any FPGA?
    43032: 02/05/10: Re: "easter egg" in FPGA design?
    43335: 02/05/19: Re: Need Help on FPGA and Spiking Neurons
    44804: 02/07/01: Re: Xilinx tools under WinXP
    47159: 02/09/19: What software package
    47235: 02/09/20: Re: What software package
    106257: 06/08/09: Re: Who is your favourite FPGA guru?
    106258: 06/08/09: Real-world soft-cpu performance
    106472: 06/08/13: Re: Real-world soft-cpu performance
    106539: 06/08/14: Re: Real-world soft-cpu performance
    107976: 06/09/03: Re: Impossible to download WebPACK?
Simon Graham:
    58858: 03/08/03: Nios Ethernet Development Kit Problems
Simon Greaves:
    22238: 00/05/02: VHDL / Verilog Consultant
Simon Heinzle:
    83189: 05/04/25: Experience with Hitech Global & Xilinx
    83211: 05/04/26: Re: Experience with Hitech Global & Xilinx
    83257: 05/04/26: Re: Experience with Hitech Global & Xilinx
    89711: 05/09/23: Synchronizer Flip Flop / Metastability
    89766: 05/09/26: Re: Synchronizer Flip Flop / Metastability
    90170: 05/10/06: .lib file for Xilinx FPGAs?
    90183: 05/10/06: Re: .lib file for Xilinx FPGAs?
    90239: 05/10/07: Re: .lib file for Xilinx FPGAs?
    90481: 05/10/14: Synplify Pro and automatic Retiming/Pipelining
    90646: 05/10/18: Anyone used the Xilinx' floating point core?
    90661: 05/10/18: Re: Anyone used the Xilinx' floating point core?
    91203: 05/11/01: Xilinx V2P Speed Grades
    104372: 06/06/26: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
    104424: 06/06/27: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
    104425: 06/06/27: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
    104426: 06/06/27: Re: Synplify & Fedora core 5
    104443: 06/06/27: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
    120111: 07/06/01: Xilinx MIG and verifying UCF files
    120235: 07/06/04: ISE and total equivalent gate count
    125583: 07/10/29: Xilinx, MIG, UCF: timing constraints for DDR2 DRAM
    125622: 07/10/30: Re: Xilinx, MIG, UCF: timing constraints for DDR2 DRAM
    125628: 07/10/30: Re: Xilinx, MIG, UCF: timing constraints for DDR2 DRAM
    134180: 08/07/29: Die sizes of FPGAs (approx)
    134191: 08/07/30: Re: Die sizes of FPGAs (approx)
    142494: 09/08/13: Simulating Xilinx EDK Systems
Simon Hermann MacKay:
    359: 94/10/28: Altera Flex project
Simon Hoffe:
    38971: 02/01/28: Importing ngo netlist into Foundation
Simon J Davidmann:
    2198: 95/10/31: Re: Where to find more info on PCI
    2600: 96/01/10: Re: Career value: VHDL or Verilog?
Simon J Fisher:
    53090: 03/03/03: Programming Altera parts in situ.
Simon Leung:
    36018: 01/10/26: WinXP Pro and Xilinx Foundation 3.3.8
Simon Moon:
    17549: 99/08/09: Lattice cable for 2032?
Simon Moreton:
    7449: 97/09/11: VHDL/Verilog Trainers Required in US and/or UK
    8204: 97/11/27: VHDL/Verilog Trainers Required by Esperan in US and/or UK
    9673: 98/03/30: Consultants, Discuss opportunity to teach VHDL and/or Verilog
    10707: 98/06/11: VHDL/Verilog Consultants interested in delivering Training for Esperan
Simon Méthot:
    1891: 95/09/15: ECL fpga
    1963: 95/09/25: Re: ECL fpga
    2179: 95/10/26: AMCC pci kit- problems
Simon Pawlowski:
    6142: 97/04/16: Xilinx 4KE's and SBUS
    6147: 97/04/17: Re: Xilinx 4KE's and SBUS
Simon Peacock:
    5773: 97/03/13: Re: A viewlogic story
    10626: 98/06/06: Re: Is there tiling software?
    11599: 98/08/25: Re: professional autorouters
    55497: 03/05/10: Re: Encrypted bitstream - battery lifetime solved
    58041: 03/07/13: Re: How to choose FPGA device?
    59052: 03/08/07: Re: Offshore engineering
    59139: 03/08/10: Re: from Altera to Xilinx
    59832: 03/08/29: Re: HDL Designer from Mentor
    59988: 03/09/03: Re: How to extend a pulse width without clock!
    60729: 03/09/20: Re: Transistor count
    60740: 03/09/21: Re: Parallel JTAG cable on a USB-only W2K laptop?
    60741: 03/09/21: Re: show-ahead FIFOs
    60742: 03/09/21: Re: pipelined divider
    60758: 03/09/22: Re: Xilinx
    60759: 03/09/22: Re: Parallel JTAG cable on a USB-only W2K laptop?
    60820: 03/09/23: Re: Transistor count
    60987: 03/09/26: Re: How to change "X" to "0" or "1" (VHDL) ?
    60989: 03/09/26: Re: Xilinx S3 I/O robustness question
    61099: 03/09/28: Re: How to change "X" to "0" or "1" (VHDL) ?
    61100: 03/09/28: Re: spam poll
    61115: 03/09/29: Re: Implementing Bidirectional pins
    61268: 03/10/01: Re: ByteBlaster with USB<->PP adapter?
    61502: 03/10/06: Re: Should I worry about metastability
    61504: 03/10/06: Re: Memory Handling in Altera Cyclone devices
    61575: 03/10/07: Re: Should I worry about metastability
    61576: 03/10/07: Re: beginner - exisit some free schematics programmer for fpga ?
    61640: 03/10/08: Re: Visualizing VHDL
    61641: 03/10/08: Re: Programmimg Altera serial configuration devices
    61642: 03/10/08: Re: Should I worry about metastability
    61643: 03/10/08: Re: BF957C Application
    61644: 03/10/08: Re: synplify vqm not able to fit in Quartus
    61814: 03/10/13: Re: How to select a FPGA
    62159: 03/10/21: Re: Altium DXP for designing Xilinx FPGA
    62410: 03/10/29: Re: Xilinx Spartan3: Price
    62463: 03/10/30: Re: Xilinx Spartan3: Price
    62568: 03/11/02: Re: Are there more I/O pins than I/O blocks?
    62604: 03/11/03: Re: Are there more I/O pins than I/O blocks?
    62605: 03/11/03: Re: Building the 'uber processor'
    62606: 03/11/03: Re: Power-On-Reset from a xilinx
    62607: 03/11/03: Re: How to protect fpga based design against cloning?
    63086: 03/11/14: Re: Layout examples
    63088: 03/11/14: Re: About the purchase of XCF01s
    63132: 03/11/16: Re: standalone IMPACT
    63699: 03/12/01: Re: Slightly unmatched UART frequencies
    63723: 03/12/02: Re: Slightly unmatched UART frequencies
    63787: 03/12/04: Re: Slightly unmatched UART frequencies
    64014: 03/12/12: Re: numeric_std and signed "/" operator
    64426: 04/01/04: Re: Complicated clocking in an FPGA.
    64669: 04/01/11: Re: Altera Cyclone Serial Configuration devices.
    65335: 04/01/25: Re: VHDL newbie
    66517: 04/02/21: Re: Spartan 3 - avaliable in small quantities?
    67620: 04/03/16: Re: EAB´s in ACEX 1K devices
    67735: 04/03/18: Re: Altera Quartus II 4.0 won't talk to ByteBasterMV
    68406: 04/04/03: Re: The Logic Behind License Renewal
    68615: 04/04/10: Re: Unsupported feature error:access type is not supported
    68661: 04/04/13: Re: system C - streams C
    68741: 04/04/16: Apples to Apples? XST <> Symplify
    68882: 04/04/21: Re: Issues on Shift Register in a Clockless UART
    68924: 04/04/22: Re: Issues on Shift Register in a Clockless UART
    68998: 04/04/24: Re: transport applications
    69170: 04/04/29: Re: Clock frequency converter from 1.544MHz to 2.048MHz (or multiples)
    69239: 04/05/02: Re: Altera ByteBlaster II schematic
    70322: 04/06/12: Re: Virtex4: I don't understand their thinking....
    70378: 04/06/15: Re: >Math Skills = >Engineer ?
    70379: 04/06/15: Re: Several Problems with Spartan2 Configuration
    70419: 04/06/16: Re: >Math Skills = >Engineer ?
    70967: 04/07/03: Re: *RANT* Ridiculous EDA software "user license agreements"?
    71633: 04/07/26: Re: Gate Count vs Logic Element (LE)
    72453: 04/08/19: Re: [Synthesis][VHDL] HowTo prevent Removal of Registers ...
    73294: 04/09/18: Re: Statix II vs. Virtex 4
    73349: 04/09/20: Re: Statix II vs. Virtex 4
    73456: 04/09/22: Re: Stratix II vs. Virtex 4 - features and performance
    73536: 04/09/23: Re: Mr. Greenfield, spare us the propaganda !
    75029: 04/10/25: Re: Low-power FPGAs?
    75092: 04/10/26: Re: Low-power FPGAs?
    75147: 04/10/27: Re: Low-power FPGAs?
    75173: 04/10/28: Re: Low-power FPGAs?
    75224: 04/10/30: Re: Low-power FPGAs?
    75225: 04/10/30: Re: Random number generation in testbench
    75228: 04/10/30: Re: Low-power FPGAs?
    75246: 04/10/31: Re: Low-power FPGAs?
    75254: 04/10/31: Re: Low-power FPGAs?
    74209: 04/10/06: Re: FPGA vs ASIC area -- the crucial issue is power consumption
    74516: 04/10/13: Re: Interfacing from the analogue domain
    74517: 04/10/13: Re: EP1C12 or XC3S400?
    74558: 04/10/14: Re: Where to buy cheap MAXII CPLD?
    74612: 04/10/15: Re: Where to buy cheap MAXII CPLD?
    74687: 04/10/17: Re: ModelSim
    74688: 04/10/17: Re: BCD to bin convertor
    74689: 04/10/17: Re: EP1C12 or XC3S400?
    74828: 04/10/20: Re: How To Provide External Input & Output To Startix 1S40..?
    75722: 04/11/13: Re: DualPortRAM serial IN - parallel OUT
    75724: 04/11/13: Re: Spartan3 Block RAM from WebPACK
    76161: 04/11/27: Re: Choice of FPGA device -- my view on benchmarks
    76190: 04/11/28: Re: Choice of FPGA device -- my view on benchmarks
    76191: 04/11/28: Re: XST question
    76780: 04/12/11: Re: Inferring dual port RAMs with different bus widths.
    77599: 05/01/12: Re: San Jose job offer - need advice
    79561: 05/02/21: Re: does anyone have a c compiler for the picoblaze
    79562: 05/02/21: Re: Is Altera Cyclone a good choice ?
    80775: 05/03/12: Re: Xilinx vs Altera high-end product solutions?
    81572: 05/03/28: Re: xilinx+modelsim total newbie
    81573: 05/03/28: Re: A newbie question (Xilinx or Altera Env?)
    81796: 05/04/01: Re: Coregen to generate a ROM of 32X1500 using LUT to construct multiplexer.
    81957: 05/04/05: Re: can c++ code be loaded to a hardware PGA coprocessor card
    82270: 05/04/10: Re: Spartan-3E based board available now? or is Memec advertizing vaporware ?
    82393: 05/04/12: Re: easyfpga is not easy
    82561: 05/04/14: Re: Simulation and actual FPGA implementation, how different it is?
    82677: 05/04/16: Re: Hobby or job? (FPGA User's groups anyone?)
    82679: 05/04/16: Re: salary ballpark please guys
    82785: 05/04/18: Re: Spartan 3E slower that Spartan 3?
    82867: 05/04/19: Re: Declining a job offer
    82989: 05/04/21: Re: Soft CPU vs Hard CPU's
    83112: 05/04/24: Re: Spartan 3E slower that Spartan 3?
    83113: 05/04/24: Re: A PC for make synthesis
    83222: 05/04/26: Re: A PC for make synthesis
    83821: 05/05/07: Re: embedded linux for v2pro PPC?
    83937: 05/05/10: Re: Uart16550 can't receive data over 16byte a time
    83938: 05/05/10: Re: Altera Quartus Timing Models
    83992: 05/05/11: Re: Altera Quartus Timing Models
    83994: 05/05/11: Re: DDR speed of the XUPV2P Board from Digilent
    84147: 05/05/13: Re: how can i save my received data into the SDRAM?
    84200: 05/05/14: Re: V4 vs. Stratix-II...
    84201: 05/05/14: Re: re:Uart16550 can't receive data over 16byte a time
    84202: 05/05/14: Re: floorplanning
    84215: 05/05/15: Re: floorplanning
    84216: 05/05/15: Re: floorplanning
    84222: 05/05/15: Re: floorplanning
    84223: 05/05/15: Re: floorplanning
    84518: 05/05/20: Re: Jobs going in New Zealand
    84533: 05/05/20: Re: Bullshit Achieves Literary Status
    84754: 05/05/26: Re: Ethernet / digital logic questions
    85601: 05/06/12: Re: Best Practices for Hardware Designers
    85602: 05/06/12: Re: computer upgrade time.
    88480: 05/08/19: Re: XST Help - Device Utilization Woes
    88680: 05/08/25: Re: Delays in verilog
    88681: 05/08/25: Re: Help coding a bigger project
    88682: 05/08/25: Re: FPGA Development Board Wish List
    88723: 05/08/26: Re: FPGA Development Board Wish List
    88771: 05/08/28: Re: Should I use DCM for every FPGA design?
    88773: 05/08/28: Re: Best FPGA for floating point performance
    88805: 05/08/29: Re: Best FPGA for floating point performance
    88848: 05/08/30: Re: Best FPGA for floating point performance
    88907: 05/08/31: Re: LCD Interface
    89076: 05/09/05: Re: High baud rate chips for RS232 protocol
    89172: 05/09/07: Re: Signed addition
    89257: 05/09/10: Re: Signed addition
    89288: 05/09/11: Re: Signed addition
    89392: 05/09/14: Re: 24 Counters on one board
    89394: 05/09/14: Re: Spartan-3 1000 -5 availability
    89552: 05/09/19: Re: Modelsim XE, what's the latest version?
    89810: 05/09/27: Re: Spartan3E - problem in creating LVDS DDR pads
    89811: 05/09/27: RE: vhdl state maching problem
    89812: 05/09/27: Re: jbits & reverse engineering
    89846: 05/09/28: Re: Sythesis software for Virtex-4
    89924: 05/09/30: Re: There is a way to instantiate 'N' VHDL components using a repetitive strutucture ?
    89986: 05/10/01: Re: VHDL 2 dimension array
    89987: 05/10/01: Re: PCB Software....
    89988: 05/10/01: Re: Testbench using Modelsim/VHDL - simple signal generation problem
    90006: 05/10/02: Re: VHDL 2 dimension array
    90007: 05/10/02: Re: Xilinx dev board with high quality video?
    90028: 05/10/03: Re: altera new bee
    90029: 05/10/03: Re: Prob in Synthesizing and Simulating large Mux
    90035: 05/10/03: Re: Xilinx dev board with high quality video?
    90038: 05/10/03: Re: Prob in Synthesizing and Simulating large Mux
    90058: 05/10/04: Re: Prob in Synthesizing and Simulating large Mux
    90059: 05/10/04: Re: vhdl question
    90125: 05/10/05: Re: Prob in Synthesizing and Simulating large Mux
    90126: 05/10/05: Re: Where to get informations about Virtex 4 FX Engineering Samples
    90127: 05/10/05: Re: vhdl question
    90130: 05/10/05: Re: High Load
    90131: 05/10/05: Re: Xilinx dev board with high quality video?
    90132: 05/10/05: Re: Avoiding meta stability?
    90133: 05/10/05: Re: Avoiding meta stability?
    90169: 05/10/06: Re: Prob in Synthesizing and Simulating large Mux
    90171: 05/10/06: Re: Avoiding meta stability?
    90172: 05/10/06: Re: Avoiding meta stability?
    90174: 05/10/06: Re: High Load
    90175: 05/10/06: Re: .lib file for Xilinx FPGAs?
    90245: 05/10/07: Re: Xilinx IMPACT Problem... detects 101 unknown devices
    90292: 05/10/09: Re: 3rd party JTAG cables/controllers for Virtex-4
    90303: 05/10/10: Re: FPGA behaviour when its used resource is >90% ?
    90356: 05/10/11: Re: 3rd party JTAG cables/controllers for Virtex-4
    90357: 05/10/11: Re: Compiling Altera LPM FIFO into Modelsim Error
    90359: 05/10/11: Re: VHDL : Use concatenation on port mapping
    90366: 05/10/11: Re: converting 12v signal to 3.3v
    90630: 05/10/18: Re: Compiling Altera LPM FIFO into Modelsim Error
    90632: 05/10/18: Re: Xilinx IMPACT Problem... detects 101 unknown devices
    90633: 05/10/18: Re: Storing a file onto FPGA (the last word)
    90904: 05/10/25: Re: SoC Processor design at gate level for edu
    90906: 05/10/25: Re: XC3S4000 pricing?
    91133: 05/10/31: Re: Spartan-3E starter kit
    91307: 05/11/03: Re: clock detection
    91308: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
    91419: 05/11/06: Re: Anybody understand this ISE 7.1 error, and what to do about it???
    91569: 05/11/09: Re: looking for FPGA pin header board
    91570: 05/11/09: Re: Anybody understand this ISE 7.1 error, and what to do about it???
    91572: 05/11/09: Re: ISE 8.1 news--BaseX going away, but WebPack gains devices and features
    91573: 05/11/09: Re: Verilog Editor.
    91577: 05/11/09: Re: Delay insertion in Xilinx Verilog
    91719: 05/11/11: Re: Anybody understand this ISE 7.1 error, and what to do about it???
    91721: 05/11/11: Re: Clock signal for an external peripheral
    91779: 05/11/13: Re: Clock signal for an external peripheral
    91780: 05/11/13: Re: Kingston ValueRAM double deckers
    91781: 05/11/13: Re: fastest possible USB
    91838: 05/11/15: Re: Verilog Editor.
    91891: 05/11/16: Re: Having trouble Detecting ethernet packets using ethereal
    91969: 05/11/18: Re: Trying to define Opendrain Outputs
    92037: 05/11/21: Re: CLK input DOES NOT use clk pin ( Altera Stratix II)
    92085: 05/11/22: Re: CLK input DOES NOT use clk pin ( Altera Stratix II)
    92086: 05/11/22: Re: Sounds or other means to indicate end of compilation in Xilinx ISE
    92087: 05/11/22: Re: How do I find the datasheet of this device "TIOPA 690 3BZL9"?
    92088: 05/11/22: Re: Oh no! Resets Again? Yes, but it could be important.
    92089: 05/11/22: Re: architecture
    92146: 05/11/23: Re: How do I find the datasheet of this device "TIOPA 690 3BZL9"?
    92147: 05/11/23: Re: Stupid reset question
    92148: 05/11/23: Re: CLK input DOES NOT use clk pin ( Altera Stratix II)
    92149: 05/11/23: Re: data encryption standard
    92304: 05/11/27: Re: XST :division and mod in vhdl
    92306: 05/11/27: Re: Distributed RAMs / SRL: Why not, Altera?
    92460: 05/11/30: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
    92601: 05/12/02: Re: Ethenet Multiplexers
    92602: 05/12/02: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
    92604: 05/12/02: Re: Download old Quartus versions (4.0, 4.1)
    92606: 05/12/02: Re: FPGA : Decimation Filter Implementation
    92609: 05/12/02: Re: Ethenet Multiplexers
    92680: 05/12/05: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
    92681: 05/12/05: Re: FPGA : Decimation Filter Implementation
    92682: 05/12/05: Re: how to build 32X32 LUT ROM
    92683: 05/12/05: Re: Pal programming requirement
    92684: 05/12/05: Re: Spartan3E availability update
    92743: 05/12/06: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
    92744: 05/12/06: Re: FPGA : Decimation Filter Implementation
    92746: 05/12/06: Re: ISE 8.1 release delayed?
    92882: 05/12/09: Re: How to connect 2 FPGA?
    92884: 05/12/09: Re: How to connect 2 FPGA?
    92885: 05/12/09: Re: Replace fast ethernet with VDSL2
    94398: 06/01/11: Re: Why 'a plurality of N' must be used for 'N' in patent claims
    94612: 06/01/14: Re: Don't even get me started on lead,
    95100: 06/01/21: Re: Stratix-II <==> Virtex4 interconnect; 10 GB Ethernet cores
    95370: 06/01/23: Re: ISE BaseX customers
    95375: 06/01/23: Webpack 8.1i size
    96020: 06/01/28: Re: C to FPGA Tools (Impulse C and others) and necessary trig IP
    96046: 06/01/29: Re: C to FPGA Tools (Impulse C and others) and necessary trig IP
    96156: 06/01/31: Re: Xilinx Legal
    96228: 06/02/01: Re: Xilinx Legal
    96227: 06/02/01: Re: ERROR message when programming FPGA with Altium Designer 2004
    94975: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95094: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95097: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95099: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95371: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95372: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95374: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    96397: 06/02/03: Re: Microblaze question
    96499: 06/02/05: Re: core generator
    96636: 06/02/08: Re: latest XILINX WebPack is totally broken
    96637: 06/02/08: Re: Software reset for the MicroBlaze
    96696: 06/02/09: Re: Software reset for the MicroBlaze
    96760: 06/02/10: Re: Software reset for the MicroBlaze
    96761: 06/02/10: Re: Async Processors
    97218: 06/02/19: Re: What is the best price you have gotten on for these FPGAs?
    97341: 06/02/21: Re: FPGA - software or hardware -2-
    97420: 06/02/22: Re: ISE Simulator Price
    97421: 06/02/22: Re: Layer 2 (MAC) Research Project to Eliminate Routers
    97422: 06/02/22: Re: Xilinx 8.1.02i map failure
    97423: 06/02/22: Re: FPGA - software or hardware -2-
    97469: 06/02/23: Re: FPGA - software or hardware -2-
    98088: 06/03/04: Re: why use an FPGA when a CPLD will do ??
    98109: 06/03/05: Re: why use an FPGA when a CPLD will do ??
    98127: 06/03/06: Re: why use an FPGA when a CPLD will do ??
    98128: 06/03/06: Re: Which CPU and Screen Rez for ISE 6.3i ?
    100987: 06/04/23: Re: Reliability CPLD/FPGA vs Microcontroller
    101314: 06/04/29: Re: How are constants stored ?
    103736: 06/06/10: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
    106032: 06/08/06: Re: 100m JTAG cable
    106047: 06/08/07: Re: 100m JTAG cable
Simon Pegg:
    8707: 98/01/21: Re: FPGA core for ASIC?
    8708: 98/01/21: Re: UART Spec
    8747: 98/01/23: Re: ALtera Devices.
Simon Piekert:
    147900: 10/06/01: Graphical User Interface project on Spartan-3 FPGA
Simon Ramirez:
    8819: 98/01/28: Re: ALtera Devices.
    8816: 98/01/28: Re: ALtera Devices.
    10775: 98/06/18: Re: VHDL testbench in Maxplus2
    10787: 98/06/18: Re: Non-periodic clock
    10795: 98/06/19: Re: Fpga Video interface
    10797: 98/06/19: Re: VHDL testbench in Maxplus2
    10821: 98/06/23: Re: Control skew due to routing in Xilinx M1
    10822: 98/06/23: Re: books on vhdl
    11272: 98/07/31: PCI Core In FPGA
    11282: 98/08/01: Re: how much ? prices of Xilinx chips
    11293: 98/08/02: Re: PCI Core In FPGA
    11384: 98/08/08: Re: Async design/minimum prop delays
    11383: 98/08/08: PCI Core Thanks
    11635: 98/08/27: Re: SYNTHESIS TOOLS
    11643: 98/08/28: Re: FPGA vendors
    11644: 98/08/28: Re: New Evolutionary Electronics Book
    11828: 98/09/11: Re: Constraining Xilinx tools to NOT use certain pins?
    11934: 98/09/20: Re: Xilinx Spartan and 4K speed grades
    11936: 98/09/20: Re: sync or async SRAM?
    17621: 99/08/15: Re: VHDL/Verilog? - Can of Worms
    17630: 99/08/16: Re: fpga board : make it or buy it?
    22043: 00/04/14: Re: Actel fpgas
    22636: 00/05/15: Re: XC1804 JTAG Programming Problems
    22762: 00/05/23: Re: Xilinx tools
    23036: 00/06/09: Re: WIDESPREAD INCOMPETENCE AT BELL ATLANTIC
Simon S. IBM:
    66205: 04/02/13: Random logic verilog gate netlist generator
Simon Tam:
    66395: 04/02/18: Re: Using 3.3V compliant FPGA for 5V PCI
    116166: 07/03/02: Re: Virtex 4 SATA redux
Simon Watson:
    153276: 12/01/24: Re: Semi-OT: Good Tcl Book
    153618: 12/04/05: Re: Free Seminars/Labs - Implementing PCI Express Designs in FPGAs
Simon Webb:
    33639: 01/08/01: Foundation 2.1 Schematic in WebPack
Simon Y. Foo:
    29842: 01/03/13: JBits drivers for XESS boards
Simon Zhang:
    22743: 00/05/22: About Xilinx DLL
    22756: 00/05/23: Xilinx Virtex E
    23555: 00/06/30: Who to synthesis?
<simon.charles@bloomsbury-dsp.co.uk>:
    115857: 07/02/22: Re: ROC PORT
simon.lam65-754-2315:
    6446: 97/05/25: Looking for FAQ
simon.stockton@baesystems.com:
    79186: 05/02/15: Re: ATM Cell Payload Scrambler / Descrambler Process Explaination Required
    82584: 05/04/14: Re: Fitting functionality in an XC2VP30 FPGA.
    82591: 05/04/14: Re: Fitting functionality in an XC2VP30 FPGA.
    82627: 05/04/14: Re: Fitting functionality in an XC2VP30 FPGA.
    87944: 05/08/04: Anyone had this error / knows what it means?
    93205: 05/12/15: Scrambled Net Names!
    97289: 06/02/20: Inactive signals are active!!! - Chipscope Pro 7.1i - SP4
    97346: 06/02/21: Re: Inactive signals are active!!! - Chipscope Pro 7.1i - SP4
    97355: 06/02/21: Re: Inactive signals are active!!! - Chipscope Pro 7.1i - SP4
    98409: 06/03/09: FIFO Simulation Oddities!
    98412: 06/03/09: Re: FIFO Simulation Oddities!
    98437: 06/03/10: Re: FIFO Simulation Oddities!
    100245: 06/04/05: RocketIO MGT Clocking Arrangement!
    100354: 06/04/07: Re: RocketIO MGT Clocking Arrangement!
    100841: 06/04/19: Is there anything fundamentally wrong with this code?
    100861: 06/04/19: Re: Is there anything fundamentally wrong with this code?
    100877: 06/04/20: Re: Is there anything fundamentally wrong with this code?
    100879: 06/04/20: Re: Is there anything fundamentally wrong with this code?
    101143: 06/04/26: What is the best way to clock data in on one clock edge and out on another?
    101170: 06/04/26: Re: What is the best way to clock data in on one clock edge and out on another?
    115581: 07/02/14: MGT RXRECCLK using 3 Global Clocks!
simon111:
    138532: 09/02/25: Re: Send data from FPGA to PC via USB
<simon_bacon@my-deja.com>:
    18061: 99/09/27: What are the Virtex REV connections?
    18216: 99/10/08: Re: What are the Virtex REV connections?
    18332: 99/10/16: Xilinx MAKE file
    18333: 99/10/16: Re: Interconnecting LUTs on a Virtex
    18347: 99/10/17: Re: SRAM FPGA with hardwired 40 MHz AVR RISC processor, memory and peripherals
    18376: 99/10/20: Re: Interconnecting LUTs on a Virtex
    18904: 99/11/20: Re: Virtex: Getting flip-flops into the pads
    18972: 99/11/23: Re: Virtex: Getting flip-flops into the pads
<simon_bacon@my-dejanews.com>:
    15305: 99/03/18: SRL16 simulation models
    15721: 99/04/10: Virtex PULLDOWNs
    15978: 99/04/24: Re: Using Embedded RAM in Xilinx Virtex Chips
Simone Bern:
    65672: 04/02/04: Re: ByteBlaster fails on Windows 98
Simone Winkler:
    59748: 03/08/27: Please help me!!!!! ModelSim question...
    59925: 03/09/01: parallel port
    60148: 03/09/05: switching problem
    62150: 03/10/21: please help, modelsim does not simulate
    63274: 03/11/19: SDRAM-Controller XAPP134
    63283: 03/11/19: Re: SDRAM-Controller XAPP134
    63935: 03/12/09: FIFO design
    63940: 03/12/09: Re: FIFO design
    63999: 03/12/11: Re: FIFO design
    64419: 04/01/03: please help! state machine
    64429: 04/01/04: Re: please help! state machine
    64737: 04/01/12: Making XAPP134 synthesizable
<simonray@hotmail.com>:
    23286: 00/06/21: FFT/IFFT for FPGA
SimonX:
    78272: 05/01/27: XC4005-6PQ160C datasheet
    78273: 05/01/27: XC4013E complete pci core example
    78354: 05/01/30: which version PCI LogiCore for XC4000E?
    78387: 05/01/31: which version PCI LogiCore for XC4000E?
simonz:
Simpleton Greives:
    24947: 00/08/23: Re: Non-disclosures in job interviews
    24948: 00/08/23: Re: Non-disclosures in job interviews
<simpson.eric@gmail.com>:
    106916: 06/08/22: Microblaze - Writing to instruction store
Sinbad Wilmot:
    2123: 95/10/18: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
sindhu:
    114551: 07/01/18: FPGA implementation of UHF transmitter in airborne applications
<singh.shailendra@gmail.com>:
    72914: 04/09/07: why systemc?
<singhal.prateek@gmail.com>:
    93178: 05/12/15: Parallel Cable III is not detected
sinharo:
    149477: 10/10/28: encrypted bitstream
Sink0:
    148708: 10/08/18: FPGA PCI BOARD .. Few Questions
    148733: 10/08/18: Re: FPGA PCI BOARD .. Few Questions
    148744: 10/08/19: Re: FPGA PCI BOARD .. Few Questions
    148759: 10/08/19: Re: FPGA PCI BOARD .. Few Questions
    148768: 10/08/19: Re: FPGA PCI BOARD .. Few Questions
    148769: 10/08/19: Re: FPGA PCI BOARD .. Few Questions
    148775: 10/08/20: Re: FPGA PCI BOARD .. Few Questions
    148899: 10/09/09: Question about OC PCI Cores
    148902: 10/09/09: Re: Question about OC PCI Cores
    148928: 10/09/11: Re: Question about OC PCI Cores
    148929: 10/09/11: Re: Question about OC PCI Cores
    148931: 10/09/12: Re: Question about OC PCI Cores
    148938: 10/09/13: Re: Question about OC PCI Cores
    148940: 10/09/13: Re: Question about OC PCI Cores
    148942: 10/09/14: Re: Question about OC PCI Cores
    148945: 10/09/14: Re: Question about OC PCI Cores
    148947: 10/09/14: Re: Question about OC PCI Cores
    148949: 10/09/14: Re: Question about OC PCI Cores
    148953: 10/09/15: Re: Question about OC PCI Cores
    149169: 10/10/05: Re: Starting a career with FPGAs
    149175: 10/10/06: Re: Starting a career with FPGAs
    149177: 10/10/06: Re: Starting a career with FPGAs
    149312: 10/10/15: FPGA or CPLD?
    149314: 10/10/15: Re: FPGA or CPLD?
    149327: 10/10/17: Re: FPGA or CPLD?
    149338: 10/10/17: Re: FPGA or CPLD?
    149340: 10/10/17: Re: Combined Microprocessor and FPGA
    149345: 10/10/18: Re: FPGA or CPLD?
    149347: 10/10/18: Re: ZIGBEE with FPGA
    149677: 10/11/16: Re: Spartan3 bidirectional 3.3V 5V level shifter
    149681: 10/11/17: Re: Spartan3 bidirectional 3.3V 5V level shifter
    149687: 10/11/17: Re: Spartan3 bidirectional 3.3V 5V level shifter
    149862: 10/11/29: Help with OpenCores PCI Bridge
    149885: 10/11/30: Re: PCI Architecture Question for Data Acquisition Board
    149899: 10/12/01: Re: PCI Architecture Question for Data Acquisition Board
    149909: 10/12/01: Re: PCI Architecture Question for Data Acquisition Board
    150097: 10/12/13: Re: PCI Architecture Question for Data Acquisition Board
    151394: 11/04/01: Doubts about OC PCI Bridge
    151444: 11/04/08: Little help with OC PCI Bridge (again)
    151530: 11/04/17: Help with Verilog Code
    151560: 11/04/19: Help with Assinc counter
    151561: 11/04/19: Re: Help with Verilog Code
    151562: 11/04/19: Re: Help with Verilog Code
    151572: 11/04/20: Re: Help with Assinc counter
    151629: 11/04/27: Help with good verilog practices
    151631: 11/04/27: Re: Excess Stratix IV and SIII parts inventory
    152083: 11/07/02: Help with bidirectional interface of a FPGA with a uC
    152086: 11/07/03: Re: Help with bidirectional interface of a FPGA with a uC
    152120: 11/07/10: Re: Help with bidirectional interface of a FPGA with a uC
    153101: 11/11/30: Re: Compatible Xilinx USB Cables: worth to bother?
SioL:
    95024: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95272: 06/01/22: Re: OT:Shooting Ourselves in the Foot
    95314: 06/01/22: Re: OT:Shooting Ourselves in the Foot
    95324: 06/01/22: Re: OT:Shooting Ourselves in the Foot
    95531: 06/01/24: Re: OT:Shooting Ourselves in the Foot
    95533: 06/01/24: Re: OT:Shooting Ourselves in the Foot
    95543: 06/01/24: Re: OT:Shooting Ourselves in the Foot
Sir Charles W. Shults III:
    43770: 02/06/02: Re: Clock double trigger problem
Sir Pal:
    81201: 05/03/19: Ask for PicoBlaze C compiler
Siri:
    105839: 06/08/01: Implementing Haar Decomposition on 256 sample input using only sysgen blocks
siriokds:
    148517: 10/07/29: SDRAM AutoPrecharge and Refresh
    148527: 10/07/29: Re: SDRAM AutoPrecharge and Refresh
    148600: 10/08/05: Spartan 3AN Starter Kit. Sell.
Sirish:
    76311: 04/11/30: Re: Avnet Xilinx Virtex-II Pro Development Board
    76586: 04/12/06: Re: Avnet Xilinx Virtex-II Pro Development Board
    82938: 05/04/19: avnet dev. kit flash reprogram
Sirish Kondi:
    74545: 04/10/13: Avnet Virtex 2 Pro Dev. Kit
sirisha.aluru@gmail.com:
    105558: 06/07/25: Designing a matrix multpier block using existing xilinx toolbox
siriuswmx:
    49882: 02/11/23: Re: Global clock routing
    49883: 02/11/23: What's the matter with "clock skew and data delay"?
    49889: 02/11/23: How to use altera's IP core in QUARTUS?
    49897: 02/11/24: Re: What's the matter with "clock skew and data delay"?
    49898: 02/11/24: Re: What's the matter with "clock skew and data delay"?
    49904: 02/11/24: Re: What's the matter with "clock skew and data delay"?
    49930: 02/11/26: Re: What's the matter with "clock skew and data delay"?
    50114: 02/12/02: register OR latch ?
    50116: 02/12/02: register OR latch ? (source code)
    50160: 02/12/03: Re: register OR latch ?
    50161: 02/12/03: Re: register OR latch ?
    50163: 02/12/03: Re: register OR latch ?
    50208: 02/12/04: Can QUARTUS open *.vec file?
    50293: 02/12/07: How to assign pins in VHDL?
    50372: 02/12/09: Re: How to assign pins in VHDL?
    51012: 02/12/26: Re: Altera Quartus or MAX Plus?
    51242: 03/01/07: Re: help for MAXPLUS2!
    51260: 03/01/08: can maxplusII use the result produced by other synthesize tool ,for axample synplify ?
    52882: 03/02/25: Re: VHDL & FPGA Design tools
    53055: 03/03/02: How to select the chip before using FPGA?
    53065: 03/03/02: Re: How to select the chip before using FPGA?
    53118: 03/03/04: Re: How to select the chip before using FPGA?
sirohi_rajiv@rediffmail.com:
    67329: 04/03/10: fpga
    67487: 04/03/12: hello
    67490: 04/03/12: Re: Software for synthesis
    67524: 04/03/13: any body help me about xc4010e board
    67525: 04/03/13: about edif
sitaram:
    38648: 02/01/20: SPARTAN 2-DLL USAGE
    38649: 02/01/20: Re: SPARTAN 2-DLL USAGE
siva koka:
    41173: 02/03/21: SPI-4 interface IP core available(OIF Standard) with MAC Core
Siva Velusamy:
    72583: 04/08/25: ring oscillator calibration
    72592: 04/08/26: Re: ring oscillator calibration
    73539: 04/09/23: Re: Ring Oscillator Redux
    102540: 06/05/17: Re: SystemACE bootloader for PowerPC on Virtex4 FX
    103595: 06/06/06: Re: ppc instruction count
    103672: 06/06/07: Re: Xilinx EDK: Connecting interrupt to MicroBlaze requires stdout?
    103735: 06/06/09: Re: ppc instruction count
    104230: 06/06/21: Re: Spartan-3 starter kit strange problem
    104231: 06/06/21: Re: cache aware programming
    105250: 06/07/18: Re: Virtex 4 ACE Compact Flash configuration problem
    105472: 06/07/24: Re: Microblaze: how to determine remainder after integer division
    105473: 06/07/24: Re: chipscope opb monitor
    105778: 06/07/31: Re: Accessing one SDRAM from two MicroBlazes
    105786: 06/07/31: Re: Accessing one SDRAM from two MicroBlazes
    105850: 06/08/01: Re: Accessing one SDRAM from two MicroBlazes
    106285: 06/08/10: Re: Networking : Multicast Performance
    106540: 06/08/14: Re: chipscope_opb_iba woes in XPS EDK
    106598: 06/08/15: Re: chipscope_opb_iba woes in XPS EDK
    106633: 06/08/16: Re: High rate data transfer from off-chip mem to FSL co-proc...
    106687: 06/08/17: Re: Using XMD for memory dumps (speed)
    107006: 06/08/23: Re: Microblaze : xil_malloc malloc
    108118: 06/09/05: Re: sinmple DMA Example for ML403
    108356: 06/09/08: Re: microblaze programm doesn't fit into bram...
    108400: 06/09/10: Re: Trying to get plb_temac working
    109161: 06/09/21: Re: Interrupts in Microblaze
    109625: 06/10/01: Re: System ACE woes
    109793: 06/10/05: Re: System ACE woes
    110689: 06/10/19: Re: DDR access for multiple procs on a ML310 (Virtex-II Pro)
    111401: 06/11/02: Re: DDR_controller_EDK
    111821: 06/11/10: Re: Why 64-bit PLB?
    111957: 06/11/13: Re: MPMC2: MPMC2 with DDR2 SDRAM
    112012: 06/11/14: Re: MPMC2: MPMC2 with DDR2 SDRAM
    113155: 06/12/06: Re: Remove DCM wrappers from EDK designs
    113156: 06/12/06: Re: Microblaze LMB bus
    113189: 06/12/07: Re: Microblaze LMB bus
    114004: 07/01/02: Re: PPC PLB <=> FPGA fabric
    114017: 07/01/02: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
    114047: 07/01/03: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
    116606: 07/03/13: Re: using system ACE for generic app data storage - file system intelligence
    120365: 07/06/05: Re: Weird! sysace_fwrite() cannot be found!!!???
    120451: 07/06/07: Re: EDK9.1: XTemac + LwIP + Xilkernel + unistd.h = possible?
    120882: 07/06/19: Re: Help configuring XUP PPC for Ethernet
    121647: 07/07/10: Re: Here you have the 'system.hms'
    122027: 07/07/17: Re: chipscope PLB IBA - how to get meaningful labels on signals?
    122330: 07/07/25: Re: EDK Microblaze project without OPB?
    122355: 07/07/25: Re: Why is Xilinx XPS 8.2i so slow?
    122991: 07/08/13: Re: Problems using xilfatfs on XUP V2Pro board
    123825: 07/09/05: Re: high bandwitch ethernet communication
    125024: 07/10/15: Re: DWARF2 in MicroBlaze?
    127772: 08/01/07: Re: Spartan 3E Sarter Kit Ethernet
    128060: 08/01/14: Re: Where has Xilnet gone?
    128184: 08/01/17: Re: Where has Xilnet gone?
siva.velusamy@gmail.com:
    96750: 06/02/09: Re: Microblaze Virtual platform problem
    96951: 06/02/13: Re: microblaze with FSL
    98003: 06/03/02: Re: Using time.h in EDK
    104239: 06/06/21: Re: Xilinx XC4VSX25 development board?
    106843: 06/08/20: Re: ISE/EDK "target pattern contains no `%'"
    109940: 06/10/08: Re: 75Mhz Spartan3e microblaze
    110080: 06/10/10: Re: EDK Bug
<siva007i@gmail.com>:
    97675: 06/02/25: FIFO design
sivakanth.telasula@gmail.com:
    107328: 06/08/26: Problem with netlister in System Generator
    107437: 06/08/28: Re: Problem with netlister in System Generator
    107465: 06/08/28: Re: Problem with netlister in System Generator
<sivakumar1974@my-deja.com>:
    25678: 00/09/17: post route timing simulation- help????
    25910: 00/09/26: clock skew,,,,,,,DLL instantiation
<sjadam@trog.dra.hmg.gb>:
    4131: 96/09/17: Inaccrate Xilinx simulations ???
    4638: 96/11/25: Moore vs Mealy state machines
sjb:
    112797: 06/11/29: XC3020-50 board documentation
    112871: 06/11/30: Re: XC3020-50 board documentation
<sjm1218@gmail.com>:
    88156: 05/08/10: XBERT module.
    88160: 05/08/10: Re: XBERT module.
Sjouke Burry:
    108121: 06/09/05: Re: Please help me with (insert task here)
    128191: 08/01/17: Re: effect of xray on fpga electronic circuits
SJU:
    124949: 07/10/12: Xilinx OCM memory use limitations ?
sjulhes:
    91639: 05/11/10: Looking for tutorials for bootloader writing on xilinx SOC ??
    91644: 05/11/10: Re: Looking for tutorials for bootloader writing on xilinx SOC ??
    91814: 05/11/14: downloading with XMD ?
    91818: 05/11/14: Re: downloading with XMD ?
    91842: 05/11/15: Re: downloading with XMD ?
    91897: 05/11/16: ISE 6.2i strange behavior
    91986: 05/11/18: Re: ISE 6.2i strange behavior
    92151: 05/11/23: Re: Aurora over Rocket IO and EDk
    92242: 05/11/24: simulating code loading in memory and jumping to memory
    92275: 05/11/25: Re: simulating code loading in memory and jumping to memory
    92334: 05/11/28: Re: simulating code loading in memory and jumping to memory
    92335: 05/11/28: Re: simulating code loading in memory and jumping to memory
    93878: 06/01/03: What is the best solution vor PCIe today ?
    93882: 06/01/03: Re: What is the best solution vor PCIe today ?
    94133: 06/01/06: PCI compliance ?
    94354: 06/01/10: FPGA configuration time for PCI identification ?
    94387: 06/01/11: Re: FPGA configuration time for PCI identification ?
    94388: 06/01/11: Re: FPGA configuration time for PCI identification ?
    94390: 06/01/11: Re: FPGA configuration time for PCI identification ?
    94413: 06/01/11: PLX PCI9656
    94466: 06/01/12: Re: PLX PCI9656
    94525: 06/01/13: PCI e clocking
    94526: 06/01/13: Re: PCI e clocking
    94561: 06/01/13: Re: PCI e clocking
    94735: 06/01/17: FIFO in SDRAM
    94761: 06/01/17: Re: FIFO in SDRAM
    94814: 06/01/18: Re: FIFO in SDRAM
    94905: 06/01/19: Re: FIFO in SDRAM
    100198: 06/04/05: max lvds IO speed on V2Pro
    101193: 06/04/27: Xilinx PCI 64/32 bits IP
    101245: 06/04/28: Re: Xilinx PCI 64/32 bits IP
    101249: 06/04/28: Re: Xilinx PCI 64/32 bits IP
    101255: 06/04/28: Re: Assigning MGT's in sample Aurora Design
    103925: 06/06/15: ARM cores in FPGA ?
    103967: 06/06/16: Re: ARM cores in FPGA ?
    104366: 06/06/26: VHDL model for Micron SDRAM simulation ?
    104375: 06/06/26: Re: VHDL model for Micron SDRAM simulation ?
    104434: 06/06/27: Re: VHDL model for Micron SDRAM simulation ?
    105220: 06/07/18: JED file translator
    105379: 06/07/21: Re: JED file translator
    107206: 06/08/25: Virtex 4 TEMAC and MII questions
    108323: 06/09/08: microblaze startup problem
    108340: 06/09/08: Re: microblaze startup problem
    108495: 06/09/12: Re: microblaze startup problem
    108836: 06/09/18: Re: microblaze startup problem
    120244: 07/06/04: Power PC heap initialisation on Reset
    120391: 07/06/06: Re: Power PC heap initialisation on Reset
    120505: 07/06/08: Re: Power PC heap initialisation on Reset
    120611: 07/06/12: Re: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
    120623: 07/06/12: Re: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
    120624: 07/06/12: Re: EDK Simulation Problem
sk:
    75370: 04/11/03: comparator problem
SK:
    85028: 05/06/03: Re: keypad scanner
    85134: 05/06/06: Re: FPGA : MAC FIR doubt--HELP ME PLEASE
sk.sulabh@gmail.com:
    89999: 05/10/01: Inferring design elements in ISE tool
    90754: 05/10/20: Re: Inferring design elements in ISE tool
Sk3ptic:
    152009: 11/06/21: Re: AVI container and VGA display
    152199: 11/07/19: sdxc
<sk6357@gmail.com>:
    138718: 09/03/05: Re: Configure FPGA via PCIe
<sk@glui.de>:
    80934: 05/03/14: LVDS as general differential input ?
    81180: 05/03/18: Re: LVDS as general differential input ?
    81300: 05/03/21: Re: LVDS as general differential input ?
    81302: 05/03/21: Re: LVDS as general differential input ?
Skarkada:
    813: 95/03/05: How to daisy-chain FPGAs in software?
<skatoulas@hotmail.com>:
    87591: 05/07/26: ISE makes a mistake
    87625: 05/07/27: Re: QuartusII 4.2 problem
    89098: 05/09/05: Area Estimation Issues
<SKatsyuba@gmail.com>:
    119705: 07/05/24: Re: using FPGA JTAG as GPIO
    119799: 07/05/26: Re: How can I perform Boundary Scan Testing on Altera Cyclone II FPGAs using JTAG?
    122227: 07/07/24: Re: Arming the Chipscope Pro ILA
    123163: 07/08/17: Re: Actel APA1000 and JTAG
    123633: 07/08/31: Re: Xilinx FPGA Based Board Problem
    124957: 07/10/12: Re: Graphical VHDL Viewer ?
    130005: 08/03/12: Re: Could I develop a new gui using java based on the script language
    130312: 08/03/20: Re: Altera EPM7032S reading checksum
skdjf:
    40649: 02/03/12: Re: a guide to digital design and synthesis
Skeets:
    101460: 06/05/01: Re: Question about the ip I developed
Skept:
    39800: 02/02/19: Mux implemented as tristate
    50520: 02/12/11: When to use CLKDLL vs. DCM in Virtex devices
    57337: 03/06/27: ASIC divider in FPGA?
<sketyro@gmail.com>:
    155607: 13/07/29: seperate high speed rules for HDL?
    155631: 13/07/30: Re: seperate high speed rules for HDL?
SKH:
    82391: 05/04/12: Import user Core with a Tri-state Port to EDK
skherich:
    80036: 05/02/28: high fan out skew in v2pro
    81718: 05/03/30: Re: Driving two DCM with same clock input pad.
    87732: 05/07/29: Re: Spartan3 Done is not going high
Skillwood:
    49927: 02/11/26: Frequency multiplier with digital h/w
    49932: 02/11/26: count based Frequency generator
    49969: 02/11/27: Re: count based Frequency generator
    49972: 02/11/27: Re: count based Frequency generator
    51513: 03/01/15: what is a Systolic Array
    51547: 03/01/16: HSPICE simulator
    52115: 03/02/01: Static Timing Analysis
    52252: 03/02/05: clock ditribution tree
skillwood:
    47743: 02/10/03: SoC Testing , need links
    47744: 02/10/03: Low power design
    47892: 02/10/07: Re: Low power design
    48000: 02/10/09: Gate array & standard cell based design.
skitles:
    10259: 98/05/08: Boundary Scan in XC4000: Help me
skitz:
    33988: 01/08/09: how do i LOC Virtex-II BUFGMUX and DCM?
    34468: 01/08/26: Re: Help needed: simulation OK, synthesis OK, but doesnt work :-<
skldfb:
    40534: 02/03/08: BlockRam
    40538: 02/03/08: Re: BlockRam
    40539: 02/03/08: Re: BlockRam
skoc:
    36856: 01/11/22: how can define function in terms of equation rather than gates in XC4000 series
Skogul:
    129603: 08/02/28: Re: Making changes to custom IP in EDK
    129847: 08/03/06: Re: Making changes to custom IP in EDK
Skrodzki Stefan:
    164: 94/09/05: Re: Lattice pLSI Development Question
    195: 94/09/18: Re: Lattice ISP software: really bad or just different?
<skroll@gmail.com>:
    98339: 06/03/08: Re: Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution
<skswrus@gmail.com>:
    123909: 07/09/06: ANNC: New Boundary-Scan Software
    123917: 07/09/06: Re: ANNC: New Boundary-Scan Software
    124856: 07/10/08: Re: JTAG interconnect testing, prototypes
    124861: 07/10/08: Re: JTAG interconnect testing, prototypes
Skull-Lee:
    59772: 03/08/28: serie
Sky:
    96777: 06/02/10: Altera EPLD
    96802: 06/02/10: Re: Altera EPLD
<sky465nm@trline4.org>:
    129966: 08/03/11: Re: Matlab, RS-232, Ethernet
    129977: 08/03/12: Re: New FPGA beginner's Video guide
    130032: 08/03/13: Re: Matlab, RS-232, Ethernet
    130146: 08/03/17: Re: implementing ethernet FCS code in verilog
    130148: 08/03/17: Re: Designing CPU
    130151: 08/03/17: Re: ISE 9.2SP4 error
    130215: 08/03/18: Re: implementing ethernet FCS code in verilog
    130277: 08/03/19: Re: ISE 10.0 finally with multi-threading and SV support ?
    130287: 08/03/19: Re: Xilinx interview questions
    130297: 08/03/19: Re: ISE 10.0 finally with multi-threading and SV support ?
    130310: 08/03/20: Re: A Challenge for serialized processor design and implementation
    130313: 08/03/20: SD-Card SDHC artificial 32GB limit
    130315: 08/03/20: Configure Spartan-3E w SD-Card?
    130317: 08/03/20: Re: Configure Spartan-3E w SD-Card?
    130364: 08/03/21: Re: Spartan 3E intefacing for dummies
    130365: 08/03/21: Re: Synoplify ???
    130400: 08/03/22: Re: Spartan 3E intefacing for dummies
    130434: 08/03/24: Re: counterfeit Xilinx ?
    130450: 08/03/24: Re: counterfeit Xilinx ?
    130474: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130475: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130631: 08/03/28: Re: Having trouble building an old Xilinx Spartan3 FPGA project I did on ISE 8.2i and EDK8.2 for microblaze. Also have ISE9.2i installed.
    130639: 08/03/29: Re: Newbies: Answer to "What is an FPGA?" in video
    130719: 08/03/31: Re: Using USB programming cables from Xilinx and Lattice on one Windows machine
    130743: 08/03/31: Re: Using USB programming cables from Xilinx and Lattice on one Windows machine
    130753: 08/04/01: Re: Using USB programming cables from Xilinx and Lattice on one Windows machine
    130766: 08/04/01: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
    130798: 08/04/02: Re: now I can talk about it...
    130819: 08/04/02: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
    130892: 08/04/04: Xilinx FPGA + SMPS
    130912: 08/04/05: Re: Conterfeit parts guidance
    131027: 08/04/08: Re: Starting a PCI Express Application
    131151: 08/04/13: Re: Spartan3E startup problems
    131167: 08/04/14: Re: Task in verilog
    131663: 08/04/28: Nano transistor breakthrough?
    131981: 08/05/09: Re: AHB and APB master VHDL generator
    131984: 08/05/09: Re: Xilinx Platform USB Cable II
    134434: 08/08/10: Re: Spartan 3e, LVDS LCD.
    134600: 08/08/20: Re: More work, less posts
    134621: 08/08/21: Apple II on FPGA
    135055: 08/09/12: Re: Quartus II compile speedup with New Quad Core Intel machine (compared with old dual XEON workstation)
    135056: 08/09/12: Re: Quartus II compile speedup with New Quad Core Intel machine (compared with old dual XEON workstation)
    135109: 08/09/16: Re: Xilinx build system
    135117: 08/09/17: Re: Xilinx build system
<sky465nm@trline5.org>:
    129424: 08/02/23: Re: Linux and the Digilent Basys ?
    129436: 08/02/24: Re: FPGA Editor Tutorial based on examples
    129567: 08/02/28: Re: ADC to FPGA Interface Webcast
    129610: 08/02/29: Re: Software for FPGA-based PC scope
    129668: 08/03/02: Re: FPGA/CPLD group on LinkedIn
    129709: 08/03/03: Re: FPGA/CPLD group on LinkedIn
    129719: 08/03/03: Re: my Spartan-4 wishlist
    129748: 08/03/04: Re: FPGA for a DVB common interface implementation
    129781: 08/03/05: Spartan-3E + SPI EEPROM
    129793: 08/03/05: Re: Anyone to open "FPGA museum" ? Here is first item :)
    129797: 08/03/05: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
    129807: 08/03/06: Re: Anyone to open "FPGA museum" ? Here is first item :)
    129849: 08/03/07: Re: Spartan-3E + SPI EEPROM
    129878: 08/03/08: Re: Spartan-3E + SPI EEPROM
    129885: 08/03/08: Re: SiliconBlue enters the FPGA fray
    129912: 08/03/10: Re: opencores down ?
<Sky465nm@trline5.org>:
    128704: 08/02/04: Re: Possible CRC error on XC3S400 - now what?
    128719: 08/02/05: Re: Server configuration for Virtex5
    128738: 08/02/05: Re: Possible CRC error on XC3S400 - now what?
    128739: 08/02/05: Re: Bitstream verification through readback
    128753: 08/02/05: Re: Possible CRC error on XC3S400 - now what?
    128760: 08/02/06: Re: Possible CRC error on XC3S400 - now what?
    128796: 08/02/06: Re: Possible CRC error on XC3S400 - now what?
    128840: 08/02/07: Re: Possible CRC error on XC3S400 - now what?
    128842: 08/02/07: Re: Possible CRC error on XC3S400 - now what?
    128847: 08/02/07: I/O mode to use for USB ..?
    128851: 08/02/07: Re: I/O mode to use for USB ..?
    128856: 08/02/07: Re: I/O mode to use for USB ..?
    128867: 08/02/08: Re: I/O mode to use for USB ..?
    128930: 08/02/11: Re: Downloading codes to FPGA development Board
    129060: 08/02/13: Re: When are FPGAs the right choice?
    129079: 08/02/14: Re: When are FPGAs the right choice?
    129255: 08/02/19: Re: Which Linux Distro to use for Xilinx tools
    129270: 08/02/19: Re: Which Linux Distro to use for Xilinx tools
    129348: 08/02/21: Re: Random Number Generation in VHDL
<skyhawk172L@attbi.com>:
    49105: 02/11/01: XC18VXX PROM Corruption
    49107: 02/11/01: Re: XC18VXX PROM Corruption
    49147: 02/11/02: Re: XC18VXX PROM Corruption
Skyrunner:
    110806: 06/10/23: iMPACT:923 - Can not find cable, check cable setup !
    110810: 06/10/23: Re: iMPACT:923 - Can not find cable, check cable setup !
    110856: 06/10/24: Re: iMPACT:923 - Can not find cable, check cable setup !
    110870: 06/10/24: Re: iMPACT:923 - Can not find cable, check cable setup !
skywave:
    67040: 04/03/03: Module design:why design can't run in "virtex2"
skyworld:
    108269: 06/09/07: Altera simulation model
    108473: 06/09/11: FPGA timing
    108491: 06/09/12: Re: FPGA timing
    114438: 07/01/16: four phase clock using DCM with xilinx FPGA
    114462: 07/01/16: Re: four phase clock using DCM with xilinx FPGA
    114466: 07/01/16: Re: four phase clock using DCM with xilinx FPGA
    114500: 07/01/17: Re: four phase clock using DCM with xilinx FPGA
    114653: 07/01/22: Clock constraints
    114686: 07/01/22: Re: Clock constraints
    114698: 07/01/23: XdmHelpers:662
    114920: 07/01/26: Timing analyzer with Virtex 4
    114937: 07/01/26: Re: Timing analyzer with Virtex 4
    114957: 07/01/27: Re: Timing analyzer with Virtex 4
    114991: 07/01/28: Re: Timing analyzer with Virtex 4
    115042: 07/01/29: Re: Timing analyzer with Virtex 4
    115974: 07/02/26: $recovery
    116069: 07/02/28: Re: $recovery
    116134: 07/03/01: Re: $recovery
    116728: 07/03/16: chipscope
    122226: 07/07/24: 3 input adder in Spartan 3E
    122231: 07/07/24: Re: 3 input adder in Spartan 3E
    122306: 07/07/25: Re: 3 input adder in Spartan 3E
    134245: 08/07/31: xilinx FPGA "program failed"
    141325: 09/06/18: synplify script for constraint
    141329: 09/06/18: Re: synplify script for constraint
    141333: 09/06/18: Re: synplify script for constraint
    141339: 09/06/18: Re: synplify script for constraint
    143807: 09/10/27: synplify question for FPGA
    143808: 09/10/27: Re: synplify question for FPGA
    143823: 09/10/27: Re: synplify question for FPGA
    143824: 09/10/27: Re: synplify question for FPGA
    143826: 09/10/27: Re: synplify question for FPGA
    143830: 09/10/28: Re: synplify question for FPGA
    144351: 09/11/30: How to evaluate design performance for FPGA
slamwu:
    54214: 03/04/04: PCB for Altera APEX20KE failed ?
    58774: 03/08/01: How to update LPM_ROM in ALTERA device quickly?
Slamy:
    152186: 11/07/17: Issues with Soft-Cores
    152195: 11/07/18: Re: Issues with Soft-Cores
slarty:
    41397: 02/03/27: Re: synplify, quartus II 2.0
Slavek Przepiorski:
    16159: 99/05/07: 68HC11+EPLD development system
slawc:
    90333: 05/10/10: Verilog VPI
Slawek:
    59321: 03/08/14: Problems with ModelSim (Atmel's System Designer)
    59350: 03/08/15: Re: Problems with ModelSim (Atmel's System Designer)
    59369: 03/08/17: Re: Problems with ModelSim (Atmel's System Designer)
    122421: 07/07/27: Re: regarding the post PnR timing simulation.....
<slax0r.hax0r@gmail.com>:
    112834: 06/11/29: Spartan-3E or Generic FPGA -> PC133 interface details??
slebetman:
    124036: 07/09/11: Re: Uses of Gray code in digital design
slebetman@yahoo.com:
    124073: 07/09/11: Re: Uses of Gray code in digital design
    124192: 07/09/14: Re: Uses of Gray code in digital design
sleeman:
    141475: 09/06/25: Re: True dual-port RAM in VHDL: XST question
Sleep Mode:
    45894: 02/08/09: BLUETOOTH newbie
    46018: 02/08/14: Re: BLUETOOTH newbie
    46021: 02/08/14: Re: BLUETOOTH newbie
    64706: 04/01/12: How to generate a CSA tree?
    89488: 05/09/16: problem with programming avnet edk board over LPT
    89494: 05/09/16: Re: problem with programming avnet edk board over LPT
    97155: 06/02/17: Memory initialization for synthesis in ISE
slide_o_mix:
    133660: 08/07/08: JTAG IR length detection
    133712: 08/07/10: Re: JTAG IR length detection
slight_return:
    151492: 11/04/13: Re: Altium Limited closing up shop - Altium Designer discontinued
    151501: 11/04/14: Re: Altium Limited closing up shop - Altium Designer discontinued
Slim:
    119856: 07/05/28: Proper word for total delay?
<slkjas@gmail.com>:
    111570: 06/11/06: PCIe latency
<slmccaskill@gmail.com>:
    125731: 07/11/02: Re: To Xilinx users - PLB bus features (for PPC)
SLO JAM:
    372: 94/10/31: Re: High Bus Drive (24mA) FPGAs/CPLDs?
<sloman@sci.kun.nl>:
    6940: 97/07/11: Re: fast scopes: how?
Slonik:
    18079: 99/09/27: for Russian
Slurp:
    88263: 05/08/13: Re: Peter Alfke's SPDT Switch Debouncer
    89037: 05/09/03: Re: The best way to sum 8 datas?
    89045: 05/09/03: Re: High baud rate chips for RS232 protocol
    89059: 05/09/04: Re: Logic??
    90387: 05/10/11: Re: how to implement 8x8 circular shifter on FPGA
    90521: 05/10/15: Re: 3.3v<->5V
    93031: 05/12/12: Re: FPGA in industrial environment
    93830: 06/01/01: Re: basic DSP with FPGA
    95650: 06/01/25: Re: help:dual-edge flip-flop possible using Verilog?
    96562: 06/02/06: Re: Arbiter for several wires competing
    96876: 06/02/12: Re: digital logic library by 74xxxx part number?
    97004: 06/02/14: Re: digital logic library by 74xxxx part number?
    99974: 06/03/31: Re: Xilinx Schematic Entry
    100894: 06/04/20: Re: Reliability CPLD/FPGA vs Microcontroller
    102007: 06/05/09: Re: help me to about clock in fpga
    102019: 06/05/09: Re: help me to about clock in fpga
    102255: 06/05/12: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
    102472: 06/05/16: Re: Xilinx or Altera...
    102552: 06/05/17: Re: Xilinx or Altera...
    103016: 06/05/24: Re: Stopping Quartus using multipliers?
    104807: 06/07/06: Re: debouncing a switch (in hardware)
    105231: 06/07/18: Re: Reuse a Speed Grade -8 Stratix image in Speed Grade -6 ...?
    106434: 06/08/13: Re: Maximum Current Draw of FPGA
    109603: 06/09/30: Re: DDR RAM
    110799: 06/10/23: Re: Camera link specification
    111659: 06/11/07: Re: confused result in Logic Analyser, being crazy...
    111853: 06/11/11: Re: Virtex-5 Webpack?
    111887: 06/11/12: Re: Power-on reset
sly:
    128440: 08/01/25: Re: Random Number Generation in VHDL
SM Sasaki:
    4398: 96/10/24: Re: VHDL for Xilinx designs?
<smackeron@gmail.com>:
    115252: 07/02/05: Re: four phase clock using DCM with xilinx FPGA
smart:
    18323: 99/10/14: Re: Virtex Board
smart0604:
    147643: 10/05/11: what is the fmax of the simple dual port ram in the altera fpga
Smartchip:
    11750: 98/09/07: ahdl to vhdl or verilog
    11793: 98/09/10: ZILOG (Z80) SIMULATION CORE
    11819: 98/09/11: Hardware spec or document
    15810: 99/04/15: Composer (Cadence) ?
<smcc_adps@my-deja.com>:
    18381: 99/10/21: Re: Best FPGA for PCI ?
    20702: 00/02/18: Re: RECONFIGURABLE board for image processign
<smeiyapp@my-dejanews.com>:
    13095: 98/11/16: Re: VHDL project
    13151: 98/11/17: Re: Synthesizeablel fifo
<smensor@altera.com>:
    83069: 05/04/22: Re: Is Cyclone-2 EP2C5 or EP2C8 available? If not, when?
    84776: 05/05/26: Re: What's the difference between Altera EPM1270T144C5 and EPM1270T144C5N?
Smi:
    143136: 09/09/23: IP core for FIR filter
    143516: 09/10/14: Netlist generation error
    143787: 09/10/26: HI.. Help Needed Its Urgent
    143802: 09/10/26: Re: HI.. Help Needed Its Urgent
<smileforthecamerahotshot@gmail.com>:
    154279: 12/09/22: multi-source errors
    154294: 12/09/23: Re: multi-source errors
SMiOUxrH:
    19160: 99/12/02: <!-- To use a different cobrand, make sure you have a template for it in /parts/cobrand/ -->
smitch01:
    10587: 98/06/03: Re: Xilinx 5200 - XACT 6.0.1 vs. M1.4
Smith:
    147212: 10/04/19: Need to run old 8051 firmware
    147217: 10/04/19: Re: Need to run old 8051 firmware
<smith410@gmail.com>:
    140422: 09/05/13: Re: cheapest FPGA?
<smith@q.continuum.net>:
    4181: 96/09/23: test
<smithers12@my-deja.com>:
    19289: 99/12/10: Virtex boards
<smithie@altavista.com>:
<smithsa@gmail.com>:
    153768: 12/05/16: Re: Spartan-6 66mhz pci
<smount>:
    113985: 07/01/02: Surface mount ic's
    113999: 07/01/02: Re: xilinx xc9536?
    114000: 07/01/02: Re: Surface mount ic's
smu:
    59536: 03/08/21: ise 5.2 timing summary
    75027: 04/10/25: FPGA board checking
    78207: 05/01/26: Spartan 2E and SDRAM
    100013: 06/04/01: Xilinx SelectMAP problem
    100050: 06/04/02: Re: Xilinx SelectMAP problem
SN:
    31500: 01/05/28: what cables and softwares do you need to use "Xilinx FPGA Demonstration Evaluation Board"?
    31906: 01/06/08: XC4005XL is it a modern chip?
    32667: 01/07/04: 8031 microcontroller on FPGA development board :-(
SneakerNet:
    60590: 03/09/17: USB Transreceiver (PDIUSBP11A)
    60805: 03/09/23: USB 1.1/2.0 Implementation
    60855: 03/09/24: Re: USB 1.1/2.0 Implementation
    60866: 03/09/24: Re: USB 1.1/2.0 Implementation
    60907: 03/09/25: Re: USB 1.1/2.0 Implementation
    60965: 03/09/26: Reducing Clock Speed
    60971: 03/09/26: Re: Reducing Clock Speed
    60973: 03/09/26: Re: Reducing Clock Speed
    61108: 03/09/29: Re: Reducing Clock Speed
    61168: 03/09/30: USB Core (Japanese Version)
    61174: 03/09/30: Re: USB Core (Japanese Version)
    61187: 03/09/30: Re: Reducing Clock Speed
    61192: 03/09/30: Re: USB 1.1/2.0 Implementation
    61234: 03/10/01: Re: USB Core (Japanese Version)
    61236: 03/10/01: Re: USB 1.1/2.0 Implementation
    61237: 03/10/01: Re: USB 1.1/2.0 Implementation
    61244: 03/10/01: Re: USB Core (Japanese Version)
    61249: 03/10/01: Re: USB Core (Japanese Version)
    61250: 03/10/01: Re: USB 1.1/2.0 Implementation
    61253: 03/10/01: Re: USB 1.1/2.0 Implementation
    61303: 03/10/02: Re: USB Core (Japanese Version)
    61314: 03/10/02: Re: USB Core (Japanese Version)
    61328: 03/10/02: Re: USB Core (Japanese Version)
    61830: 03/10/14: mp3 project
    61834: 03/10/14: Re: mp3 project
    61878: 03/10/15: Re: mp3 project
    61884: 03/10/15: Re: mp3 project
    61897: 03/10/15: USB Core (Japanese Version) Revisited ;o(
    61963: 03/10/16: Re: USB Core (Japanese Version) Revisited ;o(
    62017: 03/10/17: Re: USB Core (Japanese Version) Revisited ;o(
    66049: 04/02/12: Sine Wave Generation
    67211: 04/03/09: Using ALTPLL
    67230: 04/03/09: Re: Using ALTPLL
    67290: 04/03/10: Re: Using ALTPLL
    68300: 04/04/01: Msg for Rudolf Usselmann
    68351: 04/04/02: Re: Msg for Rudolf Usselmann
    68472: 04/04/06: Fan Out Problem..
    69482: 04/05/12: FPGA + CF
    72360: 04/08/17: Spooling from FPGA to the PC
    77433: 05/01/07: VHDL Test Bench + Help
<sneakypete81@googlemail.com>:
    134051: 08/07/23: Xilinx tcl: How to determine if a process fails
SneeR:
    45321: 02/07/18: AMBA specyfication
Snesarev, Victor (BNR:BNRTP:3H55):
    12660: 98/10/22: Re: state assignment & fpgas
Sniper Daryl:
    40725: 02/03/13: the server to access to this newgroup
    45447: 02/07/23: How to implement efficient wide word comparator?
snowball67:
    142335: 09/08/05: Driving Multiple FPGAs and Fanout (Cyclone III)
Snowbin:
    4159: 96/09/20: Crosspoint FPGA
SnowBin:
    2832: 96/02/14: Crosspoint Solutions FPGA
Snowy:
    153364: 12/02/07: Re: 'x' state on one bit of the input bus of an adder cause the output bus be all 'x' during simulation
    153454: 12/03/01: Touchscreen For Terasic Technologies DE0 Nano
<snyderkena@my-deja.com>:
    25983: 00/09/29: FPGA development on the cheap?
<soar2morrow@yahoo.com>:
    80735: 05/03/10: Re: Xilinx vs Altera high-end solutions
    93700: 05/12/28: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
    93705: 05/12/28: Re: Power Optimization: can the routing and placement really save power?
    94006: 06/01/04: Re: Why 'a plurality of N' must be used for 'N' in patent claims
    94305: 06/01/09: Re: Why 'a plurality of N' must be used for 'N' in patent claims
    94488: 06/01/12: Re: Why 'a plurality of N' must be used for 'N' in patent claims
    97314: 06/02/20: Re: Is FPGA code called firmware?
    102338: 06/05/15: IEEE-1394 (aka FireWire) Core
    102451: 06/05/16: Re: USB2 camera to Xilinx ML40x boards
    102599: 06/05/17: Re: IEEE-1394 (aka FireWire) Core
    140987: 09/06/01: Has anyone tried to install a Xilinx floating license? The
    140991: 09/06/01: Re: Has anyone tried to install a Xilinx floating license? The
    140997: 09/06/01: Re: Has anyone tried to install a Xilinx floating license? The
    141089: 09/06/04: Re: Has anyone tried to install a Xilinx floating license? The
    141090: 09/06/04: Re: How to generate clocks of higher frequency?
<socaciu.claudiu@gmail.com>:
    102502: 06/05/16: hy I need a code example for spartan 3 series in Xilinx regarding the implementation of a PID alghoritm
Socrat:
    64403: 04/01/02: Re: Xilinx Parallel cable
Socrates:
    147920: 10/06/02: Job experience? How?
    147925: 10/06/02: Re: Job experience? How?
    147938: 10/06/03: Re: Job experience? How?
    147940: 10/06/03: Re: Job experience? How?
    148390: 10/07/17: Re: Another Xilinx webpack download rant
    148431: 10/07/22: Re: WTB: Xilinx USB JTAG Cable
    148613: 10/08/06: Re: xilinx usb cable
    148859: 10/09/04: Re: Want to get into FPGA
    148868: 10/09/05: Re: Want to get into FPGA
    148892: 10/09/08: Re: Want to get into FPGA
    148912: 10/09/09: Re: Want to get into FPGA
    149235: 10/10/11: Re: Spartan-6 Boards
    149622: 10/11/12: Re: Spartan3 bidirectional 3.3V 5V level shifter
    150146: 10/12/19: Re: FPGA modules/cards with peripheral functions
    150800: 11/02/13: Using Altera SDI core
    151093: 11/03/05: Re: Finding cheap PCI-E FPGA board for a student
Soenke:
    89363: 05/09/13: floppycontroller
    93671: 05/12/28: DigitalRadioMondiale
Soeryanto:
Softley, C.:
    43436: 02/05/21: Re: Synchronous Single Clock Designs
Soha Hassoun:
    8793: 98/01/27: Ph.D. forum at DAC
    9423: 98/03/12: PhD forum at DAC -- Submission deadline Reminder
    10112: 98/04/27: Reminder: PhD forum at DAC submission deadline
    10598: 98/06/04: PhD forum at DAC -- Update
    14655: 99/02/09: Ph.D. Forum at DAC: Announcement & First Call for participation
    15152: 99/03/10: Ph. D. Forum at DAC -- Final Call for Participation
Sohaib Majzoub:
    70523: 04/06/18: Virtex II : partial reconf, bus macro
Sohoman:
<solazzimarco@gmail.com>:
    92287: 05/11/25: PLB GEMAC
solo:
    109413: 06/09/26: PUBLISHABLE PAPER RELATED TO FPGA!
    109415: 06/09/26: Re: PUBLISHABLE PAPER RELATED TO FPGA!
    109453: 06/09/27: Re: PUBLISHABLE PAPER RELATED TO FPGA!
    109518: 06/09/27: Re: PUBLISHABLE PAPER RELATED TO FPGA!
    109533: 06/09/27: Re: PUBLISHABLE PAPER RELATED TO FPGA!
solomon Alemu:
    146958: 10/04/04: How to convert Verilog in to VHDL code
Som Sikdar:
    1287: 95/05/28: OrCAD HDL (OHDL) and Lattics pLSI devices
    2384: 95/11/27: CRC-32 implementation
somayeh2010:
    148673: 10/08/17: I have problem in writing testbench
some call me... Robert:
    17: 94/07/28: Re: Does the iFX780 qualify for discussion here?
Some member of the Douglas Family:
somebody:
    16060: 99/04/30: Xilinx Implementation error
Someone Else:
    31981: 01/06/10: Re: Flash programming via FPGA's JTAG ????
someone2003@gawab.com:
    68145: 04/03/27: Question : Serial PROM
<someone92@hotmail.com>:
    85819: 05/06/16: Good FPGA introduction book ?
someone@example.com:
    77192: 04/12/28: Re: Google is turning usenet into crap - was Primers for Handel-C
<someone@somedomain.com.invalid>:
    66671: 04/02/25: SmartMedia writer (implments using VHDL)....
<somrqu@my.com>:
somser:
    3198: 96/04/24: new bbs
Son Huynh:
    8545: 98/01/07: Re: SDRAM model
Son P. Huynh:
    11965: 98/09/21: Re: Verilog newsgroup
    12015: 98/09/24: Re: Which FPGA tool is better
    12340: 98/10/09: Re: Software tool
Sonal Santan:
    130787: 08/04/01: Re: ISE 10.1 - Initial experience
Sonali:
    96325: 06/02/01: high input to CPLD
    96342: 06/02/02: Re: high input to CPLD
    96961: 06/02/14: ModelSim Licence problem
    97080: 06/02/16: delay using integrator
Sonali Kale:
    51901: 03/01/24: PROM : Master serial configuration
sonetguest:
    113499: 06/12/14: Adding Jitter
    113500: 06/12/14: Using SYSTEM_JITTER and INPUT_JITTER for timing analysis.
    113502: 06/12/14: Xilinx SYSTEM_JITTER, INPUT_JITTER Questions - Part II
Song:
    63165: 03/11/17: Tool for connecting modules,download free,quick demo
Song Qian:
    49068: 02/10/31: 250MHz Data Bus connected directly to Xilinx Virtex-II
SongDragon:
    101908: 06/05/08: PCI Express and DMA
    102001: 06/05/09: Re: PCI Express and DMA
Songhyun Yun:
    21066: 00/03/06: To use synplify in command mode
Songqing Zhang:
    43308: 02/05/18: Xilinx 4000XLA-8: is 4 stages of logic ok?
    43309: 02/05/18: Re: Xilinx 4000XLA-8: is 4 stages of logic ok?
    43386: 02/05/20: Re: Xilinx 4000XLA-8: is 4 stages of logic ok?
<songrise@gmail.com>:
    131488: 08/04/22: Can somebody help about Period Timing Constraints
songsong:
    8427: 97/12/14: Re: bus design in Altera 10K, how to increase speed
Songsong:
    7918: 97/10/30: Help about ALTERA FPGA!!
SongWei:
    26772: 00/10/27: why?
<sonic@sega.net>:
    19123: 99/11/30: Free classified ads
sonne123:
    88802: 05/08/29: Xilinx PC4 Download Cable
SonnyAnd:
    153257: 12/01/19: Re: Compatible Xilinx USB Cables: worth to bother?
Sonu Abraham:
    49122: 02/10/31: Reference Schematics
SoonHuat Goh:
    14097: 99/01/13: Re: I2C core
    14497: 99/02/02: Re: Off topic DRAM/SIMM question....
soonph87:
    151248: 11/03/17: DMA (memory to memory)
soos:
    82101: 05/04/06: LVDS PCI card is needed
    82610: 05/04/14: Re: LVDS PCI card is needed
    82813: 05/04/18: DSP-PC architectural advice needed.
    82992: 05/04/21: Re: DSP-PC architectural advice needed.
Sophi:
    105654: 06/07/27: Does MAC FIR filter need special care?
    105710: 06/07/28: Re: Does MAC FIR filter need special care?
    105730: 06/07/30: Re: Does MAC FIR filter need special care?
    105793: 06/07/31: Re: Does MAC FIR filter need special care?
Sophie Liu:
    94337: 06/01/10: Re: tcam implemented in fpga
    94279: 06/01/09: about the ftp.altera.com
    94340: 06/01/10: Re: about the ftp.altera.com
    94408: 06/01/11: Re: Stepping vs. ES
    95313: 06/01/22: Re: post-fit simulation failed
    97023: 06/02/15: What is back_annotate?
Soren 'Disky' Reinke:
    30464: 01/04/09: free software
Soren Kristensen:
    2645: 96/01/18: 8259 interrupt controller source
    4073: 96/09/08: Re: ..people NOT using Xilinx
    4213: 96/09/27: Source for 8259 PIC
    14592: 99/02/05: Lattice ispLSI 2000V opendrain problem.
Sosgez:
    29484: 01/02/23: Re: PCI : Not booting on ASUS
    34568: 01/08/29: Atmel JTAG cable
sotl:
    12330: 98/10/09: LUXEMBOURG: DEMOCRACY OR POLICE STATE
<soto@caviar.igce.unesp.br>:
    13964: 99/01/05: Dynamic reconfig
Soul in Seoul:
    48764: 02/10/24: Who has some Lecture materialson I2C Bus?
    48833: 02/10/25: comp.cad.synthesis.
    48834: 02/10/25: Re: Who has some Lecture materialson I2C Bus?
    48948: 02/10/28: Porting from Xilinx to Altera?
    48949: 02/10/28: Re: Porting from Xilinx to Altera?
sovan:
    90207: 05/10/06: Re: Verification using Chipscope
    102323: 06/05/15: Re: Synchronous Scrambler
    105972: 06/08/03: RocketIO simulation in VCS
    110956: 06/10/25: Re: V5LXT support for ISE released yesterday
    112380: 06/11/21: V5 LXT PCIe Block simulation
    112398: 06/11/21: Re: V5 LXT PCIe Block simulation
    117974: 07/04/14: Re: ML506 Platform Flash
    117989: 07/04/15: Re: Writing to BRAM using OPB
    125411: 07/10/25: Re: MPMC2 NPI Help!
    125437: 07/10/25: Re: MPMC2 NPI Help!
    125777: 07/11/04: Re: Xilinx PCI-Express Endpoint Block IP
<sowjanyanarla@yahoo.com>:
    78371: 05/01/31: Master Serial Programming
sowteng:
    49632: 02/11/18: counter error no matching overload for "+"
soxmax:
    86318: 05/06/24: Re: How do I convert a polynomial into a parallel scrambler formula?
    130491: 08/03/25: Timing constraints in ucf
SoyAnarchisto:
    132004: 08/05/09: Re: Anyway to secure a Xilinx NGC file ?
    132007: 08/05/09: Re: ISE 9.2 - how do I extract component/slice placements for locking
SP:
    56765: 03/06/14: Kit Recommendation
    56975: 03/06/20: FPGA device + CPU
    57617: 03/07/03: ARM+FPGA
    156976: 14/08/10: Has anyone forked any Xilinx IP?
    156977: 14/08/10: Re: Has anyone forked any Xilinx IP?
    156993: 14/08/14: Re: Has anyone forked any Xilinx IP?
<sp_mclaugh@yahoo.com>:
    113235: 06/12/08: 50 MSPS ADC with Spartan 3 FPGA - clock issues
    113246: 06/12/08: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
    113249: 06/12/08: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
    113252: 06/12/08: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
    113268: 06/12/09: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
Spaced Cowboy:
    41529: 02/04/01: Laying out the design
    41540: 02/04/01: Re: Laying out the design
<spacegato@gmail.com>:
    121756: 07/07/12: Xilinx PCIe endpoint core minimalistic design
    122310: 07/07/25: Re: Xilinx PCIe endpoint core minimalistic design
spacetimerake:
    149846: 10/11/28: 1653 - At least one timing constraint is impossible to meet
    149853: 10/11/28: Re: 1653 - At least one timing constraint is impossible to meet
    149855: 10/11/29: Re: 1653 - At least one timing constraint is impossible to meet
    149858: 10/11/29: Re: 1653 - At least one timing constraint is impossible to meet
<spacexxspace@yahoo.com>:
    78429: 05/01/31: Any solution for solving setup or hold time violation?
    80610: 05/03/08: Differences among the FPGA development tools.
Spam Hater:
    40843: 02/03/16: Re: FPGA tools and Win2000 - problems
    41130: 02/03/21: Re: Possibility of RTL and Gate-level simulation dont match?
    41200: 02/03/22: Re: Possibility of RTL and Gate-level simulation dont match?
    41260: 02/03/23: Re: Any DDR SDRAM controller stories?
    41460: 02/03/29: Re: strange RAM timing problem (VirtexE)
    41495: 02/03/30: Re: Possibility of RTL and Gate-level simulation dont match?
    41756: 02/04/07: Re: strange RAM timing problem (VirtexE)
    41766: 02/04/07: Re: strange RAM timing problem (VirtexE)
    41996: 02/04/12: Re: DDR SDRAM Controller
    41997: 02/04/12: Re: Need help with Spartan2 and ISA bus interface please.
    42013: 02/04/12: Re: DDR SDRAM Controller
    42097: 02/04/16: Looking for SpartanXL demo board
    42150: 02/04/17: Re: Looking for SpartanXL demo board
    42164: 02/04/17: Re: FPGA Timing Problem
    42212: 02/04/18: Re: Looking for SpartanXL demo board
    42601: 02/04/29: Re: FlexLM
    42957: 02/05/08: Re: DDR reference design
    43047: 02/05/10: Re: DDR reference design
    43596: 02/05/25: Re: SDRAM controler for Virtex-II
    43761: 02/06/01: WTB: Insight SpartanXL Demo board
    43950: 02/06/07: Re: Spartan II Proto. Board
    43993: 02/06/08: Re: opencore PCI bridge versus LogiCORE
    44282: 02/06/16: Re: Xilinx ISE BaseX... What is it?
    44388: 02/06/19: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
    44438: 02/06/20: Re: Xilinx ISE BaseX... What is it?
    44516: 02/06/22: Re: Xilinx ISE BaseX... What is it?
    44517: 02/06/22: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
    44810: 02/07/02: Re: Converting Altera Block Ram to Xilinx Block Ram
    45053: 02/07/11: Re: Altera equivalent for GAL 16V8
    45325: 02/07/19: Re: How's the FPGA design job market near you??
    45356: 02/07/20: Re: How's the FPGA design job market near you??
    45417: 02/07/23: Re: Translate the design from FPGA to Custom IC
    45679: 02/08/01: Re: Name of reset net
    45774: 02/08/05: Re: ATMEL GAL
    45809: 02/08/06: Re: Xilinx hiring practises
    45950: 02/08/12: Re: Synthesis Verilog to ASIC
    45971: 02/08/13: Re: Synthesis Verilog to ASIC
    46458: 02/08/30: Re: SDRAM - is concurrent auto precharge common?
    46481: 02/08/31: Re: SDRAM - is concurrent auto precharge common?
    46637: 02/09/04: Re: why the need for HIGH speed design?
    47243: 02/09/21: Re: designing DDR I/O in CPLD
    47387: 02/09/25: Re: IC layout
    47389: 02/09/25: Re: writing across a column in an SDRAM
    47617: 02/10/01: Re: Search help about architecture of STARTUP?
    47678: 02/10/02: Re: TCP/IP in FPGA
    47882: 02/10/07: Re: Xilinx WebPack ISE 5.1.01i XC9500 Implement problems
    47953: 02/10/08: Re: Cosimulation of VHDL and Verilog Files in ISE?
    48061: 02/10/10: Re: TCP/IP in FPGA
    48110: 02/10/11: Re: Gate array & standard cell based design.
    48149: 02/10/12: Re: How to keep components from being optimized out of VHDL
    48438: 02/10/17: Re: I need your experience, very important for me
    48439: 02/10/17: Re: PCI simulation model, available as open source
    48479: 02/10/18: Re: HELP please! creating FPGA for first time
    48552: 02/10/20: Re: 32-bit PCI Target core
    48623: 02/10/22: Re: 32-bit PCI Target core
    48624: 02/10/22: Re: ISE vs. Foundation
    48769: 02/10/24: Re: ISE vs. Foundation
    48933: 02/10/27: Re: Xilinx FPGA <> CPLD implementation "mis-match"
    49017: 02/10/29: Re: Xilinx FPGA <> CPLD implementation "mis-match"
    49155: 02/11/03: Re: 16-bit FGPA CPU core (commercial)
    49204: 02/11/05: Re: new to fpga, what language is better to start with
    49926: 02/11/26: Re: problems programming/verifying fpga using ISE 5.1
    50056: 02/11/29: Re: SDRAM technology
    50283: 02/12/07: Re: Warnings in FPGA express
    50292: 02/12/08: Re: Warnings in FPGA express
    50373: 02/12/10: Re: Warnings in FPGA express
    50376: 02/12/10: Re: How to assign pins in VHDL?
    50407: 02/12/10: Re: Xilinx ISE 5.1 Wait for statement unsupported??
    50690: 02/12/17: Re: Is it true that if you have a clock routed to non-clock resources then you are not allowed to use the clock nets?
    51104: 03/01/01: Re: Unused FPGA I/O Pins?
    51510: 03/01/15: Re: SChematic design approach compared to VHDL entry approach
    51674: 03/01/18: Re: Schematic design approach compared to VHDL entry approach
    52816: 03/02/23: Re: VHDL & FPGA Design tools
    53256: 03/03/08: Re: PCMCIA to IDE interface
    53257: 03/03/08: Re: Xilinx ISP Header
    53761: 03/03/21: Re: schematics/layouts for basic PCB circuit w/ an FPGA?
    53908: 03/03/27: Re: xilinx/modelsim simulate a subsystem ?
    54261: 03/04/06: Re: Altera not supplying Leonardo any more
    54263: 03/04/06: Re: Xilinx V2.1i Licensing
    54264: 03/04/06: Re: Should I bother with Xilinx Foundation 1.5 vs 2.1?
    54391: 03/04/10: Re: Altera not supplying Leonardo any more
    54821: 03/04/19: Re: Non Volatile FPGA
    54849: 03/04/20: Re: Moving from PAL's to Altera ATF750 Series
    54891: 03/04/21: Re: Xilinx programming (xc9500)
    55287: 03/05/02: Re: IP Core for CAN communication
    55525: 03/05/11: Re: Information about XC9536 ?
    55669: 03/05/15: Re: Can XST takes place of Synplify or FPGA Compiler?
    55671: 03/05/15: Re: Moore Vs Mealy machine ..
    56020: 03/05/27: Re: 2 Questions about VHDL
    56050: 03/05/28: Re: 2 Questions about VHDL
    56207: 03/05/30: Re: 2 Questions about VHDL
    56587: 03/06/10: Re: Xilinx's Device Pin Configuration
    57866: 03/07/08: Re: constraints, etc
    57973: 03/07/11: Re: Spartan XL Prom Selection
    58044: 03/07/13: Re: Wanted: Orcad Capture symbol for Xilinx Spartan IIE XC2S300E PQ208
    58823: 03/08/02: Re: 5 volt tolerant Xilinx parts
    58824: 03/08/02: Re: Ground planes on 4-layer PCB
    58837: 03/08/02: Re: 5 volt tolerant Xilinx parts
Spam Hater 7:
    50930: 02/12/23: Re: serdes
    51492: 03/01/14: Re: SChematic design approach compared to VHDL entry approach
    51632: 03/01/17: Re: Multiple FPGA-boards integration issues
    52699: 03/02/19: Re: Verilog failed,please help
    53382: 03/03/12: Re: FPGA new problems.
    53846: 03/03/25: Re: Permanent Local Damage to FPGA
    53962: 03/03/28: Re: How can I fix module inputs
    57774: 03/07/06: Re: QuartusII software licencing
    59349: 03/08/15: Re: Replacement for Cypress Delta 39K part
    62153: 03/10/20: Re: please help, modelsim does not simulate
<spam@gustad.com>:
    26759: 00/10/27: Re: Fpga vs. ASIC
<spam@oxfordbromley.plus.com>:
    135700: 08/10/13: Re: Complex Event Processing on FPGA
<spamfree.usa1@gov.abuse.net>:
    8033: 97/11/10: Get YOUR free pager, or get PAID to give them away!!!
spammersarevermin:
    94629: 06/01/15: Re: FPGA Journal Article
    96370: 06/02/02: Microblaze question
    96391: 06/02/02: Re: Microblaze question
    96392: 06/02/02: Re: Microblaze question
spanchag:
    68107: 04/03/26: implementing LVDS deserialization using logic
    68395: 04/04/02: Logic required for multiplication
    68450: 04/04/05: Equation to calculate logic required for multipliers
    68452: 04/04/05: Re: Logic required for multiplication
<sparky_chan@ibm.net>:
    16678: 99/06/02: Xilinx XC9500 series product term 3-state (tPTTS) time delays
<sparky_chan@no_spam_ibm.net>:
    16679: 99/06/02: speed optimisation for Xilinx XC9500
spartan:
    79740: 05/02/23: "DSP Dev kit stratix II edition" Vs "ML401 Evaluation platform"
    79819: 05/02/24: NiosII Vs MicroBlaze
Spartan Ray:
    70472: 04/06/17: VHDL code for EPP parallel port with xc2s200-pq208
spartan3wiz:
    113783: 06/12/21: Re: ANN: PicoBlaze C: compile to bitstream!
    113825: 06/12/23: Re: ANN: PicoBlaze C: compile to bitstream!
    115153: 07/02/01: Re: Graphics demo using FPGA?
    115187: 07/02/02: Re: Graphics demo using FPGA?
    115218: 07/02/03: Re: circle generation algorithm
    115257: 07/02/05: Re: Graphics demo using FPGA?
    115637: 07/02/15: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
    116835: 07/03/19: Re: Xilinx ISE support for dual/quad core CPUs?
    119461: 07/05/20: Re: Single Chip MSX computer full schematic and VHDL sources
    119463: 07/05/20: Re: Single Chip MSX computer full schematic and VHDL sources
    119832: 07/05/27: Re: VGA signal through breadboard?
    119834: 07/05/27: Re: 6502 FPGA core
    119840: 07/05/27: Re: 6502 FPGA core
    124818: 07/10/05: Re: XUPV2P from digilentinc
    125374: 07/10/24: Re: LEDs, buttons and LCD
<spartanius@arcor.de>:
    112402: 06/11/21: Spartan 3E-Kit
    112412: 06/11/21: Re: Spartan 3E-Kit
    112453: 06/11/22: Re: Spartan 3E-Kit
    112516: 06/11/23: Re: Spartan 3E-Kit
    112569: 06/11/24: Re: Spartan 3E-Kit
    112572: 06/11/24: Re: Spartan 3E-Kit
Spatel:
    19140: 99/12/01: Free Data Management Software
Specialist Verilog Engineers Roles:
    121169: 07/06/27: VHDL and Verilog - 15 x Contract Engineers Required Urgently - Long Term Contract
spectrallypure:
    114528: 07/01/18: Different Modelsim versions disagree in same backannotation!
    114606: 07/01/20: Re: Different Modelsim versions disagree in same backannotation!
    117331: 07/03/28: Need help with sequential fault simulation in Tetramax!!!
Speed:
    146998: 10/04/08: Debug multiple FPGAs using ChipScope via single JTAG chain
    147045: 10/04/11: Re: Debug multiple FPGAs using ChipScope via single JTAG chain
Speedy:
    30410: 01/04/07: Re: Why FPGA/CPLDs draw a lot current?
    38746: 02/01/24: NTSC/IEEE1394 input to VGA output in FPGA, with overlay
    40215: 02/03/02: Re: Xilinx Virtex Family die photos...
Speedy Zero Two:
    30050: 01/03/21: Yet Another Newbie Question
    30255: 01/03/29: FPGA V CPLD
    30317: 01/04/02: Re: FPGA V CPLD
    30319: 01/04/02: Re: FPGA V CPLD
    31462: 01/05/25: xilinx webpack warning !!
    31535: 01/05/29: Re: xilinx webpack warning !!
    31627: 01/05/31: Xilinx webpack and modelsim
    31658: 01/06/01: Re: Xilinx webpack and modelsim
    31965: 01/06/09: off topic subject
    33365: 01/07/24: Re: Homemade Xilinx parallel cable problem + new question
    33371: 01/07/24: Re: Schematic libraries in webpack ?
    33453: 01/07/26: Re: PQFP sockets
    33480: 01/07/27: Re: Homemade Xilinx parallel cable problem + new question
    33499: 01/07/28: Re: Laid-off worker needs software
    33568: 01/07/30: Re: ERROR
    33569: 01/07/30: Re: Opinions on cypress warp 6.1 and devices?
    33891: 01/08/07: Xilinx + WebPack + Verilog + Pin designation + Help?
    34262: 01/08/17: Xilinx DLL in VirtexE
    34398: 01/08/23: DRAM burst mode
    34413: 01/08/23: Re: DRAM Burst Mode
    34445: 01/08/24: Re: DRAM burst mode
    34455: 01/08/25: Re: DRAM burst mode
    34703: 01/09/04: Re: WebPack Con-Game
    35248: 01/09/27: Re: Gated clocks and shortage of clock buffers
    35386: 01/10/02: Webpack V4 && IBUFG
    35387: 01/10/02: Re: barrel shifter in Xilinx Virtex-E
    35393: 01/10/02: Re: Webpack V4 && IBUFG
    35522: 01/10/09: Re: VHDL code
    35523: 01/10/09: Re: Virtex-2 maximum clock speed
    36233: 01/11/02: Re: 64-bit PCI core for Lattice CPLD?
    36579: 01/11/12: Re: ZX81 production run, is there any interest?
    36840: 01/11/21: Re: slew rate of virtex output buffers figures
    36900: 01/11/23: Re: Creating a jitter free clock
    37354: 01/12/07: Webpack V4 SVF file generation
    37496: 01/12/12: Re: Crosstalk on clocks
    37533: 01/12/13: Re: svf files in webpack 4.2
    37552: 01/12/14: Re: svf files in webpack 4.2
    38562: 02/01/17: Re: CoreGen question
    39582: 02/02/13: Re: Problem with Lattice Design Expert Starter
    41769: 02/04/07: Re: A learner of Modelsim
    41959: 02/04/11: Re: Insight service and PCI demo board question
    42137: 02/04/16: Re: Need Help to Implement Div Operation
    42426: 02/04/23: Re: problem with coding a bidirectional bus simulation
    43716: 02/05/30: Re: Engineering Samples for free?
    45537: 02/07/25: Re: Is the WebPack Constraints Editor evil?
    45702: 02/08/01: PCI Interrupt latency
    47963: 02/10/08: Re: Why can Xilinx sw be as good as Altera's sw?
    47970: 02/10/08: Re: Has anyone noticed that messages posted through Mailgate.org aren't reaching this newsgroup?
    48142: 02/10/11: Re: Simple PCI target core in XILINX Spartan2
    48600: 02/10/21: Re: 6502 core available
    48678: 02/10/22: Re: Webpac Simulation
    49643: 02/11/18: Re: Webpack and Virtex Pro?
    49820: 02/11/21: Re: webpack 5.1 under w2k
    49867: 02/11/22: Re: Simple PCI target core in XILINX Spartan2
Spehro Pefhany:
    22657: 00/05/16: Re: SMT 7 segment display ??
    22672: 00/05/17: Re: SMT 7 segment display ??
    25106: 00/08/25: Re: Non-disclosures in job interviews, Round Two
    32671: 01/07/04: Re: 8031 microcontroller on FPGA development board :-(
    32712: 01/07/05: Re: 8031 microcontroller on FPGA development board :-(
    33387: 01/07/25: Re: In-Circuit Power Supply Verification of Xilinx Chips
    45401: 02/07/22: Re: TMS 1000
    46494: 02/09/01: Re: Thermoelectric Controller by FPGAs
    46513: 02/09/02: Re: Thermoelectric Controller by FPGAs
    53185: 03/03/05: Re: Issues in Outsourcing?
    64401: 04/01/01: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
    65616: 04/02/03: Re: 4 bit divisor with flip-flop ?
    65643: 04/02/04: Re: 4 bit divisor with flip-flop ?
    67546: 04/03/14: Re: ANN: new Pulsonix version 3 PCB software released
    78599: 05/02/03: Re: Exportability of EDA industry from North America?
    78604: 05/02/03: Re: Exportability of EDA industry from North America?
    78613: 05/02/04: Re: Exportability of EDA industry from North America?
    78642: 05/02/04: Re: Exportability of EDA industry from North America?
    78698: 05/02/06: Re: Exportability of EDA industry from North America?
    95055: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95066: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95069: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95124: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95132: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95134: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95146: 06/01/20: Re: OT:Shooting Ourselves in the Foot
    95215: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95237: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95344: 06/01/22: Re: OT:Shooting Ourselves in the Foot
    95399: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95433: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95519: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95520: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    96584: 06/02/07: Re: Verilog 2's Complement Shifter
    97516: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
    99902: 06/03/30: Re: deglitching a clock
    102800: 06/05/21: Re: CPLD (CoolRunner failures)
    102806: 06/05/21: Re: CPLD (CoolRunner failures)
    102898: 06/05/22: Re: CPLD (CoolRunner failures)
    107864: 06/09/01: Re: Performance Appraisals
    107874: 06/09/01: Re: Performance Appraisals
    107984: 06/09/03: Re: Please help me with (insert task here)
    108043: 06/09/04: Re: Please help me with (insert task here)
    112296: 06/11/19: Re: board - T562.jpg
    114331: 07/01/11: Re: inserting text into a video stream (from a pre-existing video source)
    125859: 07/11/07: Re: not totally repulsive
    125909: 07/11/08: Re: not totally repulsive
    125910: 07/11/08: Re: not totally repulsive
    126675: 07/11/29: Re: lossless compression in hardware: what to do in case of uncompressibility?
    130572: 08/03/27: Re: A Challenge for serialized processor design and implementation
    150574: 11/01/26: Re: Xilinx news
    156078: 13/11/22: Re: microZed adventures
    156208: 14/01/17: Re: my first microZed board
SPG:
    21041: 00/03/03: BOOKS ON FPGA
<spgoldman@gmail.com>:
    122235: 07/07/24: Aldec ActiveHDL vs. ModelSim
SpiffyGuy:
    143553: 09/10/15: Softcore for ADSP-2181/2191
    143582: 09/10/16: Re: Softcore for ADSP-2181/2191
Spike:
    67753: 04/03/18: PCI Development Board
    67759: 04/03/18: Re: PCI Development Board
    67765: 04/03/18: Re: PCI Development Board
    67784: 04/03/19: Re: PCI Development Board
    67823: 04/03/19: Re: PCI Development Board
    67837: 04/03/20: Re: PCI Development Board
    67864: 04/03/21: Re: PCI Development Board
    67894: 04/03/22: Re: PCI Development Board
    68006: 04/03/24: Re: PCI Development Board
    68007: 04/03/24: Re: PCI Development Board
    67822: 04/03/19: Re: PCI Development Board
    75004: 04/10/24: SCSI
Spike Technologies:
    15131: 99/03/09: Re: Selt-Timed circuit
    15691: 99/04/08: Career Opportunities
Spiro Egarhos:
    18288: 99/10/12: FPGA Design Job
Spiros Lakkos:
    13614: 98/12/13: Re: Magazine IEEE for FPGA ???
    120606: 07/06/11: Re: adaptive filter FPGA
spman:
    152271: 11/08/01: Pipeline stages of the Multiplier core (ISE Coregen)
    154736: 13/01/01: MIG help (Virtex-6)
<spp@bob.eecs.berkeley.edu>:
    6414: 97/05/22: Re: Cadence or World Technology, or other NT vendors...
    6434: 97/05/23: Re: Cheap way to develop for FPGAs?
    6877: 97/07/05: Re: Altera archiving
    7297: 97/08/22: Re: MaxPlusII from Altera.
    7301: 97/08/22: Re: MaxPlusII from Altera.
    7459: 97/09/13: Re: Cheap (sub $10) hardwired FPGA? Which manufacturers?
    7460: 97/09/13: Re: SYNC RAM in XCilinx/Altera...
    7497: 97/09/17: Re: 6809 in FPGA?
    8223: 97/11/30: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
    13569: 98/12/10: Re: Verilog/FPGA Express Synth Problem
    22369: 00/05/06: Re: Q: simplest FPGA structure for novel technology demonstration
    27716: 00/12/04: Re: ANNOUNCE: Checksum and CRC Code/Article
spr:
    67883: 04/03/22: Re: JAM and Xilinx/Altera CPLDs
    70066: 04/06/01: Re: Malfunctioning dual port block ram.
SPR Inc.:
    13478: 98/12/04: ASIC Project
    13537: 98/12/08: Anyone Heard of GOVJOBS.COM
spring:
    58397: 03/07/22: Internal Error again in Quartus II 3.0
springzzz@gmail.com:
    89841: 05/09/28: a ISE installation problem on linux
    89887: 05/09/29: Re: a ISE installation problem on linux
sprocket:
    131116: 08/04/11: Re: Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE
Sprow:
    20193: 00/01/31: Re: ARM core?
    20711: 00/02/18: Re: clock
    21255: 00/03/14: Where've Xilinx hidden it then?
sps:
    84180: 05/05/13: Re: Tristate-Master-Slave testbench description
    85668: 05/06/13: Adding Verilog processing core to Viretx2Pro at ML310
    85768: 05/06/15: Re: Adding Verilog processing core to Viretx2Pro at ML310
    86480: 05/06/28: Soft core for MPEG codec
<spygame81@gmail.com>:
    126395: 07/11/20: An error occured while using Dual Port Block Memory
spyng:
    25806: 00/09/21: Re: VHDL to SCHEMATIC
    31805: 01/06/06: auto increment register
    34071: 01/08/13: virtex2 Block Ram: dual port ram with different da
    34075: 01/08/13: Re: virtex2 Block Ram: dual port ram with different da
    34098: 01/08/14: Re: virtex2 Block Ram: dual port ram with different da
    38748: 02/01/23: Re: Simple shift register not working
    41341: 02/03/26: how to prevent infer of Mult18x18 in VirtexII
    41436: 02/03/28: Re: how to prevent infer of Mult18x18 in VirtexII
    41470: 02/03/29: Re: how to prevent infer of Mult18x18 in VirtexII
    42619: 02/04/29: un-constraint path - from Clock pad to FFS clock pin
    42654: 02/04/30: Re: un-constraint path - from Clock pad to FFS clock pin
    42786: 02/05/02: Re: Vertex 2 IOB- unwanted flops inside
    44591: 02/06/24: skew control between different signals ?
    44672: 02/06/26: Re: skew control between different signals ?
    44704: 02/06/27: Re: skew control between different signals ?
    46440: 02/08/29: sustainable rate for Random Read of DDR SDRAM
    56112: 03/05/28: need help on sending 500Mbit/s data through 100 feet of cable, Giga-Ethernet?
    56208: 03/05/30: Re: need help on sending 500Mbit/s data through 100 feet of cable, Giga-Ethernet?
    56209: 03/05/30: Re: need help on sending 500Mbit/s data through 100 feet of cable, Giga-Ethernet?
    56632: 03/06/10: Re: DVI with a Virtex-II
<spyng@my-deja.com>:
    21566: 00/03/25: Clock on non-dedicate pin
    21622: 00/03/27: Re: Clock on non-dedicate pin
    21650: 00/03/28: Re: Clock on non-dedicate pin
    21692: 00/03/29: Re: Clock on non-dedicate pin
    21719: 00/03/30: Re: Global clock nets. Can I use it for signal other than clock.
    21779: 00/03/31: physical macro (Xilinx)
Spyros Lyberis:
    67638: 04/03/16: Logiclock TCL flow for Quartus II
    67738: 04/03/18: Re: Logiclock TCL flow for Quartus II
    67781: 04/03/18: Re: Logiclock TCL flow for Quartus II
    67789: 04/03/19: Re: Logiclock TCL flow for Quartus II
    67943: 04/03/23: Re: Logiclock TCL flow for Quartus II
    67944: 04/03/23: Re: Logiclock TCL flow for Quartus II
    68174: 04/03/28: Re: Logiclock TCL flow for Quartus II
    69446: 04/05/11: Logiclock TCL flow -- near completion
Squidge:
    84827: 05/05/29: Re: beginer
Squirrel:
    71339: 04/07/15: Re: FPGAs starting with incorrect bitstream !?
    72955: 04/09/09: Re: PCI Noise
    73377: 04/09/21: Re: Modelsim wave viewing in batch mode
    111681: 06/11/08: Re: Chip to Chip LVDS
    115290: 07/02/06: Re: Is Digilent still in business ???
Sramana Mitra:
    42939: 02/05/07: MIT Entrepreneurship Panel - EDA and Beyond: Funding and Industry Trends
<sramsden@my-deja.com>:
    21638: 00/03/27: Digital Filters
    21661: 00/03/28: Digital Filters - Help me!!
sree:
    63469: 03/11/21: Generating core using .mif file
    67248: 04/03/09: sorting need help as soon as possible
    67876: 04/03/21: cpu and linux on a fpga (new to FPGAs)
sreedevi1988:
    143138: 09/09/23: Problem with using write and write function
    143263: 09/09/28: Re: Problem with using write and write function
Sreedhar Sampath:
    22103: 00/04/23: CLKDLL
    22728: 00/05/19: Processor
    23899: 00/07/14: Timing Analysis
Sreejit Chakravarty:
    715: 95/02/15: Advance Program 5th Great Lakes Symposium on VLSI
sreekanth:
    148606: 10/08/05: Re: DMA operation to 64-bits PC platform (continued)
<sreenivas.jyothi@gmail.com>:
    134610: 08/08/20: ADC7874 Timing violations
    134677: 08/08/25: Verification methods importance
    136937: 08/12/14: Duty Cycle change effects on Internal reg's
    136939: 08/12/14: clock reducing leads what
    137416: 09/01/14: Re: Duty Cycle change effects on Internal reg's
sri:
    85339: 05/06/07: Atmel CPLD development tools for verilog
    86134: 05/06/22: Setting ucf for DLLs:Urgent
Sri Saripalle:
    12092: 98/09/28: Re: ASIC -> FPGA async issues
    12093: 98/09/28: Re: US ASIC jobs+work visa
    12094: 98/09/28: Re: Announcement: 200.000 Gates FPGA Prototyping Board
    12346: 98/10/09: Re: clock divider chips
    12455: 98/10/12: Re: I2C Core
sridar:
    149623: 10/11/12: Design chaos
    149651: 10/11/13: Re: Design chaos
Sridhar Hegde:
    73143: 04/09/14: Synthesis issues in Modelsim 5,7g SE for a simple ROM
    73261: 04/09/16: Re: Synthesis issues in Modelsim 5,7g SE for a simple ROM
    73262: 04/09/16: Re: Synthesis issues in Modelsim 5,7g SE for a simple ROM
Srikanth Anumalla:
    60415: 03/09/12: Newbie
    60504: 03/09/15: fpga +cpu + wireless
    60551: 03/09/16: Re: fpga +cpu + wireless
    60572: 03/09/16: Re: fpga +cpu + wireless
    60615: 03/09/17: Re: fpga +cpu + wireless
    68144: 04/03/27: rs232 interface on nios
    70090: 04/06/02: FPGA + A/D converter
Srikanth BJ:
    103277: 06/05/30: generating IP cores
    103278: 06/05/30: generating IP cores
    103288: 06/05/30: Re: generating IP cores
    103566: 06/06/06: Efficient implementation of Address Decoding logic
    103622: 06/06/06: Re: Efficient implementation of Address Decoding logic
    103680: 06/06/07: Re: Efficient implementation of Address Decoding logic
    104410: 06/06/26: Xilinx 7.1 ISE : Problem while doing post place and route simulation
    106307: 06/08/11: consistancy in synthesis/ simulation model
    106480: 06/08/14: Re: consistancy in synthesis/ simulation model
Srikanth Gurrapu:
    8673: 98/01/19: Xilinx Info.
    8672: 98/01/19: Xilinx Info.
    8674: 98/01/19: FPGA Info.
    8735: 98/01/22: ALtera Devices.
    11605: 98/08/26: Re: FPGA vendors
    12219: 98/10/05: Re: Maxplus2 Timing Analyzer
    18715: 99/11/09: Sample Rate Conversion.
srikanth srikanth:
    146377: 10/03/15: Memory Blocks in Arria II GX Devices - mixed port read during write
srikanth.b:
    17608: 99/08/13: Re: Philips Semiconductors (NL) seeks digital designers
srikanthv2:
    138529: 09/02/25: Send data from FPGA to PC via USB
sriley:
    21976: 00/04/10: creating a bit stream
    23502: 00/06/28: digital phase lock loop
    23525: 00/06/28: Re: digital phase lock loop
    23526: 00/06/28: Re: digital phase lock loop
    23813: 00/07/10: phase lock different frequencies
    24320: 00/08/03: Re: End of my rope.
    24312: 00/08/03: Re: foundation 2.1i problems
    26597: 00/10/21: foundation 3.1 crash
    26600: 00/10/21: reusing macros in F3.1i
sriman:
    122526: 07/07/30: Help on TRB_DC2 Camera module interface
    122527: 07/07/30: Help on TRB_DC2 Camera module interface
    122538: 07/07/30: Re: Help on TRB_DC2 Camera module interface
    122575: 07/07/31: regarding RTOS in NIOS II
    122617: 07/08/01: help on basics of ethernet interface
    122686: 07/08/03: camera module interface to FPGA
    122747: 07/08/05: DSP design into FPGA
    123176: 07/08/18: help on camera ports
    123240: 07/08/21: help on how to assign data to the function of nios program
    123257: 07/08/21: help to sort out the errors
    123338: 07/08/24: Re: help to sort out the errors
    128339: 08/01/22: Matlab code in nios processor
    129658: 08/03/02: clock generation
srinas:
    35980: 01/10/25: 2/3 trellis code in vhdl
    36531: 01/11/11: Interleaver and Reed Solomon Encoder example
srini:
    58300: 03/07/19: looking for SystemC cores
    100910: 06/04/20: How to trsiate o/p pins?
    102133: 06/05/10: Xilinx warning for DCM
    102168: 06/05/11: Synplify - Not satisfactory results with re-timing option
    102228: 06/05/12: Re: Synplify - Not satisfactory results with re-timing option
    102230: 06/05/12: How to check IOB register packing?
    102241: 06/05/12: How to decide Fanout limit?
    102246: 06/05/12: Re: How to check IOB register packing?
    102283: 06/05/13: Re: How to check IOB register packing?
    102284: 06/05/14: Re: How to decide Fanout limit?
    102305: 06/05/14: Re: How to decide Fanout limit?
    102306: 06/05/14: Re: How to check IOB register packing?
    102311: 06/05/14: How to decide Setup/Hold time values ?
    102419: 06/05/15: Synplify Pro warning - cudnt understand
    103148: 06/05/26: DCM lock - require clarification
    103266: 06/05/30: Re: COREGEN: DCM
    104698: 06/07/04: ASCI to FPGA - require details
    104714: 06/07/04: Re: ASCI to FPGA - require details
Srini:
    115249: 07/02/05: DFT Details....
Srini Krishnamoorthy:
    52430: 03/02/09: RTL area/delay estimation
Srinivas:
    48952: 02/10/28: Re: High Performance FPGA's - Xilinx and ??????
    75080: 04/10/26: Re: interfacing a PC based program with a FPGA
    74898: 04/10/21: interfacing a PC based program with a FPGA
Srinivasan Venkataramanan:
    19738: 00/01/10: Re: timing diagrams
    20320: 00/02/04: Re: Conditional compilation in VHDL?
    23697: 00/07/05: Re: VHDL code for LFSR
    24775: 00/08/18: Re: Accessing internal signals and ports for writing to a file using testbench
    26791: 00/10/29: Re: help on a simple ALU
    27517: 00/11/27: Re: how do i?
    27687: 00/12/03: Re: glbl
    27756: 00/12/06: Re: what's meaning?
    27948: 00/12/16: Re: Verilog or VHDL
    27955: 00/12/17: Re: Verilog or VHDL
    28179: 00/12/24: Re: Verilog or VHDL
    29746: 01/03/07: Re: Netlis : Webpack Vs Foundation
    29747: 01/03/07: Re: ROM-based FSM implementation
    29902: 01/03/16: Re: Passing text strings to procedures in VHDL
    30263: 01/03/30: Re: VHDL Test bench
    30334: 01/04/03: Re: some info. on FPGA
    30475: 01/04/10: Re: free software
    30996: 01/05/08: Re: SYnopsys Library Compiler and LUT synthesis
    31080: 01/05/11: Re: Waveforms painting
    31233: 01/05/16: Re: Fine phase shift in Virtex2
    31745: 01/06/05: Re: Virtex LUT4 problems in FPGA Express
    32132: 01/06/15: Re: Fpga tutorial
    32171: 01/06/18: Re: Teramac FPGA mapping for Pentium
    32196: 01/06/19: Re: ee
    32201: 01/06/19: Re: ee
    32598: 01/07/02: Re: obfuscated tools
    33030: 01/07/15: Re: FPGA Express search path
    33345: 01/07/24: Re: Silo-3 Demo Program Crashes onDell 4100
    33378: 01/07/25: Re: Silo-3 Demo Program Crashes onDell 4100
    33425: 01/07/26: Re: Silo-3 Demo Program Crashes onDell 4100
    33540: 01/07/30: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
    33582: 01/07/31: Re: Webpack Tutorials
    33668: 01/08/02: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
    33908: 01/08/08: Re: Looking for a Particular Used Book
    34728: 01/09/05: Re: Interfacing Verilog and VHDL
    34747: 01/09/06: Re: Interfacing Verilog and VHDL
    34748: 01/09/06: Re: Model sim vhdl simulation crash
    34782: 01/09/07: Re: Interfacing Verilog and VHDL
    34843: 01/09/11: Re: Give me some information!
    34896: 01/09/13: Re: convert
    35212: 01/09/26: Re: Handle C
    35871: 01/10/22: Re: FPGA based IPv6 router -- hi
    35962: 01/10/25: Re: Recommend a book
    35976: 01/10/25: Re: Recommend a book
    36406: 01/11/08: Re: VHDL testbench question
    36446: 01/11/09: Re: Maxplus error
    36604: 01/11/13: Re: Incrementing counter from state-machine
    36991: 01/11/28: Re: Alliance
    37041: 01/11/29: Re: Help needed in choosing the right PC for VLSI EDA
    37938: 01/12/26: Re: Where could I get a signal waveform editor?
    37954: 01/12/27: Signal Spy feature available for NC VHDL - Thanks to Martyn, Cadence
    37289: 01/12/06: using UNIX Environment variables in "ncvlog -file option" - Help!
    39017: 02/01/30: Re: random
    39345: 02/02/07: Re: Announce: VHDL Simili 2.0 - Graphics, Windows, Linux, Affordable
    39349: 02/02/07: Looking for Free EDIF/Verilog netlist - Schematic Viewer
    39745: 02/02/18: Re: Book Recommendation for Designing Complex System using HDL.
    40878: 02/03/17: Re: Looking for EBook?
    45297: 02/07/18: Re: Good VHDL Book...
    45301: 02/07/18: Re: Problem with OpenCore PCI IP Core
    49884: 02/11/23: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
    69526: 04/05/13: Re: Instantiating subblock signals with VHDL
Srinu:
    108363: 06/09/08: Can a FPGA work like a microprocessor ?
    115345: 07/02/07: Parallelism in HDL
Sriram:
    53941: 03/03/27: XILINX FPGA as SUN Sparc coprocessor
    54309: 03/04/07: VCC's HOT 2 development board
    54522: 03/04/12: Re: VCC's HOT 2 development board
    56035: 03/05/27: Dynamic Reconfiguration of arithmetic units
    58600: 03/07/28: Partial Reconfiguration support for Spartan 2 or Spartan 2E devices
    59084: 03/08/07: Post synthesis(PAR) Simln in Xilinx WEbPack 5.2: Port Mismatch error
    61773: 03/10/10: VCC's HOTman
    61829: 03/10/13: Re: VCC's HOTman
    62433: 03/10/29: Fatal Error obtained while translating in xilinx ISE 5.2
Sriram S:
    34658: 01/09/02: Clock Multiplication
    34718: 01/09/05: Re: Clock Multiplication
    35490: 01/10/07: VIRTEX-II PCIX CORE
SRIRAM SRINIVASAN:
    7750: 97/10/10: HELP: FPGA, MGA, Std. Cell Break-even analysis
Sriraman:
    77134: 04/12/24: Re: XST Question
Srisurya Konduri:
    58289: 03/07/19: CPLD Interface to PC's requirements
    58299: 03/07/19: Re: CPLD Interface to PC's requirements
    59621: 03/08/25: Xilinx Webpack 5.2i tutorial
<srivasta@cobaf.unt.edu>:
    2278: 95/11/16: Tape
sruthi:
    74210: 04/10/06: CAche memory
    74211: 04/10/06: Re: CAche memory
SS:
    95326: 06/01/22: Re: OT:Shooting Ourselves in the Foot
    98373: 06/03/08: XST issue / Answer record does not help
Ssa:
    122043: 07/07/17: How do I use Lattice Mico32's debug-engine on a non-Lattice FPGA?
ssaleem:
    68888: 04/04/21: Partial Reconfiguration
<ssimpson@hertreg.ac.uk>:
    13039: 98/11/12: Re: DES in VHDL?
ssirowy@gmail.com:
    92138: 05/11/22: Microblaze and custom peripherals
    92155: 05/11/23: Re: Microblaze and custom peripherals
    92189: 05/11/23: Re: Microblaze and custom peripherals
    92200: 05/11/23: Re: Microblaze and custom peripherals
    100523: 06/04/10: Area Constraints in Xilinx
    100554: 06/04/11: State Machine and Area Estimate Question
    100573: 06/04/12: Re: State Machine and Area Estimate Question
    138087: 09/02/05: Xilinx Powerpc issue with custom peripherals
sssrrr:
    95075: 06/01/20: Reading user data from PROM
    95292: 06/01/21: Re: Reading user data from PROM
ssy:
    36748: 01/11/19: how to limit the fanout in APEX20K400E
    36780: 01/11/19: Re: Synopsys+Xilinx vs Synplicity
    36781: 01/11/19: Re: modelsim: free, evaluation or full !?
    36782: 01/11/19: how to imply CAM in APEX20K
    36783: 01/11/19: Re: Does anybody knows where have a free(open hardware) FPGA PCI Development board whith PCB data.....?
    36784: 01/11/19: what is the price of XC2V2000?
    36848: 01/11/21: too large a 32 entry 3 read 2 write register file
    36859: 01/11/22: how to imply tristate buffer in APEX20K
    36903: 01/11/23: an unespected clock
    36909: 01/11/24: Why "Can't scan device chains in APEX20K400E SOPC board from Altera"?
    36915: 01/11/25: an error of quartus
    37055: 01/11/29: the timing of LPM_RAM_DP
    37139: 01/11/30: quartus do not support parameter value assignment in module instantation
    37694: 01/12/18: the effect of syn_maxfan
    37824: 01/12/20: how to group a critical path into a most small area
    37899: 01/12/23: where can I find a indepth manual about place and route in Quartus II
    38114: 02/01/05: Q:where can I find an indepth manual about P&R in Quartus II ?
    38122: 02/01/06: Re: Q:where can I find an indepth manual about P&R in Quartus II ?
    38144: 02/01/06: Re: WARNING
    38263: 02/01/10: Q:Hand placed fast 32 bit barrel shifter for APEX?
    38306: 02/01/11: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
    38351: 02/01/11: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
    38375: 02/01/12: the timng of the lpm_fifo
    38686: 02/01/21: Q: can ROM content affect logic syn result
    38752: 02/01/24: Re: Q: can ROM content affect logic syn result
    39077: 02/01/31: the cause of the simulation/synthesis mismatch
    39086: 02/01/31: the post synthesis simulation problem
    39404: 02/02/08: the problem of post simulation
    39405: 02/02/08: Re: the cause of the simulation/synthesis mismatch
    40295: 02/03/04: convert_hex2ver can not generate the *.ver file
    40360: 02/03/05: possible problem of asyn read of block ram in apex 20k device
    40431: 02/03/06: high active and low active reset signal mixed in a design
    40440: 02/03/07: Re: high active and low active reset signal mixed in a design
    40504: 02/03/08: a simulation question about apex20ke_asynch_lcell
    40505: 02/03/08: Re: high active and low active reset signal mixed in a design
    41028: 02/03/19: how to deal with signal pass through two clock domain
    41099: 02/03/20: Re: how to deal with signal pass through two clock domain
    41114: 02/03/20: Re: how to deal with signal pass through two clock domain
    41878: 02/04/09: Re: Low-cost FPGA + processor board?
    41884: 02/04/10: Re: Low-cost FPGA + processor board?
    42559: 02/04/27: synplicity 6.2.4 can not recongnize "altera_implement_in_esb" directive
    44618: 02/06/24: too hot fpga device
    44654: 02/06/25: Re: too hot fpga device
    45029: 02/07/10: How to locate the combinational loop in RTL source
    45062: 02/07/11: Re: How to locate the combinational loop in RTL source
    45063: 02/07/11: Re: FPGA/CPLD Decision help?
    45136: 02/07/13: Re: FPGA CPU?
    49169: 02/11/03: read and write same address of the ESB memory in the same cycle
ssylee:
    134904: 08/09/05: Reviewing Equation information on Altera Quartus II version 8
st:
    70995: 04/07/05: Re: crc32 vhdl implementation (4 bit data)
St.Peter:
    6087: 97/04/11: Re: About the usage of Altera maxplus2
    6088: 97/04/11: Re: Pentium Pro Worth it for Altera Max Plus?
stabilization:
    27351: 00/11/19: help
Stacey:
    53480: 03/03/13: Re: AMD Temp Specs
Stacey Secatch:
    78271: 05/01/27: Re: Synopsys Designware and FPGA mapping
Stacey Son:
    3996: 96/08/30: Re: DES in Xilinx
STAFFING:
Staffing:
Stamatis Sotiropoulos:
    47122: 02/09/18: State of FPGA I/O pins before programming
    52650: 03/02/18: PCB Design for a Xilinx Spartan-II FPGA
    52684: 03/02/19: Re: PCB Design for a Xilinx Spartan-II FPGA
    52932: 03/02/26: Spartan II PCB, I/O pins consederations
    53070: 03/03/03: Re: Spartan II PCB, bypass Capacitors
    53576: 03/03/17: FPGA based PCB
    53589: 03/03/17: PROM for SpartanII Configuration
    54093: 03/04/02: Multilinx Cable
    54328: 03/04/08: Power Supply for Spartan II FPGA
    54340: 03/04/08: Re: Power Supply for Spartan II FPGA
Stan:
    45716: 02/08/02: Re: spiral / waterfall /watersluice : Which are your methods?
    45717: 02/08/02: Re: Translate the design from FPGA to Custom IC
    46537: 02/09/02: Re: synthesizing hard coded numbers
    46538: 02/09/02: Re: high-speed design rule on FPGAs?
    46584: 02/09/04: Re: C/C++ to Verilog/VHDL ?!
    46586: 02/09/04: Re: C/C++ to Verilog/VHDL ?!
    46587: 02/09/04: Re: synthesizing hard coded numbers
    46922: 02/09/12: Re: scan insertion is easily feasible
    47983: 02/10/09: Re: Xilinx XST VHDL Compiler does not pack Registers in IOB
    48247: 02/10/15: Re: A nice one-off project for a competent UK based FPGA designer :)
    49403: 02/11/12: Re: HDL vs RTL
    49404: 02/11/12: Re: Associative memory and multiport memories
    49405: 02/11/12: Re: functional test for Xilinx virtex II Pro
    49406: 02/11/12: Re: functional test for Xilinx virtex II Pro
    49407: 02/11/12: Re: LU-decomposition
    49408: 02/11/12: Re: LU-decomposition
    49409: 02/11/12: Re: LU-decomposition
    49410: 02/11/12: Re: LU-decomposition
    49470: 02/11/13: Re: HDL vs RTL
    49475: 02/11/13: Re: Feedback from a 200 MHz Virtex2 design
    49521: 02/11/14: Re: Registering inputs or outputs of modules
    49522: 02/11/14: Re: creating a fabric in an FPGA
    49556: 02/11/15: Re: LU-decomposition
    49673: 02/11/19: Re: Are block RAMs supported in simulation?
    49725: 02/11/20: Re: how to use carry chain in Virtexe
    49776: 02/11/21: Re: how to use carry chain in Virtexe
    49841: 02/11/22: Re: exp^x in virtex 2
    60667: 03/09/19: Re: hardware image processing - log computation
stan:
    63292: 03/11/19: State Machines....
    64550: 04/01/07: Xilinx Question
Stan Baker:
    4328: 96/10/16: WinEDA Plenary Session
    4329: 96/10/16: Conference Sessions Open at WinEDA
    7179: 97/08/11: VSI Meeting Notice
    7363: 97/09/02: A Year of Achievement Meeting
    7388: 97/09/05: VSI Specs Posted for Review
    7607: 97/09/26: VSI Conference
    9212: 98/03/02: VSI Meeting
    11805: 98/09/10: VSIA Member Meeting
    12064: 98/09/26: Keynote, Sangiovanni-Vincentelli
    15423: 99/03/23: Virtual Socket meeting
    17651: 99/08/18: VSIA SoC Forum&Meeting
Stan Eker:
    386: 94/11/04: Re: about downloading FPGAs
    406: 94/11/09: Re: about downloading FPGAs
    423: 94/11/14: Re: Sources for FGPA's and "exotic" PLDs?
    564: 95/01/05: Re: Xilinx and Protel for Windows?
    641: 95/01/26: Re: Xilinx Chips
    763: 95/02/25: Xilinx is releasing a cheap version!
    829: 95/03/09: goof on cheaper Xilinx price ($1K US, not $100)
    867: 95/03/17: Re: Protel now connects to Xilinx
    1398: 95/06/15: Re: HELP on programming XC3090A
    2006: 95/10/01: Re: Xilinx Flash FPGA ??
    2257: 95/11/11: Re: FPGAs as a substitute for glue logic?
    5343: 97/02/09: Re: Suggestions how wire wrap mount a Xilinx PG223
Stan Hodge:
    1163: 95/05/08: Re: How to choose an FPGA vendor
    2188: 95/10/28: AT&T vs. Xilinx
    3082: 96/03/27: PCI Support...
    4241: 96/10/03: Re: Q on Xilinx/Viewsim macros
    4798: 96/12/16: Experience with Altera 10K Family
Stan Lackey:
    50807: 02/12/19: Re: 16-bit LFSR
    50809: 02/12/19: Re: Multi cycle Paths..
    51158: 03/01/04: Re: Latch edge sensitive on data & RESET
    53329: 03/03/10: Re: State of the PCB world
    53691: 03/03/20: Re: write a single byte in to DRAM
    53832: 03/03/25: Re: Latch inferring : Async OR Sync ?
    54123: 03/04/02: Re: Excel and FPGA's
    54395: 03/04/10: Re: Force a rising edge of clk
    56368: 03/06/03: Re: For Loop Synthesis
    58509: 03/07/25: Re: FIFO Controller
    58510: 03/07/25: Re: FIFO Controller
    58511: 03/07/25: Re: FIFO Controller
    61331: 03/10/01: Re: Good VHDL/Verilog editor?
    70539: 04/06/19: Re: scatter gather DMA in OPB MAC core
    70771: 04/06/27: Re: Divided by 11 in VHDL
    73394: 04/09/21: Re: Need assistance with an FPGA based project.
Stan Ng:
    12516: 98/10/14: Re: Schematic entry?
Stan Pawlukiewicz:
    87915: 05/08/03: Re: System Engineering in the R/D World
Stan Ramsden:
    21035: 00/03/03: EDA tools
    21051: 00/03/04: Long Island Consultant Available
    21167: 00/03/08: Re: Quick questions for Xilinx tools
    25361: 00/09/08: ORCAD Xilin GSR
    29359: 01/02/16: Xilinx XC18v04 programming via FPGA
    30824: 01/04/30: FPGA : JTAG emulation in FPGA
    31032: 01/05/09: Xilinx : 1553 interface
Stan Zaborowski:
    53983: 03/03/29: Re: More xilinx webpack verilog questions: always @(clock) legal?
<stang99@my-deja.com>:
    20941: 00/02/29: Book recommendations?
stanIam:
    108786: 06/09/16: old computer architecture book
stanislav shalunov:
    20720: 00/02/19: Re: protocol implementations
Stanley:
    83398: 05/04/28: How to implement this C function in FPGA
    83407: 05/04/29: Re: How to implement this C function in FPGA
Stanley Chow:
    5359: 97/02/10: Re: DES Challenge
    8369: 97/12/10: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
    11533: 98/08/21: Re: vector product minimization problem
Stanley Lee:
    104735: 06/07/05: Re: Can I use all 18bits of a BlockRAM?
    104859: 06/07/07: The difference betweeen SLICEM and SLICEL
    104861: 06/07/07: Re: stable reset in fpga
    104921: 06/07/09: The FFs with synchronous reset perform worse?
    104924: 06/07/09: Re: The FFs with synchronous reset perform worse?
StanleyLee:
    104647: 06/07/03: Re: Synthesis changes after ISE upgrade
    104653: 06/07/03: Re: stable reset in fpga
    104676: 06/07/03: Re: stable reset in fpga
    104729: 06/07/05: Can I use all 18bits of a BlockRAM?
starbugs:
    90695: 05/10/19: How to speed up the critical path (Xilinx)
    90696: 05/10/19: Re: How to speed up the critical path (Xilinx)
starfire:
    71622: 04/07/25: 1GHz FPGA counters
    71628: 04/07/25: Re: 1GHz FPGA counters
    75616: 04/11/10: Re: Xilinx Tshirts in football package.....
    76093: 04/11/24: better choice for high-speed, multi-clock FPGA?
    77503: 05/01/08: weird problem printing Xilinx state machine
    82286: 05/04/10: edk annual renewal cost?
    82703: 05/04/16: Re: Hobby or job? (FPGA User's groups anyone?)
    82747: 05/04/17: Re: Spartan 3E slower that Spartan 3?
    85400: 05/06/08: anyone tried the Actel ProASIC3 Starter Kit?
    85422: 05/06/09: Re: anyone tried the Actel ProASIC3 Starter Kit?
Stargazer:
    24735: 00/08/17: Re: Non-disclosures in job interviews
    24739: 00/08/17: Re: Non-disclosures in job interviews
    24741: 00/08/17: Re: Non-disclosures in job interviews, Round One
starpanda:
    39253: 02/02/05: Core generator Asynchronous FIFO
    39758: 02/02/19: Maximum # of logic level
    39911: 02/02/21: cross clock domain signals
Starry Hung:
    3493: 96/06/10: Wanted: HDL CD-ROM DECODER
    24303: 00/08/03: Re: GPIO board for Avnet Virtex Development system ?
    24500: 00/08/11: Comparing Xilinx FPGAs
    24710: 00/08/17: Board suggestion for high gate count FPGA board
statepenn99:
    79700: 05/02/23: Frustrated with Altera
    79701: 05/02/23: Re: what's the difference between syn FIFO and asyn FIFO?
    79735: 05/02/23: Re: Frustrated with Altera
    79758: 05/02/23: Re: Frustrated with Altera
    79759: 05/02/23: Re: Memory Controller Operation
    79761: 05/02/23: Re: Hardcopy Vs ASIC
    79834: 05/02/24: Re: Hardcopy Vs ASIC
<staylor@dspsystems.com>:
    9701: 98/03/31: Re: XactStep6 - The cure for a dongle
    9722: 98/04/01: Re: XactStep6 - The cure for a dongle
    9757: 98/04/03: Re: XactStep6 - The cure for a dongle
    9769: 98/04/04: Re: XactStep6 - The cure for a dongle
    9835: 98/04/08: Re: XactStep6 - The cure for a dongle
    9854: 98/04/09: Re: XactStep6 - The cure for a dongle
    9855: 98/04/09: Re: XactStep6 - The cure for a dongle
    9856: 98/04/09: Re: XactStep6 - The cure for a dongle
    9871: 98/04/09: Re: XactStep6 - The cure for a dongle
    9886: 98/04/10: Re: XactStep6 - The cure for a dongle
    9891: 98/04/11: Re: XactStep6 - The cure for a dongle
    9794: 98/04/05: Re: One time programmables
    9821: 98/04/07: Re: Effects of IC production
    9870: 98/04/09: Re: max7000
    9878: 98/04/10: Re: Investigate anyone right from your browser!
    9892: 98/04/11: Re: Event counting?
    9912: 98/04/13: Re: FLEX 10K : FPGA or CPLD
    9920: 98/04/13: Re: VHDL compiler differences ?
    9929: 98/04/14: Re: Event counting?
    10022: 98/04/22: Re: Could you help me save CLB's?
    10047: 98/04/23: Re: Could you help me save CLB's?
    10092: 98/04/27: Re: Could you help me save CLB's?
    10093: 98/04/27: Re: Make a delay in Xilinx FPGAs (more Details)?
    10105: 98/04/27: Re: Make a delay in Xilinx FPGAs (more Details)?
    10106: 98/04/27: Re: FPGA pin assignment for I/O
    10115: 98/04/28: Re: Enforcing Clock Enable Connection in Synthesis
    10121: 98/04/28: Re: Make a delay in Xilinx FPGAs (more Details)?
    10122: 98/04/28: Re: FPGA input data rate limitations?
    10123: 98/04/28: Re: Enforcing Clock Enable Connection in Synthesis
    10135: 98/04/29: Re: FPGA input data rate limitations?
    10147: 98/04/29: Re: Enforcing Clock Enable Connection in Synthesis
    10148: 98/04/29: Re: Enforcing Clock Enable Connection in Synthesis
    10163: 98/04/30: Re: Enforcing Clock Enable Connection in Synthesis
    10164: 98/04/30: Re: Enforcing Clock Enable Connection in Synthesis
    10208: 98/05/04: Re: Make a delay in Altera
    10248: 98/05/06: Re: Cool Clock Enable Synthesis Fix
    10272: 98/05/08: Re: Altera relative placement
stbcasa:
    86772: 05/07/06: Spartan II 2s200 PCI Board
    87384: 05/07/22: Place Error
    89661: 05/09/21: Xilinx Webpack Schematic
<stchebel@gmail.com>:
    156802: 14/07/01: FT2232H synchronuous FIFO mode problem.
<1stderivative@gmail.com>:
    136217: 08/11/06: face recognition
    136345: 08/11/12: Bluespec
    140142: 09/04/30: FPGA simulator for face recognition
    140148: 09/04/30: Re: FPGA simulator for face recognition
Ste:
    35535: 01/10/09: Re: Help reading from SmartMedia cards
    69909: 04/05/24: How to convert a pattern to SVF
    144530: 09/12/13: Re: Nintendo DS Screenshots / Video Capture
    144564: 09/12/14: Best "bang for buck" Student Starter board for image/video processing?
    151077: 11/03/03: Video Framebuffer using Nexys2 (Spartan-3E)
    151175: 11/03/14: Re: Video Framebuffer using Nexys2 (Spartan-3E)
    151323: 11/03/23: Re: Video Framebuffer using Nexys2 (Spartan-3E)
Stebanoid:
    151455: 11/04/11: Virtex-5 GTP with oversampling
    151486: 11/04/12: Re: Virtex-5 GTP with oversampling
Stece Lutz:
    31706: 01/06/03: ASIC-FPGA job in USA
<stee8033@bureau.ucc.ie>:
    51: 94/08/04: Field Programmable Interconnect
Steele Chen:
    19956: 00/01/20: which PLD support Hot-swap
Steen:
    34947: 01/09/14: Re: Wanted: ISA bus implementation for Xilinx
Steen Larsen:
    5579: 97/02/25: FGPA to ASIC
    6550: 97/06/02: Re: Fine Pitch PQFP : anyone any hassles?
    19460: 99/12/22: Re: fpga cost
    19536: 99/12/29: Re: USB2 core call for Volunteers
    19629: 00/01/05: Re: fpga cost
    20226: 00/02/01: Re: PCI core in public domain
    22787: 00/05/24: Re: ISA interface on FPGA or CPLD
    38678: 02/01/21: Re: Quartus 2 and bus ripping
    38962: 02/01/28: Re: Quartus 2 and bus ripping
    39149: 02/02/01: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
    39821: 02/02/20: Re: Need good PCI book
    39832: 02/02/20: Re: Need good PCI book
    46050: 02/08/15: Re: Altera Byteblaster MAX7k programming problem
    46827: 02/09/09: Re: PCI bus problems
    47476: 02/09/26: Re: fpga eval kits
    47489: 02/09/26: Re: PCB Design for Altera FPGA
    47822: 02/10/04: Re: Altera FPGA as ISA I/O device
    48017: 02/10/09: Re: Parallel bus interface to a SmartMedia card.
    48526: 02/10/18: Re: PCB Design for Altera FPGA
    50363: 02/12/09: Re: FPGA/PCI on low budget
    50946: 02/12/23: Re: State of the PCB world
    52983: 03/02/27: Re: Extend PCI slot to outside PC
    53033: 03/02/28: Re: PCB board design software vs outsourcing?
<steen_tech@yahoo.com>:
    77082: 04/12/21: Re: PCB construction for PCI
Stef:
    78559: 05/02/03: gdb-stib and microblaze
    78736: 05/02/07: xilkernel and threads
    79405: 05/02/18: Using c++ with xilinx EDK tools
    122257: 07/07/24: Altera or Xilinx
    122262: 07/07/24: Re: Altera or Xilinx
    122338: 07/07/25: Re: Altera or Xilinx
    122363: 07/07/26: Re: Altera or Xilinx
    122365: 07/07/26: Re: Altera or Xilinx
    122370: 07/07/26: Re: Altera or Xilinx
    122420: 07/07/27: Re: Altera or Xilinx
    122646: 07/08/02: Re: Altera or Xilinx
    124393: 07/09/20: Re: Gated Clock Problems
    124444: 07/09/22: Re: Gated Clock Problems
    125378: 07/10/24: Programming Atmel dataflash with xilinx impact
    125404: 07/10/24: Re: Programming Atmel dataflash with xilinx impact
    125418: 07/10/25: Re: xilinx spi flash programming
    125423: 07/10/25: Re: xilinx spi flash programming
    125440: 07/10/25: Re: xilinx spi flash programming
    126047: 07/11/13: Re: implementing MAC protocols on fpga
    127157: 07/12/12: Re: spartan 3e VQ100 serious question
    129360: 08/02/22: How to use xilinx specific features from Modelsim Designer 6.3a VHDL
    129377: 08/02/22: Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL
    129414: 08/02/23: Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL
    129434: 08/02/23: Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL
    129454: 08/02/25: Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL
    129531: 08/02/27: Viewing RTL schematic in Xilinx ISE
    129540: 08/02/27: Re: Viewing RTL schematic in Xilinx ISE
    131476: 08/04/22: Re: Newbie: Testbench question
    132648: 08/06/04: Compare and update in same clock cycle synthesis problem
    132757: 08/06/06: Re: Compare and update in same clock cycle synthesis problem
    132765: 08/06/06: Re: Compare and update in same clock cycle synthesis problem
    132801: 08/06/07: Re: Compare and update in same clock cycle synthesis problem
    132836: 08/06/08: Re: Compare and update in same clock cycle synthesis problem
    136158: 08/11/04: Re: RS-232 Bus controller design in VHDL
    136161: 08/11/04: Re: RS-232 Bus controller design in VHDL
    136162: 08/11/04: Re: RS-232 Bus controller design in VHDL
    136214: 08/11/06: Re: TCP/IP 3 way handshake
    136351: 08/11/12: Re: clock problem
    136869: 08/12/10: Re: Sampling a clock
    138365: 09/02/17: Xilinx ISE complete device IBIS file generation?
    138432: 09/02/23: Re: Xilinx ISE complete device IBIS file generation?
    138858: 09/03/12: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
    138860: 09/03/12: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
    145231: 10/02/02: Re: What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for ?RS232 communication?
    147833: 10/05/26: Re: crc16 with 16 bit inputs
    147836: 10/05/26: Re: crc16 with 16 bit inputs
    147855: 10/05/27: Re: crc16 with 16 bit inputs
    148771: 10/08/20: Re: CE compliance testing
    148780: 10/08/21: Re: CE compliance testing
    148883: 10/09/07: Re: Text compression Huffman Encoder and Decoder
    149013: 10/09/21: Re: Xilinx XST and a State Machine - A Mystery
    149676: 10/11/16: Re: Huffman Encoder
    151052: 11/03/02: Xilinx Parallel cable III 3V3 and current impact version?
    151060: 11/03/02: Re: Xilinx Parallel cable III 3V3 and current impact version?
    151076: 11/03/04: Re: Xilinx Parallel cable III 3V3 and current impact version?
    151090: 11/03/05: Re: Xilinx Parallel cable III 3V3 and current impact version?
    153559: 12/03/27: Re: FPGA communication with a PC (Windows)
    153733: 12/05/02: Re: Smallest GPL UART
    154312: 12/09/26: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
    154700: 12/12/20: USB power and debug signals on micro USB connector
    154703: 12/12/20: Re: USB power and debug signals on micro USB connector
    154704: 12/12/20: Re: USB power and debug signals on micro USB connector
    155107: 13/04/19: Re: FPGA board with 4 channel 500Msps ADC?
    155108: 13/04/19: Re: FPGA board with 4 channel 500Msps ADC?
    156112: 13/11/27: Re: LCD test on Spartan 3E FPGA
    156117: 13/11/27: Re: LCD test on Spartan 3E FPGA
    156694: 14/06/05: Re: ECG signals Compression/Decompression
    156696: 14/06/05: Re: ECG signals Compression/Decompression
    156706: 14/06/06: Re: ECG signals Compression/Decompression
    156707: 14/06/06: Re: ECG signals Compression/Decompression
    156837: 14/07/08: Using FPGA as dual ported ram
    156847: 14/07/08: Re: Using FPGA as dual ported ram
    156848: 14/07/08: Re: Using FPGA as dual ported ram
    156853: 14/07/09: Re: Using FPGA as dual ported ram
    156855: 14/07/10: Re: Using FPGA as dual ported ram
    156859: 14/07/11: Re: Using FPGA as dual ported ram
    156863: 14/07/12: Re: Using FPGA as dual ported ram
    156864: 14/07/12: Re: Using FPGA as dual ported ram
    156874: 14/07/15: Re: Using FPGA as dual ported ram
    156875: 14/07/15: Re: Using FPGA as dual ported ram
    156878: 14/07/15: Re: Using FPGA as dual ported ram
    156880: 14/07/15: Re: Using FPGA as dual ported ram
    157464: 14/12/11: Re: Using FPGA to feed 80386
    157476: 14/12/12: Re: VHDL Synchronization- two stage FF on all inputs?
Stef Mientki:
    85202: 05/06/06: Re: Sch & Layout Free Program
    85203: 05/06/06: Re: Sch & Layout Free Program
Stef Winteraeken:
    19636: 00/01/05: Lattice Vantis GDX
Stef?:
    108759: 06/09/16: JOP @ Spartan3 Starter Kit - Compile error (missing components)
    109700: 06/10/03: Re: Driving a 30 bit wide LVTTL bus at 160MHz
stefaan:
    22079: 00/04/19: Re: Parallel to serial
stefaan vanheesbeke:
    31882: 01/06/07: Re: Xilinx SpartanII Configuration
    35410: 01/10/03: Re: Xilinx Foundation vs. ISE
    35411: 01/10/03: Re: Barrel Shifter
    35439: 01/10/04: Re: Xilinx Foundation vs. ISE
    37856: 01/12/21: Re: A ram wish
    37893: 01/12/23: Re: A ram wish
    39963: 02/02/22: Re: Replacing expensive configuration SPROM
    43348: 02/05/20: Re: Difference between Altera and Xilinx.
    43379: 02/05/20: fpga cpu
    43801: 02/06/03: Re: fpga cpu
Stefaan Vanheesbeke:
    27003: 00/11/07: unique serial nr
    31427: 01/05/23: RS422 - RS485 conversion
    31917: 01/06/08: Re: Xilinx SpartanII Configuration
    33078: 01/07/17: Re: PROBLEM!!!
    54932: 03/04/22: Re: NIOS 3.0 Spurious Interrupts
    55713: 03/05/16: Re: wire and reg and modelling of combinational logic
Stefan:
    87387: 05/07/22: Overmapped
    87683: 05/07/28: GLCKs on Spartan3
    87719: 05/07/29: Re: GLCKs on Spartan3
    87821: 05/08/02: Re: circular read address generator
    87910: 05/08/03: Re: hi stefen
    88188: 05/08/11: Clocks
    88192: 05/08/11: Re: Clocks
    97369: 06/02/21: fix: Xilinx USB Platform Cable on linux 2.6
    97373: 06/02/21: Re: fix: Xilinx USB Platform Cable on linux 2.6
    97539: 06/02/23: Re: fix: Xilinx USB Platform Cable on linux 2.6
    110214: 06/10/12: Implementing the Aurora Example Design V2.4 to a Virtex4
Stefan Derhaschnig:
    13195: 98/11/19: Combination of Xilinx FPGA and TMS320c40 or c60
Stefan Doll:
    4604: 96/11/20: Re: Advantage of third party software?
    5040: 97/01/15: Re: ASIC/FPGA Synthesis for LINUX... It's HERE!
    10099: 98/04/27: Re: Make a delay in Xilinx FPGAs (Help)?
    45368: 02/07/20: Re: spiral / waterfall /watersluice : Which are your methods?
    45722: 02/08/02: Re: Division
    45869: 02/08/08: Re: Modelsim in ISE pack
Stefan Duenser:
    77416: 05/01/06: is this memory implementation synthesizeable?
    77427: 05/01/06: Re: is this memory implementation synthesizeable?
Stefan Frank:
    64944: 04/01/16: Re: Good software to experiment with VHDL
    65390: 04/01/27: Re: Xilinx JTAG download under Linux (urgent)
    67739: 04/03/18: Re: UCF or XCF - which one to use ?
    69499: 04/05/12: Re: Mapping port for simulation only in VHDL
    75355: 04/11/03: Re: hostid for Actel Designer
    78515: 05/02/02: Re: Model Sim: Color Printing
Stefan Huebner:
    154344: 12/10/10: Spartan 6 MCB refresh timing
    155842: 13/09/29: Re: Legal Issues Reproducing Old CPU
Stefan Kamps:
    1851: 95/09/09: Looking for Scan-Path-Insertion-Too
Stefan Klanke:
    14117: 99/01/14: Problem with reducing bus width / Foundation Series v1.5
Stefan Klein:
    38548: 02/01/17: Re: PCI Solution: LogiCore?
Stefan Kopetsch:
    69212: 04/04/30: Ethernet & FPGA
Stefan Kulke:
    49625: 02/11/18: problem with clkdll on spartan2
    49694: 02/11/19: Re: problem with clkdll on spartan2
    49744: 02/11/20: Re: problem with clkdll on spartan2
    49818: 02/11/21: Re: problem with clkdll on spartan2
    49862: 02/11/22: Re: problem with clkdll on spartan2 - Bug on Xilinx webpack 4.2 wp3????
    51878: 03/01/24: Problems with "impact.exe" from ISE webpack 5.1
    51888: 03/01/24: Re: Problems with "impact.exe" from ISE webpack 5.1
    52775: 03/02/21: questions: create mcs-file / problem with downloading
    52930: 03/02/26: Re: questions: create mcs-file / problem with downloading
Stefan Ludwig:
    147: 94/09/01: Re: Dynamic Incremental Reconfiguration
    1356: 95/06/06: Re: HELP AT6000
    2951: 96/03/05: Re: Comp.Arch.FPGA
    2979: 96/03/08: Re: Reconfigurable Computing Languages
    3393: 96/05/24: Re: Evolvable HW
    4039: 96/09/05: Help: Code for adder circuit in VHDL/Verilog
    4877: 96/12/23: New CAD tools for new Xilinx XC6200 FPGA
    4991: 97/01/09: Repost: New CAD tools for new Xilinx XC6200 FPGA
    8190: 97/11/26: Trianus and Hades theses available: Fast CAD-tools for 6200
    11895: 98/09/17: Re: sync or async SRAM?
    11922: 98/09/18: Re: sync or async SRAM?
    12861: 98/11/02: Re: Q: 3.3 V regulators suitable for XILINX - ?
    14677: 99/02/10: Re: Supercomputer uses 280 Xilinx FPGAs
    18846: 99/11/18: Re: Need advice on interfacing SDRAM modules
    20119: 00/01/27: Re: What has happened to freecore.com ?
    23749: 00/07/06: Re: PamDC question.
    26190: 00/10/07: Re: FPGA Express strikes again! Xilinx response
Stefan Lund:
    15063: 99/03/04: Virtex & Xchecker
Stefan Monnier:
    152559: 11/09/14: Re: The Manifest Destiny of Computer Architectures
Stefan Oedenkoven:
    74484: 04/10/12: level converter for high frequencies
    75794: 04/11/15: Soft Processor Core
    75803: 04/11/15: Re: Soft Processor Core
    75832: 04/11/16: Re: Soft Processor Core
    77300: 05/01/04: code fragment causes error during bitstream generation... ISE 6.2 & Spartan3
    77314: 05/01/04: Re: code fragment causes error during bitstream generation... ISE 6.2 & Spartan3
Stefan Philipp:
    59847: 03/08/29: Re: keep_hierarchy in project manager
    68793: 04/04/19: Xilinx Rocket IO CRC+Clock Corrections results in CRC error
    109577: 06/09/29: Xilinx Virtex-2 Pro MUXCY does not drive local FF
    109762: 06/10/05: Re: Xilinx Virtex-2 Pro MUXCY does not drive local FF
Stefan Rave:
    11869: 98/09/15: XC4000: config. EPROM usable for dynamic reconfiguration / data storage?
    11882: 98/09/16: sync or async SRAM?
    11890: 98/09/17: Re: sync or async SRAM?
    11994: 98/09/23: Re: sync or async SRAM?
Stefan Rybacki:
    93337: 05/12/20: Re: real-time compression algorithms on fpga
Stefan Schmid:
    15495: 99/03/26: xilinx virtex parallel download from SUN
Stefan Schulte:
    44951: 02/07/08: Xilinix or Altera - which dev-board?
    45030: 02/07/10: Re: Xilinix or Altera - which dev-board?
    53803: 03/03/24: Which Prom for Spartan-II?
Stefan Tillich:
    55010: 03/04/24: Xilinx Virtex-E and PROM devices for Eagle
    59104: 03/08/08: Virtex-E power trace
    59920: 03/09/01: Virtex-E Select-RAM refresh rate
    74574: 04/10/14: Xilinx VirtexE internal oscillator
    109395: 06/09/26: Migration from Spartan-2E to Spartan-3E
    115363: 07/02/08: Floorplanning with Altera APEX20KE device
Stefan Wimmer:
    19103: 99/11/29: Re: MACH445 - parallel port programming cable
<stefan.elmsted@gmail.com>:
    119632: 07/05/24: LVDS termination scheme to nonstandard ribbon cable
    119903: 07/05/29: Re: LVDS termination scheme to nonstandard ribbon cable
<stefanludwig@my-deja.com>:
    21568: 00/03/25: Re: Chip-to-Chip benchmarks?
Stefano Cagnoni:
    12730: 98/10/26: CFP: EvoIASP '99
Stefano Ho:
    35724: 01/10/15: Re: JTAG-Programmer Linux
Stefano M:
    41943: 02/04/11: iMPACT FPGA detection error
    42196: 02/04/18: Re: iMPACT FPGA detection error
    42197: 02/04/18: Schematic editor and module descriptions
    42462: 02/04/24: Newbie with signals
    42519: 02/04/26: Re: Newbie with signals
    48258: 02/10/15: GCK as normal IO ?
    48271: 02/10/15: Re: GCK as normal IO ?
    51979: 03/01/28: AND gate into CPLD
    52624: 03/02/17: HDL Bench
Stefano Moser:
    151066: 11/03/03: Xilinx FPGA Clocking resources and design implementation.
    151113: 11/03/08: Re: Xilinx FPGA Clocking resources and design implementation.
Stefano Trucco:
    62258: 03/10/23: problem with Xilinx
    62292: 03/10/24: not replaced by logic error
<stefano.in.korea@gmail.com>:
    157254: 14/11/08: Program IO 1.2V
    157258: 14/11/08: Re: Program IO 1.2V
    157262: 14/11/09: Re: Program IO 1.2V
Stefanos:
    40780: 02/03/15: VHDL:Problem with depuncturing unit
    40781: 02/03/15: Re: VHDL:Problem with depuncturing unit
Stefanos Sidiropoulos:
    8367: 97/12/10: Re: what is metastability time of a flip_flop
Steffan Westcott:
    46631: 02/09/04: Re: Handel-C: Undeclared identifier: take2
    46691: 02/09/05: Re: HAndel-C types not matching
    46737: 02/09/06: Re: HAndel-C types not matching
    51353: 03/01/11: Re: typedef ram in Handel-C
    51899: 03/01/24: Re: Using Xilinx Logicores in Handel-C!
steffen kremser:
    125: 94/08/18: Self-Programming Devices (was Re: Proprietary Configuration Data)
Steffen Thieringer:
    35063: 01/09/20: Digital PLL for implementing in FPGA
    36111: 01/10/30: Autostart Problem SPROM->FPGA
    41437: 02/03/28: PLLs included in Altera Stratix Devices
    42189: 02/04/18: 8051 Core for Motor Electronics
    42198: 02/04/18: Re: 8051 Core for Motor Electronics
    42199: 02/04/18: Re: 1000 I/O Pins -- What is cheapest FPGA?
    42205: 02/04/18: Re: 8051 Core for Motor Electronics
    42441: 02/04/24: ISE 4.2 Java Problem
    43486: 02/05/22: 50Mhz driven - Overheat by Program?
stefkeB:
    54551: 03/04/14: Re: Hardware acceleration for raytracing purposes
Stein Kjølstad:
    42608: 02/04/29: Partial reconfiguration
Stelios Zontos:
    48997: 02/10/29: Information--conference paper
    49071: 02/10/31: Re: Information--conference paper
stella:
    79851: 05/02/25: Ml310(xc2vp30) with ppc 405,multi processor share memory?
    80890: 05/03/14: Re: FIFO Problem
STELLA:
Stella, Wang Zhanqing:
    37100: 01/11/30: RC10000-PP(Serial Number)
Sten Soegaard:
    7302: 97/08/23: Re: MaxPlusII from Altera.
Sten Sogaard:
    26434: 00/10/16: Sporadic Error: ERROR:JTag - Illegal character ?
Sten Søgaard:
    11907: 98/09/18: Problems with the Floorplanner in Xilinx Alliance 1.5
    11911: 98/09/18: Re: Synthesis warning
    11948: 98/09/21: Re: Problems with the Floorplanner in Xilinx Alliance 1.5
<stenasc@yahoo.com>:
    93839: 06/01/01: Re: basic DSP with FPGA
    101504: 06/05/02: Re: Output bus bit resolution of a digital filter
    103060: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
    105320: 06/07/20: ANN: Tyd-IP Code Generator adds NCO design capability
    108046: 06/09/04: Re: FIR Implementation with System Generator 8.2
    118109: 07/04/17: ANN: Tyd-IP Code Generator V3.1 released
    118182: 07/04/19: Re: VHDL source code for polyphase filter
    118188: 07/04/19: Re: VHDL source code for polyphase filter
Steph&Lise.:
    6512: 97/05/29: FREE HOT PICTURES HOT!
Stephan:
    88350: 05/08/15: Re: Spartan-3 configuration -- peculiar problem
    89670: 05/09/21: Re: ISE 7.1i incremental synthesis
Stephan Buchholz:
    61321: 03/10/01: Re: Automatic I/O voltage sensing (as XILINX ParallelCable IV)
    62581: 03/11/02: Re: Picoblaze development tool
    67661: 04/03/17: Re: FPGA protyping board (Avnet or others)
Stephan Diemer:
    18045: 99/09/25: absolut Newbie
    18053: 99/09/26: Re: absolut Newbie
    18088: 99/09/29: Performance of reprogrammable =?iso-8859-1?Q?FPGA=B4s=3F?=
Stephan Dubach:
    2814: 96/02/12: uC HDL models
Stephan Eichler:
    50215: 02/12/05: Communication between DSP and FPGA
Stephan Flock:
    38268: 02/01/10: Re: FPGA Synthesis and implementation
    46466: 02/08/30: Webpack 4.2 Schematic
    46487: 02/09/01: Re: Webpack 4.2 Schematic
    60096: 03/09/05: Re: How to extend a pulse width without clock!
    89750: 05/09/24: Re: Question on Metastability
    90373: 05/10/11: question: timing constraint for clock enable
    90422: 05/10/12: Re: question: timing constraint for clock enable
    111956: 06/11/13: Re: Xilinx USB cable - can't install driver
Stephan Gehring:
    3589: 96/07/02: Re: INDUSTRY GADFLY "Why I Hate Wally"
Stephan Gick:
    4854: 96/12/20: I2C Bus Interface in FPGAs
    6658: 97/06/10: ATMEL 17Cxxx ISP function
    8158: 97/11/22: ViewSynthesis and LogiBlox
Stephan Hegel:
    9317: 98/03/06: Re: The case for free operating systems and EDA
Stephan Klauke:
    42893: 02/05/06: Re: VirtexII : Reserving IO Pins as inputs
Stephan Mueller:
    76840: 04/12/14: Newbie question: fitting in cpld
    76875: 04/12/15: Re: Newbie question: fitting in cpld
Stephan Neuhold:
    32961: 01/07/13: Re: Problems: Xilinx 3.1i Service Pack 8
    33081: 01/07/17: Re: Xilinx .bit file format
    33089: 01/07/17: Re: Unconnected nets
    33653: 01/08/01: Re: Foundation 2.1 Schematic in WebPack
    34429: 01/08/24: Re: Spartan-II & clock
    42813: 02/05/03: Re: creating my own hard macro or similar
    42881: 02/05/06: Re: VirtexII : Reserving IO Pins as inputs
    42883: 02/05/06: Re: PCI-32/Spartan II Pin Outs?
    42890: 02/05/06: Re: Hard macro with Xilinx
    42958: 02/05/08: Re: Xilinx 2GB limit... something has to be done
    43237: 02/05/17: Re: PCI target with FPGA question
    43239: 02/05/17: Re: PCI Board Project
    43261: 02/05/17: Re: PCI Board Project
    44448: 02/06/20: Re: WebPack - How to view synthesis results?
    44964: 02/07/08: Re: 3.3 volt tolerance in Virtex-II Pro?
    44995: 02/07/09: Re: Multiple constraints, same net?
    44997: 02/07/09: Re: DCM - LOCKED output stays high when it shouldn't?
    45459: 02/07/24: Re: RLOC Origin problems in ISE4.2sp3?
    46271: 02/08/23: Re: XPLA3 coolrunner erased i/o state?
    47418: 02/09/25: Re: spartan II and PCI 5 volt
    49087: 02/10/31: Re: Spartan-IIE Constraint Question
    52828: 03/02/24: Re: fe_shell.exe needed
    60763: 03/09/22: Moderator of comp.arch.fpga
    67330: 04/03/10: Re: Very strange Xilinx timing report.
    67459: 04/03/12: Re: Issues in Rocket I/O
    80999: 05/03/15: Re: Xilinx ISE and IP cores
    106629: 06/08/16: Re: XILINX XAPP694
Stephan Schirrmann:
    29716: 01/03/06: rising_edge() on virtex
    29721: 01/03/06: Re: School project
    29783: 01/03/09: Re: rising_edge() on virtex
Stephan van Beek:
    133543: 08/07/03: Re: Insert IP cores
    133550: 08/07/03: Re: Insert IP cores
    133572: 08/07/04: Re: Insert IP cores
    133624: 08/07/07: Re: Re:V4FX20 upgrade to FX40 problem (was: Xilinx ISE speed files compatibilit)
    136169: 08/11/04: Re: Critical Path
Stephane:
    31426: 01/05/23: Re: Counter problem
    31915: 01/06/08: Flash programming via FPGA's JTAG ????
    81800: 05/04/01: Virtex DCM phase alignment and CLK2X registering
    82187: 05/04/08: Re: Interesting article about Xilinx FPGAs in the new Cray
    82320: 05/04/11: Re: CCD and Graphics - which FPGA?
    82477: 05/04/13: virtex4 reconfiguration time
    82495: 05/04/13: Re: virtex4 reconfiguration time
    82572: 05/04/14: Re: virtex4 reconfiguration time
    82630: 05/04/15: Re: virtex4 reconfiguration time
    85254: 05/06/07: Re: Fast/low area Sorting hardware.
    85353: 05/06/08: Re: Fast/low area Sorting hardware.
    89295: 05/09/12: several ucf files?
    89630: 05/09/21: Re: picoblaze IDE for Linux
    91973: 05/11/18: Re: FPGA Reconfiguration : Virtex-4 Frames
    91987: 05/11/18: Re: FPGA Reconfiguration : Virtex-4 Frames
    92271: 05/11/25: Re: XST :division and mod in vhdl
    92286: 05/11/25: Re: XST :division and mod in vhdl
    93118: 05/12/14: Re: ISE WebPack 8.1i
    93380: 05/12/21: Re: Place and Route Algorithms
    96959: 06/02/14: Re: How to decode FAR register in Virtex-4?
    97025: 06/02/15: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    97259: 06/02/20: Re: Xilinx HardMacro "configurable" ?
    97360: 06/02/21: Re: Is FPGA code called firmware?
    99080: 06/03/20: Re: slice macro replace the bus macro in the virtex-4 how to do that?????
    99190: 06/03/21: Re: slice macro replace the bus macro in the virtex-4 how to do that?????
stephane:
    32020: 01/06/11: Flash programming via FPGA's JTAG ?
    32131: 01/06/15: NIOS users ?
    72523: 04/08/23: plb_ddr_1.00.c cas latency ?
Stephane BRETTE:
    6915: 97/07/08: Vhdl synthesis tools for PC
Stephane Guyetant:
    57249: 03/06/26: Re: CoreGen/Ngdbuild help
    57254: 03/06/26: content of a LUT
    57329: 03/06/27: XAPP132: CLKDLL constraints pb
Stephane Julhes:
    72459: 04/08/19: Edk BMM file problem in ISE
<stephaneo@gmail.com>:
    105393: 06/07/21: IIR FPGA 'crosspost'
Stephanie McBader:
    41132: 02/03/21: Maximum device usage for successful PAR
Stephanie Tapp:
    14953: 99/02/26: Re: Xilinx 9500XL
    19998: 00/01/21: Re: WebFitter???
Stephen:
    6751: 97/06/24: Query: Anyone ever install Xilinx Foundation on a Jaz drive? If so how?
    23243: 00/06/18: Re: How to cut the power disipation down ?
    39555: 02/02/13: Re: student F2.1i printing problem
    58078: 03/07/14: problems on using CLKDLL in Xilinx ISE
    92784: 05/12/06: Re: xilinx research labs
    92830: 05/12/07: Re: xilinx research labs
    135230: 08/09/22: Avalda's Parallel F# to RTL FPGA Compiler
    135616: 08/10/09: Re: I need a good reference for VHDL
stephen:
    48785: 02/10/24: Quartus LogicLock problem
    49035: 02/10/30: Re: Quartus LogicLock problem
    49037: 02/10/30: Re: Quartus LogicLock problem
    49038: 02/10/30: Re: Leonardo and lpm (Altera)
Stephen A. Bailey:
    1104: 95/04/28: Re: Sunrise ???
Stephen A. Bailey -- SRBailey Consulting:
    2534: 95/12/28: Re: Career value: VHDL or Verilog?
Stephen Baynes:
    3629: 96/07/05: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
Stephen Bell:
    2738: 96/01/31: Xilinx or Altera?
    3115: 96/04/04: Re: Comp.Arch.FPGA
Stephen Boltinghouse:
    4492: 96/11/05: Just try this, it will work
Stephen Bradshaw:
    47323: 02/09/23: Re: Fast serial interconnect bus using spartan-II
    49924: 02/11/26: Re: Anybody know of vendors of PCI boards with FPGAs?
    52419: 03/02/08: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
Stephen Brown:
    70231: 04/06/09: Re: Logiclock TCL flow -- near completion
Stephen Byrne:
    35602: 01/10/11: Use of Global in Altera FLEX 10KA
    37643: 01/12/18: Best-case Timing?
    37706: 01/12/19: Best-case timing?
Stephen Charlwood:
    18226: 99/10/08: Capacity metrics for Virtex
    18262: 99/10/11: Any ideas what Xilinx plans for Virtex are?
Stephen Colley:
    5130: 97/01/25: Altera MAX+Plus II 10K timing model changes
Stephen Craven:
    89688: 05/09/22: Re: JBits query
    89701: 05/09/22: Re: downlaoding bit files to Xilinx FPGA
    89720: 05/09/23: C-to-gates experiences
    89795: 05/09/26: Re: downlaoding bit files to Xilinx FPGA
    89894: 05/09/29: Re: Preloading SDRAM?
    90065: 05/10/04: Re: Floating point multiplication on Spartan3 device
    90348: 05/10/10: Re: What is a "full custom" design?
    90450: 05/10/13: Re: Storing a file onto FPGA
    90856: 05/10/23: Re: Implementing five stage pipeline
    91028: 05/10/27: Re: Coregen Memory Initialization issue
    91322: 05/11/03: Re: XC2VP125
    91468: 05/11/07: Re: how to map kernel element of FFT to VIRTEX Pro Board
    91650: 05/11/10: Re: fpga speed logic/density MIPS/FLOPS as compared to general purpose microprocessors
    91758: 05/11/11: Re: FPGA KIT recommendation
    91865: 05/11/15: Re: Research Position
    91936: 05/11/17: ml310 DDR problem
    92056: 05/11/21: Reconfiguration Issue -- Pulse Program?
    92983: 05/12/10: Re: ISE purchase
    94877: 06/01/18: Re: data2bram and coregen
    95614: 06/01/24: Re: Verilog tutorial by John Sanguinetti
    96253: 06/02/01: Re: Die Area
    97444: 06/02/22: Ray Andraka's Book?
    97449: 06/02/22: Re: Cannot use ML310 DDR
    97643: 06/02/25: Re: A dev board supporting partial/dynamic reconf.
    100218: 06/04/05: Re: Virtex-4 readback via ICAP
    100224: 06/04/05: Re: Virtex-4 readback via ICAP
    101347: 06/04/29: Re: URGENT: Xilinx site
    101587: 06/05/03: Re: Unreactive Output Pins on Xilinx Virtex-II
    102020: 06/05/09: Re: Superscalar Out-of-Order Processor on an FPGA
    102109: 06/05/10: Re: Superscalar Out-of-Order Processor on an FPGA
    102532: 06/05/17: Re: "disappointing" 550Mhz performance of V5 DSP slices
    102592: 06/05/17: Re: Verilog Draggable Window Library
    103114: 06/05/25: Re: Virtex 5 announced
    103347: 06/05/31: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103358: 06/05/31: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103524: 06/06/05: Re: MIL Qualified RTOS for PowerPc 405
    105226: 06/07/18: Re: OpenFire - public domain MicroBlaze clone in verilog
    105232: 06/07/18: Re: OpenFire - public domain MicroBlaze clone in verilog
    105280: 06/07/19: Re: OpenFire - public domain MicroBlaze clone in verilog
    139199: 09/03/23: Re: Silicon Blue last datesheet correct URL
Stephen D:
    81073: 05/03/17: Re: Potential Uses of Atmel FPSLIC Devices?
Stephen D. Scott:
    997: 95/04/11: journal suggestions
    6771: 97/06/26: Re: FPGA prototype board
    6772: 97/06/26: Re: Info on VHDL
    7006: 97/07/22: tech. report available
    10915: 98/06/30: Visiting Faculty / Post-Doctoral Fellow Positions
    11771: 98/09/08: faculty openings at the University of Nebraska
Stephen Dcombe:
    81009: 05/03/16: Potential Uses of Atmel FPSLIC Devices?
Stephen du Toit:
    31326: 01/05/19: Xilinx Webfitter fails with exit code 0002
    54113: 03/04/02: Help implementing BlockRAM on Spartan-II
    54122: 03/04/02: Re: Help implementing BlockRAM on Spartan-II
    59573: 03/08/21: Question about slew rate for SpartanII using ISE5.1
    59613: 03/08/24: Re: Question about slew rate for SpartanII using ISE5.1
    59614: 03/08/24: Re: Question about slew rate for SpartanII using ISE5.1
Stephen Fraleigh:
    16680: 99/06/02: Re: Modelsim, VHDL & mem core
    16681: 99/06/02: Re: Modelsim, VHDL & mem core
Stephen Fuld:
    46521: 02/09/02: Re: Hardware Code Morphing?
    156131: 13/12/07: Re: Implementing multiple interrupts
Stephen Glow:
    65482: 04/01/30: Firewire (IEEE 1394a) link layer IP block?
Stephen Henry:
    42463: 02/04/24: Newbie Advice Please
    50752: 02/12/18: Embedded Linux for V2Pro
Stephen Ingram:
    25807: 00/09/21: Re: A Question on Virtex Configuration
    25832: 00/09/22: Virtex: partial reconfiguration
Stephen J Smith:
    41: 94/08/02: wanted: logic net lists
    295: 94/10/14: Re: FLEX8000 architecture / routability with fixed pin-out
    399: 94/11/07: Re: Altera FTP
    1274: 95/05/24: Altera Contacts ...
    1698: 95/08/17: Re: FPGAs with embedded RAM
Stephen J. Byrne:
    16573: 99/05/28: Re: FPGA express + VHDL: strange SR implementation?
Stephen J. Singer:
    5501: 97/02/20: Re: State Diagram Tools
Stephen Kempenaers:
    18040: 99/09/25: Evolvable Hardware
Stephen King:
    9434: 98/03/13: FPGA/VHDL design tools review < $10K
    9502: 98/03/19: Looking for space qualified FPGAs/ASICs
    15568: 99/03/31: Re: FPGAs with ECL-compatible I/Os
    16770: 99/06/08: ALtera 20KE LVDS IO
    16799: 99/06/09: Re: ALtera 20KE LVDS IO
    18064: 99/09/27: Altera 20KE LVDS IO
Stephen Lannard:
    80442: 05/03/05: Help with 22v10 and WinCupl :(
    80459: 05/03/06: Re: Help with 22v10 and WinCupl :(
    80461: 05/03/06: Re: Help with 22v10 and WinCupl :(
    80472: 05/03/06: Re: Help with 22v10 and WinCupl :(
Stephen Lohning:
    24034: 00/07/24: Re: Real time sims with NC-Verilog
    26689: 00/10/25: Jtag programing 18V02 prom
    61707: 03/10/09: Initilization of block rams to create rom
    84503: 05/05/20: Simulation of rocket IO in virtex 2 pro
Stephen Maudsley:
    8722: 98/01/22: Re: Opinions of My FPGA - Like Chip Design Wanted
    9004: 98/02/13: Re: Why altera CPLDS are slow to power-up?
    11357: 98/08/06: Re: Silicore VHDL 8-bit RISC uC core for FPGA
    15309: 99/03/18: Re: Reconfigurable computing thesis on the web
    16146: 99/05/06: Re: BGA Prototyping ?
    16172: 99/05/07: Re: BGA Prototyping ?
    77003: 04/12/19: Re: Seeking FPGA and 8MB SDRAM in a PCMCIA Type I card
    79794: 05/02/24: Re: Multiple addition(2)
Stephen Melnikoff:
    37112: 01/11/30: Re: RC10000-PP(Serial Number)
    37255: 01/12/05: Re: Where to get JBit or Jroute
    37710: 01/12/19: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
    53298: 03/03/10: Chip release dates
    53373: 03/03/12: Re: Are there any FPGA magazines/journals?
Stephen Molloy:
    8124: 97/11/19: XACT 5.0 problem under DOS
    11437: 98/08/13: Re: Fixed Division by 3, 5, 7, 9, 15, 17 ...
Stephen P. Pope:
    6422: 97/05/23: Cypress WARP question
Stephen Peddle:
    12048: 98/09/25: Re: 3.3V PCI to 5V local bus interface?
    12049: 98/09/25: Re: Anyone received Xilinx Foundation 1.5 ?
    12050: 98/09/25: Re: Cypress CPLDs
    12110: 98/09/29: Re: Simple programmable device suggestions please?
Stephen Pelc:
    46539: 02/09/02: Re: Hardware Code Morphing?
    66256: 04/02/16: Re: Dual-stack (Forth) processors
    66263: 04/02/16: Re: Dual-stack (Forth) processors
    66313: 04/02/17: Re: Dual-stack (Forth) processors
    66486: 04/02/20: Re: Dual-stack (Forth) processors
    66812: 04/02/26: Re: Dual-stack (Forth) processors
    67889: 04/03/22: Re: Dual-stack (Forth) processors
    73852: 04/09/30: Re: embedded linux on FPGA?
    73927: 04/10/01: Re: embedded linux on FPGA?
    149194: 10/10/06: Re: Driving a design via TCP/IP
Stephen Phillipson:
    9192: 98/03/01: Newbie Question : FPGA and VHDL
    9693: 98/03/31: Re: Digital PLL's or Manual Synching?
    9828: 98/04/08: Implementation of Shift Registers and Buffers
Stephen R. Synakowski:
    6920: 97/07/09: Re: Generating Sine/Cosine digitally
stephen smith:
    918: 95/03/29: meta-systems, who are they ?
Stephen Smith:
    7083: 97/07/30: Re: information on RIPP10
    16801: 99/06/09: Re: Free IP library?????
Stephen Swearingen:
    12417: 98/10/11: Re: Xilinx F1.5/FPGA Express wackiness
    12464: 98/10/12: Re: Xilinx F1.5/FPGA Express wackiness
    13008: 98/11/10: Power Consumption
    13009: 98/11/10: CCLK on Spartan
    14647: 99/02/08: Contract Job in Boston
    14648: 99/02/08: Contract Job in Boston II
    15204: 99/03/12: Re: Virtex LUT equation syntax in Xilinx EPIC 1.5?
    17024: 99/06/25: Re: Read/Writes to memories/register files for PIC core
Stephen Williams:
    28872: 01/01/26: Re: looping and ranges
    34421: 01/08/24: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
    34463: 01/08/26: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
    42575: 02/04/28: Suspicious code in Verilog model for Xilinx DCM module
    42866: 02/05/05: Bug in Xilinx DCM.v simulation model
    42879: 02/05/06: Re: static logic vs LUT
    43026: 02/05/09: Re: PCI bus software for Xilinx PCI core
    46591: 02/09/04: Re: Warning: Xilinx 4.2i + Windows 2000 SP3 => blue screen of death
    47008: 02/09/14: Synthesis of 4:1 and 8:1 MUX devices in Virtex
    47229: 02/09/20: Re: Xilinx ISE5.1 and Windows NT
    47239: 02/09/21: Re: Xilinx ISE5.1 and Windows NT
    47262: 02/09/21: Re: Xilinx ISE5.1 and Windows NT
    47379: 02/09/25: Re: MTBF
    49010: 02/10/29: Re: Modelsim help
    49250: 02/11/06: Re: 5.1i and Win-NT
    49339: 02/11/09: Re: new to fpga, what language is better to start with
    49507: 02/11/13: Re: jedec
    49953: 02/11/26: Re: Custom FPGA synthesis
    50270: 02/12/07: Re: free software for XC4000
    50360: 02/12/09: Re: FPGA/PCI on low budget
    50599: 02/12/13: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    52127: 03/02/02: Re: SChematic design approach compared to VHDL entry approach
    53263: 03/03/08: Re: Mac Os X for FPGA design
    54168: 03/04/03: Re: Internal net names on ISE Foundation
    54198: 03/04/04: Re: Xilinx V2.1i Licensing
    55019: 03/04/24: Re: ise4.2i and wine
    55088: 03/04/25: Re: ise4.2i and wine
    55636: 03/05/14: Re: OK I am pissed off with Xilinx webpack.
    55638: 03/05/14: Re: "Primitives" in XST?
    59043: 03/08/06: Tool chains that take in EDIF 2 0 0/LPM 2 1 0
    59174: 03/08/11: Re: Upgrading OS or WebPack
    59266: 03/08/13: Re: Upgrading OS or WebPack
    59519: 03/08/20: Re: 22V10, ABEL & Current Design Tools?
    59520: 03/08/20: Re: Legacy 4005 series and current Xilinx ISE offerings?
    59345: 03/08/15: Re: Free VHDL Simulator
    60392: 03/09/11: Re: Time Killing Post P&R Simulation
    60393: 03/09/11: Re: Xilinx 6.1i on Red Hat 9
    61176: 03/09/29: Re: ISE: Parallel Processing
    64958: 04/01/16: Re: System Ace - Flash card formatting
    64959: 04/01/16: Re: Which version of ISE Webpack has FPGA Editor on it?
    68597: 04/04/08: [OT] Is anyone alive at Opencores.org?
    70306: 04/06/11: Xilinx ParallelCable IV vs. Linux
    70310: 04/06/11: Re: Xilinx Parallel Cable IV vs. Linux
    70315: 04/06/11: Re: Xilinx Parallel Cable IV vs. Linux
    70326: 04/06/12: Re: Xilinx ParallelCable IV vs. Linux
    70374: 04/06/14: Re: Xilinx Parallel Cable IV vs. Linux
    70434: 04/06/16: Re: Xilinx Parallel Cable IV vs. Linux
    70437: 04/06/16: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
    70929: 04/07/01: Re: *RANT* Ridiculous EDA software "user license agreements"?
    71147: 04/07/09: Re: Icarus Verilog for Windows
    71924: 04/08/03: Re: Foundation evaluation on linux
    72656: 04/08/27: Impact vs. Linux RedHat Linux
    72666: 04/08/27: Re: Impact vs. Linux RedHat Linux
    72670: 04/08/27: Re: Impact vs. Linux RedHat Linux
    72760: 04/08/31: Re: Synthesize verilog code with Icarus for Spartan?
    73021: 04/09/10: Xilinx ISE vs. SuSE Linux 9.x
    73024: 04/09/10: Re: Xilinx ISE vs. SuSE Linux 9.x
    73301: 04/09/18: Re: USER RESET in XILINX FPGA
    73302: 04/09/18: Re: FPGA with PCI interface for video processing?
    73438: 04/09/21: Re: USER RESET in XILINX FPGA
    75037: 04/10/25: PicoBlaze Assembler in C (was Re: Assembler for PicoBlaze in Perl)
    74269: 04/10/06: Re: 64 bit version of xilinx ISE
    74270: 04/10/06: Re: FPGA not turning off
    74322: 04/10/07: Re: DCM and CLKFX - is this allowed?
    75557: 04/11/09: Re: C Compiler for Picoblaze !!!!!
    76715: 04/12/09: Software controllable clock generator, Xilinx Virtex-II
    76735: 04/12/09: Re: Software controllable clock generator, Xilinx Virtex-II
    76972: 04/12/17: Re: how to start with development of eda tools
    77714: 05/01/14: XST vs. Verilog Libraries
    77715: 05/01/14: Re: Seeking FPGA and 8MB SDRAM in a PCMCIA Type I card
    79406: 05/02/18: Xilinx: Pitfalls of chaining DLLs
    79426: 05/02/18: Re: Xilinx: Pitfalls of chaining DLLs
    79537: 05/02/20: Re: why are PCI-based FPGA cards so expensive ?
    79550: 05/02/20: Re: why are PCI-based FPGA cards so expensive ?
    99320: 06/03/22: ACE Formatter for Linux (was Re: Parallel Cable IV...)
    99398: 06/03/23: Re: ACE Formatter for Linux (was Re: Parallel Cable IV...)
    100162: 06/04/04: Re: spartan FPGA with PLCC package
    100805: 06/04/18: Re: PLD610
    100893: 06/04/20: Xilinx PCIe core vs. Icarus Verilog
    101148: 06/04/26: Re: Picoblaze C Compiler
    101236: 06/04/27: Xilinx SystemACE on multi-FPGA board
    101287: 06/04/28: Re: Working Altera USB-Blaster compatible design published under
    101300: 06/04/28: Re: Xilinx SystemACE on multi-FPGA board
    101321: 06/04/28: Re: Working Altera USB-Blaster compatible design published under
    101325: 06/04/28: Re: Xilinx SystemACE on multi-FPGA board
    103951: 06/06/15: Re: How to get lowest price for a ModelSim license?
    104025: 06/06/16: Re: How to get lowest price for a ModelSim license?
    104064: 06/06/18: Re: How to get lowest price for a ModelSim license?
    104088: 06/06/18: Re: --.-Low Cost High quality pcb prototype and Assembly manufacturer(CHINA).
    104351: 06/06/25: Re: Xilinx ISE S/W Install kernel version "mismatch"
    111037: 06/10/27: Re: Survey: simulator usage
    112547: 06/11/24: Re: Verilog problem: default case to set signal xxxx
    117252: 07/03/27: Re: Open-source CPU-core for standard-cell ASIC?
    117685: 07/04/06: Re: Flash memmory model
    117688: 07/04/06: Re: Where is Open Source for FPGA development?
    117706: 07/04/07: Re: Initialisation of two dimensional array to known non-zero values
    118743: 07/05/02: Xilinx WebPACK 91i on vmware RHEL4
    118792: 07/05/03: Re: Xilinx WebPACK 91i on vmware RHEL4
    118849: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
    118855: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
    119008: 07/05/09: Re: Ubuntu and Webpack?
    119014: 07/05/09: Re: An Open-Source suggestion for Xilinx
    120047: 07/05/31: Re: Nexys by Digilen xbd file
    120125: 07/06/01: Re: Nexys by Digilen xbd file
    120138: 07/06/01: Re: Nexys by Digilen xbd file
    133216: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
    133323: 08/06/24: Re: which commercial HDL-Simulator for FPGA?
    153117: 11/12/07: Xilinx 7 series PCIe core models vs. Icarus Verilog
    153121: 11/12/07: Re: Xilinx 7 series PCIe core models vs. Icarus Verilog
stephen.craven@gmail.com:
    108580: 06/09/13: Re: FPGA timing
    109164: 06/09/21: Re: NIOS speed
    114610: 07/01/20: Re: How can I make xst to infer BlockRAM instead of Distributed RAM
    114728: 07/01/23: FPGA damage from bad bitstream
    116676: 07/03/15: Re: .bit file to VHDL/verilog source code
    120923: 07/06/20: Re: Linux 2.6.20 on MicroBlaze now available
    121461: 07/07/05: Re: ICAP in V4 FX20 only working after Reset
    124659: 07/09/29: Re: XUPV2P from digilentinc
    133326: 08/06/24: Re: 1D or 2D Placement for dynamically partially reconfigurable
    139488: 09/03/31: Xilinx partitions vs. smartguide
    143709: 09/10/22: OS for Xilinx tools
    145041: 10/01/21: Networking Board Recommendation
    145061: 10/01/23: Xilinx online documentation issues
    145082: 10/01/25: Re: Achronix FPGA
    147252: 10/04/20: Virtex 7?
    147479: 10/04/28: Re: xilinx arm finally announced
    149765: 10/11/23: Intel Atom + FPGA
    149982: 10/12/04: Re: : The Danger of When Programmable Logic Meets the Consumer Market
    150665: 11/02/01: Bit-accurate C simulation
    150846: 11/02/16: PLD suggestions for classroom use
    152279: 11/08/02: Re: FPGA security, Actel down, now Xilinx too?
    152299: 11/08/04: Re: FPGA security, Actel down, now Xilinx too?
<stephen.horsford@gmail.com>:
    111793: 06/11/10: Code for Verilog 8bit * 8bit pipelined multiplier
stephen_niosII:
    75572: 04/11/09: Re: Problem including header files in a C/C++ project using Altera's Nios II IDE
<stephenmck@gmail.com>:
    115603: 07/02/14: Xilinx Platform Studio adding Xilinx coreGen IP
    115821: 07/02/21: Re: Xilinx Platform Studio adding Xilinx coreGen IP
Steve:
    10889: 98/06/28: Xilinx file compression
    12931: 98/11/05: Re: 3.3V PCI to 5V local bus interface?
    13058: 98/11/13: Re: Alternative to EPM5128 OTP
    13111: 98/11/16: Re: Xilinx Foundation vs. Altera Max Plus
    13146: 98/11/17: Re: Is there an alternative to Altera EPM5128 OTP?
    13224: 98/11/20: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
    13302: 98/11/24: Which parts are fastest for 3-state enables?
    13317: 98/11/25: Re: Which parts are fastest for 3-state enables?
    13318: 98/11/25: Re: Which parts are fastest for 3-state enables?
    13339: 98/11/26: Re: Which parts are fastest for 3-state enables?
    13341: 98/11/26: Re: Which parts are fastest for 3-state enables?
    13378: 98/11/30: Is it normal to have to edit the xnf file???
    13409: 98/12/01: Re: Is it normal to have to edit the xnf file???
    13423: 98/12/02: Re: Is it normal to have to edit the xnf file???
    13422: 98/12/02: Re: XILINX FPGA reaches GHz speeds
    13545: 98/12/08: What are the 'rules' for assigning large buses to fpga's
    13558: 98/12/09: Re: What are the 'rules' for assigning large buses to fpga's
    13669: 98/12/17: Re: Fast *Industrial* 22V10?
    13672: 98/12/17: MP3 and FPGA's
    13732: 98/12/21: Xilinx FlowEngine vs Batch file?
    13762: 98/12/22: Xilinx FPGA Express cmd line
    14105: 99/01/13: Re: Orcad Express Plus vs Foundation Express
    14124: 99/01/14: Re: Hard porting to FPGA Express
    14334: 99/01/26: Re: FPGA architecture
    14762: 99/02/15: Re: Xilinx Spartan and pin-locking
    14764: 99/02/15: Re: orcad
    14775: 99/02/16: Re: orcad
    14875: 99/02/22: Re: connecting 2 FPGA
    14979: 99/03/01: PC for CAD
    15120: 99/03/08: Re: Foundation Express: Edit Constraints
    17385: 99/07/23: What does a SpartanXL look like prior to configuration?
    18285: 99/10/12: Re: ALTERA design ---> XILINX
    18286: 99/10/12: Re: Any ideas what Xilinx plans for Virtex are?
    21497: 00/03/23: Preferred Configuration Approach
    21671: 00/03/28: CoreGen incompatible with NT SP6 and Win2K?
    21715: 00/03/29: Re: New Place and Route Software for Non-Commercial Research (Academic VPR 4.30 Available)
    23557: 00/06/30: Re: Which notebook is for you?
    23580: 00/07/01: Re: Which notebook is for you?
    32204: 01/06/19: Bitstream to NCD file conversion for Virtex
    34374: 01/08/22: Re: How does For Loop works in AHDL
    39198: 02/02/04: Re: solutions manuals, and no they are not for school
    39249: 02/02/04: Re: solutions manuals, and no they are not for school
    41811: 02/04/08: W2000 HotFix Xilinx compatible?
    41813: 02/04/08: Re: W2000 HotFix Xilinx compatible?
    50316: 02/12/09: LFSR question
    51058: 02/12/29: Re: meaning of system gates vs. logic gates?
    52118: 03/02/01: Spartan2E and parallel port
    52145: 03/02/03: Re: Spartan2E and parallel port
    55115: 03/04/27: 4 bit Multiplier and Divider
    62622: 03/11/03: Re: Some FPGA questions
    65730: 04/02/05: Do Xilinx Fix Their Prices?
    65775: 04/02/06: Re: Do Xilinx Fix Their Prices?
    65827: 04/02/07: Re: Pricing, 101
    65828: 04/02/07: Re: Pricing, 101
    65830: 04/02/07: Re: Pricing, 101
    65864: 04/02/09: Re: Pricing, 101
    65887: 04/02/09: Re: Pricing, 101
    65889: 04/02/09: Re: Pricing, 101
    65891: 04/02/09: Re: Do Xilinx Fix Their Prices?
    65956: 04/02/10: Re: Pricing, 101
    66032: 04/02/11: Re: Pricing, 101
    66073: 04/02/12: Re: Pricing, 101
    66074: 04/02/12: Re: Pricing, 101
    66162: 04/02/13: Re: Pricing, 101
    66163: 04/02/13: Re: Pricing, 101
    66178: 04/02/13: Re: Pricing, 101
    68128: 04/03/26: Spartan RAMB4 Timing
    71186: 04/07/11: Re: Altera configuration Problem?? Help
    71656: 04/07/26: www.opencores.org?
    71657: 04/07/26: Re: www.opencores.org?
    71668: 04/07/27: Re: www.opencores.org?
    74921: 04/10/21: Re: interfacing a PC based program with a FPGA
    77493: 05/01/07: Re: Xilinx CPLD configuration under Linux ?
    78147: 05/01/25: Re: Xilinx Engineering Samples [JTAG issues]
    78211: 05/01/26: Re: Xilinx Engineering Samples [JTAG issues]
    79262: 05/02/16: Virtex4: On using a LC clock pin for global clock.
    79521: 05/02/20: Xilinx Memory Interface Generator
    81163: 05/03/18: Xilinx - ucf file parsing errors
    82429: 05/04/12: General question about soft CPUs
    83914: 05/05/09: Re: Altera: Maxplus rules!
    93455: 05/12/22: Re: ISE project with a Microblaze submodule: timing constrains warning
    109145: 06/09/21: DCM multiplier and EDK design
    109163: 06/09/21: Re: DCM multiplier and EDK design
    109643: 06/10/02: Net names from EDK => ISE
    109667: 06/10/02: Re: Net names from EDK => ISE
    109671: 06/10/02: Re: Net names from EDK => ISE
    110616: 06/10/18: Executing PPC code from external flash memory
    110670: 06/10/19: Re: Executing PPC code from external flash memory
    111253: 06/10/31: XPS Flashwriter tool errors on last location in flash
    111391: 06/11/03: EDK software development
    111925: 06/11/13: Re: XPS Flashwriter tool errors on last location in flash
    112719: 06/11/28: Re: Microblaze Code and XMP functions
    113165: 06/12/07: FPGA+Ethernet
    113198: 06/12/08: Re: FPGA+Ethernet
    113477: 06/12/14: How to get ISE to create a _bd.bmm file for BRAM initialization
    115109: 07/01/31: Re: How to get ISE to create a _bd.bmm file for BRAM initialization
    118070: 07/04/17: xilinx unused I/O state
    122425: 07/07/27: Re: regarding the post PnR timing simulation.....
    129159: 08/02/16: Ballpark PLB frequency
    129162: 08/02/16: Re: Ballpark PLB frequency
    131284: 08/04/17: Re: Survey: FPGA PCB layout
    133197: 08/06/20: DDR2 termination
    138812: 09/03/11: Xilinx design flow
    142286: 09/08/01: Xilinx 3E design programs fine with 500E but fails with 250E
    142291: 09/08/02: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142302: 09/08/03: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142303: 09/08/03: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142313: 09/08/03: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142556: 09/08/16: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142601: 09/08/20: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142602: 09/08/20: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    142611: 09/08/20: Re: Xilinx 3E design programs fine with 500E but fails with 250E
    152346: 11/08/11: Re: Newbie PCB
    152360: 11/08/12: Re: Help needed to emulate a microcontroller.
    152390: 11/08/18: Re: extracting D from 1 / D*D
    152391: 11/08/18: Re: Spartan6 PCB debugging: how badly do you have to screw up for
    152394: 11/08/18: Re: Spartan6 PCB debugging: how badly do you have to screw up for
    152397: 11/08/18: Re: extracting D from 1 / D*D
    152404: 11/08/19: Re: Spartan6 PCB debugging: how badly do you have to screw up for
    152409: 11/08/20: Re: Spartan6 PCB debugging: how badly do you have to screw up for
    152434: 11/08/23: Re: MAXDELAY constraint
    152495: 11/08/29: Re: Very cheap Spartan3 board that can be configured by simple USB
    152540: 11/09/09: Re: reduce EDK synthesis time
    152541: 11/09/09: Re: facing problem in creating ..BMM file with RAMB18X2
    152564: 11/09/15: Re: Can't get the Xilinx cable drivers installed on SL6.1 (RHEL 6.1)
steve:
    9369: 98/03/07: Re: The case for Linux and EDA
    9376: 98/03/07: Re: The case for free operating systems and EDA
    9630: 98/03/27: Re: XactStep6 - The cure for a dongle
    9689: 98/03/31: Re: XactStep6 - The cure for a dongle
    60020: 03/09/03: Re: ISE 5.2 constraint file problem
    80899: 05/03/14: editing waveforms under Linux
    82192: 05/04/08: DLL feedback delay
    87378: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87435: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87736: 05/07/29: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87898: 05/08/03: Re: System Engineering in the R/D World
    141668: 09/07/03: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
    141743: 09/07/06: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
    151493: 11/04/13: Re: Need PCIe Help
SteVe:
    23513: 00/06/28: Virtex power estimation
    23645: 00/07/04: Virtex Global Set Reset
    23652: 00/07/04: Programming Virtex with the MultiLINX cable
    25924: 00/09/26: Re: Global clock buffers and secondary clock buffers.
Steve Allen:
    3332: 96/05/14: Re: which coding style is better for synthesis?
Steve at fivetrees:
    95213: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95223: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95234: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95270: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95271: 06/01/21: Re: OT:Shooting Ourselves in the Foot
    95316: 06/01/22: Re: OT:Shooting Ourselves in the Foot
    95424: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95547: 06/01/24: Re: OT:Shooting Ourselves in the Foot
    95553: 06/01/24: Re: OT:Shooting Ourselves in the Foot
    95555: 06/01/24: Re: OT:Shooting Ourselves in the Foot
    108064: 06/09/04: Re: Please help me with (insert task here)
    120806: 07/06/17: Re: EDK - Microblaze question
    121185: 07/06/27: Re: Bidirectional LVDS
    121187: 07/06/27: Re: Bidirectional LVDS
    121195: 07/06/28: Re: Bidirectional LVDS
    139030: 09/03/19: Re: Zero operand CPUs
    139031: 09/03/19: Re: Bullshit! - Re: Zero operand CPUs
Steve B:
    152343: 11/08/11: Re: image storing into BRAM
    152363: 11/08/12: Re: Help needed to emulate a microcontroller.
    152441: 11/08/23: Re: [actel] resource usage by entity
    152442: 11/08/23: Re: [actel] resource usage by entity
    152646: 11/09/22: Re: Xilinx Spartan-3 Starter Kit and Webpack 13.2
    153099: 11/11/30: Re: Compatible Xilinx USB Cables: worth to bother?
Steve Baldwin:
    3046: 96/03/20: Re: Xact6.o too slow
    5637: 97/03/03: Re: JTAG config on ALTERA FLEX10K10: How?
Steve Battazzo:
    115924: 07/02/25: Xilinx ISE webpack in Ubuntu?
    115926: 07/02/26: Re: Xilinx ISE webpack in Ubuntu?
    115935: 07/02/26: Re: Xilinx ISE webpack in Ubuntu?
    116020: 07/02/27: Re: Xilinx ISE webpack in Ubuntu?
    116021: 07/02/27: Re: Xilinx ISE webpack in Ubuntu?
    116138: 07/03/02: Re: Xilinx ISE webpack in Ubuntu?
    116155: 07/03/02: Re: Xilinx ISE webpack in Ubuntu?
    116183: 07/03/03: Re: Xilinx ISE webpack in Ubuntu?
    116385: 07/03/08: odd warning in Xilinx ISE webpack
    116511: 07/03/11: Re: odd warning in Xilinx ISE webpack
    117971: 07/04/14: How many RAM words can I implement in my Xilinx FPGA?
    117972: 07/04/14: Re: How many RAM words can I implement in my Xilinx FPGA? --NEVERMIND--
    117975: 07/04/14: Re: How many RAM words can I implement in my Xilinx FPGA?
    118267: 07/04/20: Memory generator IP core ISE Webpack
    118270: 07/04/20: Re: Summer with fpgas
Steve Beaver:
    32029: 01/06/11: Re: Triscend A5: can it reconfigure itself?
Steve Berman:
    24632: 00/08/15: JTAG, Xilinx, Winnt, and the Parallel Port
    24684: 00/08/16: Xilinx, JTAG, Parallel Ports and Winnt
steve bessette:
    46313: 02/08/26: Re: sensing an oscillator
Steve Bird:
    5528: 97/02/22: Re: State Diagram Tools
    5715: 97/03/10: Re: Galileo... Leonardo... Renoir... ?
    7659: 97/10/01: Re: Xilinx licensie idiocy
    12722: 98/10/26: Re: Schematic entry?
    13193: 98/11/19: Re: VHDL Block Capture
    17308: 99/07/20: Re: License sharing for synopsys/cadence/modeltech
    20064: 00/01/26: Re: Anyone changed an NT disk serial number?
    20099: 00/01/27: Re: Anyone changed an NT disk serial number?
    67641: 04/03/16: Re: Schematic Edition Tool : Suggestions
Steve Bradshaw:
    30784: 01/04/28: Re: Comparison of FPGA and DSP
Steve Brainard:
    21064: 00/03/05: Re: Divider
Steve Casselman:
    209: 94/09/22: Brust Mode (For the SBus)
    322: 94/10/19: Verilog for Synopsys vs Cadence
    350: 94/10/26: Whats the point?
    398: 94/11/07: Random Number Tests
    458: 94/11/23: Horror Story
    495: 94/12/07: Re: L-Edit and Benchmarks
    509: 94/12/14: Benchmark Specs. in C
    512: 94/12/16: Random numbers.
    1028: 95/04/18: Re: Free Hardware
    1129: 95/05/03: Short Floats
    1160: 95/05/08: RE: Short Floats
    1218: 95/05/17: Re: Price/Performance
    1374: 95/06/09: Low cost ISA board
    1465: 95/06/26: Re: low cost ISA board
    2208: 95/11/02: XC4025 routing
    2779: 96/02/06: Test Bounce of comp-arch-fpga@super.org
    2793: 96/02/09: New Reconfigurable Computing Threads.
    2795: 96/02/09: Performance Benchmarks
    2851: 96/02/16: JAVA and beer
    2873: 96/02/21: Java and reconfigurable computing
    2876: 96/02/22: Re: Floating Point and Reconfigurable Architectures
    2899: 96/02/26: Languages for reconfigurable computing.
    2914: 96/02/28: High Level Languages
    2922: 96/02/29: Re: Comp.Arch.FPGA
    2932: 96/03/01: Reconfigurable Computing Languages
    2940: 96/03/03: Re: Reconfigurable Computing Languages
    2965: 96/03/07: Re: Reconfigurable Computing Languages
    2993: 96/03/10: Re: Reconfigurable Computing Languages
    3092: 96/03/30: Reconfigurable Computer Languages
    3523: 96/06/14: Reconfigurable Computing
    3692: 96/07/16: Re: What about the XC6200 ?
    3710: 96/07/19: Re: What about the XC6200 ?
    5102: 97/01/23: Re: XC6200 Announcement by VCC
    5151: 97/01/27: Re: Processorless FPGA computer help
    5152: 97/01/27: Re: XC6200 Announcement by VCC
    5192: 97/01/30: Re: Safety Critical Apps -> Xilinx Checker.
    5206: 97/01/30: Re: Reconfigurable Logic Query
    5208: 97/01/31: DES Challenge
    5285: 97/02/04: Re: DES Challenge
    5944: 97/03/28: Re: Xilinx XC6200 -- any sightings?
    6258: 97/05/05: Hollywood Blonde
    6373: 97/05/19: Re: Cheap way to develop for FPGAs?
    6409: 97/05/22: Re: Scientific American article on FPGAs
    6540: 97/06/02: Re: New Reconfigurable Computing newsgroup?
    6559: 97/06/03: Re: New Reconfigurable Computing newsgroup?
    6625: 97/06/06: Re: New Reconfigurable Computing newsgroup?
    6635: 97/06/07: Re: PCI how to
    6649: 97/06/09: Re: PCI how to
    6652: 97/06/09: Re: XC6200 Gate Count
    6739: 97/06/21: DES Cracked
    6790: 97/06/28: Re: FPGA prototype board
    7174: 97/08/10: Re: PCI Interface
    9649: 98/03/27: Re: Partially reconfigurable FPGA
    10214: 98/05/05: Re: Hotworks G1 step clock
    10234: 98/05/05: Re: HOT Works C++ Interface
    10317: 98/05/11: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
    10318: 98/05/11: Re: Xilinx Configuration Problem
    10391: 98/05/15: Re: Minimal ALU instruction set.
    10622: 98/06/06: Re: Evolutionary FPGAs
    10623: 98/06/06: Re: minimalist FPGA - C API for FPGA
    10624: 98/06/06: Re: minimalist FPGA - C API for FPGA
    10625: 98/06/06: Re: minimalist FPGA - C API for FPGA
    12734: 98/10/26: Re: New Evolutionary Electronics Book
    12767: 98/10/28: Re: FPGA Decouple Capacitor values
    12814: 98/10/30: Re: Xilinx mode pins.
    12816: 98/10/30: Re: 3.3V PCI without clamp diodes.
    12820: 98/10/30: Re: 3.3V PCI without clamp diodes.
    12822: 98/10/30: Re: Degradation of results from Xilinx F1.3 -> F1.4 -> F1.5
    12825: 98/10/30: Re: Design security again - the Actel solution
    12828: 98/10/30: Re: 3.3V PCI to 5V local bus interface?
    13568: 98/12/09: Re: Add-in board with FPGA Secondary Processor
    13861: 98/12/29: Re: FAQ Address Please
    15485: 99/03/25: Re: Free Xilinx Vendor Tools ... JBits
    15513: 99/03/28: Re: Free Xilinx Vendor Tools ... JBits
    15541: 99/03/29: Re: virtex partial reconfiguration
    15577: 99/03/31: Re: vcc virtex workbench
    15798: 99/04/14: Re: Info about FPGA/PLD
    15681: 99/04/07: Re: Best FPGA for High Speed DSP Logic?
    15693: 99/04/08: Re: ZBT to Virtex Interface at +100M
    15695: 99/04/08: Re: ZBT to Virtex Interface at +100M
    15781: 99/04/13: Re: VCC Hotworks
    15783: 99/04/13: Re: Does any one want to talk about Dynamic Configuration?
    15797: 99/04/14: Re: bitstream
    15818: 99/04/15: Re: Looking for 6200 FPGA
    15820: 99/04/15: Re: craig
    15822: 99/04/15: Re: bitstream
    15849: 99/04/16: Re: High speed reconfigurability
    15856: 99/04/16: Re: partial reconfiguration
    18407: 99/10/22: Re: XILINX: XDL - is this a secret?
    19696: 00/01/08: Re: Newbie question on CPU's
    20059: 00/01/25: Re: Xilinx programming from a Linux PC
    20170: 00/01/29: Re: picoJava & Xilinx
    20978: 00/03/01: Re: Xilinx PCI pinout ?
    21867: 00/04/04: Re: FPGA openness (JBits)
    21868: 00/04/04: Initialization of Ram in a marco
    21889: 00/04/05: Re: Initialization of Ram in a marco
    22590: 00/05/12: Re: Future of FPGAs?
    22635: 00/05/15: Re: Do you know xilinx FPGAs well?
    23827: 00/07/11: Re: Xilinx Logic Cell counts and carry chains
    23992: 00/07/19: Re: Xilinx Logic Cell counts and carry chains
    24091: 00/07/26: Re: Power PC with Xilinx - what do you think?
    24594: 00/08/14: Re: Help!!! Bit serial Baugh-Wooley multiplier
    29317: 01/02/13: Re: Can a Virtex control its own reconfiguration?
    32395: 01/06/25: Re: Xilinx Configuration Bitstream
    32432: 01/06/26: Re: Xilinx Configuration Bitstream
    32485: 01/06/27: Re: Stupid Xilinx Patent
    32619: 01/07/02: Undocumemted Xilinx Tools
    32634: 01/07/03: Re: poor man's floating point...
    32800: 01/07/09: Re: Virtexe Config problem
    32815: 01/07/09: Re: What chip!?
    32878: 01/07/10: Re: Virtex2: Is it possible to place distributed DPRAM
    32974: 01/07/13: Re: How do I distribute cores?
    32998: 01/07/14: Re: Shift and Add Multiplier With Signed Numbers
    39042: 02/01/30: Re: Dynamic Reconfiguration of single Xilinx FPGA
    40052: 02/02/26: Re: FPGA: JTAG CABLE
    40082: 02/02/27: Re: Xilinx XDL documentation
    40117: 02/02/28: Re: Here is an argument and can anyone help me out
    41083: 02/03/20: Re: questions from a newby
    41454: 02/03/28: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
    41457: 02/03/28: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
    41480: 02/03/29: Re: Clock termination affecting JTAG interface
    41483: 02/03/29: Re: Homebuilt Altera-programmer totally dead...
    41580: 02/04/02: Re: Configuring the Virtex II FPGA
    41665: 02/04/04: Re: hand placement
    41667: 02/04/04: Re: powerpc in virtex2pro
    41673: 02/04/04: Re: hand placement
    41753: 02/04/06: Re: How to probe internal signals from Xilinx netlist?
    41805: 02/04/08: Re: powerpc in virtex2pro
    41806: 02/04/08: Re: hand placement
    41809: 02/04/08: Re: How to probe internal signals from Xilinx netlist?
    41810: 02/04/08: Re: How to probe internal signals from Xilinx netlist?
    41812: 02/04/08: Re: Xilinx programmer
    41846: 02/04/09: Re: Low-cost FPGA + processor board?
    41865: 02/04/09: Re: Low-cost FPGA + processor board?
    41874: 02/04/09: Re: Low-cost FPGA + processor board?
    41879: 02/04/10: Re: Low-cost FPGA + processor board?
    41897: 02/04/10: Re: Low-cost FPGA + processor board?
    41916: 02/04/10: Re: ChipScope ILA, cable requirements
    41917: 02/04/11: Re: hand placement
    41948: 02/04/11: Re: Low-cost FPGA + processor board?
    41958: 02/04/11: Re: iMPACT FPGA detection error
    42019: 02/04/13: Re: Stupid .ngd file questions....
    42143: 02/04/16: Beta Testers Need for HOTMan
    42302: 02/04/19: Re: Xilinx Easypath- Selling parts with known defects
    42335: 02/04/20: Xilinx Parallel III cable and Solaris 8
    42539: 02/04/26: Re: Spartan II configuration
    42774: 02/05/02: Re: JTAG programmer (ick!)
    42775: 02/05/02: Re: XC4000 readback woes
    42995: 02/05/09: Re: Does an EDIF schematic editor exist?
    43029: 02/05/09: Re: PCI bus software for Xilinx PCI core
    43090: 02/05/13: Re: Architecture for high-level reconfigurable computing
    43134: 02/05/14: Re: Architecture for high-level reconfigurable computing
    43135: 02/05/14: Re: Architecture for high-level reconfigurable computing
    43680: 02/05/29: Re: Rounding Accumulator
    43682: 02/05/29: Re: JTAG ICE or programmer
    43683: 02/05/29: Re: Xilinx proprietary format?
    43711: 02/05/30: Re: Can we edit an RBT Configuration file for a Xilinx FPGA?
    43741: 02/05/31: Re: IO simulations
    43748: 02/05/31: Re: IO simulations
    43831: 02/06/04: Re: divide by 5
    43896: 02/06/05: Re: FPGA destruction possible?
    44032: 02/06/10: Re: Bad Behavior of JTAG Download on Altera CPLD with Other Devices
    44075: 02/06/11: Re: burning a design
    44254: 02/06/14: Re: Virtex Readback
    44425: 02/06/19: Re: Xilinx .bit file via jtag ?
    44426: 02/06/19: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
    44590: 02/06/24: Re: Bad Virtex2 devices - any similar experiences
    45202: 02/07/15: Re: Communication between FPGA and PC
    45613: 02/07/29: Re: Programming FLASH with Xilinx Parallel Cable III
    45852: 02/08/07: Re: Programming bits reverse engineering
    46083: 02/08/16: Re: Xilinx iMPACT/Parallel Port programming in Win XP soloution?
    46107: 02/08/19: Re: Manipulating Altera SOF Files
    46163: 02/08/20: Re: And detailed documentation about XDL format?
    46463: 02/08/30: Re: XNF vs. EDIF
    46464: 02/08/30: Re: Virtex-II partial reconfiguration flow diagram
    46573: 02/09/03: Re: Hardware Code Morphing?
    46618: 02/09/04: Re: xilinx contact with regard to qpro
    46742: 02/09/06: Re: Virtex-II bit-file and strange configuration command
    46775: 02/09/09: Re: Fault tolerant FPGA design
    47104: 02/09/17: Re: Readback size for virtex2
    47430: 02/09/25: Re: Spartan II JTAG reconfiguration bug - workaround
    47502: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
    47526: 02/09/27: Re: JTag question
    47920: 02/10/07: Re: String Matching Developments on FPGA's
    48094: 02/10/11: Re: Why can Xilinx sw be as good as Altera's sw?
    48139: 02/10/11: Worlds lowest cost FPGA
    48170: 02/10/12: Re: programming the FPGA by a microcontroller
    48172: 02/10/12: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
    48177: 02/10/12: Re: where can I find the FAQs for this news group???
    48241: 02/10/14: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
    48517: 02/10/18: Number of Fpga posts vs dsp..
    48518: 02/10/18: Re: Size of configuration bitstream for xcv50 (xilinx)
    48568: 02/10/21: Re: Size of configuration bitstream for xcv50 (xilinx)
    48589: 02/10/21: Re: Device support
    48787: 02/10/24: Re: Silly Virtex 2 Pro question...
    49055: 02/10/31: Re: How important is simulation?
    49056: 02/10/31: Re: Information--conference paper
    49550: 02/11/14: MiroTech
    49605: 02/11/17: Re: Virtex is the 4th Xilinx Fpga generation
    49642: 02/11/18: Re: Virtex is the 4th Xilinx Fpga generation
    49836: 02/11/22: Re: 8B/10B patent problems? IBM Patent # 4486739
    50108: 02/12/02: Re: string to int conversion
    50229: 02/12/05: Re: meaning of system gates vs. logic gates?
    50302: 02/12/08: Re: FPGA Downloader
    50554: 02/12/12: Re: Using smaller configuration device possible with Xilinx
    50561: 02/12/12: Re: what makes an implementation a patent?
    50586: 02/12/13: Re: Using smaller configuration device possible with Xilinx
    50669: 02/12/16: Re: what makes an implementation a patent?
    50673: 02/12/16: Re: what makes an implementation a patent?
    50915: 02/12/23: Re: distributed computing with Modesim
    50979: 02/12/24: Re: FPGA accelerated FPGA/ASIC tools
    50983: 02/12/24: Re: FPGA accelerated FPGA/ASIC tools
    51125: 03/01/02: Re: Any Xilinx Design Language(.xdl) document?
    51288: 03/01/10: Re: Virtex-II Pro misfire?
    51292: 03/01/10: Re: Virtex-II Pro misfire?
    51357: 03/01/11: Re: Partial reconfiguration
    51395: 03/01/13: Re: Open FPGA please!
    51447: 03/01/13: Re: Open FPGA please!
    51622: 03/01/17: Re: PCI Device/Vendor resource off line now...
    51733: 03/01/20: Re: Multi Project DIE
    52385: 03/02/07: Re: Xilinx Virtex-II Readback
    52485: 03/02/11: Re: JBits
    52564: 03/02/13: Re: JBits
    52588: 03/02/14: Re: Dynamic Reconfig Terminology
    52671: 03/02/18: Re: Communicating with a configured FPGA through the JTAG interface
    53821: 03/03/24: Re: Does Xilinx have self-boot option like Cypress?
    54074: 03/04/02: Re: What would it take?
    54487: 03/04/11: Re: VCC's HOT 2 development board
    54803: 03/04/18: Re: fpga_edline.exe
    54805: 03/04/18: Re: Help with this component: ADD_BITSLICE
    55460: 03/05/09: Re: Xilinx VirtexII Pro Rocket-IO
    55492: 03/05/10: Re: Encrypted bitstream - battery lifetime problem
    55531: 03/05/12: Re: Info about development kit
    55847: 03/05/21: Evolvable Hardware Class at UCLA
    55863: 03/05/22: Re: FPGA design: firmware or hardware?
    55882: 03/05/22: Re: FPGA design: firmware or hardware?
    55922: 03/05/23: Re: FPGA design: firmware or hardware?
    56535: 03/06/08: Re: Topic for Masters Project
    56564: 03/06/09: Re: Controlling FPGA speed with VCCINT
    56578: 03/06/10: Re: Xilinx Parallel Cable IV and non-captive software
    56641: 03/06/10: Re: What's in a bitstream?
    57001: 03/06/20: Re: Partial Reconfiguration with BITGEN
    57003: 03/06/20: Re: Partial Reconfiguration
    57435: 03/06/30: Re: why so many problems Xilinx ?
    57835: 03/07/08: Re: GSR
    57836: 03/07/08: Re: Dynamic Reconfiguration, Contentions
    57847: 03/07/08: Re: About BRAM in VirtexII
    57950: 03/07/10: Re: Looking for DIMM format FPGA board
    58134: 03/07/15: Re: Wanted: Orcad Capture symbol for Xilinx Spartan IIE XC2S300E PQ208
    58348: 03/07/21: Re: Logiblox library - help please!
    58620: 03/07/29: Re: FPGA research
    59059: 03/08/07: Re: Offshore engineering
    59231: 03/08/13: Re: PalmChip Patent
    59236: 03/08/13: Re: PalmChip Patent
    59926: 03/09/01: Re: Virtex-E Select-RAM refresh rate
    60317: 03/09/10: Re: pipelined divider
    60431: 03/09/12: Re: FPGA Reconfiguration Question
    60502: 03/09/15: Re: Downloading into XCV600 FPGA using PCI
    60579: 03/09/16: Re: Xilinx-gdb Sources publicly available?
    60707: 03/09/19: Re: Reconfiguration, Spartan 3, Compressed bit stream, ICAP
    60830: 03/09/23: Re: Regarding XC6216
    61090: 03/09/27: Re: FPGA implementation of a lexer and parser - feasible?
    61663: 03/10/08: Re: Problem with PCI cards
    61823: 03/10/13: Re: VCC's HOTman
    61833: 03/10/13: Re: VCC's HOTman
    62010: 03/10/16: Looking for Hot 2 Boards
    62014: 03/10/16: Re: Blocks RAM in HandelC
    62336: 03/10/27: Re: BoardScope
    62486: 03/10/30: Re: Xilinx XC95108 Chip
    63943: 03/12/09: Re: ASMBL - hmmm
    65008: 04/01/19: Re: Downloading to an FPGA
    65054: 04/01/19: Re: Where can I find Xilinx M1 tools
    65057: 04/01/19: Re: par problems with modular design for partial reconfiguration
    65380: 04/01/27: Re: PowerPC and JTAG
    65854: 04/02/09: Re: Virtex-3 PRO
    65855: 04/02/09: Re: Online debate: Programmable Logic vs ASIC vs Gate Array
    66404: 04/02/18: Re: GZIP algorithm in FPGA
    66590: 04/02/23: Re: FPGA vendors and their patents
    67210: 04/03/08: Re: 66B mode of VirtexII-ProX Rocket I/O
    69024: 04/04/25: Re: Byteblaster Download cable schematics not available from altera site
    69062: 04/04/26: Stretch Inc
    70493: 04/06/17: Re: compressing Xilinx bitstreams
    71149: 04/07/09: Re: comparison between FPGA and computer
    71479: 04/07/19: Re: IDE or ATA controler on a Fpga
Steve Charlwood:
    16976: 99/06/21: Question: Does FPGA Express 3.2 support RPMs?
    16977: 99/06/21: Request for information on discontinued Xilinx XC4000-series variants
    20704: 00/02/18: Interfacing multiple clock domains via FIFOs in XCV300
    20967: 00/03/01: Error in Xilinx application note XAPP131?
    42984: 02/05/08: Transistor Counts for Xilinx FPGAs
    45146: 02/07/13: What proportion of an FPGA's configuration data is used for routing?
    45152: 02/07/13: Re: What proportion of an FPGA's configuration data is used for routing?
    45165: 02/07/14: Re: What proportion of an FPGA's configuration data is used for routing?
    45253: 02/07/17: Re: Commercial FPGA Architectures
    52208: 03/02/04: Partitioning interconnect in Xilinx FPGAs
Steve Daphne Martindell:
    22056: 00/04/17: Virtex-EM speed files
Steve Darby:
    7114: 97/08/01: XILINX part changes
    7128: 97/08/04: Re: jtag isp guidance request
    7281: 97/08/21: Re: ISP Stories
Steve Dewey:
    3244: 96/05/02: What EPLD system to buy ?
    3304: 96/05/11: Anyone use Orcad PLD tools ?
    4420: 96/10/26: Altera Configuration EPROM Equivalents
    5467: 97/02/18: Re: Xilinx or Altera?
    6208: 97/04/27: Re: SIN/COS Functions in AHDL
    6230: 97/04/30: Anyone done an IEEE488 talker/listener in AHDL for Altera ?
    6942: 97/07/12: Re: Altera FLEX10K initialization
    7857: 97/10/23: Re: PROM for FLEX10K
    7934: 97/10/31: Re: [Reposted due to Enlow UCE cancel]: PROM for FLEX10K
    9081: 98/02/18: Re: Free FPGA tools???
    9880: 98/04/10: VHDL compiler differences ?
    9931: 98/04/14: Re: VHDL compiler differences ?
    10073: 98/04/25: Re: Why Altera & Cypress Software Clashes (was: VHDL compiler differences?)
    10857: 98/06/25: Re: AHDL
    12190: 98/10/03: Anyone used the Altera 74297 PLL function ?
    12197: 98/10/04: Re: Anyone used the Altera 74297 PLL function ?
    13670: 98/12/17: Re: Xilinx XC4000 cinfigured from EPC2?
    14465: 99/01/30: Re: PLL in FPGA
    14514: 99/02/02: Re: Opinions requested : Minc/Synario alternatives
    14999: 99/03/02: Re: LCD driver
    15036: 99/03/03: Re: Getting started in programmable logic
    19111: 99/11/29: Re: Xilinx FPGA Editor guessing games solved!
    19213: 99/12/06: Re: hobbyist friendly pld?
    19595: 00/01/03: Re: Design security
    19596: 00/01/03: Re: VGA controller in FPGA
    20085: 00/01/26: What has happened to freecore.com ?
    20086: 00/01/26: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
    21326: 00/03/16: Altera literature misleading
    22316: 00/05/04: Re: How to Prevent theft of FPGA design
    22268: 00/05/03: Re: Beginner's Guide
    22269: 00/05/03: Re: Bi-dir pass-thru w/switch in MAX+Plus II?
    22705: 00/05/18: Re: Q: Creating custom flip-flops in Altera MAX+Plus II
    23033: 00/06/09: Re: TTL device Libraries
    23084: 00/06/13: Re: Altera vs Xilinx
    26205: 00/10/08: Analogue FPGAs ?
Steve Diferdinando:
    20203: 00/01/31: Virtex DLL inoperability
Steve Duncan:
    32391: 01/06/25: Re: what tools run OK on windows 2000?
Steve Emm:
    8638: 98/01/15: Re: Byteblaster
Steve Fair:
    27121: 00/11/11: Re: CoolRunner news :(
    27120: 00/11/11: Re: PLL vs DLL
    27134: 00/11/12: Re: PLL vs DLL
    27240: 00/11/16: Re: Basic question on PLD & FPGA
    36212: 01/11/02: Re: Altera Local Routing
Steve Glow:
    77656: 05/01/13: Re: Starting with xilinix and Linux
Steve Golson:
    280: 94/10/12: CALL FOR PAPERS -- 1995 PLD DESIGN CONFERENCE
steve goodwin:
    5266: 97/02/03: Re: Altera support better than Xilinx
    5871: 97/03/21: Re: Multiple clocks in Xilinx
    7310: 97/08/24: Re: ISP Stories
    7309: 97/08/24: Re: Unbonded Pad Resources
Steve Goodwin:
    7626: 97/09/29: Re: Still for sale OrCAD SDT & Xilinx XACT
    7663: 97/10/01: Re: vme vs compact pci
    8025: 97/11/08: Re: scsi host adapter
    8150: 97/11/21: Re: what is metastability time of a flip_flop
    8504: 97/12/29: Re: Xilinx XACT 2.10 memory error
    8507: 97/12/29: Re: Xilinx XACT 2.10 memory error
    8846: 98/02/01: Re: VHDL vs schematics
    27480: 00/11/23: Re: jobs for FPGA designer (remote)
    130311: 08/03/20: Re: A Challenge for serialized processor design and implementation
    130330: 08/03/20: Re: A Challenge for serialized processor design and implementation
Steve Gross:
    3902: 96/08/16: Xilinx: question about bitstream and parallel download
    4596: 96/11/19: Configuring Xilinx XC4000 device in Asynch. Peripheral Mode
    5750: 97/03/12: Xilinx/NeoCAD software vs. XC4KE question
    6761: 97/06/25: Re: Asynchronous Peripheral Download Mode, Probs
    7477: 97/09/15: Mentor, __qp_prim, and Xilinx symbol libraries
    8282: 97/12/05: Re: A suggestion for Xilinx
    11077: 98/07/17: Re: Floorplanning Intro?
    13433: 98/12/02: Xilinx Guided par
    18268: 99/10/11: Xilinx Alliance 2.1i Virus
    18646: 99/11/04: Tuesday night
    20677: 00/02/17: Re: RLOC_RANGE property.
Steve Guccione:
    24: 94/07/29: Re: FPGA based processors ?
    268: 94/10/10: List of FPGA-based Computing Machines (10/94)
    269: 94/10/10: List of FPGA based Computing Systems
    296: 94/10/14: ANNOUNCE: WWW Page of FPGA-based Computing machines
    424: 94/11/14: Updated List of FPGA-based Computing Machines
    507: 94/12/13: Re: L-Edit and Benchmarks
    894: 95/03/22: List of FPGA-based computing machines
    923: 95/03/30: Re: Neocad merges with Xilinx
    1734: 95/08/21: Re: List of FPGA Based Computing Machines
    3033: 96/03/18: Re: Reconfigurable Computing Languages
    3034: 96/03/18: Re: Reconfigurable Computing Languages
    3202: 96/04/24: Re: On FPGAs as PC coprocessors
    3222: 96/04/29: Re: Looking for FPGA Boards taking Xilinx 4000 series FPGA
    3228: 96/04/30: Re: On FPGAs as PC coprocessors
Steve Harlow:
    54760: 03/04/17: fpga_edline.exe
Steve Higgins:
    32324: 01/06/22: Re: Xilinx webpack annoyances (long and whiny)
Steve Hoeft:
    527: 94/12/20: Re: Analog FPGA ???
    2611: 96/01/10: ECL PALs or FPGAs
Steve Holle:
    3085: 96/03/28: Re: Troubles with Altera Bitblaster
    22813: 00/05/25: Programming using *.rbt file
    22838: 00/05/26: Re: Programming using *.rbt file
    22925: 00/06/02: Convert Xilinx Foundation ourput to C/C++ compatible file.
    22944: 00/06/05: Re: Convert Xilinx Foundation ourput to C/C++ compatible file.
    24724: 00/08/17: Re: Non-disclosures in job interviews
Steve Holmes:
    1550: 95/07/13: Re: Flex 8000: Locking down pins
    1696: 95/08/17: Re: FPGAs with embedded RAM
    18047: 99/09/25: Re: Evolvable Hardware
Steve Holmes NT:
    222: 94/09/27: Re: Xilinx 4000
Steve Holroyd:
    38325: 02/01/11: APEX-II vs VIRTEX-II
    38587: 02/01/18: Re: APEX-II vs VIRTEX-II
    38589: 02/01/18: Fast LVDS Backplanes
    40084: 02/02/26: Re: APEX-II vs VIRTEX-II
Steve Hurlock:
    51098: 03/01/01: bitfile back to ncd?
Steve Jones:
    2408: 95/12/01: Industry Trends
Steve Joures:
    44822: 02/07/02: DC to DC converter at 1.5V
    44890: 02/07/04: Routing Virtex-II 256 pin BGA on 4 layers
Steve Kerman:
    12664: 98/10/22: Re: State machines in VHDL/Verilog
Steve Kinkead:
    17705: 99/08/25: Re: Virtex BRAM Initialization
    17994: 99/09/21: Vertex Select I/O
Steve Knapp:
    2475: 95/12/13: Re: Median filter
    52989: 03/02/27: Re: spartan III what is it?
    54666: 03/04/15: Re: Xilinx has released SpartanIII
    54667: 03/04/15: Re: Xilinx has released SpartanIII
    54723: 03/04/16: Re: spartan 3 pin compatible with 2E?
    54724: 03/04/16: Re: Xilinx has released SpartanIII
    54778: 03/04/17: Re: spartan2e vs cyclone
    54781: 03/04/17: Re: spartan-3 vs cyclone
    54783: 03/04/17: Re: spartan2e vs cyclone
    54789: 03/04/17: Re: spartan2e vs cyclone
    130484: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130526: 08/03/26: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    130528: 08/03/26: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
    132782: 08/06/06: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
    132785: 08/06/06: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
    132826: 08/06/07: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
    132827: 08/06/07: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
    132828: 08/06/07: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
    132829: 08/06/07: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
    132918: 08/06/10: Re: Whitepapers are taking over the lost TechXclusives
    135118: 08/09/16: Re: Ultra low power FPGAs
    135194: 08/09/19: Re: Peter says Good Bye
    135195: 08/09/19: Re: LED lights flashing while LCD shows chars, Spartan-3A
    135278: 08/09/23: Re: Xilinx Mode Select Pins
    135310: 08/09/25: Re: Peter says Good Bye
Steve Knapp (a):
    127826: 08/01/08: Re: Please, help - I have got confused about package type
Steve Knapp (Xilinx Spartan-3 Generation FPGAs):
    88119: 05/08/09: Re: What are IO standard defaults in S3 ?
    88207: 05/08/11: Re: Welcome back Mr. Knapp
    88523: 05/08/21: Re: Welcome back Mr. Knapp
    93251: 05/12/16: Re: Avnet hav2 s3e starter kit?
    93252: 05/12/16: Re: Avnet hav2 s3e starter kit?
    93253: 05/12/16: Re: Avnet hav2 s3e starter kit?
    93254: 05/12/16: Re: Avnet hav2 s3e starter kit?
    94802: 06/01/17: Re: Samples
    94800: 06/01/17: Re: S3e slower than S3
    94801: 06/01/17: Re: xilinx free Sample Pack info now also on Xilinx own webpages
    95884: 06/01/26: Re: Spartan-3 Starter Board
    95741: 06/01/25: Re: Spartan-3 Starter Board
    95739: 06/01/25: Re: Spartan3 DC datasheet
    96369: 06/02/02: Re: Spartan3 pullups
    96804: 06/02/10: Re: Spartan3 embedded synchronous multipliers
    97609: 06/02/24: Re: 8051 IP core with JTAG debugger for FPGA?
    98741: 06/03/15: Re: CSV files available for Xilinx FPGA parts pinouts?
    98750: 06/03/15: Re: CSV files available for Xilinx FPGA parts pinouts?
    99651: 06/03/27: Re: FPGA : HSWAP
    100034: 06/04/01: Re: Configuration pins on Spartan-3
    100035: 06/04/01: Re: Configuration pins on Spartan-3
    100037: 06/04/01: Re: Spartan3E Phase-Shifter
    100173: 06/04/04: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
    100175: 06/04/04: Re: about the low power design
    100176: 06/04/04: Re: about the low power design
    100241: 06/04/05: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
    100244: 06/04/05: Re: LVDS in Cyclone-II
    100334: 06/04/06: Re: rather simple gsr Q
    100336: 06/04/06: Re: LVDS in Cyclone-II (or in Spartan-3E)
    100387: 06/04/07: Re: rather simple gsr Q
    100388: 06/04/07: Re: Xst warning, dangling RAMB16B output
    100395: 06/04/07: Re: rather simple gsr Q
    100396: 06/04/07: Re: LVDS in Cyclone-II (or in Spartan-3E)
    100597: 06/04/12: Re: Spartan3E readback, SPI programming
    100598: 06/04/12: Re: Spartan 3E Starter Kit is finally here!
    100655: 06/04/14: Re: Spartan 3 chips in power up
    100658: 06/04/14: Re: humble suggestion for Xilinx
    100763: 06/04/17: Re: Which is the best way to measure low frequencies?
    100764: 06/04/17: Re: Spartan 3 chips in power up
    100813: 06/04/18: Re: FPGA + FTDI
    100815: 06/04/18: Re: FPGA + MAC board?
    100816: 06/04/18: Re: Spartan 3 chips in power up
    101116: 06/04/25: Re: SPARTAN3E SK LCD
    101117: 06/04/25: Re: Spartan 3 documentation confusing...
    101119: 06/04/25: Re: ISE 8.1i for Linux ?
    101410: 06/04/30: Re: Xilinx PROM
    102460: 06/05/16: Re: Xilinx or Altera...
    102491: 06/05/16: Re: Xilinx or Altera...
    102493: 06/05/16: Re: Spartan 3E
    102894: 06/05/22: Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
    113041: 06/12/05: Re: Spartan3 Configuration Puzzler
    113043: 06/12/05: Re: Spartan-3A launched
    113046: 06/12/05: Re: Spartan-3A launched
    113048: 06/12/05: Re: Spartan-3A launched
    113181: 06/12/07: Re: differential I/O with ISE 8.2 / spartan3E
    113336: 06/12/11: Re: Spartan-3A launched [Device DNA, Right Page, Corrected URL]
    115970: 07/02/26: Re: Spartan-3AN
    115971: 07/02/26: Re: Spartan-3AN
    115972: 07/02/26: Re: XC3S400 and XC3S500E in PQ208
    115999: 07/02/27: Re: Spartan-3AN
    116002: 07/02/27: Re: Spartan-3AN
    116073: 07/02/28: Re: Spartan-3AN
Steve Knapp (Xilinx, Inc.):
    2527: 95/12/28: Re: Xiling 4025E routing info (Multiplier Arrays)
    2544: 95/12/30: Re: Programmable Interconnect ICs
    2691: 96/01/24: Re: Revision Figure of Merit?
    2693: 96/01/24: Re: HowTo access a SRAM with a XC4000
    2857: 96/02/18: Re: Help ! Xilinx FPGA -> ASIC conversion
    2858: 96/02/18: Re: Info wanted on high speed(3-5ns) FPGA's
    2895: 96/02/26: Re: Xilinx 8100 Series
    3088: 96/03/29: Re: PCI Support...
    3192: 96/04/22: Re: Looking for FPGA Boards taking Xilinx 4000 series FPGA
Steve L:
    23603: 00/07/02: First time chip design. Is my roadmap correct ?
Steve Lass:
    392: 94/11/05: Re: Xilinx chip partitioning
    1262: 95/05/23: Re: Multi-chip partitioning for XC4k devices
    1267: 95/05/24: Re: What's happening with NeoCAD?
    6735: 97/06/20: Re: What is M1?
    7198: 97/08/13: Re: Should Xiling have more local clock nets?
    7250: 97/08/18: Re: Should Xiling have more local clock nets?
    7652: 97/10/01: Re: Xilinx M1 Back Annotated SDF Question
    51445: 03/01/13: Re: Open FPGA please!
    51494: 03/01/14: Re: Open FPGA please!
    51497: 03/01/14: Re: Open FPGA please!
    51586: 03/01/16: Re: Support for older Virtex
    51630: 03/01/17: Re: Support for older Virtex
    51642: 03/01/17: Re: Support for older Virtex
    51744: 03/01/20: Re: Support for older Virtex
    52014: 03/01/28: Re: XC3020 .nph
    52106: 03/01/31: Re: Xilinx Design Softwares?
    52160: 03/02/03: Re: Xilinx Design Softwares?
    52234: 03/02/04: Re: What's the difference: WebPack 5.1 vs. Xilinx Student Edition 4.2i ?
    52376: 03/02/07: Re: blockram initialization
    52994: 03/02/27: Re: VHDL & FPGA Design tools
    53683: 03/03/19: Re: unsupported switches of PAR
    54030: 03/03/31: Re: microblaze gnu tool info ?
    54426: 03/04/10: Re: Webpack 5.2 and Win98se
    55634: 03/05/14: Re: OK I am pissed off with Xilinx webpack.
    55642: 03/05/14: Re: OK I am pissed off with Xilinx webpack.
    56027: 03/05/27: Re: 2 Questions about VHDL
    56806: 03/06/16: Re: Spartan3 in WebPack
    56908: 03/06/18: Re: Spartan3 in WebPack
    56953: 03/06/19: Re: Spartan3 in WebPack
    56998: 03/06/20: Re: Spartan3 in WebPack
    57025: 03/06/20: Re: How to trace the FPGA signals without a logical analyzer?
    57217: 03/06/25: Re: Xilinx Webpack bugs bugs bugs
    57269: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
    57327: 03/06/27: Re: Partial reconfiguration of Vertex-2 devices.
    57335: 03/06/27: Re: Partial reconfiguration of Vertex-2 devices.
    57498: 03/07/01: Re: Xilinx ISE drops support for more parts
    57583: 03/07/02: Re: Xilinx ISE drops support for more parts
    57593: 03/07/02: Re: why so many problems Xilinx ?
    57654: 03/07/03: Re: Xilinx ISE drops support for more parts
    57680: 03/07/03: Re: Xilinx ISE drops support for more parts
    57799: 03/07/07: Re: Spartan XL Tool Support
    57800: 03/07/07: Re: Exceptional conditions on XST.
    58549: 03/07/25: Re: Multi Pass Place & Route
    58798: 03/08/01: Re: Spartan 3 support in Webpack
    58799: 03/08/01: Re: AREA_GROUP constraint for Xilinx FPGAs
    59063: 03/08/07: Re: Does Xilinx Webpack 5.2 work on WinNT SP6?
    59232: 03/08/12: Re: Upgrading OS or WebPack
    59339: 03/08/15: Re: Old Xilinx FPGAs
    59637: 03/08/25: Re: Xilinx Webpack 5.2i tutorial
    60163: 03/09/05: Re: EDK problem!
    60263: 03/09/09: Re: Programming Xilinx CPLD under linux
    60501: 03/09/15: Re: WebPack - mixed design flow
    60888: 03/09/24: Re: ISE 6.1 and Redhat 9
    60904: 03/09/24: Re: ISE 6.1 and Redhat 9
    60946: 03/09/25: Re: ISE 6.1 and Redhat 9
    60951: 03/09/25: Re: ISE 6.1 and Redhat 9
    61061: 03/09/26: Re: Partial Reconfiguration, ISE 6.1
    61062: 03/09/26: Re: ISE 6.1 and Redhat 9
    61144: 03/09/29: Re: Free WebPack 6.1i Download Available Now for Spartan-3
    61233: 03/09/30: Re: ISE: Parallel Processing
    61379: 03/10/02: Re: High-performance workstation
    61384: 03/10/02: Re: Xilinx XST 6.x and Verilog-2001?
    61672: 03/10/08: Re: 5V Tolerant Spartan 2
    61901: 03/10/14: Re: How to program an XC5210
    61949: 03/10/15: Re: Partial Reconfiguration
    62018: 03/10/16: Re: Partial Reconfiguration
    62058: 03/10/17: Re: How to get Synplify 7,0 Pro and Xilinx EDK 3,2 work together.
    63097: 03/11/14: Re: XILINX Foundation Series 3_1i Problem with installation...
    63099: 03/11/14: Re: XST Timing report
    63392: 03/11/20: Re: Xilinx legacy situation
    63562: 03/11/25: Re: area constraints
    63612: 03/11/26: Re: area constraints
    63710: 03/12/01: Re: modular design flow in Xilinx ISE 6.1.
    63914: 03/12/08: Re: Using FPGA Editor to introduce PULLUP and PULLDOWN
    64076: 03/12/15: Re: download ise foundation
    64082: 03/12/15: Re: download ise foundation
    64157: 03/12/18: Re: Help me converting Mathlab code to VHDL? DSPBuilder or SystemGenerator
    64248: 03/12/22: Re: Parallel Cable 4 & Linux
    64365: 03/12/30: Re: Parallel Cable 4 & Linux
    64893: 04/01/15: Re: Microblaze simulation
    68489: 04/04/06: Re: minimum software for virtex II pro
    68609: 04/04/09: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
    73592: 04/09/24: Re: Webpack 6.3 and Spartan3-1000/1500?
    75118: 04/10/26: Re: Hello Xilinx folks -- please answer
    75122: 04/10/26: Re: Webpack 6.3i support for Spartan 3
    75135: 04/10/26: Re: Webpack 6.3i support for Spartan 3
    75940: 04/11/19: Re: Ordering Xilinx BaseX software for Linux
    82369: 05/04/11: Re: where can i get xilinx ise 7.1 evalution ?
    96628: 06/02/07: Re: latest XILINX WebPack is totally broken
    96735: 06/02/09: Re: latest XILINX WebPack is totally broken
    97017: 06/02/14: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    97375: 06/02/21: Re: WebPACK license (and Quartus Web Edition too).
    97376: 06/02/21: Re: ISE Simulator Price
    98010: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98122: 06/03/05: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98236: 06/03/07: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98697: 06/03/14: Re: Why does Xilinx hate version control?
    98731: 06/03/15: Re: Why does Xilinx hate version control?
    98746: 06/03/15: Re: synthesis time with XST
Steve Lee:
    2722: 96/01/29: ABEL
Steve Letkeman:
    18731: 99/11/10: Re: CAN tools reccomendations?
Steve Logue:
    23850: 00/07/12: How may ns should a 32-bit add take ?
Steve Lovell:
    18728: 99/11/10: Re: CAN tools reccomendations?
Steve Martindell:
    6765: 97/06/25: FPGA prototype board
    11554: 98/08/23: Looking for info on modified booth
    17914: 99/09/16: Xilinx development board > XVC400
    18016: 99/09/23: Synopsys inside Foundation 2.1i does not infer fast-adder
    19338: 99/12/14: memory init file format for Foundation simulator ?
Steve Maudsley:
    72108: 04/08/09: Re: What is the future of superconducting circuits
Steve McDowell:
    11967: 98/09/21: Re: What is the current revision of the Xilinx M1.x s/w?
    17619: 99/08/15: Best synthesis tools for virtex?
    17934: 99/09/17: Re: speeding up place and route
Steve Mensor:
    47552: 02/09/28: Re: Altera Cyclone low-cost FPGA chips?
Steve Merritt:
    68572: 04/04/08: Re: Multiple DCM ? (Virtex II)
    68667: 04/04/13: Re: VirtexII : XC2V2000 Design
    68668: 04/04/13: Re: Is Xilinx Parallel Cable III OK For Memec V2Pro / Xilinx EDK?
    68670: 04/04/13: Re: Problem using EDK tutorial for Memec board with Synplicity.
    68693: 04/04/14: Re: VirtexII : XC2V2000 Design
    68695: 04/04/14: Re: what is a better approach to synthezise synchronous reset on FPGA?
    68696: 04/04/14: Re: VirtexII : XC2V2000 Design
    68717: 04/04/15: Re: what is a better approach to synthezise synchronous reset on FPGA?
Steve Methley:
    2724: 96/01/30: Re: VHDL/Verilog training
    3446: 96/05/31: Re: Help on ALtera FPGA configuration
Steve Meyer:
    40937: 02/03/18: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
    41036: 02/03/20: Announce: Commercial/Non-Commercial Verilog simulator
    43949: 02/06/07: Scientific puzzle of formal circuit verification at next week's DAC
    44005: 02/06/09: Re: Scientific puzzle of formal circuit verification at next week's DAC
Steve Michaels:
    53046: 03/03/01: Verilog/FPGA help needed
Steve Mitchell:
    8919: 98/02/07: Re: Asic to FPGA
    9063: 98/02/18: Simulator & Synthesis Engine Comparisons
    9148: 98/02/25: Re: ¿Altera to Xilinx? ¿Max+Plus II to Foundation??
    9149: 98/02/25: Re: Leonardo/VHDL and pullups in FPGAs.
    9351: 98/03/07: ModelSim, Active-VHDL simulators
    10543: 98/05/29: Xilinx 5200 - XACT 6.0.1 vs. M1.4
Steve Moulding:
    95115: 06/01/20: Re: OT:Shooting Ourselves in the Foot
Steve Newman:
    12898: 98/11/03: Re: New free FPGA CPU
    12920: 98/11/04: Re: New free FPGA CPU
Steve Nordhauser:
    5860: 97/03/20: Re: Development board with multiple FPGAs
    8890: 98/02/05: Job Posting: FPGA Video Processing
    13621: 98/12/14: Re: FPGA Data compression
    17163: 99/07/06: Re: A better way to access this newsgroup
    17834: 99/09/09: Re: Virtex dev boards
    27422: 00/11/21: Low Power FPGA?
    27524: 00/11/27: Re: Low Power FPGA?
    28248: 01/01/03: Re: driving color VGA from FPGA ??
Steve O'Hara-Smith:
    28557: 01/01/17: Re: revision control tools ??
Steve Oldridge:
    23782: 00/07/07: Re: Canadian University
    23781: 00/07/07: Xilinx 6200 series data sheets
    25044: 00/08/24: Re: create a RAM in a Virtex
    27406: 00/11/20: HELP! Lucent ORCA datasheets needed!
Steve Perrin:
    97170: 06/02/17: low level ethernet interface driver
Steve Phillipson:
    10117: 98/04/28: Adapter
Steve Pope:
    2671: 96/01/22: Re: How Big Chips Will Be Designed In The Not Too Distant Future
    2701: 96/01/25: Re: How Big Chips Will Be Designed In The Not Too Distant Future
    3867: 96/08/12: Re: Technical Job posting ( and ads) not related to the newsgroup.
    141458: 09/06/24: Re: 720 Mhz IF Processing
    141488: 09/06/25: Re: 720 Mhz IF Processing
    143583: 09/10/17: Re: Softcore for ADSP-2181/2191
    148524: 10/07/29: Re: Data-path accuracy in IIR filters?
    148530: 10/07/30: Re: Data-path accuracy in IIR filters?
    148538: 10/07/30: Re: Data-path accuracy in IIR filters?
    148539: 10/07/30: Re: Data-path accuracy in IIR filters?
    148542: 10/07/31: Re: Data-path accuracy in IIR filters?
    148545: 10/07/31: Re: Data-path accuracy in IIR filters?
    148547: 10/07/31: Re: Data-path accuracy in IIR filters?
    148551: 10/08/01: Re: Data-path accuracy in IIR filters?
    148555: 10/08/01: Re: Data-path accuracy in IIR filters?
    148556: 10/08/01: Re: Data-path accuracy in IIR filters?
    148560: 10/08/01: Re: Data-path accuracy in IIR filters?
    148570: 10/08/02: Re: Data-path accuracy in IIR filters?
    148584: 10/08/03: Re: Xilinx ISE Webpack and Pipeline Optimization
    152846: 11/10/27: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
Steve Prokosch:
    28354: 01/01/09: Re: FPGA starter kit recommendations
    46712: 02/09/06: Re: question about quiescent current
    47131: 02/09/18: Re: Can I run a 3.3V CPLD off of 3V?
    47756: 02/10/03: Re: Low power design
    57506: 03/07/01: Re: NAND flash file
    63379: 03/11/20: Re: Small PLD choices
    63396: 03/11/20: Re: 400 Mb/s ADC
Steve Ravet:
    143977: 09/11/05: Does anyone ever use placement?
    144008: 09/11/06: Re: Does anyone ever use placement?
    144058: 09/11/09: Re: OK Xilinx users, it's time I was let in on the joke...
    144079: 09/11/10: Re: How to script Xilinx ISE - xflow, batch file, tcl, ?
    144113: 09/11/11: Re: OK Xilinx users, it's time I was let in on the joke...
    144287: 09/11/24: Re: Deskew Reginal clock input
    148890: 10/09/08: clock net placement and routing
    148924: 10/09/10: Re: clock net placement and routing
    149454: 10/10/26: using FPGA editor to set IOSTANDARD
    149457: 10/10/26: Re: using FPGA editor to set IOSTANDARD
    149467: 10/10/27: Re: using FPGA editor to set IOSTANDARD
    149468: 10/10/27: using FPGA editor to add a new output pin
    149470: 10/10/27: Re: using FPGA editor to add a new output pin
    149474: 10/10/27: Re: using FPGA editor to add a new output pin
    149542: 10/11/03: Re: Combined Microprocessor and FPGA
    149595: 10/11/09: Re: ucf impact to synplify pro
    150601: 11/01/27: Re: ISE 12.4
    150625: 11/01/28: Re: ISE 12.4
    150677: 11/02/02: Re: FPGA changes behaviour when the resource's usage percentage changes
steve ravet:
    149063: 10/09/27: Re: Stack Exchange site for programmable logic and FPGA design
    149072: 10/09/28: Re: Adding PLB Module to AMBA
    149317: 10/10/15: Re: Old LOC constraint stuck somewhere
    149318: 10/10/15: Re: Regarding Synchronization of multiple control signals
    149355: 10/10/18: Re: Regarding Synchronization of multiple control signals
    149408: 10/10/22: Re: Combined Microprocessor and FPGA
Steve Rencontre:
    13641: 98/12/15: Re: Dedicated pin in ALTERA 10K familly
    14384: 99/01/28: Re: AHDL VS. VHDL
    15231: 99/03/16: Re: multiport register file--Altera Flex10k20 ?
    15232: 99/03/16: Re: programming cplds and serial roms and fpgas
    15434: 99/03/24: Re: HELP ME : About JTAG on Altera Flex 10k
    15506: 99/03/28: Re: Free Xilinx Vendor Tools ... JBits
    16321: 99/05/15: Re: Fancy Dram problem
    16370: 99/05/19: Re: JTAG program Altera and Xilinx same chain?
    16646: 99/06/01: Re: FPGA express + VHDL: strange SR implementation?
    16647: 99/06/01: Re: Printing to picture files
    16645: 99/06/01: Re: YOURE NOT GOING TO BELIEVE THIS! 7449
    17684: 99/08/24: Re: JTAG 1149 Info
    17802: 99/09/06: Re: Newbie question: Reading FPGA programming?
    18008: 99/09/23: Re: Reset signal and Altera's FPGAs
    18066: 99/09/27: Re: Altera hierarchical design
    18246: 99/10/09: Re: Can't detect Flex 10K Altera device through JTAG port
    18299: 99/10/13: Re: Can't detect Flex 10K Altera device through JTAG port
    18787: 99/11/16: Re: configure_flex10k30e_jtag_jam
    18930: 99/11/22: Re: Altera JAM
    19009: 99/11/24: Re: VHDL vs. schematic entry
    19448: 99/12/22: Re: JamPlayer and 10K10
    19517: 99/12/29: Re: status during ISP
    19778: 00/01/12: Re: Design security
    19809: 00/01/13: Re: Altera Flex10K bitstream compatibility ?
    19842: 00/01/14: Re: Design security
    20879: 00/02/25: Re: PWM implementation in Flex 10K.
    21335: 00/03/17: Re: Difference between FPGA, PLD, CPLD ?
    21515: 00/03/24: Re: How to solder FPGA in BGA package ?
    21817: 00/04/02: Viewlogic ViewSim/Vwaves question
    23124: 00/06/15: Re: Simple JTAG programmer for Altera MAX 7128A?
    23351: 00/06/23: Re: Simple JTAG programmer for Altera MAX 7128A?
    23399: 00/06/24: Re: dual processor PC for PPR - are they worth the extra cost?
    23400: 00/06/24: Re: Looking for 'FREE' FPGA software
    23434: 00/06/25: Re: dual processor PC for PPR - are they worth the extra cost?
    23574: 00/07/01: Re: Free PCI core
    23575: 00/07/01: Re: PCI with Xilinx controller
    23711: 00/07/06: Re: Graphic LCD controller design
    23884: 00/07/14: Re: Remedies after the Fathers' Day Massacre
    24182: 00/07/28: OT: was: Re: Which one is good coding style?
    24240: 00/07/31: Re: OT: was: Re: Which one is good coding style?
    24255: 00/08/01: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
    24317: 00/08/03: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
    24318: 00/08/03: Re: 32-input AND and 100-input OR - can I do it fast?
    24672: 00/08/16: Re: JTAG, Xilinx, Winnt, and the Parallel Port
    24935: 00/08/22: Re: Mealy vs Moore FSM model
    24936: 00/08/22: Re: Leonardo Spectrum with Altera - am I being stupid???
    24888: 00/08/21: Leonardo Spectrum with Altera - am I being stupid???
    26089: 00/10/03: Re: Altera FPGA experts needed
    26152: 00/10/05: Re: pci host
    26178: 00/10/06: Re: pci host
    26700: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
    26735: 00/10/26: Re: How safe is the algorithm implemented with FPGA?
    26637: 00/10/23: Re: xilinx floor planner issues
    26670: 00/10/24: Re: New PACT 50 GOP Reconfigurable Processor
    26852: 00/11/01: Re: Alliance under Linux?
    26948: 00/11/04: Re: ACEX1K vs FLEX10K
    26960: 00/11/05: Re: ACEX1K vs FLEX10K
    27045: 00/11/08: Re: 'event synthesis question
    27070: 00/11/09: Re: unique serial nr
    27100: 00/11/10: Re: Leonardo for Altera
    27528: 00/11/27: Re: Altera MAX+PlusII v.s. Xilinx Foundation
    28566: 01/01/17: Re: Altera Jam player on SHARC
    28580: 01/01/17: Re: CMOS or TTL
    29006: 01/02/01: Re: Encryption is supported in new Virtex II but.....
    29007: 01/02/01: Re: Encryption is supported in new Virtex II but.....
    29023: 01/02/02: Re: Encryption is supported in new Virtex II but.....
    29470: 01/02/22: Re: Programming Altera CPLD?
    29501: 01/02/23: Re: Is anybody using Quicklogic PCI/FPGA devices?
    29526: 01/02/25: Re: Is anybody using Quicklogic PCI/FPGA devices?
    29552: 01/02/26: Re: Is anybody using Quicklogic PCI/FPGA devices?
    29697: 01/03/05: Re: Full Time - No contractors
    29728: 01/03/06: Re: Full Time - No contractors
    30888: 01/05/02: Re: VHDL coding question.
    30889: 01/05/02: Re: Shannon Capacity
    30890: 01/05/02: Re: Shannon Capacity
    31256: 01/05/16: Re: PCI The Real Hardware
    31257: 01/05/16: Re: Counter problem in Altera AHDL...
    31378: 01/05/21: Re: JTAG and Debugging
    31406: 01/05/22: Re: JTAG and Debugging
    31937: 01/06/08: Re: Flash programming via FPGA's JTAG ????
    31959: 01/06/09: Re: Async FIFO in maxplus2
    38092: 02/01/04: Re: multiplexing a clock
Steve Richfield:
    152555: 11/09/14: The Manifest Destiny of Computer Architectures
Steve Schossow:
    5203: 97/01/30: Altera BitBlaster
    5331: 97/02/07: Altera BitBlaster/ByteBlaster replacement
Steve Sharp:
    67431: 04/03/11: Re: Does iseWebPack 6.2w has FPGA-Editor inside?
Steve Shaver:
    34912: 01/09/13: Re: FPGA--? huh
Steve Smith:
    68734: 04/04/15: Spartan 3 POR Spec?
Steve Su:
    26294: 00/10/10: Modular Exponentiation
Steve Sutherland:
    4739: 96/12/10: Xilinx configuration PROM
Steve Swam:
    1651: 95/08/10: Re: Xilinx PROMs
    1975: 95/09/27: Protel Xilinx Libraries
Steve Sweet:
    19621: 00/01/04: Altera, Lattice, Xilinx
steve synakowski:
    42056: 02/04/14: Re: FPGA config without boot PROM???
    44494: 02/06/21: Coolrunner Orcad, Pads ChipScale packages?
    44788: 02/07/01: Can Coolrunner's be daisy chained?
    44796: 02/07/01: Re: Can Coolrunner's be daisy chained?
    44800: 02/07/01: Re: Can Coolrunner's be daisy chained?
    46268: 02/08/23: XPLA3 coolrunner erased i/o state?
    46273: 02/08/23: Re: XPLA3 coolrunner erased i/o state?
    46730: 02/09/06: Synthesis problem, my inputs are never used?
    55875: 03/05/22: Re: Asynchronous State Machines and HDLs
Steve T Shannon:
    45142: 02/07/13: serial configuration in parallel? Xilinx Spartan-II
    49831: 02/11/21: 8B/10B patent problems? IBM Patent # 4486739
    50328: 02/12/09: clock recovery suggestions
    50341: 02/12/09: Re: clock recovery suggestions
    52679: 03/02/19: Quick FPGA PCI I/O in Spartan-IIE for single peripheral
    52736: 03/02/20: Re: Quick FPGA PCI I/O in Spartan-IIE for single peripheral
    52737: 03/02/20: Re: Quick FPGA PCI I/O in Spartan-IIE for single peripheral
    52830: 03/02/24: two-clock FSM?
    64880: 04/01/15: Spartan-IIE as an ASYNC RAM?
    64922: 04/01/16: Re: Spartan-IIE as an ASYNC RAM?
Steve Trimberger:
    380: 94/11/02: FPGA Books (Was: Altera Flex project)
    1892: 95/09/15: Design Automation Conference
Steve Underwood:
    37693: 01/12/19: Re: Kindergarten Stuff
    38544: 02/01/17: Re: Signal processing using FPGAs
    85970: 05/06/19: Re: Idea exploration - Image stabilization by means of software.
    87370: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87415: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87444: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87472: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87485: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87556: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87557: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87777: 05/08/01: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    92589: 05/12/02: Re: Quick question, how do I supply +-5V?
    102726: 06/05/19: Re: Output gain adjuster of digital filters
    107705: 06/09/01: Re: Performance Appraisals
    107708: 06/09/01: Re: Performance Appraisals
    107757: 06/09/01: Re: Performance Appraisals
    109205: 06/09/22: Re: Dell Laptop for Embedded Work
    109206: 06/09/22: Re: Dell Laptop for Embedded Work
    109207: 06/09/22: Re: Dell Laptop for Embedded Work
Steve Vallerand:
    14906: 99/02/24: 4002A .bit -> .hex
Steve W.:
    16713: 99/06/03: Re: Altera EPC1 PROM + Data IO ChipWriter
    16859: 99/06/15: Re: Configuring AlteraFlex10k with maxII
    17031: 99/06/25: Re: DS2 and E2 Framer???
    28102: 00/12/20: Re: Hand Soldering a PQ208 - It looks tough to do
    28350: 01/01/08: Re: FPGA for radar digital downconversion
Steve Weigand:
    2517: 95/12/22: Re: Career value: VHDL or Verilog?
    2536: 95/12/28: Re: Career value: VHDL or Verilog?
steve wenner:
    21162: 00/03/08: pal design using GAL22V10 and PROTEL
Steve Wenner:
    68763: 04/04/16: generic mapping
Steve Wilton:
    1293: 95/05/29: Example/Benchmark circuits with Memory
Steve Winkelman:
    4082: 96/09/09: Re: xilinx programing
Steve Wiseman:
    2073: 95/10/10: Re: Workview Pro-series doesn't work with windows 95.
    2086: 95/10/11: Re: Workview Pro-series doesn't work ((with windows 95)).
    2263: 95/11/14: Re: AT&T vs. Xilinx
    2972: 96/03/07: Re: Reconfigurable Computing Languages
    4455: 96/10/31: Weird pre-config VCC-GND short in Altera or Xilinx
    4454: 96/10/31: Re: Altera & Verilog
    4544: 96/11/12: Re: Suggest an interesting but manageable undergrad project.
    4625: 96/11/22: Re: ViewLogic PRO series under win95
    4648: 96/11/26: Re: How to use Xilinx ?
    4658: 96/11/26: Re: How to use Xilinx ?
    4680: 96/11/29: Re: How to use Xilinx ?
    4806: 96/12/17: Re: Anyone tried a FFT in a FPGA?
    4870: 96/12/22: Re: design should fit, but it doesn't
    4966: 97/01/06: Re: Serial download to Altera & Xilinx ?
    5027: 97/01/14: Re: Any PEEL22CV10A replacements with more capacity?
    5088: 97/01/22: Re: GAL programming timing
    5128: 97/01/25: Re: Altera support better than Xilinx
    5178: 97/01/29: Re: Altera support better than Xilinx
    5353: 97/02/10: Re: Anyone for Linux ?
    5403: 97/02/13: Re: [Q].FIFO in FPGA XILINX
    5527: 97/02/22: Re: Xilinx or Altera?
    5537: 97/02/23: Re: Xilinx or Altera?
    5573: 97/02/25: Re: Xilinx or Altera?
    5671: 97/03/05: Re: Timing simulator for Warp 4.1 that works under Win NT 4.0
    5799: 97/03/16: Re: PEEL16V8 with PALASM
    5982: 97/04/02: Re: Sole source
    6030: 97/04/06: Re: Pentium Pro Worth it for Altera Max Plus?
    6079: 97/04/10: Re: Pentium Pro Worth it for Altera Max Plus? (subject drifting to P+R speeds)
    6376: 97/05/19: Re: Fast comparator
    6639: 97/06/08: Re: Fine Pitch PQFP : anyone any hassles?
    7194: 97/08/13: Re: Download FLEX10K over the LPT port
    26065: 00/10/02: Re: Programming Cypress Graphics Clock Generator
Steve Work:
    2633: 96/01/16: Re: [q][Reverse Engineering Protection]
<steve.lass@xilinx.com>:
    114815: 07/01/24: Re: Xilinx ISE 8.2
    114816: 07/01/24: Re: Xilinx ISE 8.2
    114832: 07/01/24: Re: Xilinx ISE 8.2
    114934: 07/01/26: Re: Xilinx ISE 8.2
    115165: 07/02/01: Re: EDK-Modelsim XE
    115384: 07/02/08: Re: Read CLB information from NCD file
    116236: 07/03/05: Re: Ise foundation and Ise Webpack
    117015: 07/03/21: Re: Off topic: what is the purpoe of XST?
    117016: 07/03/21: Re: Xilinx ISE support for dual/quad core CPUs?
    117067: 07/03/22: Re: Off topic: what is the purpoe of XST?
    117076: 07/03/22: Re: Off topic: what is the purpoe of XST?
    117138: 07/03/23: Re: Off topic: what is the purpoe of XST?
    118938: 07/05/07: Re: Xilinx software quality - how low can it go ?!
    118988: 07/05/08: Re: An Open-Source suggestion for Xilinx
    119334: 07/05/16: Re: An Open-Source suggestion for Xilinx
    121527: 07/07/06: Re: Xilinx ISE, EDK and some ground roules in software development
    121971: 07/07/16: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    122674: 07/08/02: Re: Best CPU platform(s) for FPGA synthesis
    122682: 07/08/02: Re: Best CPU platform(s) for FPGA synthesis
    122698: 07/08/03: Re: Best CPU platform(s) for FPGA synthesis
    123222: 07/08/20: Re: Synthesizing fixed_pkg in ISE 9.2
    125746: 07/11/02: Re: Xilinx EDK and Windows Vista?
    125751: 07/11/02: Re: Xilinx EDK and Windows Vista?
    126389: 07/11/20: Re: FPGA Editor (9.2.03i) under Linux x86_64
    126519: 07/11/26: Re: FPGA Editor (9.2.03i) under Linux x86_64
    127938: 08/01/10: Re: Multiple UCF support in Xilinx ISE
    128328: 08/01/22: Re: When will Xilinx Webpack and EDK support Vista/64?
    130399: 08/03/21: Re: ISE 10.0 finally with multi-threading and SV support ?
    131189: 08/04/14: Re: 64 bit WebPack
<Steve@s-deweynospam.demon.co.uk>:
    16327: 99/05/16: Re: Trade-In Offer - ABEL, MINC & Synario Users in Europe
<steve@sk-tech.com>:
    22096: 00/04/21: Virtex-E and LVDS
    22106: 00/04/24: Re: Virtex-E and LVDS
    28759: 01/01/23: Foundation - Source Constraints
steve_blah:
    126988: 07/12/07: Pin assignment with Quartus II for PCB placement
    127027: 07/12/09: Re: Pin assignment with Quartus II for PCB placement
    127028: 07/12/09: Re: Pin assignment with Quartus II for PCB placement
    127029: 07/12/09: Re: Pin assignment with Quartus II for PCB placement
steveb:
    148213: 10/06/29: ML605 Dev Board Problems
stevedb:
    6100: 97/04/11: Re: Cadence dfII Layout Plotter: which type are the best solution ?
<stevedonovanm@gmail.com>:
    137328: 09/01/08: Re: How to contact SiliconBlue ?
stevem:
    142030: 09/07/22: gate capacity between old Virtex-II and newer Virtex-4
stevem1:
    148675: 10/08/17: CPLD development board with 8-bit wide Flash/EEProm
    148679: 10/08/17: Re: CPLD development board with 8-bit wide Flash/EEProm
Steven:
    25912: 00/09/25: Re: Using the xilinx "pull-up to 5V" in VHDL
    50458: 02/12/11: Re: Some boards for designers...
    50624: 02/12/14: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    61816: 03/10/13: EPC16 will not Flash Program
    68264: 04/03/31: XAPP134's VHDL code
    68578: 04/04/08: Re: XAPP134's VHDL code
    68966: 04/04/23: SDRAM's dqm
    69045: 04/04/26: Re: SDRAM's dqm
    69109: 04/04/27: Re: SDRAM's dqm
    70000: 04/05/26: Re: SDRAM
    71279: 04/07/13: micron sdram module
    71348: 04/07/15: Re: micron sdram module
    72562: 04/08/24: Re: XC2V250 protoboard
    72716: 04/08/30: Re: how can I simulate the vhdl and verilog mixed design in modelsim?
    72981: 04/09/09: Problem with timing in post PAR with Xilinx Virtex II
    94653: 06/01/15: New PCI extender
    94721: 06/01/16: Re: New PCI extender
steven:
    79871: 05/02/25: Virtex4 : speed improvement
    94535: 06/01/13: Re: How to create a delay BUF?
Steven Archibald:
    60639: 03/09/18: High Bandwidth Virtex II boards
    73762: 04/09/29: Re: luts are optimized away
Steven Bird:
    2710: 96/01/27: Re: How Big Chips Will Be Designed In The Not Too Distant Future
    3373: 96/05/22: Re: *** The Great ESDA Shootout ***
    3442: 96/05/30: Re: INDUSTRY GADFLY: Synopsys Redeemed; Summit Rises
    3601: 96/07/02: Re: INDUSTRY GADFLY "Why I Hate Wally"
Steven C. Gerson:
    3518: 96/06/13: Re: Xilinx 4013E and PCI
Steven Casselman:
    16102: 99/05/03: Re: pricess for Xilinx Virtex XV300 and XV800
    16103: 99/05/03: Re: IRQ Controller
    16104: 99/05/03: Re: P I/O core
    16105: 99/05/03: Re: JBITs
    16346: 99/05/17: Re: Virtex based PCI cards
    16435: 99/05/21: Re: High Speed Reconfigurability
    16466: 99/05/24: Re: Virtex based PCI cards
    16222: 99/05/10: Re: PCI slave in FPGA?
    16272: 99/05/12: Re: floating points to fixed points on a FPGA
    16385: 99/05/19: Re: High Speed Reconfigurability
    16416: 99/05/20: Re: High Speed Reconfigurability
    16434: 99/05/21: Re: High Speed Reconfigurability
    16439: 99/05/21: [Fwd: High Speed Reconfigurability]
    16556: 99/05/27: Re: High Speed Reconfigurability
    16590: 99/05/28: Transmogrifier C
    16245: 99/05/11: Re: UART Design
    16766: 99/06/07: Re: [Q] low cost asic
    16934: 99/06/17: Re: aobut analog
    16935: 99/06/17: Re: Virtex Boards
    16954: 99/06/18: Re: Simple PCI card prototyping.
    16979: 99/06/21: Re: Virtex Boards
    16991: 99/06/22: Re: Simple PCI card prototyping.
    17059: 99/06/28: Re: 100 Billion operations per sec.!
    17067: 99/06/28: Re: Simple PCI card prototyping.
    17083: 99/06/29: Re: 100 Billion operations per sec.!
    17139: 99/07/02: Re: FW: Xilinx Acquisition of CoolRunners
    17142: 99/07/02: Re: 100 Billion operations per sec.!
    17168: 99/07/06: Re: Simple PCI card prototyping.
    17171: 99/07/06: Re: 100 Billion operations per sec.!
    17239: 99/07/13: Re: 100 Billion operations per sec.!
    17547: 99/08/09: Re: RLOC constraint not interpreted correctly?
    17602: 99/08/12: Re: port name reg_input won't sim.
    17603: 99/08/12: Hollywood Blonde and Reconfigurable Computing
    17633: 99/08/16: Re: Virtx' Configuration with the Xchecker cable
    17716: 99/08/26: Re: Virtex BRAM Initialization
Steven DeLong:
    25087: 00/08/25: Large amout of Interconnect between FPGAs
Steven Derrien:
    13666: 98/12/17: Problem with clock IOB placement
    15571: 99/03/31: Re: virtex partial reconfiguration
    15587: 99/04/01: Re: virtex partial reconfiguration
    15608: 99/04/02: Re: virtex partial reconfiguration
    16002: 99/04/27: FPGA and Virtex die size
    17117: 99/07/01: Heat disspa
    17376: 99/07/23: Designing a Virtex board
    18754: 99/11/12: FPGA density evolution
    19104: 99/11/29: Re: FPGA vs DSP vs PENTIUM MMX
    19116: 99/11/30: Re: FPGA vs DSP vs PENTIUM MMX
    19117: 99/11/30: AGP based FPGA board
    19120: 99/11/30: Re: FPGA vs DSP vs PENTIUM MMX
    18812: 99/11/17: Foundation configuration
    19128: 99/12/01: Re: FPGA vs DSP vs PENTIUM MMX
    19137: 99/12/01: Re: FPGA vs DSP vs PENTIUM MMX
    20410: 00/02/09: Mapped design file
    20663: 00/02/17: Re: Logiblox and virtex
    20664: 00/02/17: Re: Spartan-II Pricing - What gives?
    20861: 00/02/24: Re: PCI 64 bit / 66 MHz
    21245: 00/03/13: Xilinx FPGA densities
    21254: 00/03/14: Pb with Coregen in F2.1i
    21935: 00/04/07: Retiming for Virtex FPGA with synopsys
    22177: 00/04/28: Initial DFF value for Virtex in VHDL
    23100: 00/06/14: PCI for a fpga board
    23106: 00/06/14: Re: PCI for a fpga board
    23130: 00/06/15: FPGA board, PCI PLX bridge, DMA and Linux ..
    23132: 00/06/15: Re: PCI for a fpga board
    23272: 00/06/20: Single Floating point adder ansd multiplier core
    23561: 00/06/30: Re: There is no output on pins
    23315: 00/06/22: Re: FPGAs for Bioinformatics accelerators
    24088: 00/07/26: Retiming for Virtex with FC2
    26311: 00/10/11: Re: LUT to CLB assignment
    26366: 00/10/13: Re: VHDL synthesis with synopsys
    26368: 00/10/13: Re: VHDL synthesis with synopsys
    26569: 00/10/20: "Number of logic levels" in xilinx PAR reports
    26627: 00/10/23: Typical toggle rates for power estimation ...
    26634: 00/10/23: Re: Typical toggle rates for power estimation ...
    26733: 00/10/26: High fan out CE signal.
    26761: 00/10/27: Re: High fan out CE signal.
    26889: 00/11/02: Re: clock multiplication and Spartan2 DLL placement constraints
    27069: 00/11/09: Non routable design
    27084: 00/11/10: Re: Non routable design
    27088: 00/11/10: Re: Non routable design
    27116: 00/11/11: Re: Non routable design
    27152: 00/11/13: Re: LUT and EDIF
    27158: 00/11/13: Synopsys VSS and XilinxCorelib weirdness
    27184: 00/11/14: Re: Synopsys VSS and XilinxCorelib weirdness
    27453: 00/11/22: Re: Virtex-PCI-Boards
    28440: 01/01/12: Re: Stereo vision on Virtex
    28568: 01/01/17: Re: Stereo vision on Virtex
    30110: 01/03/23: Re: reduced precision floating point
    30612: 01/04/19: Voltage supply reduction for low power in FPGAs.
    30762: 01/04/27: Re: Comparison of FPGA and DSP
    30792: 01/04/29: Re: Comparison of FPGA and DSP
    30849: 01/05/01: Using synospys power compiler for Xilinx Virtex design ..
    31365: 01/05/21: Interfacing with serial port
    31371: 01/05/21: Re: Interfacing with serial port
    32370: 01/06/25: Re: Register balancing in FPGA Express
    32896: 01/07/11: file flush in VHLD for synopsys VSS
    32941: 01/07/12: Re: file flush in VHLD for synopsys VSS
    33692: 01/08/02: Spartan II and asynchronous memory interface
    33697: 01/08/02: Re: Spartan II and asynchronous memory interface
    33708: 01/08/02: Re: Spartan II and asynchronous memory interface
    33736: 01/08/03: Re: Spartan II and asynchronous memory interface
    33740: 01/08/03: Re: Spartan II and asynchronous memory interface
    33755: 01/08/03: Re: Spartan II and asynchronous memory interface
    33821: 01/08/06: Re: Spartan II and asynchronous memory interface
    33876: 01/08/07: Re: Spartan II and asynchronous memory interface
    33949: 01/08/09: Re: Question on use of FPGA in a special Data Aquisition system
    34102: 01/08/14: Re: VHDL floating point arithmetic
    34112: 01/08/14: Modeling delay on a bidirectionnal signal
    34214: 01/08/16: Re: Xilinx Floorplanner in batch mode?
    34836: 01/09/10: Data cache for fpga-cpu using Xilinx BlockRam
    36359: 01/11/07: Xpower and vcd files
    37595: 01/12/17: Re: Certicom challenge and FPGA based modular math
    37596: 01/12/17: Re: Certicom challenge and FPGA based modular math
    37599: 01/12/17: Configuring Xilinx FPGA through parallel port
    37658: 01/12/18: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
    38055: 02/01/03: Re: Automatically pipeline combinatorial EDIF
    38911: 02/01/28: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
    38914: 02/01/28: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
    38917: 02/01/28: ARe: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
    39027: 02/01/30: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
    41405: 02/03/27: Re: XPower & Power Estimator Spreadsheet
    41863: 02/04/09: Re: Low-cost FPGA + processor board?
    42500: 02/04/25: FPGA vs Multi-processors
    44493: 02/06/21: Xpower accuracy
    44774: 02/06/30: Xpower accuracy (is there anybody from Xilinx out there ?)
    48847: 02/10/25: Re: PCI burst reads w/ Spartan
    49459: 02/11/12: EPP slave interface
    49541: 02/11/14: Re: EPP slave interface
    50721: 02/12/18: Re: Avoiding SRL16 in Synplify
    78509: 05/02/02: Re: MP3 Player Project
    83410: 05/04/29: Problem with JTAG server on Quartus 4.0 for XP
    91734: 05/11/11: Re: fastest possible USB
    92759: 05/12/06: Re: xilinx research labs
    92765: 05/12/06: Re: xilinx research labs
    92822: 05/12/07: Re: xilinx research labs
    112747: 06/11/28: Xilinx ML555 availability
    113017: 06/12/05: Using quartus "In system memory editor" from command line
    124111: 07/09/12: Command line quartus_pgm very slow
    124121: 07/09/12: Re: VHDL Design Pattern Book
    124129: 07/09/12: Re: precision errors. microblaze vs matlab single precision... huh?
    124782: 07/10/04: Optimized bitcounting on FPGA
    124811: 07/10/05: Re: Optimized bitcounting on FPGA
    125816: 07/11/06: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
    127749: 08/01/07: Re: Compilation of Plasma SW under Linux
    143204: 09/09/25: Re: Super Small MIPS-compatible Altera-Based Soft Processor and compiler
    155102: 13/04/16: Re: Catapult C floating point exp() function?
steven derrien:
    63609: 03/11/26: IDE Ultra DMA on a SPARTAN II
    63610: 03/11/26: Re: Xilinx Microblaze SDRAM burst access
    63618: 03/11/26: IDE Ultra DMA on a SPARTAN II (corrected version)
    63619: 03/11/26: Re: IDE Ultra DMA on a SPARTAN II
    64713: 04/01/12: Re: Modify Memory after P&R in Xilinx Virtex2
    71215: 04/07/12: Using gprof with Nios II
    71344: 04/07/15: Re: Using gprof with Nios II
    76621: 04/12/07: Re: Performance claims
Steven E. Raasch:
    4749: 96/12/10: Re: ASICs Vs. FPGA in Safety Critical Apps.
Steven Elzinga:
    43366: 02/05/20: Re: verilof parameter and XST
    43527: 02/05/22: Re: Inferring BlockROMs
    43543: 02/05/23: Re: virtex II : FDDRRSE instantiation
    43582: 02/05/24: Re: Xilinx STARTUP and PADS problems
    44512: 02/06/21: Re: How to generate a valid EDIF netlist?
    44738: 02/06/28: Re: amplify and xilinx : map error 679
    46688: 02/09/05: Re: Viewing Xilinx netlist
    46713: 02/09/06: Re: Viewing Xilinx netlist
    47481: 02/09/26: Re: Finding nets in hierarchy
    57324: 03/06/27: Re: Xlilin xc9572XL Default register values
    57484: 03/07/01: Re: Xlilin xc9572XL Default register values
    57492: 03/07/01: Re: defparam LUT_4
    57558: 03/07/02: Re: defparam LUT_4
    57559: 03/07/02: Re: Xlilin xc9572XL Default register values
    64554: 04/01/07: Re: XST cant compile with blaxkboxes.
    65569: 04/02/02: Re: Verilog 2001 indexed part select in XST 6.1.3?
Steven Esau:
    4581: 96/11/18: Asymetrix Embraces KaiZenWare
Steven Groom:
    6205: 97/04/26: SIN/COS Functions in AHDL
    8131: 97/11/20: Re: Donloading MAX7000 via JTAG, MAX PLUS 2
    8132: 97/11/20: Re: MAX7000S
    8133: 97/11/20: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
    8539: 98/01/07: Re: Newbe to fpga
    8547: 98/01/08: Re: serial conf. PROMS
    8548: 98/01/08: Re: Synthesize large LUT
    8879: 98/02/05: Re: can u give me some advice?
    8947: 98/02/09: Re: Free FPGA tools???
    9166: 98/02/27: Re: Altera CPLD power-up procedure?
    10478: 98/05/22: Re: Minimal ALU instruction set.
    10479: 98/05/22: Re: XABEL problem
    10668: 98/06/10: Re: Multipliers on FPGA's
Steven Guccione:
    6734: 97/06/20: Re: Java and Giga Ops FPGA Boards
    26863: 00/11/01: Re: JBits
    125007: 07/10/15: DWARF2 in MicroBlaze?
    127517: 07/12/31: Re: Architectural level CMP simulators
    129969: 08/03/11: Re: Need info on systolic arrays in actual use
    130369: 08/03/21: Re: A Challenge for serialized processor design and implementation
Steven Hirsch:
    149118: 10/10/03: Re: Another Xilinx webpack download rant
    150720: 11/02/06: Looking for off-the-shelf 3.3 <--> 5v level shifter
    150723: 11/02/06: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
    150726: 11/02/06: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
    150733: 11/02/07: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
    150735: 11/02/07: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
    150741: 11/02/08: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
    150742: 11/02/08: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
    150747: 11/02/08: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
    150752: 11/02/08: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
    150818: 11/02/14: Re: Xilinx USB programming cable.
    152860: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
    152862: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
    153208: 12/01/06: Re: Handling overflow in a self-repeating frequency counter
Steven J. Ackerman:
    4358: 96/10/19: Re: Anyone use Lattice's CPLD
    7256: 97/08/19: Re: ISP Stories
    7305: 97/08/23: Re: ISP Stories
    7304: 97/08/23: Re: ISP Stories
    7504: 97/09/18: Re: 6809 discontinued
    11321: 98/08/04: Re: [Q] motor control onto an FPGA
    12066: 98/09/26: ANNOUNCE: Xilinx FPGA / CPLD and CODEC Demo Boards
    13089: 98/11/15: Re: Board for FPGA ?
    15967: 99/04/23: Synplicity
    17084: 99/06/29: Re: FW: Xilinx Acquisition of CoolRunners
    17135: 99/07/02: Re: FGPA Servo Motor Controller
    20900: 00/02/26: Re: Bit Serial Arithmetic De-mystified
    31335: 01/05/19: Any Triscend E5 (8051 core w/FPGA) Users ?
    32207: 01/06/19: Has anyone used the Atmel FPSLIC part ?
    32906: 01/07/11: Re: 8031 microcontroller on FPGA development board :-)
Steven J. Hill:
    84559: 05/05/20: Reading the contents of a FPGA in-circuit.
    84832: 05/05/29: [NEWBIE] Linux WebPack questions...
    89541: 05/09/18: [PATCH] Xilinx Linux driver package clean-up.
    89579: 05/09/19: Re: Reverse Engineering Output Files
    90556: 05/10/16: Re: CPLD design software under WINE?
    90955: 05/10/25: Re: 7.1i on Linux installation saga
Steven J. Tucker:
    9126: 98/02/23: Good book for FPGA starter?
Steven John Buckley:
    53125: 03/03/04: EP310
Steven K. Knapp:
    1863: 95/09/11: CORRECTED PINOUT: XC4010 and XC4013 in 225-Pin Ball Grid (BG225) Package
    1864: 95/09/11: Re: Looking for Scan-Path-Insertion-Too
    1886: 95/09/15: Re: Fast FPGA's?
    1912: 95/09/19: Re: Fast FPGA's?
    1931: 95/09/20: Re: Fast FPGA's?
    4431: 96/10/28: PCI Compliance in FPGAs
    4432: 96/10/28: Re: Multipliers on Xilinx FPGAs
    4561: 96/11/13: Re: Fast FPGA
    4563: 96/11/13: Re: UART FOR FPGAS
    4564: 96/11/13: Re: recent FPGA boards ?
    4562: 96/11/13: Re: UART FOR FPGAS
    4944: 97/01/03: Re: Usb Cores ( synthesisable ) and ( simulation models )
    5002: 97/01/10: Re: FAQ
    5003: 97/01/10: Re: Are you looking for CHIP MANUFACTURER websites ???
    5014: 97/01/13: Re: ASICs Vs. FPGA in Safety Critical Apps.
    5050: 97/01/16: Re: Safety Critical Apps -> Xilinx Checker.
    5094: 97/01/22: Re: GATEFIELD from Zycad
    5133: 97/01/25: ANNOUNCEMENT: New Web Site Dedicated to Programmable Logic
    5135: 97/01/26: Re: Verilog --> FPGA
    5156: 97/01/27: Re: Altera PCI experience anyone?
    5158: 97/01/28: Re: FPGAs with internal Tri-state busses ?
    5159: 97/01/28: Re: FPGAs with internal Tri-state busses ?
    5180: 97/01/29: Re: Safety Critical Apps -> Xilinx Checker.
    5200: 97/01/30: Re: FPGA Lab.
    5248: 97/02/01: This is just a test. DELETE
    5262: 97/02/03: DISREGARD: Test Message
    5269: 97/02/03: Re: Q is Xilinx Foundation BASE worth buying?
    5270: 97/02/03: Re: Altera PCI experience anyone?
    5276: 97/02/03: Re: Reconfigurable Logic Query
    5283: 97/02/03: Re: Steven K. Knapp - no such article
    5284: 97/02/04: Re: boundary scan - vhdl - xilinx
    5287: 97/02/04: REPOST: New Web Site Dedicated to Programmable Logic
    5494: 97/02/20: Re: Search Engines for Electronic Parts?
    5575: 97/02/25: Re: Who's there?
    5594: 97/02/27: Re: Instatiation of Xilinx Primitives in VHDL?
    5776: 97/03/13: Re: Reverse Engineering FPGAs
    5686: 97/03/07: Re: Xilinx 4002 RAM Question
    5714: 97/03/10: Re: Xilinx config pins M0..M2
    5784: 97/03/14: Re: ACTEL RAM BASED FPGAs
    5821: 97/03/18: Re: Development board with multiple FPGAs
    5875: 97/03/21: Re: Development board with multiple FPGAs
    5935: 97/03/27: Re: Xilinx XC6200 -- any sightings?
    5936: 97/03/27: Re: What tools for $8000?
    5937: 97/03/27: Re: viewoffice <--> viewoffice compatibility
    5938: 97/03/27: Re: FIFOs
    5939: 97/03/27: Re: Development board with multiple FPGAs
    5950: 97/03/29: Re: Any FPGA with 6809 core?
    6070: 97/04/09: Re: Chip Temperature (was:Re: Sole source)
    5985: 97/04/02: Re: xess
    5986: 97/04/02: Re: 8051 core for XC40xx
    6040: 97/04/07: Re: FFT in FPGA
    6055: 97/04/08: Re: Reconfig computing and multimedia?
    6103: 97/04/12: The Programmable Logic Jump Station has moved ...
    6117: 97/04/13: Re: PCI Bus Problems
    6127: 97/04/14: Re: PCI Bus Problems
    6140: 97/04/16: Re: XC5204PQ160 Configuration
    6158: 97/04/19: Re: PCI Reset Spec...
    6340: 97/05/16: Re: VHDL PCI FPGA Implementation
    6341: 97/05/16: Re: Scientific American article on FPGAs
    6343: 97/05/16: Re: Wide edged decoders in Xilinx XC4000 series!
    6345: 97/05/16: Re: Cheap way to develop for FPGAs?
    6362: 97/05/18: Re: File Format for Xilinx bitstream
    6363: 97/05/18: Re: VHDL PCI FPGA Implementation
    6371: 97/05/19: Re: File Format for Xilinx bitstream
    6470: 97/05/27: Re: Best way to learn VHDL?
    6469: 97/05/27: Re: Looking for FAQ
    6499: 97/05/29: Re: Glitches in timing simulation of Xilinx FPGAs with Synopsys
    6506: 97/05/29: Re: Glitches in timing simulation of Xilinx FPGAs with Synopsys
    6529: 97/05/31: Re: FAQ's / Documentation sites wanted
    6569: 97/06/03: Re: new to FPGAs
    6570: 97/06/03: Re: What is M1?
    6571: 97/06/03: Re: Any designs to avoid in FPGAs
    6671: 97/06/12: Re: XC1700 programming algorithm
    6822: 97/06/30: Re: FPGA prototype board
    6821: 97/06/30: Re: Info on VHDL
    6856: 97/07/02: Re: Does FAQ for this group exist? (empty)
    6857: 97/07/02: Re: inexpensive Xilinx 3042A development
    6858: 97/07/02: Re: Which Xilinx devices of the 40xxE, 40xxEX series available ?
    6873: 97/07/04: Re: How to describe XC4000EX/XL FIFOs/RAMs in VHDL?
    6888: 97/07/06: Re: Quicklogic PASIC1 to PASIC2 problems?
    7214: 97/08/15: Re: Low-cost programming FPGAs (was: Re: free FPGA software from actel)
    7155: 97/08/07: Re: jtag isp guidance request
    7167: 97/08/08: Re: FPGA help required immediately
    7208: 97/08/14: Re: FPGA power consumption
    7290: 97/08/22: Re: FPGA prototyping board
    7361: 97/09/01: Re: MCS - intel86 format
    7362: 97/09/01: Repost: MCS - intel86 format -- full path names
    7442: 97/09/10: Re: University FPGA Project
    7456: 97/09/12: Re: Cheap (sub $10) hardwired FPGA? Which manufacturers?
    7515: 97/09/18: Re: Choosing a good pin assignment for multiple-xilinx prototype.
    7516: 97/09/18: Re: vme interface
    7534: 97/09/19: Re: FPGA/CPLD Overview
    7560: 97/09/22: Re: cpld and fpga help needed
    7665: 97/10/01: Re: fifos design for fpga
    7708: 97/10/06: Re: Wanted: cheap way to learn VHDL
    7725: 97/10/07: Re: XILINX and ALTERA development boards
    7757: 97/10/11: Re: FPGA News Resource Page
    7784: 97/10/14: Re: design sites
    7789: 97/10/15: Re: Previous FPGA articles
    7790: 97/10/15: Re: Help on coding numerical algorithms using VHDL
    7895: 97/10/27: Re: XILINX pin compatible replacements
    7914: 97/10/29: Re: design sites
    7917: 97/10/29: Re: Modeling using Altera devices
    8003: 97/11/06: Re: I'm interested in FPGAs. How do I start ?
    8004: 97/11/06: Re: interface between FPGA & user?
    8038: 97/11/10: Re: FPGA basics please ?
    8042: 97/11/10: Re: switching between clock domains in Xilinx FPGA's
    8085: 97/11/16: Re: What is the difference between CPLD and FPGA ?
    8086: 97/11/16: Re: I need Help
    8121: 97/11/19: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
    8218: 97/11/29: Re: FPGAs for hobbyist, HELP
    8219: 97/11/29: Re: need help on FPGA
    8269: 97/12/04: Re: Xilinx P&R - how does M1 compare to XACT6?
    8302: 97/12/06: Re: Xilinx P&R - (One-Hot State Machines)
    8231: 97/12/01: Find out about it on The Programmable Logic Jump Station!
    8321: 97/12/08: Re: SDRAM & SSTL
    8359: 97/12/10: Re: combinational multipliers
    8397: 97/12/12: Re: Z80 in FPGA: clockspeed?
    8398: 97/12/12: CROSSPOST: WANTED: Electronics Company with Experience in Space Projects
    8419: 97/12/13: Re: JTAG configuration of Xilinx XC4000E FPGAs?
    8420: 97/12/13: Re: JTAG configuration of Xilinx XC4000E FPGAs?
    8755: 98/01/23: Re: ASIC and PCB makers for Hobbyists wanted
    8756: 98/01/23: Re: PCI Bus
    8849: 98/02/01: Re: Introduction book on Verilog/VHDL
    8848: 98/02/01: Re: can u give me some advice?
    8918: 98/02/06: Re: Simple questions; please answer
    8952: 98/02/08: Re: Free FPGA tools???
    8959: 98/02/09: Re: x86 soft cores?
    8972: 98/02/10: Re: TPC1020AFN-068C DEVICES REQUIRED
    9116: 98/02/21: Re: crossbar switch
    9117: 98/02/21: Re: Free FPGA tools???
    9118: 98/02/21: See What's New on The Programmable Logic Jump Station
    9164: 98/02/26: Re: Questions about FPGA
    9242: 98/03/04: Re: Spartan config. Mode
    9475: 98/03/16: FPGA: Upcoming Seminars and Events
    9638: 98/03/27: Re: VHDL shareware editor?
    9639: 98/03/27: Re: XactStep6 - The cure for a dongle
    9658: 98/03/28: Re: Newbie question - FAQ for this group?
    9659: 98/03/28: Re: Random number generator
    9661: 98/03/28: NEW: The Programmable Logic Bookstore
    9802: 98/04/06: Upcoming Programmable Logic Events in April 1998 (FPGA, CPLD)
    9877: 98/04/10: Re: Xilinx XC9500 series -- software?
    9925: 98/04/14: Re: Synplicity
    9981: 98/04/20: UPDATE: The Programmable Logic Jump Station (www.optimagic.com)
    10016: 98/04/22: Re: Ask for / Discuss which FPGA & ASIC tools best buy
    10133: 98/04/28: Re: [Q] Cheap Xilinx Proto Boards
    10151: 98/04/29: Re: High Speed FPGAs??
    10186: 98/05/02: Re: TMS9902ANL UART in FPGA - anyone wants to do this?
    10254: 98/05/07: Looking for Ultra 2 SCSI Synthesizable Core
    10269: 98/05/08: Re: Low power FPGA design
    10353: 98/05/13: UPDATE: The Programmable Logic Jump Station
    10423: 98/05/18: Re: XABEL problem
    10458: 98/05/19: Re: Xilinx Foundation Student Edition
    10461: 98/05/19: FPGA/Programmable Logic/Reconfigurable Computing Conferences in May-June 1998
    10470: 98/05/20: Re: FPGA-based CPUs (was Re: Minimal ALU instruction set)
    10471: 98/05/20: Re: Archives for comp.arch.fpga?
    10521: 98/05/27: UPDATE: The Programmable Logic Jump Station (www.optimagic.com)
    10545: 98/05/28: Re: Compiling a HLL to FPGA
    10706: 98/06/11: Re: floorplanning in xilinx
    10776: 98/06/18: Re: Paging VCC..
    10777: 98/06/18: Re: books on vhdl
    10793: 98/06/19: Re: Fpga Video interface
    10801: 98/06/20: Re: Getting into using FPGAs
    10817: 98/06/23: FYI: Motorola terminates FPGA efforts
    10832: 98/06/24: Re: I squared C on an FPGA
    10853: 98/06/25: Re: AHDL
    10883: 98/06/27: Re: Simple XC95xx isp - howto?
    10937: 98/07/05: Re: Consultants
    10952: 98/07/06: Re: Altera MAX+PLUS 8.1
    11032: 98/07/13: Re: Reed-Solomon encoding
    11149: 98/07/21: Re: Wanted: CPLD Primer
    11150: 98/07/21: Re: Partial reprogramming
    11167: 98/07/21: Re: Aldec's Active-VHDL Behavorial Simulator-Thanx
    11216: 98/07/26: Re: CPLD vs. FPGA
    11229: 98/07/28: Re: Async design/minimum prop delays
    11290: 98/08/02: Re: how much ? prices of Xilinx chips
    11413: 98/08/11: ANNOUNCEMENT: The Programmable Logic Jump Station (www.optimagic.com)
    11426: 98/08/12: Re: FFT-Speed
    11436: 98/08/13: Re: Newbie seeks cheap fun w/FPGAs
    11537: 98/08/21: Re: Big FPGA on PCI card with Linux support?
    11626: 98/08/27: Re: CPLD/FPGA software
    11682: 98/08/31: Re: PROM alternative
    12083: 98/09/28: Re: shareware
    12084: 98/09/28: Re: FPGA information
    12117: 98/09/29: Re: Where can I get comp.arch.fpga newsarticle archive?
    12307: 98/10/08: Re: Design security again - the Actel solution
    12500: 98/10/13: Re: books
    12501: 98/10/13: Re: FPGA info..
    12751: 98/10/27: FYI: FPGA/Programmable Logic Topics at November Embedded Systems Conference
    12994: 98/11/09: Re: New free FPGA CPU
    13001: 98/11/10: Re: free Xilinx developer tools
    13069: 98/11/14: Re: Board for FPGA ?
    13070: 98/11/14: Re: Looking for a good documentation on FPGA
    13147: 98/11/17: Re: Low Cost FPGA Development Tools
    13148: 98/11/17: Re: Looking for a good documentation on FPGA
    13291: 98/11/24: Re: Report problems
    13292: 98/11/24: Re: FPGA vs. CPLD
    13474: 98/12/04: Visit The Programmable Logic Jump Station (www.optimagic.com)
    13627: 98/12/14: Re: FAQ Address Please
    13692: 98/12/18: Re: VHDL books (seeking)
    13772: 98/12/23: Re: This topic is new to me, ANY ONLINE FPGA TUTORIALS?
    14170: 99/01/16: Re: General FPGA introduction needed
    14171: 99/01/16: Re: AT40K popularity and available tools...
    14335: 99/01/26: Re: FPGA architecture
    14558: 99/02/04: Re: PCI based development board?
    14660: 99/02/09: Re: Board for XC4085XL
    14661: 99/02/09: Re: Q:EEPROM for Xilinx XC4k
    14672: 99/02/10: Visit The Programmable Logic Jump Station (www.optimagic.com)
    14684: 99/02/11: Re: Altera freecore library ?
    14761: 99/02/15: Re: comp.arch.fpga Archives
    14916: 99/02/25: Re: Xilinx ABEL?
    14972: 99/03/01: Re: newbie questions
    15102: 99/03/06: Re: Student edition!
    15159: 99/03/10: Re: need info
    15399: 99/03/22: UPDATE: The Programmable Logic Jump Station (www.optimagic.com)
    15447: 99/03/24: Re: Booth or Wallace Trees Multipliers
    15448: 99/03/24: Re: Info about FPGA/PLD
    15669: 99/04/07: Re: EEPROM for XC4010XL
    15705: 99/04/09: Re: Help: Need Tech. Info on PGA's and FPGA's
    15840: 99/04/16: Re: I NEED AN FAQ!!!!!!!!!!!! NOW!!!!!
    15842: 99/04/16: Re: What's the best way to learn about fpga's?
    15872: 99/04/17: Visit The Programmable Logic Jump Station (www.optimagic.com)
    16070: 99/04/30: Re: pricess for Xilinx Virtex XV300 and XV800
    16087: 99/05/01: Re: ISP,schematics and sim for free???
    16175: 99/05/07: Re: AHDL books
    16233: 99/05/11: Re: Need Altera 10k Prototype bd
    16654: 99/06/01: Re: ANy good recommendations for Books on FPGA
    16694: 99/06/03: ANN: The Industry's Largest Independent Information Source of FPGAs and CPLDs (www.optimagic.com)
    16775: 99/06/08: Re: Any free timing diagram tools?
    16834: 99/06/11: Re: Virtex Boards
    17052: 99/06/28: Re: newbie -- What's the best way to get started?
    17054: 99/06/28: Re: Altera EPC1 replacement?
    17155: 99/07/05: Re: newbie -- What's the best way to get started?
    17283: 99/07/16: Re: Beginner in need of help
    17343: 99/07/21: Re: Dongle problems.
    17381: 99/07/23: Re: Low Cost latched I/O
    17382: 99/07/23: Re: Looking for proceedings
    17902: 99/09/16: Re: free/demo/low cost verilog synthesis tools available?
    17927: 99/09/17: Re: Help
    17928: 99/09/17: ANN: The Industry's Largest Independent Information Source of FPGAs and CPLDs (www.optimagic.com)
    17932: 99/09/17: Re: A mix is best (Microcontrollers and Programmable Logic)
    18046: 99/09/25: Re: absolut Newbie
    18071: 99/09/27: Re: New to fpga's can you help
    18307: 99/10/13: ANN: The Industry's Largest Independent Information Source of FPGAs and CPLDs (www.optimagic.com)
    18230: 99/10/08: Re: Announcement: VHDL/FPGA Development Boards (up to 400.000 Gates) (Corrected Links, More Boards)
    18365: 99/10/19: Re: New to FPGA
    18373: 99/10/20: Re: Seeking for FPGA/CPLD (Starter) kit
    18374: 99/10/20: Re: Seeking for FPGA/CPLD (Starter) kit
    18492: 99/10/27: Re: FPGA
    18716: 99/11/09: Re: Virtex Board
    18746: 99/11/11: Re: looking for Xilinx/Actel Board
    19408: 99/12/20: ANN: The Industry's Largest Independent Information Source of FPGAs and CPLDs (www.optimagic.com)
    19925: 00/01/18: Re: hc11 core & fpga or cpld
    20187: 00/01/30: Re: Why Sinplicity make combinatorial loops from latches ?
    20189: 00/01/30: Re: Lattice isp & FPGA
    20197: 00/01/31: Re: EEPROM based FPGAs
    20891: 00/02/25: Re: fpga
    21241: 00/03/12: Re: Book recommendations?
    21240: 00/03/12: FPGA Prototype Boards/System Listing Updated
    21790: 00/03/31: Re: Adrian Thompson's and GA work on Xilinx
    21792: 00/03/31: Re: Good book on learning FPGA/VHDL/Verilog programming
    22042: 00/04/14: Re: FPGA controlling S-7600A TCP/IP ...
    26575: 00/10/20: Re: Virtex E development boards
    32069: 01/06/12: Re: Triscend A5: can it reconfigure itself?
    32839: 01/07/10: Re: 8031 microcontroller on FPGA development board :-)
    33191: 01/07/18: Re: processor core
    33448: 01/07/26: Re: Free VHDL cores - where?
    33449: 01/07/26: Re: Bound Scan
    33493: 01/07/28: Re: Book Recommendation (bit different)
    33495: 01/07/28: Re: free VHDL and/or Verilog tools?
    33511: 01/07/28: Re: Laid-off worker needs software
    33616: 01/07/31: Re: multi-context FPGA
    33924: 01/08/08: Re: prospects for tiny FPGA supercomputer?
    33935: 01/08/08: Re: prospects for tiny FPGA supercomputer?
    34120: 01/08/14: Re: Development Boards for FPGA based Application
    34486: 01/08/27: Re: DUART core synthesizable in Xilinx FPGA.
    34862: 01/09/11: Re: Give me some information!
    35355: 01/09/30: Re: future Xilinx products wish list ...
    35392: 01/10/02: Re: future Xilinx products wish list ...
    36237: 01/11/02: Re: what about FPGA with embedded processor?
    57520: 03/07/02: Re: Cyclone vs Spartan-3
    57681: 03/07/03: Re: Why not DDR in FPGAs?
    59038: 03/08/07: Re: Size does matter
    59039: 03/08/07: Re: Spartan 3 support in Webpack
    59111: 03/08/08: Re: Spartan-IIE LVDS?
    59170: 03/08/11: Re: DDR-ram interface (xapp200)
    60056: 03/09/04: Re: Memory
    60057: 03/09/04: Re: pricing, cyclone or spartan
    60203: 03/09/08: Re: Original (5V) Xilinx Spartan ?
    60204: 03/09/08: Re: PIC Programming Help
    60205: 03/09/08: Re: Spartan3 multiplier
    60229: 03/09/08: Re: Xilinx S3 I/O robustness question
    60307: 03/09/10: Re: Spartan-3 3S50 in Web ISE 5.2i = no block RAM, no multiplier?
    60336: 03/09/10: Re: What clock domain is a Xilinx DCM LOCK signal in?
    60366: 03/09/11: Re: Spartan-3 3S50 in Web ISE 5.2i = no block RAM, no multiplier?
    60429: 03/09/12: Re: What clock domain is a Xilinx DCM LOCK signal in?
    60430: 03/09/12: Re: FPGA Reconfiguration Question
    60479: 03/09/15: Re: Spartan 3 ICAP primitive
    60562: 03/09/16: Re: spartan3 pin tables
    60566: 03/09/16: Re: Spartan-3 : preconfiguration pull-up/float ?
    60903: 03/09/24: Free WebPack 6.1i Download Available Now for Spartan-3
    61722: 03/10/09: Re: Spartan 3 pinout typo?
    61835: 03/10/13: Re: Spartan 3 pinout typo?
    62028: 03/10/16: Re: Spartan-3 non-ES availability, and misleading pricing info
    62281: 03/10/23: Re: Spartan 3 pinout typo?
    64475: 04/01/05: Re: How do I make use of local-clocks in a Virtex-2 FPGA?
    64600: 04/01/08: Re: Large/Fast static RAM
    64781: 04/01/13: Re: using signal as clk source
    65042: 04/01/19: Re: Deriving 36MHz from a 40MHz crystal using DCM?
    65070: 04/01/19: Re: Deriving 36MHz from a 40MHz crystal using DCM?
    65244: 04/01/22: Re: Xilinx Spartan3 Timing Problems - Whats about the chips
    65684: 04/02/04: Re: Reconfiguring at runtime internally?
    65751: 04/02/05: Re: Reconfiguring at runtime internally?
    67104: 04/03/05: Re: A newbie question
    68503: 04/04/06: Re: XIL DCM Reset on XAPP462
    68809: 04/04/19: Re: FPGA power supply circuits
    70222: 04/06/09: Re: V4 teaser, correction
    70435: 04/06/16: Re: XCS10-84PC: How JTAG-Pins as I/O ?
    70464: 04/06/17: Re: Is there a verilog version of PicoBlaze?
    70497: 04/06/17: Re: Is there a verilog version of PicoBlaze?
    70823: 04/06/29: Re: Family Photo Album
    70824: 04/06/29: Re: Family Photo Album
    70829: 04/06/29: ANN: Xilinx Delivers Lowest Cost, Easy-to-use $99 Spartan-3 FPGA Starter Kit
    70864: 04/06/30: Re: Xilinx $99 Spartan-3 kit
    70877: 04/06/30: Re: Xilinx $99 Spartan-3 kit [Windows Only]
    71332: 04/07/14: Re: new Lattice FPGAs vs Cyclone and SpartanIII
    71762: 04/07/29: Re: Spartan 2E FG456 package file
    71892: 04/08/03: Re: SPARTAN-3 VCCAUX supply current
    71904: 04/08/03: Re: Spartan 3 errata and pricing
    71919: 04/08/03: Re: SPARTAN-3 VCCAUX supply current
    71920: 04/08/03: Re: Spartan 3 errata and pricing
    71922: 04/08/03: Re: Xilinx Spartan-3 Supply Issues?
    71923: 04/08/03: Re: Xilinx Spartan-3 Supply Issues?
    71951: 04/08/04: Re: Xilinx Spartan-3 Supply Issues?
    71954: 04/08/04: Re: Spartan 3 errata and pricing
    72096: 04/08/08: Re: What is the price of the micro-blaze, ... ?
    72180: 04/08/10: Re: Spartan III I/O robustness
    72222: 04/08/11: Re: DDR Lines on FPGA : Physical considerations
    72254: 04/08/12: Re: Different capabilities
    72340: 04/08/15: Re: Free Spartan3 download program for GNU/Linux
    72358: 04/08/16: Re: Xilinx VQ100 package drawings?
    72398: 04/08/17: Re: Xilinx Spartan 3 XAPP462 DCM (Digital Clock Manager)
    72660: 04/08/27: Re: Xilinx Spartan 3 DCM/DFS
    72664: 04/08/27: Re: Channel Link signals into Xilinx
    72712: 04/08/29: Re: Problems With Spartan 3 Starter Board
    72808: 04/09/02: Re: Spartan 3 Starter Kit and ISE WebPACK
    73778: 04/09/29: Re: Spartan-3 VCCIO ramp up time
    73780: 04/09/29: Re: Spartan-3 VCCIO ramp up time
    73781: 04/09/29: Re: Spartan-3 VCCIO ramp up time
    73984: 04/10/01: Re: JOP on Spartan-3 Starter Kit
    72891: 04/09/07: Re: spartan3 pci above 33MHz
    73129: 04/09/14: Re: spartan-3 I/O timing
    73193: 04/09/15: Re: Xilinx DCMs
    73245: 04/09/16: Re: USER RESET in XILINX FPGA
    73293: 04/09/17: Re: Virtex 4 released today [256x64 BRAM]
    73334: 04/09/19: Re: Reconfigure Spartan 3 without losing BRAM?
    73516: 04/09/22: Re: spartan-3 sram
    73517: 04/09/22: Re: Reconfigure Spartan 3 without losing BRAM?
    73518: 04/09/22: Re: Can Map and Par still handle the XC4000e family?
    73555: 04/09/23: Re: Spartan-3 VCCIO ramp up time
    73656: 04/09/27: Re: Spartan-3 VCCIO ramp up time
    74143: 04/10/04: Re: JOP on Spartan-3 Starter Kit
    74144: 04/10/04: Re: JOP on Spartan-3 Starter Kit
    74145: 04/10/04: Re: JOP on Spartan-3 Starter Kit
    80200: 05/03/02: Re: Spartan3E
    80207: 05/03/02: Re: Spartan-3E and SPI Flash bootstrap
    80214: 05/03/02: Re: spartan3 development board in Europe?
    80468: 05/03/06: Re: EST Guide
    80469: 05/03/06: Re: Spartan 3 - insurge current
    80470: 05/03/06: Re: adding SDRAM to the S3 starter kit
    82844: 05/04/18: Re: Spartan 3E slower that Spartan 3?
    82906: 05/04/19: Re: Spartan 3E availability
    84167: 05/05/13: Re: To Xilinx: Problem with Digilent Spartan III Starter Kit Documentation
    85394: 05/06/08: Re: Pissed off with Xilinx - Spartan 3 [The Rest of the Story]
    85664: 05/06/13: Re: Can I use a 18k ram as 2 single-port ram?
    85665: 05/06/13: Re: Searching FPGA board for private use
    85766: 05/06/15: Re: VHDL Synthesis tutorial
    86010: 05/06/20: [SPARTAN-3]: Parts Back on Xilinx Online Store (www.xilinx.com/store)
    86178: 05/06/22: Re: Spartan 3 availability [XC3S1000 and XC3S1500 Now Back on Online Store!]
    86179: 05/06/22: FYI: Spartan-3 XC3S50 through XC3S1500 Back on Xilinx Online Store (www.xilinx.com/store)
    86199: 05/06/22: Re: FYI: Spartan-3 XC3S50 through XC3S1500 Back on Xilinx Online Store (www.xilinx.com/store)
    86311: 05/06/24: Re: Spartan-3e order of availability?
    86425: 05/06/27: Re: Xilinx Spartan 3 CLB Slice Options - more detail than in datasheet available?
    86527: 05/06/29: Re: Spartan-3e order of availability?
Steven K. Knapp, Xilinx, Inc.:
    1965: 95/09/25: Re: cheap (free) fpga design software
    1982: 95/09/28: Re: Protel Xilinx Libraries
    1983: 95/09/28: Re: FPGA for a 20k gates micro-controller.
    2012: 95/10/02: Re: Xilinx Flash FPGA ??
    2013: 95/10/02: Re: FPGA for a 20k gates micro-controller.
    2025: 95/10/03: Re: Xilinx security
    2040: 95/10/05: Re: Memory Protection Fault
    2153: 95/10/20: Re: Help - Searching an PLD/FPGA Selection Software
    2347: 95/11/21: Re: Xilinx Configuration Memory Hacking
    2355: 95/11/22: Re: Xilinx Viewlogic simulation
    2375: 95/11/25: Re: Xilinx Viewlogic simulation
    2376: 95/11/25: Re: request for synthesizable VHDL for RAM
    2422: 95/12/03: Re: Xilinx XACT Windows Version
Steven Knapp:
    6690: 97/06/14: Re: Don't Design With Altera Parts... Altera Obsolete Parts
Steven Lee:
    2026: 95/10/03: Xact to VST
Steven Menk:
    38424: 02/01/14: Synthesis: Protel 99SE to XC2S200
    98365: 06/03/08: Xilinx ISE 7.1.4: Timing Contraints/Fan-Out/Placement
    98366: 06/03/08: Re: Xilinx ISE 7.1.4: Timing Contraints/Fan-Out/Placement
Steven Nowick:
    40356: 02/03/05: 2nd Call for Papers: IWLS-02 - IEEE/ACM Int. Wkshp. on Logic &
Steven P:
    104107: 06/06/19: ABEL to VHDL translate
    112956: 06/12/02: Re: Opencores DDR SDRAM controller
Steven R. Eckert:
    1715: 95/08/18: Re: Obscuring Code For Customers (was VHDL Obfuscators)
    3973: 96/08/28: Re: INDUSTRY GADFLY: EDA Goes OJ
Steven Rubin:
    12692: 98/10/23: Re: Need VHDL tools for Win NT/ Win 95
Steven Sanders:
    20048: 00/01/25: Xilinx Foundation: VHDL to symbol
    20220: 00/02/01: Xilinx Foundation 2.1: VHDL to MACRO error
    21178: 00/03/09: Xilinx Foundation 2.1:Functional simulation
    21969: 00/04/10: Xilinx Foundation 2.1 error
    22535: 00/05/11: FPGA emulators?
    22540: 00/05/11: Re: FPGA emulators?
    23270: 00/06/20: library not found in Foundation 2.1
    23316: 00/06/22: JTAG for debugging on Xilinx devices?
    24457: 00/08/09: 3-state busses on Virtex?
    26668: 00/10/24: Virtex Dual Port RAM simulation failure in Modelsim
    29719: 01/03/06: order Xilinx FPGA`s in Benelux
    30271: 01/03/30: Reed/Solomon ENcoder
    30362: 01/04/04: Re: Reed/Solomon ENcoder
    30611: 01/04/19: wanted: dig. board with FPGA and processor
    30942: 01/05/04: CompactPCI card with Virtex
    31399: 01/05/22: Xilinx PCI JTAG programming
    31611: 01/05/31: PCI to compactPCI adapter
    32727: 01/07/06: Xilinx PCI development board
Steven Sharp:
    52847: 03/02/24: Re: parameters in ANSI-style Verilog port maps
    53151: 03/03/04: Re: conditional `include
    53189: 03/03/05: Re: conditional `include
    54064: 03/04/01: Re: More xilinx webpack verilog questions: always @(clock) legal?
    60478: 03/09/14: Re: Verlog 2001 signed numbers
    63905: 03/12/08: Re: Verilog-2001 `define expressions?
    74780: 04/10/18: Re: Constrained Random Value in verilog
    75914: 04/11/18: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
    76008: 04/11/22: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
    76009: 04/11/22: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
Steven W Schlosser:
    11063: 98/07/16: Floorplanning Intro?
    11070: 98/07/16: Re: Floorplanning Intro?
Steven Weigand:
    1802: 95/09/05: Re: Help Needed-FPGA Apps Eng.-Allentown,PA.-Recruiter
Steven Weller:
    12940: 98/11/05: Re: New free FPGA CPU
Steven Zedeck:
    28012: 00/12/19: Re: jtag for fpga
    28013: 00/12/19: Re: jtag for fpga
    28014: 00/12/19: Re: jtag for fpga
Steven(Xunhua) Wang:
    8026: 97/11/08: ALPHA AXP architecture
<steven.elzinga@gmail.com>:
    118626: 07/05/01: Re: Xilinx software quality - how low can it go ?!
Steven_Guccione:
    80338: 05/03/04: re:Implementing Multi-Processor Systems in FPGAs
Stevenson:
    48351: 02/10/16: Delay elements using the schematic editor (Xilinx)
    48443: 02/10/17: Re: Delay elements using the schematic editor (Xilinx)
    49343: 02/11/10: Unexplained signal interaction
    51161: 03/01/04: Re: Running 2 inter related programs on the FPGA
    58064: 03/07/14: Re: wireless 802.11
    58133: 03/07/15: Re: mac & phy interface
<steves@traclabs.com>:
    17751: 99/08/30: Virtex LPCILOGIC site??
    18011: 99/09/23: Fineline BGAs
<steveu@coppice.org>:
    135636: 08/10/10: Re: XMOS XC-1 kits are shipping
    135690: 08/10/12: Re: XMOS XC-1 kits are shipping
    135727: 08/10/13: Re: XMOS XC-1 kits are shipping
Stevo Bailey:
    156898: 14/07/24: Re: Chisel as alternative HDL
Stevo_V2pro:
    110625: 06/10/18: DDR access for multiple procs on a ML310 (Virtex-II Pro)
    110816: 06/10/23: Data2Mem Error Help on dual PPC system
    110852: 06/10/24: Re: Data2Mem Error Help on dual PPC system
Stevy:
    80157: 05/03/02: Pci
<stewarma@gmail.com>:
    134512: 08/08/15: video timing with TFP410
    134532: 08/08/16: Re: video timing with TFP410
Stewart Cobb:
    56293: 03/06/02: Re: Need help with Xilinx ISE
    56295: 03/06/02: Xilinx : BEL constraint vs. ModelSim
    56301: 03/06/02: Re: Xilinx : BEL constraint vs. ModelSim
Stewart Smith:
    67122: 04/03/05: PWM, PLD programming ,(up/down ramp frequency)
    67138: 04/03/06: Re: PWM, PLD programming ,(up/down ramp frequency)
    67473: 04/03/12: Re: PWM, PLD programming ,(up/down ramp frequency)
    67540: 04/03/13: Re: PWM, PLD programming ,(up/down ramp frequency)
    68064: 04/03/25: Re: PWM, PLD programming ,(up/down ramp frequency)
Stewart, Nial [HAL02:HH00:EXCH]:
    19663: 00/01/07: Re: Desperate Xilinx problem SOLVED!
    19754: 00/01/11: Re: hobbyist friendly pld?
    20275: 00/02/03: Re: Can hobbyist buy altera in uk?
    20377: 00/02/08: Re: Can hobbyist buy altera in uk?
    21344: 00/03/17: Re: SpartanXL Express mode configuration
sthiruppathirajan:
    50575: 02/12/12: Single Event Upset in One Time PROM configuring FPGA
    50587: 02/12/13: Single event Upset effect in One Time PROM used for configuration in Xilix FPGA
    50590: 02/12/13: Re: Single Event Upset in One Time PROM configuring FPGA
    50656: 02/12/15: Re: Single event Upset effect in One Time PROM used for configuration in Xilix FPGA
    50681: 02/12/17: Re: Single event Upset effect in One Time PROM used for configuration in Xilix FPGA
    50820: 02/12/20: Re: Single event Upset effect in One Time PROM used for configuration in Xilix FPGA
Stifler:
    57619: 03/07/03: What a fascinating board!
    58030: 03/07/12: Re: Missing something...
    58459: 03/07/23: Re: Pricing question....
    69923: 04/05/24: Nios II = Microblaze
    69978: 04/05/25: Re: Nios II = Microblaze
    70148: 04/06/05: Re: NIOS 2 memory limitations
    70276: 04/06/10: Re: Virtex4: I don't understand their thinking....
    70278: 04/06/10: Re: Nios II really available ?
    73340: 04/09/19: Re: Statix II vs. Virtex 4
    73417: 04/09/21: Re: Stratix II vs. Virtex 4 - availability & fab partnership
    76025: 04/11/22: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial I/O
    76146: 04/11/25: Re: Choice of FPGA device
Stifler's Mom:
    85809: 05/06/16: Re: Availability of Spartan3
stijena:
    103482: 06/06/03: Re: Cardbus Power On Reset !!!!!!!!
Stijn Goris:
    69433: 04/05/11: FPGA wanted
    69443: 04/05/11: Re: FPGA wanted
    69453: 04/05/11: Re: FPGA wanted
Stijn Vanorbeek:
    24777: 00/08/18: NDA's outside the US.
<stillwaters.zhj@gmail.com>:
    140269: 09/05/07: Re: Can the complex DSP archetecture based on FPGA+DSP be replaced by
stockton:
    67587: 04/03/15: Xilinx Vertex-II Pro Logic Cells compared to Slices
    69435: 04/05/11: VHDL Standard Supported by Xilinx ISE 6.1
    77377: 05/01/05: Utilisation of Xilinx FPGAs
    79165: 05/02/15: ATM Cell Payload Scrambler / Descrambler Process Explaination Required
    79173: 05/02/15: Re: ATM Cell Payload Scrambler / Descrambler Process Explaination Required
    79260: 05/02/16: Re: ATM Cell Payload Scrambler / Descrambler Process Explaination Required
    82197: 05/04/08: Simualtion of Rocket I/O MGT in ModelSim XE
    82565: 05/04/14: Fitting functionality in an XC2VP30 FPGA.
StoneCold:
    65432: 04/01/29: Re: Good/Affordable Stater kits
stoneman:
    33682: 01/08/02: Altera EPM7064.............HELP
StoneThrower:
    139088: 09/03/20: Re: R/A FX2 connectors for S3A board - anyone have a couple spare?
    140181: 09/05/01: Re: ISE/EDK/SDK 11.1 licensing
    145057: 10/01/23: Re: FPGA farm
Stonethrower:
    136205: 08/11/05: Re: Learning programming an FPGAs
<StopTheHate1@netzero.net>:
<stoptheHate@optonlione.net>:
Stor Technology:
    11683: 98/08/31: CD Document Management Software
Stosh7:
    15129: 99/03/08: Re: Current State of FPGA-based PCI Interfaces?
Stout:
    13789: 98/12/28: Re: 22V10 Metastability - help please
    13826: 98/12/28: Re: 22V10 Metastability - help please
    14302: 99/01/24: Re: I really want to study VLSI design!
    38120: 02/01/05: Suitability of Atmel for project?
    38129: 02/01/06: Re: Suitability of Atmel for project?
    38130: 02/01/06: Re: Suitability of Atmel for project?
    38155: 02/01/07: Re: Suitability of Atmel for project?
    38349: 02/01/11: Re: Suitability of Atmel for project?
<stoyan.shopov@gmail.com>:
    85490: 05/06/10: Gated clock question
    85497: 05/06/10: Re: Gated clock question
Stratus Engineer:
    63162: 03/11/17: Re: Altera synthesis of registered signals ???
    63163: 03/11/17: Re: Active-HDL 6.1 pricing
strayblue:
    82310: 05/04/10: re:implement the JTAG MASTER --ACT8990 by using FPGA
    82426: 05/04/12: Re: re:implement the JTAG MASTER --ACT8990 by using FPGA
    82621: 05/04/14: Re: re:implement the JTAG MASTER --ACT8990 by using FPGA
Streetcat:
    104162: 06/06/20: Instrumentation Technologies
Strelnikov:
    87627: 05/07/27: isplever and GAL
    87675: 05/07/28: Re: isplever and GAL
strez:
    23541: 00/06/29: Re: Free PCI core
Strider:
¸.·´¯`·.¸.·>Strings:
    24626: 00/08/15: Re: Non-disclosures in job interviews
    24661: 00/08/16: Re: Non-disclosures in job interviews
    24662: 00/08/16: Re: Non-disclosures in job interviews
    24721: 00/08/17: Re: Non-disclosures in job interviews
    24722: 00/08/17: Re: Non-disclosures in job interviews
stripline:
    141561: 09/06/27: Virtex 5 Block Ram usage with Coregen FIFO
    141596: 09/06/29: Re: Virtex 5 Block Ram usage with Coregen FIFO
strong:
    40001: 02/02/23: about EPLD Rules and FLEX Rules
    40002: 02/02/24: EPLD RULES AND FLEX RULES
    42863: 02/05/05: a modelsim problem
<strshn99@my-deja.com>:
    28467: 01/01/14: Please explain these terms
    28468: 01/01/14: revision control tools ??
strut911:
    38448: 02/01/14: SYN_HIER attribute in synplify v7.0
    38644: 02/01/20: is it possible to floorplan a module and lock it down?
    38645: 02/01/20: bottom up synthesis with synplicity?
    38715: 02/01/23: Re: Virtex-II Programming Highs and Lows
    39131: 02/01/31: Virtex2-3000 (XC2V3000) engineering samples and chipscope
    39166: 02/02/02: solutions manuals, and no they are not for school
    39188: 02/02/03: Re: solutions manuals, and no they are not for school
    39322: 02/02/06: designing a protocol analyzer for proprietary serial bus
    39396: 02/02/08: Re: solutions manuals, and no they are not for school
    40847: 02/03/16: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
    40864: 02/03/16: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
    40865: 02/03/16: Re: just bought
    41839: 02/04/08: equivalence checking with FPGA
    41840: 02/04/08: uniquifying a synplicity netlist
    41873: 02/04/09: Re: Command-line Verifying Verilog with Synplify
    41877: 02/04/09: Re: uniquifying a synplicity netlist
    46873: 02/09/10: Re: OrCAD 9.2 Capture Part Library For SpartanXL&18VXX
    49720: 02/11/19: Re: Free FPGA Development Board
    49880: 02/11/23: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
    50623: 02/12/14: Strange error on Xilinx Bitgen/Netcheck DRC check
    50680: 02/12/16: Xilinx PAR looks as if it is adding X_BUF instances in my clock tree
    50684: 02/12/17: Is it true that if you have a clock routed to non-clock resources then you are not allowed to use the clock nets?
Stu Card:
    11787: 98/09/09: Re: New Evolutionary Electronics Book
Stuart:
Stuart Adams:
    13514: 98/12/07: New FPGA Brd: FPGA+PowerPC+Ethernet+TCP/IP
    26782: 00/10/29: Re: CoolRunner news :(
Stuart Brorson:
    45746: 02/08/03: Re: 2.75V IOs @ Virtex/Spartan2E
    52883: 03/02/25: Re: Licencing for downloadable FPGA tools
    52892: 03/02/25: Re: Licencing for downloadable FPGA tools
    52893: 03/02/25: Re: Licencing for downloadable FPGA tools
    53564: 03/03/16: Re: What is the diff between FPGA and CPLD?
    77650: 05/01/13: Re: Exportability of EDA industry from North America?
    77657: 05/01/13: Re: Exportability of EDA industry from North America?
    77751: 05/01/16: Re: Exportability of EDA industry from North America?
    77766: 05/01/17: Re: Exportability of EDA industry from North America?
    77833: 05/01/18: Re: Exportability of EDA industry from North America?
    77834: 05/01/18: Re: Exportability of EDA industry from North America?
    77857: 05/01/18: Re: Exportability of EDA industry from North America?
Stuart Clubb:
    4951: 97/01/03: Re: EPX880 & 8160 to Become Obsolete
    4950: 97/01/03: Re: Usb Cores ( synthesisable ) and ( simulation models )
    5104: 97/01/23: Re: FPGA with SRAM
    5397: 97/02/13: Re: Embedded SRAM in FPGAs
    5398: 97/02/13: Re: BIGGER (was Embedded SRAM in FPGAs)
    5460: 97/02/17: Re: Xilinx or Altera?
    5487: 97/02/19: Re: Xilinx or Altera?
    5525: 97/02/22: Re: Xilinx or Altera?
    5758: 97/03/12: Re: Development board with multiple FPGAs
    6377: 97/05/19: Re: VHDL PCI FPGA Implementation
    6388: 97/05/20: Re: Cheap way to develop for FPGAs?
    6428: 97/05/23: Re: Cheap way to develop for FPGAs?
    6427: 97/05/23: Re: Cheap way to develop for FPGAs?
    6452: 97/05/25: Re: Cheap way to develop for FPGAs?
    6453: 97/05/25: Re: Cheap way to develop for FPGAs?
    6454: 97/05/25: Re: Cheap way to develop for FPGAs?
    6495: 97/05/28: Re: Cheap way to develop for FPGAs?
    6503: 97/05/29: Re: VHDL PCI FPGA Implementation
    6514: 97/05/30: Re: VHDL PCI FPGA Implementation
    6528: 97/05/31: Re: VHDL PCI FPGA Implementation
    6530: 97/05/31: Re: Altera Versus Xilinx
    6552: 97/06/02: Re: Altera Versus Xilinx
    6553: 97/06/02: Re: Altera Versus Xilinx
    6598: 97/06/04: Re: VHDL PCI FPGA Implementation
    6599: 97/06/04: Re: Altera Versus Xilinx
    6632: 97/06/06: Re: Altera Versus Xilinx
    6752: 97/06/24: Re: Help: Two's complement multiplier in ORCA FPGA
    6728: 97/06/20: Re: 100MHz SDRAMs with Xilinx?
    7040: 97/07/25: Re: Should Xiling have more local clock nets?
    7050: 97/07/27: Re: How do FPGAs outperform DSP at FFT?
    7051: 97/07/27: Re: Should Xiling have more local clock nets?
    7066: 97/07/28: Re: Should Xiling have more local clock nets?
    7233: 97/08/17: Re: Should Xiling have more local clock nets?
    7126: 97/08/03: Re: Incremental changes of FPGA's possibel ?
    7142: 97/08/06: Re: Incremental changes of FPGA's possibel ?
    7175: 97/08/10: Re: Price of Serial EEPROM is Outrageous
    7190: 97/08/12: Re: Price of Serial EEPROM is Outrageous
    7243: 97/08/18: Re: FPGA Express...
    7244: 97/08/18: Re: Help!!!!
    7341: 97/08/28: Re: FIFO in Altera
    7431: 97/09/09: Re: HELP: FIFO's on an FPGA
    7432: 97/09/09: Re: HELP: FIFO's on an FPGA
    7430: 97/09/09: Re: Which FPGA ?
    7441: 97/09/10: Re: Which FPGA ?
    7466: 97/09/14: Re: Cheap (sub $10) hardwired FPGA? Which manufacturers?
    7537: 97/09/19: Re: FPGA/CPLD Overview
    7551: 97/09/21: Re: Hacking bitstream formats
    7550: 97/09/21: Re: Hacking bitstream formats
    7556: 97/09/22: Re: Hacking bitstream formats
    7575: 97/09/23: Re: Hacking bitstream formats
    7580: 97/09/24: Re: Pro series software
    7581: 97/09/24: Re: HELP: FIFO's on an FPGA
    8213: 97/11/29: Re: AHDL vs. VHDL
    8414: 97/12/13: Re: bus design in Altera 10K, how to increase speed
    8452: 97/12/16: Re: parallel counters: which device is suitable?
    8515: 98/01/02: Re: Xilinx Stock
    8520: 98/01/03: Re: Xilinx Stock
    8578: 98/01/10: Re: Xilinx Stock
    8615: 98/01/13: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8790: 98/01/27: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8791: 98/01/27: Re: comparing asic gates with gates in FPGA's
    8984: 98/02/11: Re: VHDL vs schematics
    8988: 98/02/12: Re: Free FPGA tools???
    8989: 98/02/12: Re: Devices and Prices
    9025: 98/02/15: Re: Devices and Prices
    9026: 98/02/15: Re: Devices and Prices
    9200: 98/03/01: Re: Correlation--Multichannel
    9456: 98/03/14: Re: The case for Linux and EDA
    9270: 98/03/05: Announce - Stuart jumps ship
    9271: 98/03/05: Re: Die Size Comparison of competing FPGAs
    9272: 98/03/05: Re: Die Size Comparison of competing FPGAs
    9338: 98/03/06: Re: Leonardo/Xilinx BUFGLS question
    9370: 98/03/07: Re: Die Size Comparison of competing FPGAs
    9371: 98/03/07: Re: Leonardo/Xilinx BUFGLS question
    9557: 98/03/23: Re: "CORE Competency" ???
    10060: 98/04/24: How low can they go?
    10146: 98/04/29: Re: Why Altera & Cypress Software Clashes (was: VHDL compiler differences?)
    10282: 98/05/09: Re: Xilinx Routing Delay
    10392: 98/05/15: Re: Xilinx Foundation and Linux
    10393: 98/05/15: Re: "Inferred" I/O flip-flops in XC4000E
    10431: 98/05/18: Re: XABEL problem
    10502: 98/05/25: CRC speeds and density please
    11041: 98/07/14: Re: Found problem -> Re: Need to know Xilinx M1.4's routing times...
    11177: 98/07/22: Re: Aldec's Active-VHDL Behavorial Simulator-Thanx
    11278: 98/08/01: Re: PCI Core In FPGA
    11774: 98/09/08: Re: Code coverage tools
    12025: 98/09/24: Re: Efficient max-function architecture?
    12766: 98/10/28: Re: Schematic entry?
    12966: 98/11/08: Re: FPGA HDL tool benchmarks
    13411: 98/12/01: Re: Will XILINX survive?
    13412: 98/12/01: Re: VHDL simulation of exported schematics..?
    13520: 98/12/07: Re: HELP, Tool selection
    13590: 98/12/10: Re: HELP, Tool selection
    13654: 98/12/16: Re: HELP, Tool selection
    13655: 98/12/16: Re: HELP, Tool selection
    13656: 98/12/16: Re: HELP, Tool selection
    13848: 98/12/29: Re: about using Mentor and Foudation together
    13849: 98/12/29: Re: Aldec integration
    13887: 98/12/31: Re: about using Mentor and Foudation together
    13914: 99/01/02: Re: How to import EDIF file in Foundation Software?
    13948: 99/01/04: Re: How to import EDIF file in Foundation Software?
    13975: 99/01/05: Re: Question on Exemplar synthesis
    14221: 99/01/20: Re: Secondary clock nets in Xilinx Virtex
    15061: 99/03/04: Re: Fast-turn ASIC vendors
    15088: 99/03/05: Re: Fast-turn ASIC vendors
    15287: 99/03/17: Re: Power Estimiation - report.zip (0/1)
    15288: 99/03/17: Re: Power Estimiation - report.zip (1/1)
    15348: 99/03/19: Re: Power Estimiation - report.zip (0/1)
    15402: 99/03/22: Re: Power Estimiation - report.zip (0/1)
    15508: 99/03/28: Re: Free Xilinx Vendor Tools ... NOT :-(
    15509: 99/03/28: Re: Free Xilinx Vendor Tools ... NOT :-(
    15556: 99/03/30: Re: Free Xilinx Vendor Tools ... NOT :-(
    15555: 99/03/30: Re: Free Xilinx Vendor Tools ... NOT :-(
    15645: 99/04/05: Re: Schematic Capture & FPGA synthesis
    15678: 99/04/07: Re: Best FPGA for High Speed DSP Logic?
    15709: 99/04/09: Re: Best FPGA for High Speed DSP Logic?
    15945: 99/04/23: Re: How to use TDO pin of Xilinx4000 in Exemplar ?
    16134: 99/05/05: Re: 10KE dual port RAM help ?
    16145: 99/05/06: Re: [Q]Do you recommend Altera MAXPLUS II9.01 as a VHDL compiler for Altera FPGA?
    16306: 99/05/14: Re: Verilog example for Xilinx?
    16445: 99/05/22: Re: How synthesize tools concern with size of the design?
    16446: 99/05/22: Re: Assigning pad type in Xilinx Virtex FPGA
    16478: 99/05/25: Re: How synthesize tools concern with size of the design?
    16581: 99/05/28: Re: Rom use, Renoir => leonardo => maxplus2
    17034: 99/06/26: Re: fast counter in 4013XL?
    17150: 99/07/03: Re: FW: Xilinx Acquisition of CoolRunners
    17247: 99/07/14: Re: Dongle problems.
    17268: 99/07/15: Re: Dongle problems.
    17458: 99/07/29: Re: APEX initial values
    17618: 99/08/15: Re: VHDL/Verilog? - Can of Worms
    17868: 99/09/14: Re: synthesis comparion between Synplify and FPGA express
    17888: 99/09/15: Re: synthesis comparion between Synplify and FPGA express
    17889: 99/09/15: Re: xilinx v2.1i
    17941: 99/09/18: Re: Synplfy 5.21 and 5.08a
    17957: 99/09/19: Re: Loadable arithmetic in Virtex
    18035: 99/09/24: Re: Synplfy 5.21 and 5.08a
    18236: 99/10/08: Re: UK or Europe Des. Engs for California jobs
    19113: 99/11/29: Re: VHDL vs. schematic entry
    19229: 99/12/07: Re: Problems with Leonardo Spectrum
    19230: 99/12/07: Re: tool command language (TCL)
    19598: 00/01/03: Re: Design security
    19647: 00/01/06: Re: Design security
    19648: 00/01/06: Re: Design security
    19929: 00/01/18: Re: Viterbi decoder in FPGA
    19940: 00/01/19: Re: Virtex to ASIC conversion
    21130: 00/03/07: Re: Synplicity for sale
    21232: 00/03/11: Re: Synplicity for sale
    21579: 00/03/25: Re: FPGA openness
    22797: 00/05/24: Re: % use of schematic vs VHDL ???
    23914: 00/07/14: Re: Silicon Valley Housing Nightmare?
    24251: 00/08/01: Well, it finally happenned
    24550: 00/08/13: Re: PCI core needed for Xilinx
    24780: 00/08/18: Re: When will SpartanII be in ditribution
    25371: 00/09/08: test
    25432: 00/09/11: Re: How do I mix vhdl and verilog source files in Synplify?
    28900: 01/01/28: Re: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
    29114: 01/02/06: Re: who wants to work in France ????
    29216: 01/02/09: Re: Mentor Advice
    29292: 01/02/13: Re: FPGAs take wron road. SoC NO - on-the-fly reprogrammability YES
    32526: 01/06/29: Re: Is the Grass Greener for an Engineer in the USA?
    32557: 01/06/30: Re: Is the Grass Greener for an Engineer in the USA?
    32561: 01/06/30: Re: Is the Grass Greener for an Engineer in the USA?
STUART CLUBB:
    1805: 95/09/05: Re: Xilinx PROMs
    2762: 96/02/03: Re: AT&T Orca vs Xilinx
    2776: 96/02/06: Re: AT&T Orca vs Xilinx
    3641: 96/07/07: RE: 100k gate DSP
    3642: 96/07/07: RE: Best HDL lang.
    3643: 96/07/07: Re: PCI compliance
    3644: 96/07/07: Re: FPGA Companies
    3920: 96/08/20: Synth. VHDL PCI Model?
Stuart D. Gathman:
    16482: 99/05/25: Re: High Speed Reconfigurability
Stuart J Adams:
    4261: 96/10/07: Anyone using Altera MaxPlus VHDL ???
    14753: 99/02/15: Xilinx Spartan and pin-locking
    17765: 99/09/01: FPGA/PLD in fine pitch BGA or chip scale package ???
    21086: 00/03/06: PCI reflected wave switching spec ???
    21832: 00/04/03: PCI test bench ??
    24183: 00/07/28: alternatives to costly FPGA config proms ??
    24354: 00/08/04: 5v -> 1.8v switcher supply for FPGA ??
    25255: 00/09/01: Spartan II Power Down Mode ??
    26312: 00/10/11: Xilinx FDN Express vs. Base Express ??
    26398: 00/10/14: DLL's Spread Spectrum Compatible ??
    26932: 00/11/03: level shifting buffers ??
    27773: 00/12/07: Re: Issues with Spartan II
    28136: 00/12/22: driving color VGA from FPGA ??
    86389: 05/06/27: multiprocessing with microblaze ?
Stuart Moses:
    37962: 01/12/27: Re: The speedest FPGA
    37963: 01/12/27: Re: Choice of Processor Cores in FPGAs - Both Embedded & Soft
    37964: 01/12/27: Re: ALTERA's Mercury CDR
Stuart Summerville:
    5064: 97/01/19: xact V6.0.1 & smartdrive cache....
    5704: 97/03/09: Xil FPGA: Usage of Multi-purpose pins as I/O
    5851: 97/03/20: Viewlogic Licensing delays?? Anyone?
    6187: 97/04/24: XC52xx and Hardware Debugger
    6207: 97/04/26: Re: XC52xx and Hardware Debugger
    6231: 97/04/30: Re: XC52xx and Hardware Debugger
    6464: 97/05/26: Fine Pitch PQFP : anyone any hassles?
    8872: 98/02/04: Comparison of Orcad Express, Foundation Series, & Viewlogic WVO?
Stuart Tyrrell:
    24653: 00/08/16: Re: Non-disclosures in job interviews
Stuart Wilson:
    6680: 97/06/13: Re: Altera Versus Xilinx
<stuart2775@my-dejanews.com>:
    14209: 99/01/20: Re: PLL in FPGAs?
<stuart_wilson@my-deja.com>:
    17675: 99/08/23: Re: Altera MAX2PLUS/MAX700s BIDIR problem...
StuartG:
    82563: 05/04/14: Verilog problems with SelectRAM clocking within a finite state machine
stuboy:
    144128: 09/11/12: what is ngc file
    144130: 09/11/12: Re: what is ngc file
<stud_lang_jap@yahoo.com>:
    79622: 05/02/22: USB 1.1 core
    83948: 05/05/10: dividing the clcok by 2.5
    85782: 05/06/15: MINI PCI card for testing FPGA MINIPCI core
    86132: 05/06/22: Difficult in probing through chipscope
    86228: 05/06/23: Chipscope problem
    86879: 05/07/07: Ray Andraka when will your book be on store???
    86881: 05/07/07: Re: Ray Andraka when will your book be on store???
    88626: 05/08/24: Strange FPGA problem
    88810: 05/08/29: Monitor the internal signal of EDF using chipscope
    89256: 05/09/09: implementing the tristate bus
    89275: 05/09/09: Re: implementing the tristate bus
    89297: 05/09/12: Fatal errror in ISE 6.3 i
    89379: 05/09/13: Re: Fatal errror in ISE 6.3 i
Student:
    69292: 04/05/05: Wire crossing in a large partially reconfigurable design.
    69334: 04/05/07: Re: Wire crossing in a large partially reconfigurable design.
    69495: 04/05/12: Re: FPGA + CF
    69525: 04/05/13: Re: Compact Flash FPGA card
    69682: 04/05/18: How do I perform RTL simulation with a Core Generator RAM and multiplier?
    69683: 04/05/18: Re: How do I perform RTL simulation with a Core Generator RAM and multiplier?
    69928: 04/05/25: What can I do if my chip can't meet timing?
    69973: 04/05/26: Re: What can I do if my chip can't meet timing?
    69974: 04/05/26: Re: What can I do if my chip can't meet timing?
    72401: 04/08/17: nand flash memory chips
Student (confused):
    111991: 06/11/14: FFT in VHDL (or Verilog) Tutorial
studywireless:
    155138: 13/04/25: FPGA Development Board with hard PowerPC
    155146: 13/04/26: Re: FPGA Development Board with hard PowerPC
<stuhpg@my-dejanews.com>:
    15409: 99/03/23: testboard for flex10k
StYm:
    129978: 08/03/12: Re: Matlab, RS-232, Ethernet
    130018: 08/03/13: Re: Matlab, RS-232, Ethernet
    138875: 09/03/12: libxdh_PartAnno.dll
Stéphane:
    33198: 01/07/19: 30 m cable reception with APEX LVDS I/O ?????
    39365: 02/02/07: Which PC for ALTERA development tools ?
Stéphane Julhes:
    124950: 07/10/12: Graphical VHDL Viewer ?
    124952: 07/10/12: Re: Graphical VHDL Viewer ?
Su We:
    30962: 01/05/04: Good VHDL/synthesis book
    36343: 01/11/07: XST synthesis
subagha:
    143496: 09/10/13: Problem with Black Box in VHDL in ISE 11.2 :: ERROR:NgdBuild:604
    144353: 09/11/30: XST 11.2 Takes a lot of memory and never completes the synthesis
    144359: 09/11/30: Re: XST 11.2 Takes a lot of memory and never completes the synthesis
    144361: 09/11/30: Re: XST 11.2 Takes a lot of memory and never completes the synthesis
    144369: 09/12/01: Re: XST 11.2 Takes a lot of memory and never completes the synthesis
subbu:
    126216: 07/11/16: gate count calculation in xilinx.
    126218: 07/11/16: Gate count calculation in xilinx.
subbu instru:
    136117: 08/11/02: requesting solution for error:HDLParsers:810
    136124: 08/11/02: Re: requesting solution for error:HDLParsers:810
Subbu Meiyappan:
    32279: 01/06/21: Re: LFSR Taps for 64 bit registers?
Subhasri krishnan:
    89891: 05/09/29: Preloading SDRAM?
    89893: 05/09/29: Re: Preloading SDRAM?
    90074: 05/10/04: Xilinx IMPACT Problem... detects 101 unknown devices
    90082: 05/10/04: Re: Xilinx IMPACT Problem... detects 101 unknown devices
    90255: 05/10/07: Re: Xilinx IMPACT Problem... detects 101 unknown devices
    90525: 05/10/15: Mixed voltage in JTAG chain.
    90823: 05/10/21: .dat to .bit
    91668: 05/11/10: Is this even true???
    91678: 05/11/10: Re: Is this even true???
    94072: 06/01/05: Timing constraints (again)
    94231: 06/01/08: concurrent auto precharge - memory controller
    94290: 06/01/09: Re: concurrent auto precharge - memory controller
    94326: 06/01/09: Re: concurrent auto precharge - memory controller
    94577: 06/01/13: what happens in SDR-SDRAM if i exceed tRAS(max)
    94689: 06/01/16: Re: what happens in SDR-SDRAM if i exceed tRAS(max)
    98162: 06/03/06: what do the following constraints mean?
    98244: 06/03/07: Re: what do the following constraints mean?
    98782: 06/03/16: Debugging ideas.
    98903: 06/03/17: Re: Debugging ideas.
    99056: 06/03/19: Re: Debugging ideas.
    99063: 06/03/19: Re: Debugging ideas.
    99702: 06/03/28: basic doubts about chipscope pro
    99797: 06/03/29: Re: basic doubts about chipscope pro
    100248: 06/04/05: Difference in output between testbench and chipscope
    100296: 06/04/06: Re: Difference in output between testbench and chipscope
    102176: 06/05/11: can increase simulation run time while running modelsim?
    103756: 06/06/10: initialization sequence and auto refresh for sdr-sdram
    103759: 06/06/10: Re: initialization sequence and auto refresh for sdr-sdram
    103792: 06/06/11: Re: initialization sequence and auto refresh for sdr-sdram
    104852: 06/07/07: recognizing multiple fpga's
    105298: 06/07/19: xess board problem (error downloading into ram)
    105351: 06/07/20: Re: xess board problem (error downloading into ram)
    105500: 06/07/24: Re: recognizing multiple fpga's
    105501: 06/07/24: impact.log files
    105529: 06/07/25: Re: impact.log files
    108650: 06/09/14: Looking for Hardware design consultant
    110894: 06/10/25: Single Bank Vs Multiple Banks in sdram
    110898: 06/10/25: Re: Single Bank Vs Multiple Banks in sdram
    110908: 06/10/25: Re: Single Bank Vs Multiple Banks in sdram
    110927: 06/10/25: can someone recommend a board?
    110943: 06/10/25: Re: can someone recommend a board?
Subhek:
    68350: 04/04/01: PCI development kit
    68496: 04/04/06: Re: PCI development kit
subin:
    94202: 06/01/07: Re: How to keep the design from Synplify or XST optimizing
subint:
    103390: 06/06/01: DDR SDRAM controller
    103508: 06/06/04: Help on DDR SDRAM contoller generated by MIG1.5
    103571: 06/06/06: Re: Help on DDR SDRAM contoller generated by MIG1.5
    103572: 06/06/06: Re: Help on DDR SDRAM contoller generated by MIG1.5
    103575: 06/06/06: Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5
    103576: 06/06/06: Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5
    103581: 06/06/06: Re: Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5
    103889: 06/06/14: ARM9 DDR interface
    104145: 06/06/20: Re: Xilinx bitgen vs output file name
    104146: 06/06/20: Re: xst:What happened here?
    104147: 06/06/20: Programmable clock ics8442
    104262: 06/06/22: Newbie in Chipscope-changes need to route bidirectional data port
    104302: 06/06/23: Re: Newbie in Chipscope-changes need to route bidirectional data port
    104363: 06/06/26: Re: Newbie in Chipscope-changes need to route bidirectional data port
    104427: 06/06/27: Help in the platform studio(EDK)
    104473: 06/06/28: Help in the platform studio(EDK)
    104511: 06/06/28: Re: Help in the platform studio(EDK)
    104512: 06/06/28: Re: Help in the platform studio(EDK)
    104514: 06/06/28: Re: Help in the platform studio(EDK)
    104523: 06/06/29: Re: Help in the platform studio(EDK)
    104526: 06/06/29: Re: Generic synthesis target in Synplify Pro
    104581: 06/06/30: Re: Help on simulating ddr controler generated by MIG!!
    104726: 06/07/05: mig_ddr_controller
    104791: 06/07/06: Simulation problem for the DDR controller
    104846: 06/07/07: Re: Simulation problem for the DDR controller
    105210: 06/07/17: Opencore ddr_controller
    105221: 06/07/18: Re: Opencore ddr_controller
    105572: 06/07/26: How to phase align a 10MHz clock using V4LX60 DCM
    105861: 06/08/01: Minimum frequency at which ddr can operate
    110354: 06/10/14: FPGA comparision
    110356: 06/10/14: Re: FPGA comparision
    112366: 06/11/21: Re: DDR_SDRAM_VHDL_models
    113950: 06/12/29: Tools available to split the design into multiple FPGAs.
    114068: 07/01/03: Re: Tools available to split the design into multiple FPGAs.
    114409: 07/01/15: How to install xilinx ise8.2 in Madriva linux
    115741: 07/02/18: Testing FPGA
    115742: 07/02/18: System Requirement to run V4Lx200,v5lx330
    119590: 07/05/23: How the synthesizer acutally works.
    119644: 07/05/24: Re: How the synthesizer acutally works.
    119645: 07/05/24: Re: How the synthesizer acutally works.
    120085: 07/05/31: Re: Ise Flow with PowerPC
    120106: 07/06/01: Can anyone explain the details of the FPGA design flow in ISE
    120107: 07/06/01: Can anyone explain the details of the FPGA design flow in ISE
    120109: 07/06/01: Some doubts in the FPGA design flow in the ISE
    120116: 07/06/01: Re: Xilinx MIG and verifying UCF files
    120920: 07/06/20: Re: MIG for Virtex-4 DDR dimm, only 165 Hz?
    121432: 07/07/03: Simulation problem
    121471: 07/07/05: Re: Simulation problem
submachine:
    152002: 11/06/21: Xilinx ISE ignores Max Fanout
Subodh Nijsure:
    32674: 01/07/04: Downloading FPGA (XBN) bitstream to XCV50E
    32708: 01/07/05: Downloading file to Xilinx (Vertex_E) FPGA.
    32757: 01/07/07: Re: Downloading FPGA (XBN) bitstream to XCV50E
    33016: 01/07/15: Re: Downloading file to Xilinx (Vertex_E) FPGA.
Subra:
    77183: 04/12/28: Re: RAM programming by JTAG (i need some serious help)
    77184: 04/12/28: Re: Programming flash connected to CPLD via JTAG
Subramnyeswar Saladi:
    4932: 97/01/01: Re: What Does ASIC Stand For?
Subroto Datta:
    49839: 02/11/22: Re: Altera Logick lock newbie
    49885: 02/11/24: Re: What's the matter with "clock skew and data delay"?
    50240: 02/12/06: Re: Can QUARTUS open *.vec file?
    50569: 02/12/13: Re: Problem with Symbol generation in Quartus2
    50909: 02/12/23: Re: Compiling Altera LPM on leonardo
    50937: 02/12/23: Re: Pin definition in Quartus
    51129: 03/01/03: Re: quartus-bus problem
    51239: 03/01/08: Re: Bug in Quartus2 Web 2.2
    51296: 03/01/10: Re: Bug in Quartus2 Web 2.2
    52082: 03/01/31: Re: How to set leonardo path in Quartus?
    52084: 03/01/31: Re: Quartus
    52097: 03/01/31: Re: How to set leonardo path in Quartus?
    52236: 03/02/05: Re: Can't start server quartus_cmp in quartus II 1.0
    52755: 03/02/20: Re: Quartus II problem
    52995: 03/02/27: Re: Initializing multi-ported memories using MIF
    53154: 03/03/05: Re: How to select the chip before using FPGA?
    53224: 03/03/07: Re: altera quartusII help
    53850: 03/03/25: Re: Quartus-II, how to use a user package
    53972: 03/03/28: Re: Leonardo problem
    54289: 03/04/07: Re: price of fpga chips
    54363: 03/04/09: Re: precision RTL/Synplify/LeonardoSpectrum/Quartus
    54500: 03/04/11: Re: precision RTL/Synplify/LeonardoSpectrum/Quartus
    54512: 03/04/12: Re: Quartus II and user libraries
    54525: 03/04/13: Re: Help installing Altera web tools
    54541: 03/04/13: Re: Help installing Altera web tools
    55224: 03/05/01: Re: Defining I/O pin as registered on Quartus II (v2.2)
    55571: 03/05/13: Re: QuartusII issue
    56146: 03/05/29: Re: Simulation in Altera Quartus II
    57169: 03/06/24: Re: Quartus II for Linux
    57368: 03/06/28: Re: why so many problems Xilinx ?
    57388: 03/06/29: Re: why so many problems Xilinx ?
    57440: 03/06/30: Re: Quartus produces wrong parameters for Stratix PLL
    57508: 03/07/01: Re: Quartus produces wrong parameters for Stratix PLL
    57645: 03/07/03: Re: NIOS tutorial for the Stratix1S10
    57679: 03/07/03: Re: Using Quarus to create SVF files?
    57690: 03/07/03: Quartus II 3.0 Release & Web Edition Download Links
    57718: 03/07/04: Re: Quartus II 3.0 Release & Web Edition Download Links
    58007: 03/07/11: Re: Quartus warning in NUMERIC_STD.vhd
    58241: 03/07/17: Re: Using Quartus II 3.0 w/ self-made byteblaster cable
    58564: 03/07/26: Re: Multi Cycle path and False paths
    58695: 03/07/31: Re: apex20ke library and simulation
    58812: 03/08/01: Re: How to update LPM_ROM in ALTERA device quickly?
    59124: 03/08/08: Re: Excalibur - lpm_syncram
    59222: 03/08/12: Re: Excalibur - lpm_syncram
    59270: 03/08/13: Re: Cyclone's LVDS and Quartus II
    59279: 03/08/13: Re: Limitations of Quartus II V3.0 Web
    59367: 03/08/17: Re: SynplifyPro Mapper runs endlessly
    59398: 03/08/18: Re: Quartus and dcfifo
    59897: 03/08/31: Re: Question conserning Altera's Quartus II
    59967: 03/09/02: Re: Altera Devices
    60166: 03/09/06: Re: Include design file using QuartusII
    60632: 03/09/18: Re: Quartus II 2.2 smart compile ignoring .mif
    60940: 03/09/25: Quartus Usability Feedback
    61156: 03/09/29: Re: Implementing Bidirectional pins
    61279: 03/10/01: Re: ByteBlaster with USB<->PP adapter?
    61332: 03/10/02: Re: Looking for recent Altera Quartus Verilog synthesis experience
    61478: 03/10/05: Re: Reusing code (Altera Quartus II 3.0)
    61519: 03/10/06: Re: synplify vqm not able to fit in Quartus
    61710: 03/10/09: Re: Quartus, JTAG, Programming Hardware
    61727: 03/10/09: Re: Quartus II simulation question.
    61738: 03/10/09: Re: Quartus, JTAG, Programming Hardware
    61802: 03/10/12: Re: Quartus help with package declaration
    62108: 03/10/20: Re: Several Quartus II 3.0 questions
    62191: 03/10/22: Re: Strange error in Quartus II 3.0
    62218: 03/10/22: Re: Running Quartus II on ReadHat Linux 9.0
    62230: 03/10/22: Re: Strange error in Quartus II 3.0
    62283: 03/10/24: Re: Running Quartus II on ReadHat Linux 9.0
    62284: 03/10/24: Re: Scripting (was: Re: Running Quartus II on ReadHat Linux 9.0)
    62324: 03/10/27: Re: Hex display with Quartus simulation
    62360: 03/10/28: Re: How to import QuartusII simulation waveform (vwf) and block design file(bdf) to the Word (.doc)
    62509: 03/10/31: Re: Address Mapping in 4K RAM Blocks in Altera Cyclone Devices
    63126: 03/11/15: Re: Stratix & PLL
    63178: 03/11/17: Re: Altera's altsyncram MAXIMUM_DEPTH
    63184: 03/11/17: Re: Altera synthesis of registered signals ???
    63321: 03/11/19: Re: Altera's altsyncram MAXIMUM_DEPTH
    63449: 03/11/21: Re: Quartus II Node Finder
    63732: 03/12/02: Re: Design analyse methods
    63864: 03/12/06: Re: VHDL-Testbench-Simulation in QuartusII
    63882: 03/12/07: Re: How to assign inferred logic to resource in Quartus
    63886: 03/12/07: Re: Altera's altsyncram MAXIMUM_DEPTH
    63916: 03/12/09: Re: Quartus-II question
    63917: 03/12/09: Re: VHDL-Testbench-Simulation in QuartusII
    64965: 04/01/16: Re: Altera Cyclone Programming device programming
    65068: 04/01/19: Re: Memory Initialization Files in Modelsim
    65110: 04/01/20: Re: Memory Initialization Files in Modelsim
    65191: 04/01/22: Re: Synthesis errors?
    65295: 04/01/23: Re: Quartus doesn't work with Pentium Hypertheading!
    65568: 04/02/02: Re: Differences between Xilinx ISE and Altera Quartus software
    65615: 04/02/03: Re: Altera programming
    65724: 04/02/05: Re: Quartus II taking forever to compile
    65754: 04/02/05: Re: Quartus II and Synthesis
    66009: 04/02/11: Re: .mif or .hex memory files?
    66023: 04/02/11: Re: JAM and Xilinx/Altera CPLDs
    66090: 04/02/12: Re: Altera EPC16 Configuration Problem
    66215: 04/02/14: Re: quartus II 3.0 , block editor, how to connect signals of buses
    66305: 04/02/17: Re: Manual Partitioning to Multiple FPGAs
    66602: 04/02/23: Re: Barrel shifter synthesis in QuartusII
    66656: 04/02/24: Re: spying on signals in Quartus (newbie question)
    66912: 04/03/01: Re: nios board, apex, tutorial doesn't work
    67158: 04/03/07: Re: Documentation and manuals for Quatus 3.0...
    67195: 04/03/08: Quartus II 4.0 Web Edition Software & Documentation - Available for download
    67229: 04/03/09: Re: Using ALTPLL
    67346: 04/03/10: Re: Quartus II version 4 (Web Edition) DOES NOT WORK AT ALL !?
    67378: 04/03/11: Re: Quartus II version 4 (Web Edition) DOES NOT WORK AT ALL !?
    67446: 04/03/12: Re: Quartus II 3.0 sp1 web, verilog input, memories optimized away ?
    67513: 04/03/13: Re: Altera, Cyclone: pin not connected warning
    67643: 04/03/16: Re: Schematic Editor in QuartusII version4.0
    67644: 04/03/16: Re: Schematic Edition Tool : Suggestions
    67658: 04/03/16: Re: Schematic Edition Tool : Suggestions
    67680: 04/03/17: Re: Speed of Linux vs Solaris
    67683: 04/03/17: Re: Schematic Edition Tool : Suggestions
    67713: 04/03/17: Re: Altera Quartus II 4.0 won't talk to ByteBasterMV
    67730: 04/03/18: Re: Cyclone refuses quartusII bitfiles
    67975: 04/03/23: Re: Quartus with AMD64 processors?
    68003: 04/03/24: Re: Quartus with AMD64 processors?
    68004: 04/03/24: Re: Quartus with AMD64 processors?
    68005: 04/03/24: Re: Quartus with AMD64 processors?
    68301: 04/04/01: Re: Utility for converting .esf file to .tcl file
    68414: 04/04/03: Re: The Logic Behind License Renewal
    68625: 04/04/10: Re: regardinng static timing annalysis
    68681: 04/04/14: Re: Writing PCI constraints in Altera
    68783: 04/04/18: Re: Altera flex 10k library component doubt
    69052: 04/04/26: Re: Writing PCI constraints in Altera
    69206: 04/04/30: Re: Quartus II Schematic Capture
    69341: 04/05/07: Re: Mutiple Quartus Instances?
    69369: 04/05/08: Re: SignalProbe in Quartus...
    69574: 04/05/14: Re: Quartus II Web Edition
    69614: 04/05/15: Re: Quartus Internal Errors
    69724: 04/05/19: Re: NIOS Board Stratix Edition - FPGA won't configure
    69792: 04/05/20: Re: NIOS Board Stratix Edition - FPGA won't configure
    69995: 04/05/26: Re: Altera LP4 Need Help With Device Drivers and Setting Up
    70404: 04/06/15: Re: Stratix DSP Block: Choosing which FFs are enabled
    70417: 04/06/16: Re: importing a design from maxplus2 to quartus II ver 3
    70479: 04/06/17: Re: Quartus II - Disabling the Optimizer to use gate delay
    70552: 04/06/20: Re: Altera Quartus II on Linux
    70679: 04/06/23: Re: Trying to remember how to use Quartus
    70712: 04/06/24: Re: Trying to remember how to use Quartus
    70744: 04/06/25: Re: Why does Quartus take 4 hours for a pin I/O change?
    71021: 04/07/06: Re: seperate fpga programm and a table in altera
    71042: 04/07/06: Re: Puzzled Simulating with 'X' input Quartus II v4.0 sp1
    71266: 04/07/13: Re: Quartus II 4.0 SP1 Warning: Can't find design file .../projectname0.rtl.mif
    71271: 04/07/13: Re: Puzzled Simulating with 'X' input Quartus II v4.0 sp1
    71459: 04/07/19: Re: How Bidirectional (AHDL) or INOUT (VHDL) are displayed in the Waveform Simulation?
    71539: 04/07/21: Re: Altera DEMUX Megafunction - does it exist ?
    71614: 04/07/25: Re: Image export from Quartus?
    71725: 04/07/28: Re: Choosing PLL
    71823: 04/08/01: Re: Downloading program to Nios
    71829: 04/08/01: Re: LE and EAB on FPGA board
    71941: 04/08/04: Re: Guidelines for Timing Closure on FPGAs
    72236: 04/08/12: Re: How important are software tools while choosing FPGA
    72292: 04/08/13: Re: What schematic tool (VHDL) is the best?
    72293: 04/08/13: Re: How important are software tools while choosing FPGA
    72321: 04/08/15: Re: clock enable multicycle doesn't work with altera altshift_taps megafunction
    72419: 04/08/18: Re: What schematic tool (VHDL) is the best?
    72426: 04/08/18: Re: Secret to SignalTapII Incremental Build?....
    72542: 04/08/23: Re: Secret to SignalTapII Incremental Build?....
    72586: 04/08/25: Re: Altera Quartus II 4.1 double-click on QPF-File doesn't work
    72776: 04/09/01: Re: Sentinel dongle no longer detected by Quartus
    72783: 04/09/01: Re: Altera LVDS Transceiver Megafunction - ALTLVDS - question
    73889: 04/09/30: Re: Quartus II annoyance
    73954: 04/10/01: Re: altera quartus II handbook is wrong??
    72985: 04/09/09: Re: Quartus II and MAX7000S unused pins
    72986: 04/09/09: Re: AMBA AHB
    73205: 04/09/15: Re: altera quartus II handbook is wrong??
    73860: 04/09/30: Re: Programming Cyclone 1C20 board
    74021: 04/10/02: Re: How to get 27MHz from 10 MHz in FPGA???
    74050: 04/10/03: Re: JOP on Spartan-3 Starter Kit
    72906: 04/09/08: Re: Quartus2 V4.1 SP1
    72907: 04/09/08: Re: Quartus2 4.1 SP1 Hangs
    73034: 04/09/11: Re: Simulation probs with Altera LPM_FIFO+
    73214: 04/09/16: Re: Programming Altera Config Device
    73355: 04/09/20: Re: Bi Dir Synthesis Problem in Quartus?
    73399: 04/09/21: Re: Tcl script window does not appear
    73400: 04/09/21: Re: Bi Dir Synthesis Problem in Quartus?
    73448: 04/09/22: Re: Quartus In-system Memory bug
    74175: 04/10/05: Re: Altera Quartus II 4.1 double-click on QPF-File doesn't work
    74258: 04/10/06: Re: Ripple counter ?
    74637: 04/10/15: Re: altera quartus II handbook is wrong??
    75033: 04/10/25: Re: initializing custom memory with .mif (or .hex) in Quartus 3
    75069: 04/10/26: Re: Async reset
    75538: 04/11/09: Re: QuartusII, Flex10K & fan-out
    75609: 04/11/11: Re: Timing Issues in Quartus design
    75694: 04/11/12: Re: Demote assignments
    76182: 04/11/28: Re: Choice of FPGA device -- my view on benchmarks
    76207: 04/11/28: Re: 18x18 Multipliers - Spartan III
    76485: 04/12/03: Re: Cylone Problem with Large Shift Register
    76809: 04/12/13: Re: altera DDR core simulation with NCSim
    76834: 04/12/14: Re: altera DDR core simulation with NCSim
    76900: 04/12/15: Re: Is it me or quartus ?
    76906: 04/12/15: Re: Altera Quartus II 4.2 broke our simulation!
    76907: 04/12/15: Re: Quartus II Graphic Editor Anomaly?
    77239: 05/01/01: Re: Free tools
    77263: 05/01/02: Re: Quartus and Cyclone programming problem
    77451: 05/01/07: Re: Altera Quartus Error How to track donw.
    77470: 05/01/07: Re: Altera Quartus Error How to track donw.
    77567: 05/01/11: Re: altera stratix problem
    77584: 05/01/11: Re: use of JTAG pins
    77631: 05/01/12: Re: Signaltap - Finding Nodes - FSM state register
    77816: 05/01/18: Re: Quartus II Command Line and Project Files
    77865: 05/01/19: Re: Timing Assignments in Cyclone/Stratix
    77936: 05/01/20: Re: Problem with Signal Tap II Logic Analyzer in Altera Quartus II 4.1 and Microtronix Stratix development board
    78314: 05/01/29: Re: Altera Quartus 4.2 Service Pack 1 fails to install
    78331: 05/01/29: Re: Altera Quartus 4.2 Service Pack 1 fails to install
    78355: 05/01/30: Re: Altera Quartus 4.2 Service Pack 1 fails to install
    78663: 05/02/05: Re: Altera, QuartusII and internal tristates
    78674: 05/02/05: Re: Altera FLEX 8000
    78773: 05/02/07: Re: Quartus project files
    78842: 05/02/08: Re: Quartus project files
    78844: 05/02/08: Re: quartus "make clean" ?
    78889: 05/02/09: Re: quartus - Linux or Windows
    79048: 05/02/11: Re: Altera's Megafunction altaccumulator
    79250: 05/02/16: Re: Questions about multiple rom instances in Quartus II
    79283: 05/02/16: Re: Questions about multiple rom instances in Quartus II
    79954: 05/02/27: Re: block adder for Altera!
    81080: 05/03/17: Re: Altera free web FPGA software license question
    81402: 05/03/23: Re: Xilinx ISE 7.1 - Can this get any worse?
    81487: 05/03/24: Re: Xilinx ISE 7.1 - Can this get any worse?
    81812: 05/04/01: Re: Hierarchy in Schematic-VHDL Design
    82430: 05/04/12: Re: General question about soft CPUs
    82446: 05/04/12: Re: Altera and VHDL library
    82450: 05/04/12: Re: Quartus POWER_UP_LEVEL bug?
    82511: 05/04/13: Re: Altera and VHDL library
    82774: 05/04/18: Re: Multi-page schematics (.bdf) in Quartus II?
    82956: 05/04/20: Re: Unconstrained ports for synthesis
    82981: 05/04/20: Re: Unconstrained ports for synthesis
    83230: 05/04/26: Re: quartus_pgm under Linux?
    83249: 05/04/26: Re: quartus_pgm under Linux?
    83260: 05/04/26: Re: quartus_pgm under Linux?
    83326: 05/04/27: Re: MAX II UFM data specification and programming
    84136: 05/05/13: Re: Input Maximum Delay timing assignment in Altera
    84191: 05/05/14: Re: Input Maximum Delay timing assignment in Altera
    84234: 05/05/16: Re: Input Maximum Delay timing assignment in Altera (Delay settings in Quartus)
    84556: 05/05/20: Re: Jam Byte-Code Player for 8051
    84576: 05/05/21: Re: VHDL vs. Schematic Capture
    84578: 05/05/21: Re: VHDL vs. Schematic Capture
    84814: 05/05/28: Re: Synplify 8.1 vs. Quartus II 5.0 QoR
    84823: 05/05/28: Re: Synplify 8.1 vs. Quartus II 5.0 QoR
    86163: 05/06/22: Re: FPGAs: Where will they go?
    88016: 05/08/05: Re: Quartus II 4.2 Incremental Systhesis
    88075: 05/08/08: Re: Holding in output registers
    88336: 05/08/15: Re: AHDL Abandoned in Quartus?
    88417: 05/08/17: Re: Problem with quartus 5.0 sp1
    88481: 05/08/19: Re: PLL
    88560: 05/08/23: Re: Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;
    89235: 05/09/08: Re: Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;
    89269: 05/09/09: Re: Quartus II - Timing Analyzer
    89627: 05/09/21: Re: problem with Thold violation under quartus
    89639: 05/09/21: Re: Output register instantiation in Quartus
    89674: 05/09/22: Re: Output register instantiation in Quartus
    89753: 05/09/24: Re: Output register instantiation in Quartus
    89821: 05/09/27: Re: ALTERA quartus II 5.0sp1 web edition can't program MAXII: error code 84
    90432: 05/10/13: Re: Compiling Altera LPM FIFO into Modelsim Error
    91199: 05/11/01: Re: Simulating Cyclone II PLL
    91764: 05/11/12: Re: Difficulty compiling on Quartus 2 version 5
    91900: 05/11/16: Re: Quartus crash
    92002: 05/11/19: Re: hi everyone, tell me something about Cyclone II.
    92521: 05/12/01: Re: Download old Quartus versions (4.0, 4.1)
    92545: 05/12/01: Re: Quartus db issue
    94035: 06/01/04: Re: Schematic Entry, Xilinx or Altera?
    94493: 06/01/12: Re: boundary scan of altera epm570F
    96598: 06/02/07: Re: doubt
    97068: 06/02/16: Re: What is back_annotate?
    99511: 06/03/25: Re: Nios II - Branch Prediction
    99758: 06/03/29: Re: Bidirectional signals with Altera Signaltap
    101370: 06/04/30: Re: Quartus and source control
    101484: 06/05/02: Re: Quartus and source control
    101509: 06/05/02: Re: Quartus and source control
    101701: 06/05/05: Re: Quartus and source control
    102111: 06/05/10: Re: Altera Max Plus II to Quartus migration tool
    102635: 06/05/18: Re: Where can i get "Quartus II Device Information for UNIX & Linux CD"
    103676: 06/06/07: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
    103757: 06/06/10: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
    103839: 06/06/13: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
    104202: 06/06/21: Re: Quartus 6.0 Fitter Critical Warning
    104205: 06/06/21: Re: Stratix column and row pins
    104700: 06/07/04: Re: ASCI to FPGA - require details
    105003: 06/07/11: Re: Assigning unused pins in Quartus II
    105004: 06/07/11: Re: DIFFICULT MULTICYCLE PATH WITH QUARTUS II
    105016: 06/07/12: Re: Assigning unused pins in Quartus II
    105279: 06/07/19: Re: corrupted data when accessing dual port bram in Cyclone II
    105290: 06/07/19: Re: Reuse a Speed Grade -8 Stratix image in Speed Grade -6 ...?
    105426: 06/07/22: Re: clock hold time problems reported in quartus II
    105995: 06/08/04: Re: Cyclone I & II memory fmax
    106659: 06/08/16: Re: Quartus and source control (continued)
    107295: 06/08/26: Re: Installing Quartus 6 "web edition full"
    108458: 06/09/11: Re: exporting an image with quartus 2 web edition
    108486: 06/09/12: Re: Help for Altera Nios II Cyclone EP1C12 evaluation kit!
    109273: 06/09/22: Re: Altera configuring/programming for FLEX10KE with EPC2 - sof or pof?
    109547: 06/09/28: Re: QuartusII: how to find out all the instances of a VHDL module in a design?
    109743: 06/10/05: Re: logic analyzer signal tap 2 - writing data
    109816: 06/10/05: Re: logic analyzer signal tap 2 - writing data
    110023: 06/10/09: Re: logic analyzer signal tap 2 - writing data
    110170: 06/10/11: Re: boundary scan
    110174: 06/10/12: Re: Altera Quartus II 5.1 SP2 fails on MIF/HEX reconfig
    110230: 06/10/12: Re: Altera Quartus II 5.1 SP2 fails on MIF/HEX reconfig
    111005: 06/10/26: Re: Quartus DSP Blocks
    111723: 06/11/08: Re: Modelsim problem - mixed VHDL,Verilog & VHO
    112202: 06/11/17: Re: state problems with Quartus II 6
    112338: 06/11/20: Re: Need examples/instruction: use of altpll_reconfig (Altera)
    112339: 06/11/20: Re: Need examples/instruction: use of altpll_reconfig (Altera)
    112676: 06/11/27: Re: tips for P&R in FPGA(quartus)
    112809: 06/11/29: Re: FPGA workstation - should I wait for Window Vista?
    112957: 06/12/02: Re: Hi
    113045: 06/12/05: Re: Using quartus "In system memory editor" from command line
    113073: 06/12/06: Re: query in gate level simulationin quartus s/w 6.0
    113146: 06/12/06: Re: Registers initial values with Altera Stratix II
    113648: 06/12/18: Re: incremental compiles in quartus
    113672: 06/12/19: Re: C2H problems
    114251: 07/01/08: Re: Altera Cyclone II die revision?
    115349: 07/02/07: Re: Altera ByteBlaster and SignalTap on Fedora Core
    116729: 07/03/16: Re: old Quartus project files
    117778: 07/04/10: Re: Newbie with bus width mismatch problem. Quartus II
    117877: 07/04/12: Re: Which are the best books about CORDIC algorithms and applications
    118812: 07/05/04: Re: Use of "blocks" in Quartus design
    118929: 07/05/07: Re: License problems with Quartus 7.0 on Linux
    120269: 07/06/04: Re: Quartus-II 7.1 Systemverilog support define `` ?
    122396: 07/07/26: Re: Question about Bottom-Up Incremental Compilation Methodology in Quartus II
    122470: 07/07/27: Re: Question about Bottom-Up Incremental Compilation Methodology in Quartus II
    122539: 07/07/30: Re: Question about Bottom-Up Incremental Compilation Methodology in Quartus II
    124128: 07/09/12: Re: Stratix III Memory usage efficiency
    125462: 07/10/26: Re: compile EDIF(generated by Celoxica DK4) using Quartus II
    126996: 07/12/07: Re: Pin assignment with Quartus II for PCB placement
    127011: 07/12/08: Re: Which FPGA and memory to use? The eternal X vs. A question.
    127508: 07/12/30: Re: How to inhibit a timing warning
    130289: 08/03/19: Re: Using TimeQuest Timing Analyzer
    133924: 08/07/19: Re: Howto disable Quartus infering M4Ks??
    134588: 08/08/19: Re: altera cyclone3 vertical migration
    137018: 08/12/18: Re: Altera Quartus II - 64 bit?
<Subscribe2@Juno.com>:
    4752: 96/12/11: Good Quotes (xgmgeb)
<success114@aol.com>:
    13982: 99/01/06: Great NEW Search Engine--> WWW.ISEARCH.TO
<sucharita@my-dejanews.com>:
    12539: 98/10/15: XILINX 4000XL configuration using M 1.5 JTAG programmer
suchitra:
    44637: 02/06/25: cpld fpga programming
    45420: 02/07/22: cpld programming
    45572: 02/07/26: can 555 be used as clock input to cplds
    46259: 02/08/22: programming xc9536 xl
    49564: 02/11/15: cpld pin configuration is wrongly assigned
<sudarangareddy@yahoo.com>:
    89384: 05/09/13: ARM IP Core implementation in FPGA
    90970: 05/10/26: Physical interface for PCI express(PIPE) electrical information
sudarshan banerjee:
    72262: 04/08/12: vertex-II configuration architecture
<sudarshan.onkar@gmail.com>:
    119549: 07/05/22: ISE Service pack
    119558: 07/05/22: ISE Service pack
sudha:
    77274: 05/01/03: Re: CAN WE HAVE SIGNALS WITH MULTIPLE SOURCES IN VHDL?
<sudhakarmvs@gmail.com>:
    119347: 07/05/17: DDR 2 Memory controller own implementattion
    119531: 07/05/22: Re: DDR 2 Memory controller own implementattion