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Doesn't look like much. Try http://www.synplicity.com/literature/pdf/synplify_rnotes.pdf Mostly Virtex2 and other new devices. Thank you for mentioning it, however. I didn't know there was a new version. Alan Nishioka alann@accom.com lyqin@cti.com.cn wrote: > Anyone knows? > > Leon QinArticle: 30176
Spartan-II has the same programming requirements as Virtex. Like all other Xilinx FPGAs since 1985, it accepts a serial bitstream as an input, and generates CCLK as a clock for the SPROM. You can use any serial PROM you can find, that generates the right output level and accepts the right clock level and speed. There is nothing mystical about special Spartan SPROMs. Maybe they are cheaper so they fit the economical model better... Peter Alfke, Xilinx Applications =========================================================== "Wade D. Peterson" wrote: > Hi All: > > I need to find a configuration PROM for a Spartan-II device from Xilinx. Xilinx > has a new series of parts called the 'XC17S00A series (specifically, the > XC17S150APD8C) that are intended for the Spartan-II. However, these appear to > be hard to find, plus my programmer doesn't support them yet. Does anybody know > of any alternatives? > > Also, does anybody know if the older Spartan PROMs work with the Spartan-II? > > -- > Wade D. Peterson > Silicore Corporation > URL: www.silicore.netArticle: 30177
Thanks to all of you who responded. Yes, Ray, I think placing the BlockRAMs manually is simple and will lead to better results. I just looked at my auto placed one and it is pretty odd. So that's what I'll do. And yes, Philip, XDL would be the way to properly automate it. I don't think Student Edition includes it, but anyway as you surely guessed I don't want to invest that much work into it. Philip wrote: > I believe that virtex/spartan-II devices allow partial reconfig, including > only loading/reloading the BRAM, so theoretically, you might even > be able to have a program running out of one BRAM, and the program > is talking to the reconfiguration logic, loading a new program into another > BRAM, (another part of the I address space), and then you could jump to it. Yeah. I've long thought it would be so cool for an FPGA CPU to partially reconfig itself. Who will be the first? I'm still surprised that par doesn't write a placement report. I'm sure I remember one from the old XC3090 days. Grumble. See you all at http://www.fccm.org !!! --MikeArticle: 30178
> Anybody know something about modeling Asynchronus Machine States in >FPGA? >I need some information about that. If anyone knows pages about that or have >some >information please write to me. > Try following the links at Manchester University's web site: http://www.cs.man.ac.uk/async/ Do a web search and try your nearest University Library. This subject is a favourite for academics. HTH David.Article: 30179
Hi,
I am currently using Xilinx Foundation software for our FPGAs. Now I
want to start a Spartan II design using the WebPack ISE software
package. I want to use the Cores generated with the foundation's core
generator. How can I do that ? It seems that I have to add the Xilinx
Coregenerator library. How can I do that ?
Can anybody give me a short advice ?
Matthias
--
-------------------------------------------------
\ Matthias Fuchs \
\ esd electronic system design Gmbh \
\ Vahrenwalder Straße 205 \
\ D-30165 Hannover \
\ email: matthias.fuchs@esd-electronics.com \
\ phone: +49-511-37298-0 \
\ fax: +49-511-37298-68 \
--------------------------------------------------
Article: 30180
> You really want to do asynchronous state machines?? AFAIK this is a big
> NO-NO in most designs, because its too hard to debug, validate . . . .
Yes, I really wano to asynchronous state machice (read have to :-))).
Thanks to all from information.
regards
Marcin Michalak
"Marcin Michalak" <M.Michalak@aldec.zgora.pl> wrote in message
news:99nkhf$b5q$1@news.tpi.pl...
> Hi!!
>
> Anybody know something about modeling Asynchronus Machine States in
> FPGA?
> I need some information about that. If anyone knows pages about that or
have
> some
> information please write to me.
>
> regards
>
> Marcin Michalak
>
>
Article: 30181Jim Granville wrote: > > muzaffer@dspia.com wrote: > > > > hi, > > I have an application where I have to detect whether two clocks are > > within a certain frequency range with each other. IOW, I need to be > > able to detect whether the frequencies are within %2 of each other. > > The idea I am using is to run two counters, one on each clock and when > > one overflows, check the other to see how close it is. The decision is > > made based on the value of the other counter being close enough to > > zero or not. The other counter is then reset so that both start at > > zero again. I am running the decision logic on one of the clocks and > > the other counter is a gray counter. But of course there are a couple > > of issues with respect to metastability here. The value of one counter > > needs to cross one clock boundary to be compared against zero and the > > reset signal on overflow needs to cross a clock boundary in the other > > direction. I am having difficulty coming up with a robust design and > > asking for suggestions. > > > > thanks, The robust method is to multiply the signal with the frequency f1 to the signal with the frequency f2, then the resulting signal consists of frequencies f1+f2 and f1-f2. When f1-f2 to select by the low frequency filtering then such a signal frequency can be estimated by usual frequency meter. The multiplication can be implemented as XOR. The filtering is for instance the ORing the neighboring samples, and sampling with lower CLK frequency, or other method to suppress short impulses. Regards, A.Ser.Article: 30182
"Rick Filipkiewicz" <rick@algor.co.uk> wrote > > Marcin Michalak wrote: > > > > > Anybody know something about modeling Asynchronus Machine States in > > > FPGA? > > > I need some information about that. If anyone knows pages about that or have > > > some > > > information please write to me. > and then reserve that amount of time again x4 (min) to get it working after > power-up. But they are the future. OTOH, as Keynes said, "The trouble with the long run is that in the long run we will all be in wooden boxes." For some recent work on this stuff, go to the Sun site and search for "FleetZero", by Ivan Sutherland and friends.Article: 30183
Marc Battyani wrote: > > So I restored the last known good version which was quite ok > with Foundation 2.1 > The pb is that I when I compile it with F3.1 It optimizes away > 99¨% of the design! Hi You may have forgotten to select an option which should look like "IOBUF insertion", which was the default in 2.1i and might not be in 3.3 If the synthesis tool didn't add the input and output buffers, the mapper considers your design has no connection with the pads and optimizes it all away. -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 30184
They may be teh wave of the future, but the fact of the matter is current FPGAs are designed for synchronous logic and make very poor platforms for asynchronous designs. It can be done, as evidenced by the work of several researchers as well as some commercial designers. The FPGA's structure (LUTs, which make cover terms meaningless) and lack of control over routing at the design level make it extraordinarily hard to do a proper asynchronous design. Simon Bacon wrote: > > "Rick Filipkiewicz" <rick@algor.co.uk> wrote > > > > Marcin Michalak wrote: > > > > > > > Anybody know something about modeling Asynchronus Machine States in > > > > FPGA? > > > > I need some information about that. If anyone knows pages about that or > have > > > > some > > > > information please write to me. > > > and then reserve that amount of time again x4 (min) to get it working after > > power-up. > > But they are the future. OTOH, as Keynes said, "The trouble with > the long run is that in the long run we will all be in wooden boxes." > > For some recent work on this stuff, go to the Sun site and search > for "FleetZero", by Ivan Sutherland and friends. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30185
Port enable pin now pulled low via 10K resistor as shown in XAPP343, no difference. Re-wiring the JTAG port to an external Altera Byte Blaster cable running at 3.3V and the target device at 3.3V and the rest of the target board running at 5V device can be programmed, verified, erased without problem. However, I am attempting to program the device from the contents of a BIF file via the target CPU (saves connectors and having to open the box). This fails. As I said previously this process worked without problem on a PZ5128 device but won't now. Has the format of the BIF file been changed, i.e. do I still look for the 10, 01 binary patterns to insert 100ms delays? Any further assistance would be greatfully received. Jennifer Jenkins wrote in message <3ABF767D.47D27611@xilinx.com>... >Ian, > >I'm not sure if the issue is with the Port Enable pin or not. Is there a reason >you have the Port Enable pin connected to reset on the processor? I'm sure >about the length of the processors' reset, but you may still be configuring the >device and toggling the Port Enable pin at the same time. If you are not using >the JTAG pins for I/O, you should externally pull down the port enable pin. The >Port Enable pin is only pulled high when the device has been configured where >the JTAG pins are used for I/O and it is desired to reclaim the JTAG pins. For >more information on the Port Enable pin operation - please refer to XAPP343, >which can be found at http://www.xilinx.com/xapp/xapp343.pdf. > >Are you able to perform a verify with the parallel cable and the PC-ISP >software? > >Thanks, >Jennifer > > >Ian McCarthy wrote: > Snip... > Has anyone got any experience of this process with this device as at present >> I can see no solution. >> >> Many thanks in advance >> >> Ian McCarthy >> ianmccarthy@casella.co.uk >Article: 30186
Dave Brown wrote: > > I'm failry new to FPGA's and I just noticed that an example I synthesized > had a .bit file size that was 166KB and the coresponding .hex file I made > with PROM File Formatter was 329KB. The 166KB I can undersatnd, this is just > the 1335840 configuration bits for the Spartan II S200 device. Why is the > .hex file so much bigger? Is it always bigger? Is it always the same size > for a given device? And finally, how big would a hex file be for an > XCV1000E? > Thanks > Dave Hi Dave, the .bit file represents the data in binary format (8 configuration bits per byte), plus a specific header. The .hex file represents them in text format with 4 configuration bits per character (characters 0-9, A-F). There are many hex file formats; the Xilinx one has pure configuration data, no header and no adress information (which would be meaningless for fpgas). Therefore the .hex file size is a little less than 2 * .bit file size. For a given device, it is always the same, because you must always load all the configuration bits, regardless of the size of your design. The size of the .bit file varies a little with your design, because the name of the design is recorded in the .bit file header. The hex file size for XVC1000E should be about 1600kB. Greetings WernerArticle: 30187
Unfortunately CoreGen is not included with the free Webpack tool. See the following support solution for more information: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=9858 Chris Matthias Fuchs wrote: > Hi, > > I am currently using Xilinx Foundation software for our FPGAs. Now I > want to start a Spartan II design using the WebPack ISE software > package. I want to use the Cores generated with the foundation's core > generator. How can I do that ? It seems that I have to add the Xilinx > Coregenerator library. How can I do that ? > > Can anybody give me a short advice ? > > Matthias > -- > ------------------------------------------------- > \ Matthias Fuchs \ > \ esd electronic system design Gmbh \ > \ Vahrenwalder Straße 205 \ > \ D-30165 Hannover \ > \ email: matthias.fuchs@esd-electronics.com \ > \ phone: +49-511-37298-0 \ > \ fax: +49-511-37298-68 \ > --------------------------------------------------Article: 30188
John Grider wrote: > [...] > Yeah, I'm using some Atmel devices quite effectively. Look for the > AT24Cxxx parts... An app note on their site describes the connection to > a Spartan-II... > -- john do you really mean AT24Cxxx (they have I2C interface), not AT17Cxxx (FPGA configuration memories)??? WernerArticle: 30189
I've run into power up problems with the XC95288XL that are similar to those encountered with fpga's. The power up ramp is definitely not monotonic and has three or four quite large current spikes - my current probe says >1.5A ! There are no numbers that I can find in the datasheet about powerup - only an exhortation to provide a smoothly rising ramp. The end result is a chip that just hangs up. So, since since some of you must have found this problem and got round it, what did you do ? I'm thinking along the lines of hanging a large low esr cap or two off the 5V rail and using a low dropout regulator with shutdown (LT1528) for the 3.3 V rail. So, turn on the +5, wait 200 ms and then turn on the LDO. Any comments/ideas ? regards Dave -- "Don't worry - I've read all about this sort of thing in books !" Dave Garnett Metapurple Limited dave.garnett@metapurple.co.ukArticle: 30190
--------------B704D1CFCBE1901BE3BB3A19 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Dave, The right guy to answer this is out of town till Monday, so I will answer as best I can. There were some early lots of XL material that had less than desirable power on behavior. You need to open a case on the hotline, and have them look up the date codes for you, and they can supply you with the answers you need. If you do this online, snip out this reply from me, and add it to the request. When you get the case number, email it to me at austin@xilinx.com and I will make sure it gets to the CPLD expert on Monday if there isn't an answer before then. Having a good low esr resevoir of charge locally (ie a nice big fat cap of 470uF or more) can't hurt. The "jump start" circuit you describe also works. We are putting our finishing touches on six different start circuits for Spartan II applications right now. One caution: some LDO regulators have a pulsed current limit behavior that really confuses the parts. The desirable limiting behavior does not fold-back or shut off (until tens of ms have elapsed!). We all know there is no such thing as monotonic, except in math books, so the real world device really just wants the voltage to be generally increasing (no dips of hundreds of millivolts at critical moments in the internal workings of the device). Of course, you put a load that suddenly goes from 1000 ohms to 2 ohms, and then to some other load value on any power supply, and dips are bound to happen (ESR of power supply has to be finite after all). Austin david garnett wrote: > I've run into power up problems with the XC95288XL that are similar to those > encountered with fpga's. The power up ramp is definitely not monotonic and > has three or four quite large current spikes - my current probe says >1.5A ! > There are no numbers that I can find in the datasheet about powerup - only > an exhortation to provide a smoothly rising ramp. The end result is a chip > that just hangs up. > > So, since since some of you must have found this problem and got round it, > what did you do ? > > I'm thinking along the lines of hanging a large low esr cap or two off the > 5V rail and using a low dropout regulator with shutdown (LT1528) for the 3.3 > V rail. So, turn on the +5, wait 200 ms and then turn on the LDO. > > Any comments/ideas ? > > regards > Dave > > -- > "Don't worry - I've read all about this sort of thing in books !" > Dave Garnett Metapurple Limited > dave.garnett@metapurple.co.uk --------------B704D1CFCBE1901BE3BB3A19 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Dave, <p>The right guy to answer this is out of town till Monday, so I will answer as best I can. <p>There were some early lots of XL material that had less than desirable power on behavior. You need to open a case on the hotline, and have them look up the date codes for you, and they can supply you with the answers you need. <p>If you do this online, snip out this reply from me, and add it to the request. When you get the case number, email it to me at austin@xilinx.com and I will make sure it gets to the CPLD expert on Monday if there isn't an answer before then. <p>Having a good low esr resevoir of charge locally (ie a nice big fat cap of 470uF or more) can't hurt. The "jump start" circuit you describe also works. We are putting our finishing touches on six different start circuits for Spartan II applications right now. <p>One caution: some LDO regulators have a pulsed current limit behavior that really confuses the parts. The desirable limiting behavior does not fold-back or shut off (until tens of ms have elapsed!). <p>We all know there is no such thing as monotonic, except in math books, so the real world device really just wants the voltage to be <i>generally</i> increasing (no dips of hundreds of millivolts at critical moments in the internal workings of the device). Of course, you put a load that suddenly goes from 1000 ohms to 2 ohms, and then to some other load value on any power supply, and dips are bound to happen (ESR of power supply has to be finite after all). <p>Austin <p>david garnett wrote: <blockquote TYPE=CITE>I've run into power up problems with the XC95288XL that are similar to those <br>encountered with fpga's. The power up ramp is definitely not monotonic and <br>has three or four quite large current spikes - my current probe says >1.5A ! <br>There are no numbers that I can find in the datasheet about powerup - only <br>an exhortation to provide a smoothly rising ramp. The end result is a chip <br>that just hangs up. <p>So, since since some of you must have found this problem and got round it, <br>what did you do ? <p>I'm thinking along the lines of hanging a large low esr cap or two off the <br>5V rail and using a low dropout regulator with shutdown (LT1528) for the 3.3 <br>V rail. So, turn on the +5, wait 200 ms and then turn on the LDO. <p>Any comments/ideas ? <p>regards <br>Dave <p>-- <br>"Don't worry - I've read all about this sort of thing in books !" <br>Dave Garnett Metapurple Limited <br>dave.garnett@metapurple.co.uk</blockquote> </html> --------------B704D1CFCBE1901BE3BB3A19--Article: 30191
lyqin@cti.com.cn writes: > Anyone knows? Retiming. Could be useful. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 30192
Chris Ward <elcpw@nospamstudent.lboro.ac.uk> wrote: : Does anyone know of any work to implement unsupervised ANNs in FPGAs : available on the web? There's http://www.axeon.com/ There's http://foobar.starlab.net/~degaris/ See also: http://citeseer.nj.nec.com/did/138153 -- __________ |im |yler Try my latest game - it rockz - http://rockz.co.uk/Article: 30193
vt313@comsys.ntu-kpi.kiev.ua writes: >muzaffer@dspia.com wrote: >> >> I have an application where I have to detect whether two clocks are >> within a certain frequency range with each other. IOW, I need to be >> able to detect whether the frequencies are within %2 of each other. >> The idea I am using is to run two counters, one on each clock and when >> one overflows, check the other to see how close it is. The decision is >> made based on the value of the other counter being close enough to >> zero or not. The other counter is then reset so that both start at >> zero again. I am running the decision logic on one of the clocks and >> the other counter is a gray counter. But of course there are a couple >> of issues with respect to metastability here. The value of one counter >> needs to cross one clock boundary to be compared against zero and the >> reset signal on overflow needs to cross a clock boundary in the other >> direction. I am having difficulty coming up with a robust design and >> asking for suggestions. >> >The robust method is to multiply the signal with the frequency f1 to >the signal with the frequency f2, then the resulting signal consists of >frequencies f1+f2 and f1-f2. >When f1-f2 to select by the low frequency filtering then >such a signal frequency can be estimated by usual frequency meter. >The multiplication can be implemented as XOR. >The filtering is for instance the ORing the neighboring samples, >and sampling with lower CLK frequency, or other method to suppress short >impulses. The question was not the difference, but the ratio. There may be analog ways to do that, too. I suppose I don't see the metastability question that is being asked. Some source will reset both counters and then start the counting. They may start one or two counts apart depending on which edge they are on. It seems that the gray counter needs some more bits to avoid wraparound effects. When the one counter overflows latch the value of the other counter. A gray counter can only changes one bit at a time, so the result can only be off by one. Assuming there are enough bits to detect wraparound one then must compare the gray counter to the constant count of the other. I am assuming that the counts are large enough and that a few missed counts can be tolerated. If this isn't true, the problem is much harder. Just to be different, how about PLLs designed to run at 2% more and 2% less than the input frequency. Then only a greater than/less than detection is needed. -- glenArticle: 30194
catherina wrote: > > HOW?? > > "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message > news:3ABF784C.40CC2A6@gmx.de... > > catherina schrieb: > > > > > > Hi all, > > > > > > Does F3.1 accepts hybrid design top level entry ? > > > > > > I want to instantiate in my top level entry, some modules based on : > > > 1- schematic > > > 2- Edif > > > 3- Structural Vhdl > > > 5- logicore > > > any help (or reference) on how to proceed? > > > > Iam not sure about 2), but the others work. > > > > -- > > MFG > > Falk Build a top level schematic in 3.1 of "black boxes" and inside each instantiate your VHDL or other schematics. I believe the logicores are brought in at compile time but it's been a while so that's a little fuzzy. good luck, -MikeArticle: 30195
Hi, I want to know if there are any expert Board Designers/FPGA Engineers out there, looking for a job? If you are out there , please email me at cvictor@cachevision.com. Cynthia -- Posted from un.cachevision.com [63.150.36.35] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 30196
Cynthia, I am not looking for a job but our company provides expert services for = board level embedded system design and Xilinx FPGA design.=20 Please contact if you need help with some of your projects. Regards,=20 Tom Dillon Dillon Engineering, Inc. http://www.dilloneng.com Original Message dated 3/27/2001, 5:15:31 PM Author: CVictor@CacheVision.com (Cynthia Victor) Re: Any Expert FPGA Engineers out there?: Hi, I want to know if there are any expert Board Designers/FPGA Engineer= s=20 out there, looking for a job? If you are out there , please email me at = cvictor@cachevision.com. Cynthia -- Posted from un.cachevision.com=20 [63.150.36.35] via Mailgate.ORG Server - http://www.Mailgate.ORG=20Article: 30197
I posted a solution last week for this that accurately measures the ratio of the clocks and avoids metastability issues. It is based on a frequency counter that uses one of the clocks to generate a time base over which the other clock is counted. glen herrmannsfeldt wrote: > > vt313@comsys.ntu-kpi.kiev.ua writes: > > >muzaffer@dspia.com wrote: > >> > >> I have an application where I have to detect whether two clocks are > >> within a certain frequency range with each other. IOW, I need to be > >> able to detect whether the frequencies are within %2 of each other. > >> The idea I am using is to run two counters, one on each clock and when > >> one overflows, check the other to see how close it is. The decision is > >> made based on the value of the other counter being close enough to > >> zero or not. The other counter is then reset so that both start at > >> zero again. I am running the decision logic on one of the clocks and > >> the other counter is a gray counter. But of course there are a couple > >> of issues with respect to metastability here. The value of one counter > >> needs to cross one clock boundary to be compared against zero and the > >> reset signal on overflow needs to cross a clock boundary in the other > >> direction. I am having difficulty coming up with a robust design and > >> asking for suggestions. > >> > > >The robust method is to multiply the signal with the frequency f1 to > >the signal with the frequency f2, then the resulting signal consists of > >frequencies f1+f2 and f1-f2. > >When f1-f2 to select by the low frequency filtering then > >such a signal frequency can be estimated by usual frequency meter. > >The multiplication can be implemented as XOR. > >The filtering is for instance the ORing the neighboring samples, > >and sampling with lower CLK frequency, or other method to suppress short > >impulses. > > The question was not the difference, but the ratio. There may be > analog ways to do that, too. I suppose I don't see the metastability > question that is being asked. Some source will reset both counters > and then start the counting. They may start one or two counts apart > depending on which edge they are on. It seems that the gray counter > needs some more bits to avoid wraparound effects. When the one counter > overflows latch the value of the other counter. A gray counter can only > changes one bit at a time, so the result can only be off by one. > Assuming there are enough bits to detect wraparound one then must > compare the gray counter to the constant count of the other. > > I am assuming that the counts are large enough and that a few missed > counts can be tolerated. If this isn't true, the problem is much > harder. > > Just to be different, how about PLLs designed to run at 2% more > and 2% less than the input frequency. Then only a greater > than/less than detection is needed. > > -- glen -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30198
I would like to have a file for each type of device, with the Pin number (such as AB22), the physical name (PIN2), the adjacent CLB (X1Y14), the bank number and a description of the pin. A sample line, not from a real part, might look like: PAD20 X1Y14 AB22 1 IO_LO1P/VREF Currently, for a design going into Virtex E, I am cutting and pasting out of the .pdf pinout table to build a .ucf file. Starting with the .pdf pinout table I get the bank and the pin name, but not the pad or the nearest CLB, unless I care to edit them in by hand. Starting a file like this, I can easily edit this into ucf format, easily sort and search by pad or by CLB location as well as pin name. This would make creating a pinout much easier and less error prone. My question, does this sort of file exist for Virtex E? If so, how can I get a copy? If not, why not? -- Phil HaysArticle: 30199
I'm looking for recommendations for a PCI-X core. I'm working on a design which will be initially implemented in an FPGA. We're targeting a Virtex-II 3000. For initial development, we'll be using PCI @ 33 MHz, then we plan to switch to PCI-X @ 66 MHz (or faster, if possible). Ultimately, we want to harden the design into an ASIC and have PCI-X @ 133 MHz. This is an embedded application, so once we switch to PCI-X, we won't actually need to worry about (plain) PCI anymore, and don't expect to need PCI @ 66 MHz. I know about and am looking into the following cores: 1. Xilinx LogiCORE PCI-X 2. inSilicon PCI-X 3. DCM Technologies Corex-V10 and V20 4. Synopsys DesignWare DW_PCIX 5. Compaq X-caliber (free reference implementation) Does anyone have any experience with any of these, or others, that they can share? I realize that most detailed info on these comes with an NDA attached. My main questions are these: 1. How fast can I do PCI-X in a Virtex-II? 2. Does the core include unencrypted RTL source? (looking for Verilog) 3. Does it come with a testbench? (And is it any good?) 4. What does the interface to the application logic look like? Any info is appreciated. TIA. -cb
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