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Authors (V)

v:
    82017: 05/04/05: Re: IBUFG and BUFG +xilinx
V Crabtree:
    41855: 02/04/09: Kanda AT40K STarter Kit help
V Madhuri:
    68265: 04/03/31: Utility for converting .esf file to .tcl file
V R:
    29098: 01/02/06: Xilinx XC4010
    29128: 01/02/07: Re: Xilinx XC4010
    29249: 01/02/11: OT: IEEE & Floating point
    29642: 01/03/03: Metastability, Asynchronous Signals, & Asynchronous design
    29686: 01/03/05: Re: Parallel Port EPP
    30579: 01/04/18: Re: Clean Frequency Division
    30586: 01/04/18: FPGAs & Combinatorial Chew
    36023: 01/10/26: Foundation 3.1I+SP8 vs 4.1ISE
V Ram:
    27144: 00/11/13: Config device for Altera 10K10
    27217: 00/11/15: Schematics & VHDL
    27250: 00/11/16: Re: Schematics & VHDL
    27349: 00/11/19: Synthesizable VHDL
    27765: 00/12/07: FPGA Express & VHDL files
V. Pohnetal:
    11838: 98/09/12: In System Programming
V. V.:
    32319: 01/06/22: PCB/CAD/CAM/GIS Backup Software Store/ Athens, Greece
<v_mirgorodsky@yahoo.com>:
    80237: 05/03/02: Yet another SDRAM design :)
    80277: 05/03/03: HELP!!! Interfacing Virtex-4 FPGA with SDR SDRAM
    80720: 05/03/10: RocketIO and Gigabit Ethernet
    81727: 05/03/30: Achieving required speed in Virtex-II Pro FPGA
    81750: 05/03/30: Re: Achieving required speed in Virtex-II Pro FPGA
    81752: 05/03/30: Re: Achieving required speed in Virtex-II Pro FPGA
    81758: 05/03/31: Re: Achieving required speed in Virtex-II Pro FPGA
    81828: 05/04/01: Re: Achieving required speed in Virtex-II Pro FPGA
    81832: 05/04/01: Re: Achieving required speed in Virtex-II Pro FPGA
    81834: 05/04/01: Re: Achieving required speed in Virtex-II Pro FPGA
    81835: 05/04/01: Re: Achieving required speed in Virtex-II Pro FPGA
    82507: 05/04/13: Embedded MicroBlaze solution
    88262: 05/08/13: Peter Alfke's SPDT Switch Debouncer
    88264: 05/08/13: Re: Peter Alfke's SPDT Switch Debouncer
    88270: 05/08/13: Re: Peter Alfke's SPDT Switch Debouncer
    91013: 05/10/27: ASIC HDL coding styles
    91063: 05/10/28: Re: ASIC HDL coding styles
    92156: 05/11/23: FPGA and metastability once again
    92225: 05/11/24: Re: FPGA and metastability once again
    96523: 06/02/05: Re: Protected power calculation spread sheets
    97033: 06/02/15: Re: What is back_annotate?
    97268: 06/02/20: Re: opencores.org ?
    98986: 06/03/18: Altera Cyclone II DQ/DQS pins location
    99003: 06/03/18: Re: Altera Cyclone II DQ/DQS pins location
    99491: 06/03/25: Spartan-3E 500 and PCI 33/66 design
    99494: 06/03/25: Re: Spartan-3E 500 and PCI 33/66 design
    100357: 06/04/07: Re: Virtex-4 Gigabit Ethernet design
vadim:
    69721: 04/05/18: NIOS Board Stratix Edition - FPGA won't configure
    69896: 04/05/23: Re: NIOS Board Stratix Edition - FPGA won't configure
    70056: 04/05/31: Serial I/O Standards
    70234: 04/06/09: LPM Megafunction : LPM_SHIFTREG timing
    70461: 04/06/17: Quartus II - Disabling the Optimizer to use gate delay
    71501: 04/07/20: Altera DEMUX Megafunction - does it exist ?
    71831: 04/08/01: Fast Memories
    72748: 04/08/31: Altera LVDS Transceiver Megafunction - ALTLVDS - question
    75034: 04/10/25: Programmable I/O Card for the PC - does it exist ?
    75190: 04/10/28: Re: Programmable I/O Card for the PC - does it exist ?
    75212: 04/10/29: Altera Quartus 4.0 - inconsistent simulation results
    75932: 04/11/19: Custom Megafunctions in Quartus II
    77158: 04/12/26: Anomalous Behaviour of Quartus 4.0 simulation
    77398: 05/01/05: San Jose job offer - need advice
    77465: 05/01/07: San Jose job offer - advice needed
    79551: 05/02/20: DSP56651/DSP56670 - Motorola RAM-based emulation devices
Vadim Borshchev:
    66714: 04/02/25: Re: difference btw H/W & S/W implementations !!
    81808: 05/04/01: Re: problem in driving I2C bus through memory-mapped register
Vadim Rusu:
    66633: 04/02/24: spying on signals in Quartus (newbie question)
Vadim Vaynerman:
    75299: 04/11/01: SysGnen 6.2: problem with DDS module
    75300: 04/11/01: Re: "frying" FPGAs
    75304: 04/11/01: Re: SysGnen 6.2: problem with DDS module
    75356: 04/11/03: Re: FPGA/CPLD Basics
    76500: 04/12/04: Using Spartan XL w/ modern ISE
    76502: 04/12/04: Re: PLCC84
    77913: 05/01/20: X-checker Pod : Problem w/ X-checker and Win2000
    77968: 05/01/21: Re: X-checker Pod : Problem w/ X-checker and Win2000
Vagant:
    125288: 07/10/19: LEDs, buttons and LCD
    125294: 07/10/19: Re: LEDs, buttons and LCD
    125325: 07/10/21: ISE or EDK?
    125370: 07/10/24: Addresses of subsystems
    125376: 07/10/24: Re: Addresses of subsystems
    125379: 07/10/24: Re: Addresses of subsystems
    125382: 07/10/24: Re: LEDs, buttons and LCD
    125385: 07/10/24: Re: Addresses of subsystems
    125386: 07/10/24: Re: Addresses of subsystems
    125424: 07/10/25: Re: LEDs, buttons and LCD
    125426: 07/10/25: Re: LEDs, buttons and LCD
    125470: 07/10/25: Re: fgpa beginner
    127708: 08/01/06: How to connect a LED with a clock?
    127710: 08/01/06: Re: How to connect a LED with a clock?
    127712: 08/01/06: Re: How to connect a LED with a clock?
    127721: 08/01/06: Re: How to connect a LED with a clock?
    127722: 08/01/06: Re: How to connect a LED with a clock?
    127726: 08/01/06: Re: How to connect a LED with a clock?
    127807: 08/01/08: Please, help - I have got confused about package type
    127810: 08/01/08: Re: Please, help - I have got confused about package type
    127816: 08/01/08: Warning 'clock has been changed'
    127828: 08/01/08: Re: Warning 'clock has been changed'
    127872: 08/01/09: How to program FPGA permanently?
    127875: 08/01/09: Re: How to program FPGA permanently?
    128587: 08/01/31: FPGA in Telecommunications
    128594: 08/01/31: Re: FPGA in Telecommunications
    128982: 08/02/12: Does PC-FPGA communication requires a driver?
    128990: 08/02/12: Re: Does PC-FPGA communication requires a driver?
    129594: 08/02/28: Software for FPGA-based PC scope
    132055: 08/05/11: How to input an analog signal to FPGA board for processing?
    132061: 08/05/12: Re: How to input an analog signal to FPGA board for processing?
    132070: 08/05/12: Re: How to input an analog signal to FPGA board for processing?
    132120: 08/05/14: Re: How to input an analog signal to FPGA board for processing?
    134052: 08/07/23: Any good forum devoted to digital systems design?
Vaggelis:
    87206: 05/07/19: Power PC Stall ??
Vaggelis Tripolitakis:
    42152: 02/04/17: problem installing xilinx foundation 3.1 on a P4
    42176: 02/04/18: Re: problem installing xilinx foundation 3.1 on a P4
vaibhav:
    137003: 08/12/18: Memory Allocation for ISE tools in Linux
Vakaras:
    60981: 03/09/25: How to change "X" to "0" or "1" (VHDL) ?
    61020: 03/09/26: Re: How to change "X" to "0" or "1" (VHDL) ?
    61078: 03/09/27: Re: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
    61079: 03/09/27: Re: Strange synthesis behavior from Quartus II 2.2
    61269: 03/10/01: Any chance to buy Cyclone?
    61305: 03/10/01: Re: Any chance to buy Cyclone?
Valdez:
    154705: 12/12/20: Xilinx FIFO usage
    154707: 12/12/21: Re: Xilinx FIFO usage
    154710: 12/12/21: Re: Xilinx FIFO usage
Valentin Serb:
    10482: 98/05/21: PLA, BLIF, JED files
    13758: 98/12/22: Re: Atmel's PLD
    13769: 98/12/23: Re: Atmel's PLD
    14892: 99/02/23: test, ignore please
Valentin Tihomirov:
    47466: 02/09/26: My CPLD (XC9536) is overheated
    47509: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
    47517: 02/09/27: JTag question
    47520: 02/09/27: Re: JTag question
    47546: 02/09/28: Re: My CPLD (XC9536) is overheated
    58575: 03/07/27: Any libraries (c++, java, etc) for netlist manipulations?
    59890: 03/08/31: A WEB site digesting FPGA boards and PC connectivity solutions?
    60452: 03/09/13: Reconfiguration standards
    60453: 03/09/13: WebPack - mixed design flow
    61354: 03/10/02: Re: Good VHDL/Verilog editor?
    61414: 03/10/03: Re: Good VHDL/Verilog editor?
    62100: 03/10/19: CPU vs. FPGA vs. RAM
    62263: 03/10/23: Are clock and divided clock synchronous?
    62294: 03/10/24: Thank to you and Google
    62471: 03/10/30: simulation stops preliminarily
    62511: 03/10/31: Re: Minimalist RS232 on Cyclone
    62556: 03/11/01: Re: Convert verilog to VHDL??
    62909: 03/11/11: fitting Xilinx CPLD - I/O Pin Termination
    62919: 03/11/11: Re: Transforming vector position to binary value
    63242: 03/11/18: Re: Active-HDL 6.1 pricing
    63247: 03/11/18: CPLD : Generating reset signal
    63248: 03/11/18: NB! I do not use *Keeper* feature for I/O pin termination.
    63249: 03/11/18: Mysterious observations. Puzzle 2.
    63260: 03/11/19: Thank you all for the replays.
    63285: 03/11/19: How do you keep layout info in VHDL?
valentin tihomirov:
    47868: 02/10/06: LPT voltage level and Xilinx CPLD programming?
    47872: 02/10/06: Re: LPT voltage level and Xilinx CPLD programming?
    47889: 02/10/07: Oscillator for CPLD (xc9536)?
    47904: 02/10/07: Re: LPT voltage level and Xilinx CPLD programming?
    48005: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
    48542: 02/10/20: Re: Read xilinx cpld usercode.
    48544: 02/10/20: distributed decoder
    49734: 02/11/20: good schmatic entry?
    50285: 02/12/07: and vs. nand
    50294: 02/12/08: Re: and vs. nand
    50916: 02/12/23: How to generate a clock signal for CPLD?
    50938: 02/12/23: Re: How to generate a clock signal for CPLD?
    51192: 03/01/06: asynchronous inputs
    51247: 03/01/08: Re: asynchronous inputs
    54553: 03/04/14: request for simple UART
    55939: 03/05/24: Can I implement frequency multiplier using FPGA/CPLD?
    62329: 03/10/27: Re: Are clock and divided clock synchronous?
    63527: 03/11/25: Slightly unmatched UART frequencies
    63532: 03/11/25: Re: Slightly unmatched UART frequencies
    63653: 03/11/27: Any integesting article about PLD for short presentation
    63672: 03/11/28: Re: Any integesting article about PLD for short presentation
    63692: 03/11/30: Re: Slightly unmatched UART frequencies
    63694: 03/11/30: Re: problem with RS485 or RS232
    64369: 03/12/31: A dilemma: which signal to use as a master?
    64371: 03/12/31: boolean to std_logic
    64373: 03/12/31: Re: A dilemma: which signal to use as a master?
    64378: 03/12/31: Re: A dilemma: which signal to use as a master?
    64397: 04/01/01: Getting up-to-date libraries for timing simulation
    64433: 04/01/04: Re: rs-232 trouble
    64453: 04/01/05: Re: rs-232 trouble
    64471: 04/01/05: Re: Getting up-to-date libraries for timing simulation
    64516: 04/01/06: Re: How do you initialize signals in VHDL?
    64517: 04/01/06: Re: Installation of Xlinx
    64654: 04/01/10: Re: FPGA Size
    64659: 04/01/10: Dedicated CLK lines in CPLD
    64672: 04/01/11: Re: Dedicated CLK lines in CPLD
    65083: 04/01/20: Re: Good/Affordable Stater kits
    65596: 04/02/03: Design Flow: PCI or any other high-speed PC interface ?
    65662: 04/02/04: Re: Design Flow: PCI or any other high-speed PC interface ?
    65675: 04/02/04: Re: Design Flow: PCI or any other high-speed PC interface ?
    65734: 04/02/05: Re: Design Flow: PCI or any other high-speed PC interface ?
    66264: 04/02/16: using fpga for sampling audio
    66319: 04/02/17: Re: using fpga for sampling audio
    66321: 04/02/17: Re: using fpga for sampling audio
    66358: 04/02/18: Re: using fpga for sampling audio
    66551: 04/02/22: Re: Comparator and minimum value address
    66555: 04/02/22: Re: Comparator and minimum value address
    66621: 04/02/24: ngd2edif vs. ngc2edif
    66703: 04/02/25: Modular Design in WebPack
    66875: 04/02/28: Re: using fpga for sampling audio
    66883: 04/02/28: netlist - technology remapping
    67156: 04/03/07: Bus interface - read, write signals
    67161: 04/03/07: Implementing a reliable counter inside SDRAM memory mapped device
    67187: 04/03/08: Re: Bus interface - read, write signals
    67756: 04/03/18: duration of reset
    67785: 04/03/19: Re: duration of reset
    67833: 04/03/20: Re: duration of reset
    67835: 04/03/20: Re: std_logic register resets immediately
    67852: 04/03/21: Re: duration of reset
    67856: 04/03/21: Re: std_logic register resets immediately
    68435: 04/04/05: Re: Xilinx XC9500 CPLD Wired-OR; Wired-ND
    68568: 04/04/08: Re: Xilinx XC9500 CPLD Wired-OR; Wired-ND
    68685: 04/04/14: what is a better approach to synthezise synchronous reset on FPGA?
    69462: 04/05/11: Re: FPGA wanted
    70987: 04/07/05: Re: Compact FPGA Board?
    72983: 04/09/09: Two questions about FFs
    72984: 04/09/09: Re: Two questions about FFs
    74067: 04/10/03: XST - undeterministic synthesis
    74179: 04/10/06: Re: Hash algorithm for hardware?
    76701: 04/12/09: Re: FPGA as host for a USB peripheral
    80573: 05/03/08: Re: Hierarchical Synchronous Design
    80658: 05/03/09: Re: Differences among the FPGA development tools.
    80841: 05/03/12: Re: Hierarchical Synchronous Design (corrected)
    85922: 05/06/18: circuit optimization - a feedbackless machine
    85963: 05/06/19: Re: circuit optimization - a feedbackless machine
    86398: 05/06/27: Maintaining a Pipeline
    86508: 05/06/29: Re: Maintaining a Pipeline
    86715: 05/07/05: Re: Maintaining a Pipeline
Valentino:
    63964: 03/12/10: numeric_std and signed "/" operator
    64543: 04/01/07: Re: V2Pro floating point
valeri:
    28255: 01/01/04: FPGA starter kit recommendations
Valeri Serebrianski:
    23904: 00/07/14: Re: Need help with Maxplus and large bus multiplexer
    23906: 00/07/14: Re: Need help with Maxplus and large bus multiplexer
    23907: 00/07/14: Re: Need help with Maxplus and large bus multiplexer
    25080: 00/08/26: Re: Problems Fitting Design When Inserting More Than One Internal Global Buffer...
    31245: 01/05/16: RE: Counter problem in Altera AHDL...
    39500: 02/02/11: Re: Multiple clock domein synchronization.
    51399: 03/01/12: Re: Virtex-II Pro misfire?
    52357: 03/02/07: Virtex-II Pro PowerPC cache memory as main program/data storage?
    52438: 03/02/09: Re: Virtex-II Pro PowerPC cache memory as main program/data storage?
    52552: 03/02/13: Re: Virtex-II Pro PowerPC cache memory as main program/data storage?
    63268: 03/11/19: Re: Active-HDL 6.1 pricing
    66221: 04/02/14: Re: Spartan-3 shipping, or perhaps not!
    70243: 04/06/10: Is Virtex-4 LX succesor for Spatan-3?
Valeria Dal Monte:
    54511: 03/04/12: fastest PLD
    54567: 03/04/14: Re: request for simple UART
    57710: 03/07/04: Re: Quartus II 3.0 Release & Web Edition Download Links
    58233: 03/07/17: state machine generator
    58951: 03/08/05: Re: Multiple device configuration using local update over ethernet
    59246: 03/08/13: Re: Limitations of Quartus II V3.0 Web
    59257: 03/08/13: Re: Datasheet for National PAL20L10
    59273: 03/08/13: Re: Datasheet for National PAL20L10
    59602: 03/08/23: Re: Altera ACEX 1K IOE
    60746: 03/09/21: Italy is out of FPGA world?
Valerio Gionco:
    55619: 03/05/14: Re: XC9536 - how to make my own programing device for this chip ?
    55664: 03/05/15: Re: XC9536 - how to make my own programing device for this chip ?
Valerios:
    98942: 06/03/17: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    99031: 06/03/19: Does support Partial Reconfiguration FPGA other companies except for Xilinx?
    99052: 06/03/19: Re: Does support Partial Reconfiguration FPGA other companies except for Xilinx?
    99152: 06/03/20: Re: slice macro replace the bus macro in the virtex-4 how to do that?????
    99273: 06/03/22: Re: Does support Partial Reconfiguration FPGA other companies except for Xilinx?
    100135: 06/04/04: Re: slice macro replace the bus macro in the virtex-4 how to do that?????
Valery:
    65150: 04/01/21: References to good PCI boards and some newbie questions - please help!
    65210: 04/01/22: Anybody has any experience with Tarari Content processor?
Valli:
    51069: 02/12/29: what is bus keeper / bus gate.
    51112: 03/01/02: Re: what is bus keeper / bus gate.
    52660: 03/02/18: Flop count..
    56223: 03/05/31: power consumption in CMOS..
    56768: 03/06/14: adders for xilinx virtex2..
    56798: 03/06/16: Implementaion of Mux-DFF with Virtex ..
    56835: 03/06/16: Re: Implementaion of Mux-DFF with Virtex ..
    60098: 03/09/04: Suitable FPGA architecture for Robots..
valtih1978:
    151674: 11/05/04: Logic Accessible Clock
    151703: 11/05/07: Why feedback clock in SDRAM controllers?
    151710: 11/05/09: EDK 10.1 design
    151711: 11/05/09: Re: Why feedback clock in SDRAM controllers?
    151728: 11/05/11: Re: Why feedback clock in SDRAM controllers?
    151886: 11/05/30: Re: Why feedback clock in SDRAM controllers?
    151887: 11/05/30: Re: Why feedback clock in SDRAM controllers?
    151949: 11/06/14: What is the advantage of source-syncronization (in SDRAMs)?
    151963: 11/06/15: Re: What is the advantage of source-syncronization (in SDRAMs)?
    151967: 11/06/15: Re: What is the advantage of source-syncronization (in SDRAMs)?
    151968: 11/06/15: Re: What is the advantage of source-syncronization (in SDRAMs)?
    151969: 11/06/15: Re: What is the advantage of source-syncronization (in SDRAMs)?
    152088: 11/07/04: How do they handle shorts during the dynamic reconfiguration?
    152093: 11/07/05: Re: How do they handle shorts during the dynamic reconfiguration?
    152280: 11/08/02: Re: VHDL horror in Xcell 76
    152283: 11/08/03: Re: VHDL horror in Xcell 76
    152294: 11/08/04: Re: image storing into BRAM
    152411: 11/08/20: Re: What is the advantage of source-syncronization (in SDRAMs)?
    152454: 11/08/25: Re: What is the advantage of source-syncronization (in SDRAMs)?
    152516: 11/08/30: Re: What is the advantage of source-syncronization (in SDRAMs)?
    152523: 11/09/01: Re: What is the advantage of source-syncronization (in SDRAMs)?
    152524: 11/09/01: Re: What is the advantage of source-syncronization (in SDRAMs)?
    152603: 11/09/17: Registers at I/O
    152609: 11/09/18: Re: Registers at I/O
    152689: 11/10/02: Re: How do they handle shorts during the dynamic reconfiguration?
    154883: 13/01/28: Re: Sometimes I Just Don't Get the Tools
    154891: 13/01/29: Re: Sometimes I Just Don't Get the Tools
<valwn@silvtrc.org>:
    137082: 08/12/22: Re: Need help with the I/O Standard
    137142: 08/12/28: Re: JTAG USB interface
    137199: 09/01/01: Re: Classifying different kinds of FPGA optimizations
van de Kerkhof:
    73748: 04/09/29: Re: virtex2.components.all
    73749: 04/09/29: luts are optimized away
    73759: 04/09/29: Re: luts are optimized away
    73637: 04/09/27: virtex2.components.all
    73678: 04/09/28: Re: virtex2.components.all
Van Hovey:
    887: 95/03/21: Designing FPGA's under Windows
vanan:
    15647: 99/04/06: FIFO
vandam:
    43194: 02/05/16: PCMCIA interface Logic Between PCMCIA LAN Card and ARM CPU....
Vandana:
    133775: 08/07/14: xilinx core generator
    133777: 08/07/14: Re: xilinx core generator
<vandanr007@gmail.com>:
    158638: 16/02/22: Re: lwIP RAW mode support for V4 temac
vanepp:
    146047: 10/03/04: Re: Ethernet development kit
    148709: 10/08/18: Re: Getting started with FPGA
    150577: 11/01/26: Re: strange problem with RTL
    157360: 14/11/27: Re: Low-end FPGA mezzanine standard
    157432: 14/12/05: Re: Which Altera to buy?
Vangelis:
    112328: 06/11/20: DDR_VDHL_models
    112331: 06/11/20: DDR_SDRAM_VHDL_models
    112924: 06/12/01: PowerPC_bus
    112932: 06/12/01: Re: Opencores DDR SDRAM controller
    113558: 06/12/16: PowerPC_EDK to ISE
    113583: 06/12/17: Re: PowerPC_EDK to ISE
    113687: 06/12/19: Re: Operate on RAM through FPGA
    113690: 06/12/19: PowerPC_simulation
    114243: 07/01/08: Re: Build an FPGA programmer cable
    114416: 07/01/15: PowerPC_DDR_controller
    114418: 07/01/15: Re: How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim
    119124: 07/05/12: PowerPC_DDR
    119126: 07/05/12: PowerPC_GPIO
    123213: 07/08/20: GPIO_performance
    123221: 07/08/20: Re: GPIO_performance
Vanheesbeke Stefaan:
    71227: 04/07/12: NIOS 2 HAL, libraries, ...
    71830: 04/08/01: Re: Using gprof with Nios II
    72035: 04/08/06: Re: NIOS Gnu Tools and Dynamic Memory
    72514: 04/08/22: Re: Help, synthesis for Spartan XL; does FPGA Express licenses for ISE 3 or 4 expire?
    73790: 04/09/29: Re: Nios Addressing
    74757: 04/10/18: Re: NI*S II-verilog in Virtex FPGA
    75731: 04/11/13: Re: PWM using FPGA
    75767: 04/11/14: Re: Driving towards 2V4000 during Power up
    91529: 05/11/08: old xilinx components
    91598: 05/11/09: Re: old xilinx components
vankipuram:
    129400: 08/02/22: Re: DDR SDRAM demo for Spartan-3E starter kit?
Vanni FADONE:
    5111: 97/01/24: FPGA & division
vans:
    104012: 06/06/16: High speed differential to single ended
    104015: 06/06/16: Re: High speed differential to single ended
    104018: 06/06/16: Re: High speed differential to single ended
    104077: 06/06/18: Re: High speed differential to single ended
    104109: 06/06/19: Re: High speed differential to single ended
    104113: 06/06/19: Re: High speed differential to single ended
    104137: 06/06/19: Re: High speed differential to single ended
Varin Udompanyanan:
    3205: 96/04/24: Looking for SIS to XILINX path
    3376: 96/05/22: blif ---> lca HELP!
<varin.vahia@gmail.com>:
    80409: 05/03/04: Tristate problem
Varnavi:
    74427: 04/10/11: Student SATA project
    74534: 04/10/13: Re: Student SATA project
Varun:
    70682: 04/06/23: -mapstyle option in BATCH mode operation of XST
Varun Jindal:
    70687: 04/06/23: -mapstyle option in BATCH mode operation of XST
    72402: 04/08/17: Regarding BIST in FPGA
    72503: 04/08/21: Meaning of _PINMAP in XDL file
    73701: 04/09/28: XST Tool - Want a verilog simulation netlist
    73000: 04/09/09: Re: why systemc?
    76080: 04/11/23: Choice of FPGA device
    76109: 04/11/24: Re: Choice of FPGA device
    76292: 04/11/29: Re: XST question
    76293: 04/11/29: Re: XST question
    77685: 05/01/13: Re: Xilinx FPGA editor
    82464: 05/04/13: RLOC question
    82731: 05/04/17: Re: RLOC question
varun_agr:
    147664: 10/05/13: problem in clock input in virtexpro/spartan3a/spartan3 kit
    152281: 11/08/03: Regarding process time calculation
    152452: 11/08/24: Regarding virtex II pro xilinx XC2VP30 FF896
    152571: 11/09/15: CONSTRAINTS
    153172: 12/01/03: Regarding FFT & IFFT CORE IN XILINX
    153263: 12/01/20: What is value of scale_sch for FFT5.0 IP core for IFFT
Vasant:
    81914: 05/04/04: Need Help
Vasant Hansakul:
    1841: 95/09/08: Girl of the Moment
Vasant Ram:
    16443: 99/05/22: JTAG: Altera & Xilinx
    17938: 99/09/18: Re: simple VHDL?
    22047: 00/04/15: FPGA/PLD design tools?
    24328: 00/08/04: Re: PWM implementation suggested sought for Spartan FPGA
    28758: 01/01/23: Leonardo Spectrum or FPGA Express/Compiler II
Vasanth Asokan:
    64033: 03/12/12: Re: byte order microblaze
    77033: 04/12/20: Re: edk-chipscope 6.2 to 6.3 update
    78763: 05/02/07: Re: xilkernel and threads
    79658: 05/02/22: Re: XilKernel Problem on Spartan3 Board
    80604: 05/03/08: Re: malloc doesn't work when I use OCM (with Virtex II Pro and PPC405)
    81506: 05/03/25: Re: Xilkernel: configure to use 2 PPCs
    108598: 06/09/13: Re: Xilkernel pthread_mutex_lock() broken Was: Xilkernel: Problem with mutex
    108606: 06/09/13: Re: Xilkernel pthread_mutex_lock() broken Was: Xilkernel: Problem with mutex
    108742: 06/09/15: Re: microblaze lwip
    109075: 06/09/20: Re: APU disabled after context switch in Xilkernel
    109185: 06/09/21: Re: APU disabled after context switch in Xilkernel
    109264: 06/09/22: Re: uBlaze : Programming in C++... Is Possible ?
    109368: 06/09/25: Re: uBlaze : Programming in C++... Is Possible ?
    109657: 06/10/02: Re: Declaration of xilkernel_main()
    111332: 06/11/01: Re: XPS Flashwriter tool errors on last location in flash
    113445: 06/12/13: Re: MicroBlaze : -mcpu=4.00.b option for mb-gcc compiler...
    115553: 07/02/13: Re: Disabling Interrupts/Context switching in Xilkernel
    120605: 07/06/11: Re: How to put part of program data into local ram, the rest into external memroy?
    120901: 07/06/19: Re: EDK - Microblaze question
    124143: 07/09/12: Re: microblaze toolchain compilation question
    125640: 07/10/30: Re: debugging ppc + mb
    126520: 07/11/26: Re: Start-up Xilkernel on Microblaze
    134209: 08/07/30: Re: double precision floating point alignment issues with xilkernel
    134343: 08/08/06: Re: double precision floating point alignment issues with xilkernel
vasile:
    111072: 06/10/28: Stratix II basic questions
    111075: 06/10/28: Re: Stratix II basic questions
    111850: 06/11/11: replacement for Altera EPCS64
    112191: 06/11/17: PCMCIA interface
    112247: 06/11/18: Re: PCMCIA interface
    114079: 07/01/04: Re: Surface mount ic's
    114080: 07/01/04: Re: FPGA ROUTING
    114081: 07/01/04: Re: FPGA ROUTING
    117335: 07/03/28: suggestion for choosing the right FPGA for gigabit transciever
    120655: 07/06/13: Virtex 5 static and dynamic (re)configuration
    121113: 07/06/26: VGA 1080x1920 pixel chipset
    121543: 07/07/07: multiprocessor design-shared memory-howto
    121544: 07/07/07: Re: Choosing the EPC16 or the EPCS64 for Stratix II
    121582: 07/07/09: Re: Choosing the EPC16 or the EPCS64 for Stratix II
    122666: 07/08/02: Altera-Xilinx interfacing SERDES transcievers problem
    122710: 07/08/04: Re: Altera-Xilinx interfacing SERDES transcievers problem
    123420: 07/08/28: weird issue on Xilinx ML501/ML505 evkit designs
    123474: 07/08/28: Re: PCB Layers
    123544: 07/08/30: Re: PCIe question
    123545: 07/08/30: Re: PCIe question
    123773: 07/09/04: Re: Spartan3E and DDR termination
    123774: 07/09/04: Re: PCB Impedance Control
    123777: 07/09/04: Re: PCB Impedance Control
    123817: 07/09/05: Re: Spartan3E and DDR termination
    123920: 07/09/07: Rocket IO clock
    123939: 07/09/07: Re: VCCAUX too high on a Spartan 3 design
    124164: 07/09/13: Re: VCCAUX too high on a Spartan 3 design
    124258: 07/09/17: global clock on virtex5 question
    124293: 07/09/18: Re: global clock on virtex5 question
    124294: 07/09/18: Re: Altera / Lattice / Xilinx CPLDs ?
    124352: 07/09/19: Re: global clock on virtex5 question
    124385: 07/09/20: Re: Gated Clock Problems
    124467: 07/09/23: Re: Gated Clock Problems
    124626: 07/09/28: LVDS clock management
    124627: 07/09/28: Re: FPDP to PCIe
    124647: 07/09/29: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
    124690: 07/09/30: Re: XUPV2P from digilentinc
    125316: 07/10/20: Re: Fast Sampling of digital signals
    125768: 07/11/04: Re: fpga based designs
    127621: 08/01/04: Re: Split Plane
Vasilis Stergioulis:
    8350: 97/12/10: Re: Need a fast ADC
Vass Francesco:
    5093: 97/01/22: Verilog --> FPGA
Vassili:
    104646: 06/07/03: Properties of some pins of Vertex4
    105033: 06/07/12: Binary Counter Core
    105037: 06/07/12: Re: Binary Counter Core
    105133: 06/07/14: Re: Binary Counter Core
Vassili Savinov:
    104050: 06/06/17: Temperature sensing diode on Vertex 4
    104413: 06/06/27: Webpack ISE 8 and Vertex4 XC4VLX60
vasu:
    130214: 08/03/18: Re: Chipscope
    132333: 08/05/21: Re: timing constraint is impossible to meet
    135243: 08/09/23: Re: Xilinx Timing constraint problems
    136355: 08/11/12: Re: clock problem
    150925: 11/02/22: Re: timing issues at high speed
    152079: 11/07/01: Re: Virtex 5 Rocket IO design for reading in ADC data.
    152198: 11/07/19: Re: FPGA not getting programmed
    152202: 11/07/20: Re: FPGA not getting programmed
vasudev:
    79560: 05/02/21: EDK6.3i Memory conflict.....
Vasudeva Kamath:
    35863: 01/10/21: Re: how to dublicate logic?
<vasus_ss@yahoo.co.in>:
    78368: 05/01/30: changing directory location
    78447: 05/02/01: Evaluating EDIF netlist
<vaughan@wave.co.nz>:
    2720: 96/01/30: Sunshine EXPRO-80 adapter socket for MACH210
    6204: 97/04/25: Re: ISP CPLD from AMD or Cypress???
    6442: 97/05/24: Re: Cypress WARP question
    6633: 97/06/07: Re: Fine Pitch PQFP : anyone any hassles?
Vaughn:
    144206: 09/11/19: Re: Altera Stratix IV GX Dev.Kit: PCI-E x4 device doesn't work in x8
    146618: 10/03/23: Re: Memory Blocks in Arria II GX Devices - mixed port read during
    150058: 10/12/08: Re: Multiple clock domains
Vaughn Adams:
    31253: 01/05/16: Re: XilinxCoreLib with Renoir
Vaughn Betz:
    14819: 99/02/18: Packing, Placement and Routing Tools for Academic FPGA Research
    21690: 00/03/29: New Place and Route Software for Non-Commercial Research (Academic VPR
    21865: 00/04/04: Re: New Place and Route Software for Non-Commercial Research (Academic
    21866: 00/04/04: Re: New Place and Route Software for Non-Commercial Research (Academic
    21870: 00/04/04: Re: MaxPlus9.5 License and Fitter problems
    21883: 00/04/05: Re: MaxPlus9.5 License and Fitter problems
    52371: 03/02/07: Re: Group Multiple tables
    55008: 03/04/24: Re: NIOS 3.0 Fmax and other Issues
    55009: 03/04/24: Re: NIOS 3.0 Fmax and other Issues
    55283: 03/05/02: Re: SPI-4.2 dynamic alignment - how'd they do that?
    56138: 03/05/29: Re: Altera hold violation errors
    56140: 03/05/29: Re: Cyclone doesn't non-clock rom?
    56144: 03/05/29: Re: New version,Low Speed
    56231: 03/05/31: Re: New version,Low Speed
    57187: 03/06/25: Re: Quartus II - Acex1k - Routing resources
    57647: 03/07/03: Re: cyclone on pci?
    58208: 03/07/16: Re: Is a Virtex-II Pro family a hands-down winner for DSP ?
    59267: 03/08/13: Re: Quartus II and fixing hold timing
    59314: 03/08/14: Re: Quartus II and fixing hold timing
    60482: 03/09/14: Re: Altera's Quartus II "smart compilation" feature killed my design?
    60645: 03/09/18: Re: Altera's Quartus II "smart compilation" feature killed my design?
    60649: 03/09/18: Re: LVDS in cyclone
    60669: 03/09/18: Re: Using LUTs for array of coefficients
    61286: 03/10/01: Re: Regulator for Spartan 2
    61695: 03/10/08: Re: synplify vqm not able to fit in Quartus
    62193: 03/10/21: Re: Strange error in Quartus II 3.0
    62194: 03/10/21: Re: Several Quartus II 3.0 questions
    62195: 03/10/21: Re: Quartus 2.2, SOPC builder and leonardo
    63352: 03/11/19: Re: Acek 1K - Quartus II - timing issues
    63528: 03/11/24: Re: How many dedicated clock pins EP20K1500EBC652 device?
    63529: 03/11/24: Re: How to set 'set up time' in a Quartus Tool for a PCI Device
    63550: 03/11/25: Re: Acek 1K - Quartus II - timing issues
    63601: 03/11/26: Re: How many dedicated clock pins EP20K1500EBC652 device?
    63602: 03/11/26: Re: getting started in FPGA
    63633: 03/11/26: Re: How many dedicated clock pins EP20K1500EBC652 device?
    63635: 03/11/26: Re: Affordable Development Board
    63748: 03/12/02: Re: Design analyse methods
    64237: 03/12/21: Re: From FPGA to ASIC these days
    64238: 03/12/21: Re: FLEX 10K50E, which software support it?
    64239: 03/12/21: Re: Hold violations
    64539: 04/01/06: FPGA CAD researchers: documentation, APIs, file formats & tutorials for academics to interface to Quartus
    64791: 04/01/13: Re: Altera Cyclone data is incomplete or messy
    64792: 04/01/13: How to explicitly call out cell elements in Altera Stratix (Follow-up)
    64924: 04/01/16: Re: Altera Cyclone data is incomplete or messy
    65130: 04/01/20: Re: Non deterministic routing in Quartus 3.0 ?
    65131: 04/01/20: Re: QUIP ( advance)
    65132: 04/01/20: Re: Good/Affordable Stater kits
    65558: 04/02/02: Re: Showing design in vpr
    67561: 04/03/14: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
    67562: 04/03/14: Re: APEX fit problem
    67563: 04/03/14: Re: Using ALTPLL
    67671: 04/03/16: Re: Applying Timing Constraints in the face of Synthesis consolidation : Quartus
    67936: 04/03/22: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
    68753: 04/04/16: Re: Writing PCI constraints in Altera
    68919: 04/04/21: Re: Writing PCI constraints in Altera
    68920: 04/04/21: Re: FPGA within demonstration
    68921: 04/04/21: Re: PLL and DLL
    69132: 04/04/27: Re: Design PAR in Stratix
    69133: 04/04/27: Re: Writing PCI constraints in Altera
    69231: 04/04/30: Re: Slack gets worst as I relax timing
    69385: 04/05/09: Re: Which board to buy? Status of open source tools?
    70114: 04/06/03: Re: tri-state in altera
    70858: 04/06/30: Re: File format *.eqn in Altera IDE
    70868: 04/06/30: Re: a question in the pci interface design
    70872: 04/06/30: Re: Programming Nios Ethernet Development Kit
    71246: 04/07/12: Re: PCI Timings
    71248: 04/07/12: Re: Compensated clock in Stratix
    71484: 04/07/19: Re: PLL phase after compensation
    71486: 04/07/19: Re: Problem with LogicLock and register packing
    72060: 04/08/06: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
    72153: 04/08/09: Re: Altera Bidi ports, Tristate Buffers & Prop. Delay?
    72403: 04/08/17: Re: Quartus warning
    72736: 04/08/30: Re: Delay Modelling in TVPACK
    73054: 04/09/12: Re: Altera Quartus FSM Simulation Delay?
    73111: 04/09/14: Re: Altera Quartus FSM Simulation Delay?
    76795: 04/12/12: Re: Inconsistant compilations with quartus
    76836: 04/12/14: Re: Cylone Problem with Large Shift Register
    76870: 04/12/14: Re: altera cyclone and fifo synchronisation
    76871: 04/12/15: Re: Cylone Problem with Large Shift Register
    77014: 04/12/20: Re: altera cyclone and fifo synchronisation
    77089: 04/12/22: Re: Using low-core-voltage devices in industrial applications
    77107: 04/12/23: Re: Using low-core-voltage devices in industrial applications
    77400: 05/01/06: Re: Quartus and Cyclone programming problem
    77401: 05/01/06: Re: Altera Flex10K Fast Output Register warning
    77402: 05/01/06: Re: Using low-core-voltage devices in industrial applications
    77564: 05/01/11: Re: Altera Flex10K Fast Output Register warning
    77565: 05/01/11: Re: Register names in Quartus Signal Tap Node finder
    77686: 05/01/13: Re: altera stratix problem
    77717: 05/01/15: Re: Vht to Vwf
    77867: 05/01/19: Re: Forward-Annotating constraints to Quartus
    79164: 05/02/15: Re: Updated Stratix II Power Specs & Explanation
    79248: 05/02/15: Re: Virtual Pins in QuartusII
    79251: 05/02/15: Re: Updated Stratix II Power Specs & Explanation
    79319: 05/02/17: Re: Questions about multiple rom instances in Quartus II
    79322: 05/02/17: Re: Updated Stratix II Power Specs & Explanation
    79378: 05/02/18: Re: Updated Stratix II Power Specs & Explanation
    79379: 05/02/18: Re: Updated Stratix II Power Specs & Explanation
    81339: 05/03/22: Power Net Seminar Announcement
    81340: 05/03/22: Re: Stratix II vs Virtex 4
    81684: 05/03/29: Re: Altera's power consumption net seminar
    84288: 05/05/17: Re: Quartus II Fitter Problem
    84289: 05/05/17: Re: Auto-select clock for virtual pins
    84290: 05/05/17: Re: Quartus II Fitter Problem
    84365: 05/05/17: Re: Auto-select clock for virtual pins
    84367: 05/05/17: Re: "Mine is bigger than yours..."
    84368: 05/05/17: Re: About back annotated simulations...
    84426: 05/05/18: Re: About back annotated simulations...
    84427: 05/05/19: Re: Quartus II 4.1 Problem
    84507: 05/05/19: Re: Auto-select clock for virtual pins
    84560: 05/05/21: Re: Auto-select clock for virtual pins
    84834: 05/05/30: Re: Synplify 8.1 vs. Quartus II 5.0 QoR
    84835: 05/05/30: Re: Incremental Compilation in Quartus 4.2
    85230: 05/06/06: Re: not clear about doing power estimation using xpower
    85342: 05/06/08: Re: not clear about doing power estimation using xpower
    86675: 05/07/03: Re: Cant' make SignalTap works...
    87018: 05/07/12: Re: QII simulation annoyance
    87019: 05/07/12: Re: Clock recovery in FPGA at 300 MHZ
    87020: 05/07/13: Re: Quartus Timing Issues
    87148: 05/07/17: Re: Max Sample Rate for Signal Tap in Altera Quartus?
    87149: 05/07/17: Re: VPR fundaes
    87150: 05/07/17: Re: Testbenching and verification
    87151: 05/07/17: Re: Altera QII WE Tutorials
    87152: 05/07/18: Re: QII simulation annoyance
    87235: 05/07/19: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87353: 05/07/21: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87355: 05/07/21: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87358: 05/07/22: Re: Modulo division in Verilog
    87670: 05/07/27: Re: verilog to blif(lut)
    87672: 05/07/27: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
    87673: 05/07/27: Re: Update contacts at Altera
    88894: 05/08/30: Re: ADC Clock on Stratix II DSP Dev Board
    88896: 05/08/30: Version 5.0 of Quartus University Interface Program (for researchers & graduate students) Released
    89476: 05/09/15: Re: Migration Altera APEX20KE to ???
    89705: 05/09/22: Re: Output register instantiation in Quartus
    92132: 05/11/22: Re: Quartus Problem
    92134: 05/11/22: Re: CLK input DOES NOT use clk pin ( Altera Stratix II)
    92135: 05/11/22: Re: Help Needed Regarding VPR
    92218: 05/11/24: Re: CLK input DOES NOT use clk pin ( Altera Stratix II)
    92675: 05/12/04: Re: Black Box Attribute in Quartus II
    92676: 05/12/04: Power Optimization NetSeminar: Wedesday, Dec. 7 at 11 am PST
    92745: 05/12/06: Re: Power Optimization NetSeminar: Wedesday, Dec. 7 at 11 am PST
    93895: 06/01/03: Re: optimization tips (badly) needed
    93900: 06/01/03: Re: Power Optimization: can the routing and placement really save power?
    93902: 06/01/03: Re: Power Optimization: can the routing and placement really save power?
<vaughnbetz@gmail.com>:
    124825: 07/10/05: Re: Altera PowerPlay Early Power Estimator Spreadsheet and MXCOMCT2.OCX
    128445: 08/01/25: Re: Speed of remote JTAG with Quartus jtagd on linux
    135234: 08/09/22: Re: Altera and DDR3
    135758: 08/10/14: Re: Altera and DDR3
    135832: 08/10/16: Re: Update Altera MAXII UFM post production
vax, 9000:
    75008: 04/10/24: Re: SCSI
    75219: 04/10/29: explicitly define latch to avoid WARNING in xilinx webpack?
    74641: 04/10/15: which xilinx CPLD to select?
    74707: 04/10/16: Re: which xilinx CPLD to select?
    75369: 04/11/03: XILINX Webpack VHDL synthesis question (unnecessary MUX infered)
    75401: 04/11/04: Re: XILINX Webpack VHDL synthesis question (unnecessary MUX infered)
    75449: 04/11/05: Re: Clock loading in XC9572 CPLD
    75450: 04/11/06: Re: Clock loading in XC9572 CPLD
    75566: 04/11/09: xilinx webpack simulation problem (latch in place of logic)
    75567: 04/11/09: Re: xilinx webpack simulation problem (latch in place of logic)
    75569: 04/11/09: Re: xilinx webpack simulation problem (latch in place of logic)
    75608: 04/11/10: Xilinx Webpack, simulate with off-chip-connected-pins? (VHDL)
    75611: 04/11/10: Re: Xilinx Webpack, simulate with off-chip-connected-pins? (VHDL)
    75633: 04/11/11: Re: VHDL is correct but when burn into chip is not correct. Help me to solve this problem please
    75744: 04/11/13: Re: Obsolete processors resurected in FPGAs
    75755: 04/11/14: Re: Obsolete processors resurected in FPGAs
    76135: 04/11/25: Re: 386 IP Core
    76164: 04/11/27: Re: how to evaluate the needed number of gate?
    76315: 04/11/30: Re: State Machine Woes
    76399: 04/12/01: Re: clocks switch
    76471: 04/12/03: Re: how to start with development of eda tools
    76541: 04/12/06: Re: Connecting a spartan2 FPGA to an ISA bus
    77064: 04/12/21: low cost Altera MAX II development kit with more I/O pins?
    77075: 04/12/21: Re: low cost Altera MAX II development kit with more I/O pins?
    77085: 04/12/21: Re: low cost Altera MAX II development kit with more I/O pins?
    77086: 04/12/21: Re: low cost Altera MAX II development kit with more I/O pins?
    77170: 04/12/28: Re: [Xilinx ISE6.3 SP3] WebUpdate dies at 84% ...
    77171: 04/12/28: Re: [Xilinx ISE6.3 SP3] WebUpdate dies at 84% ...
    77929: 05/01/20: Re: Simulation error with ModelSim
    77958: 05/01/20: lasy question about VHDL: logic between a bit and a vector
    78011: 05/01/22: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
    78351: 05/01/30: Re: Trouble with Post-Place Simulation
    78363: 05/01/30: could I drive Altera MAX II CPLD with LSTTL outputs?
    78436: 05/02/01: Re: could I drive Altera MAX II CPLD with LSTTL outputs?
    78440: 05/02/01: Re: could I drive Altera MAX II CPLD with LSTTL outputs?
    79367: 05/02/17: Re: 3.3V device programmable with 5V?
    79422: 05/02/18: Re: 3.3V device programmable with 5V?
    79828: 05/02/24: Altera available from Digikey
    79833: 05/02/24: Re: pld macrocell usage
    80864: 05/03/13: Re: Free Stencil For SMD Soldering
    81028: 05/03/16: Xilinx webpack map/route questions
    81050: 05/03/16: Re: Xilinx webpack map/route questions
    81054: 05/03/16: Altera free web FPGA software license question
    81125: 05/03/17: Re: Altera free web FPGA software license question
    81126: 05/03/17: Re: Xilinx webpack map/route questions
    81128: 05/03/17: Re: Beginning Xilinx FPGA Tutorials?
    81196: 05/03/18: Re: Xilinx webpack map/route questions
    81197: 05/03/19: XC3S50 or EPM1270?
    81220: 05/03/19: Re: One-hot statemachine design problems
    81263: 05/03/20: Re: XC3S50 or EPM1270?
    81619: 05/03/29: Re: What type of IO to use
    82095: 05/04/06: Re: collapse
    82118: 05/04/06: Re: 80x86 verilog (not complete!) sources released
    82225: 05/04/08: rules to assign pins to FPGA?
    82448: 05/04/12: Re: rules to assign pins to FPGA?
    84771: 05/05/26: What's the difference between Altera EPM1270T144C5 and EPM1270T144C5N?
    85206: 05/06/06: Re: Sch & Layout Free Program
vax,3900:
    67858: 04/03/21: XC95288 easy to crack?
    67895: 04/03/22: zener power supply to XC95144XL?
    68054: 04/03/25: CPLD: assign pins first, or design content first?
    68063: 04/03/25: Re: CPLD: assign pins first, or design content first?
    68170: 04/03/28: Re: CPLD: assign pins first, or design content first? (page somebody)
    69403: 04/05/10: Monolithic state machine or structured state machine?
    69404: 04/05/10: How to simulator XILINX CPLD with off_chip wiring?
<VAX9000@gmail.com>:
    89066: 05/09/04: Quartus web edition simulation with off-chip logic?
    89779: 05/09/26: ALTERA quartus II 5.0sp1 web edition can't program MAXII: error code 84
    89837: 05/09/27: Re: ALTERA quartus II 5.0sp1 web edition can't program MAXII: error code 84
    138807: 09/03/11: Best way to write to LUT based CPLD from slow CPU?
    138809: 09/03/11: asynchronous preloading a counter
    138811: 09/03/11: Re: Best way to write to LUT based CPLD from slow CPU?
    139091: 09/03/20: FPGA users, Please take a few seconds to report SPAM
    139320: 09/03/26: Re: FPGA users, Please take a few seconds to report SPAM
<VAX>:
    14580: 99/02/05: Re: Timing Simulation and Foundation
    15215: 99/03/15: SDF
    15570: 99/03/31: Timing-driven compilation
Vazquez:
    61126: 03/09/29: Memory Handling in Altera Cyclone devices
    61267: 03/10/01: Re: Memory Handling in Altera Cyclone devices
    61497: 03/10/06: Re: Memory Handling in Altera Cyclone devices
    61639: 03/10/08: Implementing a fast cache in Altera Cyclone
    61715: 03/10/09: Why no synthesis?
    61761: 03/10/09: Re: Why no synthesis?
    62041: 03/10/17: Error Message when using process with wait-statement in testbench
    62123: 03/10/20: Re: Error Message when using process with wait-statement in testbench
    62468: 03/10/30: Hit Logic
    62507: 03/10/31: Address Mapping in 4K RAM Blocks in Altera Cyclone Devices
    62617: 03/11/03: Using the Virtex Block Select RAM+ Features
    62742: 03/11/06: Creating a vector out of other vectors
    62853: 03/11/10: How to create a look up table for a RAM application
    62857: 03/11/10: Enumeration by Host Controller
    62914: 03/11/11: Transforming vector position to binary value
    62928: 03/11/11: Re: Transforming vector position to binary value
    62987: 03/11/11: Re: Transforming vector position to binary value
    63004: 03/11/12: Local nodes are not visible anymore after simulation (Altera Quartus II )
    63159: 03/11/17: Altera synthesis of registered signals ???
    63368: 03/11/20: Quartus II Node Finder
    63704: 03/12/01: Functional Simulation QuartusII
VB:
    87770: 05/08/01: webcamera access with ML310
    89680: 05/09/22: Re: xilinx ML310 board PCI DMA problem
    89681: 05/09/22: USB communication using PCI Logicore
vb:
    45711: 02/08/01: inout constrain
vballu:
    121538: 07/07/06: sdr woes
<vbberx@nowhere.com>:
vbcity:
    112021: 06/11/14: Re: xupv2p
<vbetz@altera.com>:
    81443: 05/03/23: Re: Power Net Seminar Announcement
    82151: 05/04/07: Re: Hey Xilinx
    86486: 05/06/28: Re: Lattice LFEC
    86487: 05/06/28: Re: Good FPGA for an encryptor
    88895: 05/08/30: Re: verilog to blif(lut)
    117036: 07/03/21: Re: Xilinx ISE support for dual/quad core CPUs?
    117299: 07/03/27: Re: Altera memory init file (.hex/.mif) generation using gcc objcopy - how to change base address??
    117446: 07/03/30: Re: Quartus warning messages reagarding timming and latchs
    118473: 07/04/27: Re: Quartus Fitter Seed Setting
    118665: 07/05/01: Re: differential pins assignment in Synplify fro altera device
    118813: 07/05/03: Re: Need help: Altera ALTPLL_RECONFIG state machine construction
    119147: 07/05/13: Re: Altera FIR Compiler with clock enable
    119788: 07/05/25: Re: Dual Core or Quad Core when running Quartus 7.1
    119864: 07/05/28: Re: M-RAM allocation in Stratix EPS125B672C6
vbica:
    36957: 01/11/27: Xilinx JTAG programmer: how to generate SVF
<vboykov@gmail.com>:
    131558: 08/04/25: V5, EMAC simulation problem, when 4 EMACs are used together (ISE
VC:
    110690: 06/10/19: Re: Meeting Timing Constraint
    111000: 06/10/26: Re: Xilinx Virtex4 Outputs for Camera Link
    111422: 06/11/02: Re: Warning LIT:176, DCM in Virtex 4?
    112075: 06/11/15: Re: Xilinx 2 DCMs with delay on lock
    113442: 06/12/13: Re: more of ERROR:MapLib:661
vcar:
    140389: 09/05/12: Data buffering scheme problem for PCI-E interface
    140428: 09/05/13: Re: Data buffering scheme problem for PCI-E interface
    140503: 09/05/15: Re: Data buffering scheme problem for PCI-E interface
    140553: 09/05/16: Re: Data buffering scheme problem for PCI-E interface
    140962: 09/05/31: Micron SODIMM Type Variation
    141035: 09/06/02: Re: Micron SODIMM Type Variation
    141569: 09/06/28: STA Problem on Asynchronous FIFO
    141587: 09/06/28: Re: STA Problem on Asynchronous FIFO
    141600: 09/06/29: Re: STA Problem on Asynchronous FIFO
    141687: 09/07/03: DDR2 IPCore implementation problem based on MIG2.3
    141802: 09/07/09: Re: DDR2 IPCore implementation problem based on MIG2.3
    142887: 09/09/05: Virtex5 DDR2 ref design failed at JTAG programming with CRC error
    142892: 09/09/06: Re: Virtex5 DDR2 ref design failed at JTAG programming with CRC error
    142894: 09/09/06: Re: Virtex5 DDR2 ref design failed at JTAG programming with CRC error
    142904: 09/09/07: Re: Virtex5 DDR2 ref design failed at JTAG programming with CRC error
    142910: 09/09/07: Re: Virtex5 DDR2 ref design failed at JTAG programming with CRC error
    142932: 09/09/08: Re: Virtex5 DDR2 ref design failed at JTAG programming with CRC error
    143555: 09/10/15: XAPP859 functional simulation error with testbench task : memory_read
    143556: 09/10/15: The performance of endpoint block plus for PCIe regression when
    143557: 09/10/15: Re: The performance of endpoint block plus for PCIe regression when
    143564: 09/10/16: Re: The performance of endpoint block plus for PCIe regression when
    143647: 09/10/19: Re: XAPP859 functional simulation error with testbench task :
    143648: 09/10/19: Re: The performance of endpoint block plus for PCIe regression when
    143677: 09/10/20: Re: The performance of endpoint block plus for PCIe regression when
    144724: 09/12/28: How to protect my Virtex5 design without battery?
    144738: 09/12/29: Re: How to protect my Virtex5 design without battery?
    144740: 09/12/30: Re: How to protect my Virtex5 design without battery?
    144798: 10/01/04: Re: How to protect my Virtex5 design without battery?
    144799: 10/01/04: Re: How to protect my Virtex5 design without battery?
    152551: 11/09/13: FPGA acceleration v.s. GPU acceleration
VCC:
    6097: 97/04/11: H.O.T. Works Class Announcement
    6420: 97/05/22: Re: Configurable Computing
vcc:
    2949: 96/03/05: Re: Reconfigurable Computing Languages
    2950: 96/03/05: Re: Reconfigurable Computing Languages
    5082: 97/01/21: XC6200 Announcement by VCC
<vcccck@google.com>:
<vchen@uiuc.edu>:
    58643: 03/07/30: Simulation
    58648: 03/07/30: Re: Simulation
vdauthor:
    113900: 06/12/28: Visual IP Designer
    113901: 06/12/28: Visual IP Designer
VDT153:
    147033: 10/04/10: Declaring gated clocks
Vectorblox_rob:
    154637: 12/12/06: Looking for evaluators for NEW Vector Processor for FPGAs, offers
Ved:
    114277: 07/01/10: Is this Multi-Cycle Path ?
    125527: 07/10/27: Selecting I/O pins
    126402: 07/11/21: Measuring setup and hold time in Lab
vedant:
    72861: 04/09/06: Re: SOC and ASIC ?
<vedpsingh@gmail.com>:
    97003: 06/02/14: Re: Problem of Initial Value in VHDL code
    100078: 06/04/03: Inferring RAM with FOR loop
Vedran Maler RIP pa konst. Zagar:
    4190: 96/09/24: XilinX XC5200 address pointer based FIFO
veera:
    141062: 09/06/04: Re: SGMII to MII
veeresh:
    117230: 07/03/26: Post PAR simulation for RAM Block implementations
    117231: 07/03/26: Post PAR simulation for RAM Block implementations
    117727: 07/04/08: Re: Post PAR simulation for RAM Block implementations
    119206: 07/05/15: Re: Timing constraint question
    119412: 07/05/18: Re: Timing constraint question
    119413: 07/05/18: Re: Timing constraint question
Veikko Toukomies:
    1502: 95/07/04: Re: Understanding Lattice equations
Veli-Matti Karppinen:
    486: 94/12/02: Re: Altera VHDL Opt..Second Try!
    1368: 95/06/08: Re: Fitter Quality
    3832: 96/08/08: Re: Pin assignments synopsys->Maxplus2?
    4322: 96/10/15: Re: LPM standard support?
    6812: 97/06/30: Re: Verilog Simulation and Synthesis for FPGA Devices
    39944: 02/02/22: Re: Linux tools
    46135: 02/08/20: Re: Good documentation on CPLD
    47331: 02/09/24: Re: IC layout
<veligor@gmail.com>:
    94014: 06/01/04: Re: Clock generation. Dividing/multiplying with Xilinx DCM?
    94016: 06/01/04: Xilinx Spartan3E Starter Kit, a photo?
    95122: 06/01/20: Re: need for a group FAQ?
venex:
    56403: 03/06/04: Re: Convolutional Encoder IP: Problem on puncturing
Venex:
    56341: 03/06/03: Convolutional Encoder IP: Problem on puncturing
Venkat:
    100824: 06/04/18: Viterbi IP Core
    100838: 06/04/19: Re: Multiple Independent Circuits on a Single FPGA
    100839: 06/04/19: Re: driving high speed ADC using an FPGA
    105795: 06/07/31: Usage of DDR IOBs
    105817: 06/08/01: Re: Usage of DDR IOBs
    119952: 07/05/29: Inverse of a matrix
    121011: 07/06/22: Re: Inverse of a matrix
    128085: 08/01/14: FPGA Configuration using Multiple PROMs
    134272: 08/08/04: Cordic Core for Virtex 5
    136754: 08/12/03: Query on Xilinx Nomenclature
    136780: 08/12/04: Re: Query on Xilinx Nomenclature
    136781: 08/12/04: Equivalent ASIC Gate Estimate
    136825: 08/12/07: Re: Equivalent ASIC Gate Estimate
    136849: 08/12/08: FPGA-ASIC Migration
    141034: 09/06/02: BRAM/LUT Comparison
    141039: 09/06/02: Re: BRAM/LUT Comparison
    141128: 09/06/07: Virtex 5 LUT Outpus
    156143: 13/12/10: BUFG Issue on Virtex 5 FPGA
venkat:
    45250: 02/07/17: Commercial FPGA Architectures
    96589: 06/02/07: doubt
venkata krishnnan:
    59157: 03/08/10: FPGA advantage 5.3 & unisim package
Venkata N. Peri:
    1373: 95/06/08: Pricing Info anyone?
<venkatec@gmail.com>:
    97431: 06/02/22: doubt
    97572: 06/02/23: Re: configuring stratix GX Fpga
    102830: 06/05/21: gate level simulation
Venkatesh Akella:
    30995: 01/05/08: SYnopsys Library Compiler and LUT synthesis
Venu:
    39200: 02/02/04: Virtex-II and SDRAM Controller at 133MHz
    42999: 02/05/08: Issue with X_SUH (using 4.1 sp 3)
    113756: 06/12/20: nets not recognised
    113840: 06/12/24: OPB master implementation
    113921: 06/12/29: Re: OPB master implementation
    113953: 06/12/30: ERROR:NgdBuild:604
    114107: 07/01/04: Re: ERROR:NgdBuild:604
    114111: 07/01/04: Re: FPGA-CPU THROUG ETHERNET
    115586: 07/02/14: OPB BRAM not bein detected
    115920: 07/02/25: OPB BRAM not detected in EDK
    116485: 07/03/09: Addressing scheme in Block RAM
    116568: 07/03/12: Re: Addressing scheme in Block RAM
    118403: 07/04/25: How to drop a Ethernet Packet in Xilinx EMAC
    119299: 07/05/16: Mutiple MAC on OPB Bus
    119444: 07/05/19: Re: Mutiple MAC on OPB Bus
    119445: 07/05/19: external clock frequency doubles
    119482: 07/05/21: Re: external clock frequency doubles
<venus@sunnyboy.ws.ba.dlr.de>:
    3234: 96/04/30: FPGA for Space Application
    3235: 96/04/30: FPGA from RAD-PACK ?
Vera Chung:
    11472: 98/08/18: XC6200 macro & Synopsys VHDL entry
veri-logic:
    73306: 04/09/18: "don't cares" on ibuf output
Verictor:
    145666: 10/02/17: Derived clock violation in Virtex4
    145680: 10/02/18: Re: Derived clock violation in Virtex4
    145692: 10/02/18: Re: Derived clock violation in Virtex4
    145777: 10/02/23: Re: Derived clock violation in Virtex4
    150981: 11/02/25: Altera's counter part to Xilinx's ODDR
    153526: 12/03/24: Re: Synchronizing Virtex-6 RocketIOs on RX path
Verilog USER:
    47370: 02/09/24: JHDL Help
    53686: 03/03/20: Generic SoundCard Driver/API for FPGA Device
    64569: 04/01/08: Re: SDRAM Controller timing problem
<verilog_tutorial@hotmail.com>:
    14167: 99/01/16: Verilog PLI website
<veriqiang@gmail.com>:
    129166: 08/02/16: Over utilization of FPGA resources
<veritas@mindspring.com>:
    11700: 98/09/01: Rent-to-own band instruments online!
Verleye Frank:
    43080: 02/05/13: Re: [Xilinx] EEPROM recommendation
<vermon1055@my-deja.com>:
    16987: 99/06/22: Synopsys DC & FPGA Compiler
    17756: 99/08/31: Re: Feasibility of 200 MHz, 12K design on FPGA
Vern Dunbrack:
    22208: 00/05/01: Xilinx Applications Engineer
Vernon L. Stant:
    42694: 02/05/01: Xilinx MicroBlaze, Opinion?
    42848: 02/05/04: Re: Xilinx MicroBlaze, Opinion?
Vernon Schryver:
    135388: 08/09/30: Re: Sending UDP packets over Ethernet
    135401: 08/09/30: Re: Sending UDP packets over Ethernet
Veronica Matthews:
    75636: 04/11/11: digital analog conversion
    75682: 04/11/12: Re: digital analog conversion
    75684: 04/11/12: Re: digital analog conversion
Veronica Merryfield:
    33094: 01/07/17: Re: processor core
    33749: 01/08/03: Re: 4 (8) bit Microporcessor Implementation
vertago1:
    141332: 09/06/18: Re: Virtex 2 Pro IO Banks Vcco
<vertige69@hotmail.com>:
    16007: 99/04/28: Double Port ram for Altera EPF10K20
Veselic Mladen:
    20256: 00/02/02: Foundation
Vesh:
    138601: 09/03/01: Character generator ROM and VGA controller for Spartan 3E
    138646: 09/03/02: Re: Character generator ROM and VGA controller for Spartan 3E
    138707: 09/03/05: NGDBuild 604 Error while implementing the character generator design
    138947: 09/03/16: SPI controller for FPGA
<vesta7x@earthling.net>:
    11196: 98/07/24: ORCAD 3
<Veteran_NYC_Shopper@qudumi.org>:
    27764: 00/12/06: Attention NYC Shoppers & Visitors - Beware of Rip-off SY Stores!!! ...... slNZc2N54
vhdl:
    32636: 01/07/03: Jtag programmer, and the WinNT Parallel port
    32675: 01/07/04: How to estimate the number of CLBs ?
    32680: 01/07/04: RE: How to estimate the number of CLBs ?
VHDL Technology Group:
    4628: 96/11/22: Re: VHDL code editor for Windows NT.
Vhdl.eu:
    103929: 06/06/15: Re: FPGA board for USB experiments?
    103930: 06/06/15: Re: ARM cores in FPGA ?
VHDL_HELP:
    115889: 07/02/23: help for video compression
    116163: 07/03/02: help read a pixel for picture
    116177: 07/03/03: Multiplication operation
    116198: 07/03/04: Re: Multiplication operation
    116199: 07/03/04: Re: Multiplication operation
    116241: 07/03/05: Re: Multiplication operation
    116247: 07/03/05: Re: Multiplication operation
    116583: 07/03/13: sum of array
    116600: 07/03/13: Re: sum of array
    116601: 07/03/13: Re: sum of array
    116604: 07/03/13: Re: sum of array
    116605: 07/03/13: Re: sum of array
    116646: 07/03/14: Re: sum of array
    116733: 07/03/16: Re: sum of array
    116819: 07/03/19: Re: sum of array
VhdlCohen:
    7655: 97/10/01: Re: book
    29558: 01/02/26: Re: VHDL:case
    29786: 01/03/09: Snug presentation on verification in VHDL and Verilog
    30955: 01/05/04: Re: Serial UART
    32571: 01/06/30: Re: Converting character to integer in VHDL
    32642: 01/07/03: Re: 'Initial' opinions...
    32682: 01/07/04: Re: uart rs232? (for free)
    32741: 01/07/06: white paper: MINIMIZING DESIGN ERRORS.
    32973: 01/07/13: Re: Design entry
    33324: 01/07/23: Re: Synchronous output enable not supported?
    33331: 01/07/23: Re: Synchronous output enable not supported?
    34402: 01/08/23: Re: Testbench book
    37144: 01/12/01: New book: Real Chip DSGN and Verification, Verilog/VHDL
    37291: 01/12/06: Re: Multiple Drivers & illegal connection
    38620: 02/01/19: Re: initial value
    38621: 02/01/19: Re: verilog/vhdl codeing style
    40338: 02/03/05: From Verif. Guild: Challenging the need for HVLs
    40417: 02/03/06: Re: How to create testbench (Verilog) easily ? Any tools ?
    40517: 02/03/08: Re: suggestion to comp.arch.fpga
    40605: 02/03/11: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
    40632: 02/03/12: Re: a guide to digital design and synthesis
    40882: 02/03/17: Re: just bought
    40888: 02/03/17: That vs Which // Common confusion among engineer writers
    40889: 02/03/17: Lies, damn lies and Synplicity
    40894: 02/03/17: Re: Xilinx Webpack/ModelSim VHDL Question
    40896: 02/03/17: Re: just bought...
    41310: 02/03/25: Re: question on LFSR
    42219: 02/04/18: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
    42291: 02/04/19: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
    42769: 02/05/02: Re: Modelsim testbench problems
    44265: 02/06/15: Re: Dividing constants in Synplicity
    44832: 02/07/02: Re: VHDL Compliation Problem in Synario
    44934: 02/07/06: Re: Lessons Learned -- Need your inputs
    45948: 02/08/12: Re: ModelSim takes forever
vhdlcohen:
    73982: 04/10/01: Re: PSL pros and cons
<vhdldesigner.patrick@gmail.com>:
    118237: 07/04/20: Stratix II - Cyclone II GATE COUNT
vhdlguy@gmail.com:
    128327: 08/01/22: Re: Converting a ByteBlasterMV into a ByteBlaster II?
    128520: 08/01/29: Re: Altera ByteBlaster II schematic
    138424: 09/02/22: Re: byteblaster cloning
    138581: 09/02/28: Re: byteblaster cloning
vi:
    31187: 01/05/14: Quad Decoder
    31189: 01/05/14: Re: Quad Decoder
    31193: 01/05/14: Re: Quad Decoder
    31225: 01/05/15: Comparator
    31435: 01/05/23: frequency ramp
    31447: 01/05/24: Re: frequency ramp
    37353: 01/12/07: Orcad
vibha:
    152809: 11/10/25: FPGA functional flow..please help!
VIBHOR GARG:
    22747: 00/05/22: Programming Virtex FPGAs using VPR and JBits
Vic Lopez:
    15805: 99/04/14: What's the best way to learn about fpga's?
Vic Orloff:
    148076: 10/06/18: Difficulty with Xilinx FPGA configuration using Platform Flash PROM
    148080: 10/06/18: Re: Difficulty with Xilinx FPGA configuration using Platform Flash
    148082: 10/06/19: Re: Difficulty with Xilinx FPGA configuration using Platform Flash
Vic Vadi:
    73152: 04/09/14: Re: Virtex 4 released today
    73154: 04/09/14: Re: Virtex 4 released today
    73495: 04/09/22: Re: Virtex 4 released today
    74872: 04/10/20: Re: Virtex-4: DSP48 Fmax missing?
    74873: 04/10/20: Re: Active Rece\onfiguration of Xilinx FPGAs
    76820: 04/12/13: Re: What is the purpose of the 2 registers on A and B in the V4 Extreme
    76821: 04/12/13: Re: What is the purpose of the 2 registers on A and B in the V4 Extreme
    81791: 05/03/31: Re: Achieving required speed in Virtex-II Pro FPGA
    81924: 05/04/04: Re: DPSK Receiver in Vertex-4
    82845: 05/04/18: Re: xilinx embedded MAC
    84774: 05/05/26: Re: Virtex 4 configuration frames
    93312: 05/12/19: Re: Virtex-4 Startup
    97912: 06/03/01: Re: Virtex 4 Multiplier RPM Constraints?
    97923: 06/03/01: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    110332: 06/10/13: Re: Virtex 4 RAMB16 Clock: optional inverter missing
    110335: 06/10/13: Re: Virtex 4 SX, Dedicated Configuration pins
    110336: 06/10/13: Re: Virtex 4 Configuration Pins
    110338: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
    113238: 06/12/08: Re: About partial reconfiguration in Virtex 4
<vic@alpha.podol.khmelnitskiy.ua>:
    12565: 98/10/16: Where to find comp.arch.fpga newsgroup archive (please answer by e-mail vic@alpha.podol.khmelnitskiy.ua) (nothing inside)
vicash:
    156842: 14/07/08: Perl + Xilinx + commandline = Module::Build::Xilinx
    156843: 14/07/08: Re: Perl + Xilinx + commandline = Module::Build::Xilinx
    156849: 14/07/08: Re: Perl + Xilinx + commandline = Module::Build::Xilinx
    156851: 14/07/09: Re: Perl + Xilinx + commandline = Module::Build::Xilinx
    156945: 14/08/01: floating point synthesis on Xilinx FPGAs using ISE Webpack
<vice2012@hotmail.com>:
Vicente Baena:
    15922: 99/04/21: Re: High speed reconfigurability
Vicente Marti:
    21857: 00/04/04: XCS05XL de Xilinx
    24145: 00/07/27: RE: XCS05XL de Xilinx
    24146: 00/07/27: RE: XCS05XL de Xilinx
Vick:
    75454: 04/11/05: SRAM to be able to Read/Write SDRAM
    75498: 04/11/07: SRAM to be able to read/write Micron SDRAM
    75542: 04/11/08: Re: SRAM to be able to read/write Micron SDRAM
    75543: 04/11/08: Re: SRAM to be able to read/write Micron SDRAM
vick:
    61981: 03/10/15: vhdl code
    61997: 03/10/16: explain the vhdl code
Vicky:
    49692: 02/11/19: Small Program for Functinality Test of ApexII
vicky:
    55785: 03/05/19: downloading a VHDL design on a XSV board ?
Vicky Liping Zhang:
    9075: 98/02/18: Xilinx m1.3 & Cadence 97a
Victor:
    88531: 05/08/22: Re: some virtexII clock pads are useless??
Victor A. Holen:
    1591: 95/07/23: Re: letter from Olga! =)
Victor Atkinson:
    70961: 04/07/02: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
Victor Chen:
    54734: 03/04/17: How to configure USER1 and USER2 of JTAG on Xilinx Virtex2!!
Victor Hannak:
    44261: 02/06/15: Re: GCK input routing
    44262: 02/06/15: Re: Multiple constraints, same net?
    44263: 02/06/15: Dividing constants in Synplicity
    73425: 04/09/21: combinatorial loops / feedback paths discussion
Victor Levandovsky:
    8029: 97/11/09: Heed converter
    8072: 97/11/14: ? State Machine Design
    8280: 97/12/05: Q: MAX+ Plus II External connections
    8641: 98/01/15: Re: Byteblaster
    8993: 98/02/12: Walace tree???
    10531: 98/05/28: Re: Altera 10k pin function ??
    10653: 98/06/09: Re: Multipliers on FPGA's
    10670: 98/06/10: AHDL vs. VHDL vs. Verilog HDl
    10693: 98/06/11: Re: AHDL vs. VHDL vs. Verilog HDl
    10996: 98/07/09: Re: Altera MAX+PLUS 8.1 see in www.altera.com (nothing inside)
    12106: 98/09/29: Where can I get comp.arch.fpga newsarticle archive?
    17164: 99/07/06: Need informations (articles, on-line) about fast adders and multipliers
    18081: 99/09/28: TEST
    18082: 99/09/28: TEST
    18151: 99/10/04: Does anyone have a Altera BitBlaster shematic? (0)
    18314: 99/10/14: Need info about a FAST adders. How built it? (0)
    18379: 99/10/21: Which synthesis tools (Verybest, Viewlogic, Mentor, etc.) more popular? (0)
    18519: 99/10/28: Need shematic and documentation for in-system programming ALTERA devices with MCU (0)
    38226: 02/01/09: Where can I download Maxlock`s PCI core (It`s freecore, but I can`t download this from their WWW). Can anyone sent me this by email ?
    39808: 02/02/20: Need good PCI book
Victor P. Nelson:
    455: 94/11/22: Re: any XC4000 Horror Stories?
Victor Reyes:
    16651: 99/06/01: XILINX/ALTERA compatibility
Victor Schutte:
    27966: 00/12/18: Re: Verilog or VHDL
    30200: 01/03/28: Re: speech
    30266: 01/03/30: Re: FPGA V CPLD
    30296: 01/04/02: Re: FPGA V CPLD
    30321: 01/04/02: Re: FPGA V CPLD
    30459: 01/04/09: Re: xilinx price lists
    30516: 01/04/12: Re: Problems Software Build ALTERA Quartus II
    30636: 01/04/20: Re: Wanted: ISA bus implementation for Xilinx
    30638: 01/04/20: Re: Voltage supply reduction for low power in FPGAs.
    30875: 01/05/02: Re: High resolution time measurement?
    30876: 01/05/02: Re: ccd imaging with fpga
    31154: 01/05/13: Re: 8051 microcontroller
    31372: 01/05/21: Re: Need A little prog?
    32141: 01/06/15: Re: NIOS users ?
    33238: 01/07/20: Re: FPGAs in Safety Involved Applications
    33461: 01/07/27: Re: Too low output voltage on Altera 7000S??
    33792: 01/08/05: Re: Which is the best Design Toolchain?
    33851: 01/08/06: Re: I NEED TO BUY A FPGA BOARD
    36807: 01/11/20: Re: Altera: diff betw. MAX3000 and MAX7000?
    37006: 01/11/28: Re: Got enough mebibytes of RAM ?
    37994: 01/12/29: Re: Choice of Processor Cores in FPGAs - Both Embedded & Soft
    38646: 02/01/20: Re: Altera Nios v2
    38749: 02/01/24: NIOS ver 1.1.1 type boards for sale: Money making opportunity.
    38796: 02/01/25: Re: NIOS ver 1.1.1 type boards for sale: Money making opportunity.
    39312: 02/02/06: Re: Programming Altera PGAs.
    39648: 02/02/15: Re: Is Leonardo spectrum OEM version for Altera limited?
    40109: 02/02/27: Re: microblaze
    40145: 02/02/28: Re: microblaze
    40220: 02/03/02: Re: Altera Excalibur
    41074: 02/03/20: Re: MAX7000 bypass capasitances
    42389: 02/04/22: Re: Nios 2.0 problem
    42918: 02/05/07: Re: Opinions on FPGA cores - best for a commercial project?
    43046: 02/05/10: Re: Have you designed a PCI/Ethernet Adapter using a HDL?
    43407: 02/05/21: Re: fpga cpu
    43604: 02/05/27: Re: SOPC for machine vision
    70534: 04/06/19: Re: >Math Skills = >Engineer ?
    71847: 04/08/02: Re: Downloading program to Nios
    73123: 04/09/14: Re: Adding a Delay2
    73283: 04/09/17: Re: beginner's question
    75481: 04/11/07: Re: Epp interface with Cyclone
    76370: 04/12/01: Re: NIOS II & CS8900?
    76401: 04/12/01: SD Cards
    76662: 04/12/08: Re: Fpga prices
    77534: 05/01/10: Re: Configuration devices
    78266: 05/01/27: Re: Pin Sort
Victor Snesarev:
    13771: 98/12/23: Re: Xilinx XC4000 cinfigured from EPC2?
Victor Snesarev (EXCHANGE:BNRTP:3H18):
    16757: 99/06/07: Re: Altera EPC1 PROM + Data IO ChipWriter
Victor the Cleaner:
    13399: 98/12/01: Re: Will XILINX survive?
    13718: 98/12/20: Re: Atmel's PLD
    13720: 98/12/20: Newbie's Xilinx core question
    13748: 98/12/22: Xilinx/CAST 16550 core
    19644: 00/01/06: Desperate Xilinx problem SOLVED!
    19988: 00/01/21: Re: Desperate Xilinx problem SOLVED!
    20337: 00/02/06: Re: Which is the best HDL book ?
    22572: 00/05/12: Re: Future of FPGAs?
    22625: 00/05/15: Re: Future of FPGAs?
    25173: 00/08/29: Xilinx and CD databooks (rant)
    30525: 01/04/12: Re: Changing Xilinx ROM contents without recompiling
Victor-Bossennec:
    150951: 11/02/24: How to build a VHDL package in order to use it in other projects.
    150967: 11/02/25: Re: How to build a VHDL package in order to use it in other projects.
<victory@wwa.com>:
    1302: 95/05/30: Re: What's happening with NeoCAD?
    1303: 95/05/30: Re: What's happening with NeoCAD?
    1304: 95/05/30: FPGAs for PCI Interfaces
    1305: 95/05/30: Re: Any company for conversion FPGA to ASIC?
    1807: 95/09/05: Re: Actel PCI App Note
video1:
    60650: 03/09/18: Re: Spartan 3 ICAP primitive
    60651: 03/09/18: Reconfiguration, Spartan 3, Compressed bit stream, ICAP
    60664: 03/09/18: Xilinx Spartan 3, SelectMap, Mode pins, Dynamic Reconfiguration
    60665: 03/09/18: Bitstream compression
    60674: 03/09/18: Re: Bitstream compression
    60689: 03/09/19: Re: Reconfiguration, Spartan 3, Compressed bit stream, ICAP
    60690: 03/09/19: Xilinx Impact bitstream compression
    60692: 03/09/19: Re: Spartan 3 ICAP primitive
<vidyasagar.kantamneni@gmail.com>:
    154868: 13/01/22: Re: image storing into BRAM
vignesh_karthi:
    133670: 08/07/09: Regarding Xilinx tool
vijay:
    62702: 03/11/05: Re: Voila: Nedit macro to produce verilog module instantiations
    106816: 06/08/20: Re: Hardware book like "Code Complete"?
Vijay A Nebhrajani:
    3131: 96/04/09: VHDL conversion function from int to time ...?
    3182: 96/04/20: Re: VHDL conversion function from int to time ...?
VIJAY KUMAR:
    152806: 11/10/24: microprocessor design with vhdl
    152807: 11/10/24: ADC by using counter method on FPGA using VHDL language
    152808: 11/10/24: Reference books on microprocessor design with VHDL
Vijay Lakamraju:
    17842: 99/09/12: Virtex Interconnect
Vijay Pandya:
    55877: 03/05/22: Handel-C query
Vijayan:
    129080: 08/02/13: Erratic Behavior of Virtex 4 FPGA
    144100: 09/11/11: How to interface sgmii core to copper media ?
    144122: 09/11/11: Re: How to interface sgmii core to copper media ?
Vijayant:
    119920: 07/05/29: Xilinx Coregen 2.3 problem
    119921: 07/05/29: Xilinx Coregen 2.3 problem
    119982: 07/05/30: Re: Xilinx Coregen 2.3 problem
    131752: 08/04/30: Re: asic gate count
vijayant.rutgers@gmail.com:
    128891: 08/02/08: multidimensional array
    131221: 08/04/15: asic gate count
    131766: 08/05/01: Re: asic gate count
    131847: 08/05/03: Re: asic gate count
    132348: 08/05/22: asic gate count
    132480: 08/05/28: Re: asic gate count
Vijayasimha Kadamby:
    1625: 95/08/06: Multiplier implementation...
vijayvithal jahagirdar:
    106797: 06/08/19: Re: Hardware book like "Code Complete"?
Vijayvithal Jahagirdar:
    53562: 03/03/16: Re: RESET --- Synchronous Vs Asynchronous
Vijit:
    138288: 09/02/12: EPC16 does not configure CycloneII at high temperature
Vik:
    93594: 05/12/25: Looking for 64 bit IEEE802.3 Verilog code or tips for code
    93692: 05/12/28: Re: Looking for 64 bit IEEE802.3 Verilog code or tips for code
vikas:
    54967: 03/04/23: hardware implementation of viterbi decoder
    55201: 03/04/30: Re: hardware implementation of viterbi decoder
    55376: 03/05/06: Re: hardware implementation of viterbi decoder
Vikas:
    141402: 09/06/23: Re: i2c Start and stop detection
    141403: 09/06/23: Re: i2c Start and stop detection
    141421: 09/06/24: Re: i2c Start and stop detection
<vikas@comit.com>:
    13671: 98/12/17: 3-wire specs
Vikash Rungta:
    34702: 01/09/04: Re: How to connect a clock to a non-clock pad ?
    34704: 01/09/04: Re: Virtex II sizing rule of thumb
    45897: 02/08/09: Re: I would like to find some resource for IC layout
vikashrungta@gmail.com:
    133280: 08/06/23: Linked Group for FPGAs & CPLDs
ViKi:
    82214: 05/04/08: ML310 xirtex II pro development board: HOW TO WRITE onto the DDR DIMM?
<vikinger@uni.de>:
    46296: 02/08/24: Re: I want to bay 4 Xilinx FPGA
vikram:
    60656: 03/09/18: HDL Bencher for ISE5.1 Version
    132221: 08/05/18: XILINX Ethernet MAC (URGENT...)
    132298: 08/05/20: Re: XILINX Ethernet MAC (URGENT...)
    132332: 08/05/21: Re: XILINX Ethernet MAC (URGENT...)
    132352: 08/05/22: URGENT :problem using Ethernet MAC ip core...
    132610: 08/06/03: Interrupt handler for Xilinx EMAC- URGENT!!
    132617: 08/06/03: Re: Interrupt handler for Xilinx EMAC- URGENT!!
    132630: 08/06/04: Re: Interrupt handler for Xilinx EMAC- URGENT!!
    132839: 08/06/08: FPGA reprogrammable? (urgent)
    132888: 08/06/09: fpga reprogrammable?
    132889: 08/06/09: Re: FPGA reprogrammable? (urgent)
    132979: 08/06/11: Xilinx EDK - LibGen Error!!!
    133064: 08/06/16: Base System Builder problem... no board
    133068: 08/06/17: FPGA configuration Beginner questions...
    133089: 08/06/17: Re: FPGA configuration Beginner questions...
    133227: 08/06/21: help using lwIP with xilinx EMAC
    133259: 08/06/22: is lwIP absolutely necessary for tcp-ip?
    133294: 08/06/23: How to include the Xilnet library in an EDK project?
Vikram:
    23311: 00/06/21: Re: library not found in Foundation 2.1
    23312: 00/06/21: Re: library not found in Foundation 2.1
    39113: 02/01/31: Re: Linking IP
    49663: 02/11/18: Re: problem with clkdll on spartan2
    49724: 02/11/19: Re: problem with clkdll on spartan2
    49730: 02/11/19: Re: Input / Output flop in IOB + Virtex II
    50379: 02/12/09: Re: Xilinx DCM status bits
    51035: 02/12/27: Re: Floor Planning DCM
    52007: 03/01/28: Re: FSM and XST
    52716: 03/02/19: Re: crc implementation
    53974: 03/03/28: Re: Question about case statement in XilinX webpack
    55401: 03/05/06: Re: Xilinx VirtexII Pro Rocket-IO
    67548: 04/03/13: Re: Does XST handles //synopsys parallel_case?
    71814: 04/07/31: FPGA prototype board with ethernet interfaces
    75227: 04/10/30: Re: Xilinx V-II BUFGMUX oddities..
    74741: 04/10/18: Re: Modelsim simulation problem
    74823: 04/10/19: Re: Modelsim simulation problem
    76184: 04/11/27: Re: XST question
    137356: 09/01/10: Re: Linux friendly FPGA dev board
    139781: 09/04/13: Find FPGA updates On Twitter
    142421: 09/08/10: FPGA-Camp - A mini conference on FPGAs, (Aug'26, Silicon Valley)
    147635: 10/05/10: Register Now: FPGA Camp Bangalore, INDIA. May'21
    147735: 10/05/19: FPGA Camp, Bangalore is tomorrow
    151378: 11/03/29: only 7 days to go - 4th FPGA Camp - 6'Apr 2011 Silicon Valley
Vikram Chandrasekhar:
    45907: 02/08/09: Power saving with Clock gating
    45934: 02/08/11: Advice regarding clock gating
    45951: 02/08/12: Re: Power saving with Clock gating
    45995: 02/08/13: Re: Power saving with Clock gating
    46784: 02/09/08: SystemC query
    46801: 02/09/09: SystemC query
vikram m n rao:
    30740: 01/04/26: XILINX Foundation UCF Problem
    30751: 01/04/27: Input Pins and Synthesis
    30759: 01/04/27: Setting Pins High
    30760: 01/04/27: Setting Pins High (cont'd)
    30830: 01/04/30: MORE Problems Setting Pins High!
    30961: 01/05/04: Reading FPGA output on Parallel Port
    31071: 01/05/10: Reading Data on Parallel Port
    31107: 01/05/11: Clock Waveform
Vikram Nagia:
    30114: 01/03/23: Software Pundits ASIC/FPGA
Vikram Pasham:
    23472: 00/06/26: Re: Canadian University
    23718: 00/07/06: Re: VHDL code for LFSR
    23719: 00/07/06: Re: VHDL code for LFSR
    25017: 00/08/23: Re: run time doubled with Xilinx 3.1i upgrade
    25406: 00/09/10: Re: Tutorial for ABEl-HDL
    25765: 00/09/19: Re: FPGA Express Strikes Again!
    25767: 00/09/19: Re: Bluetooth core??
    25797: 00/09/20: Re: FPGA compiler abort 219
    25844: 00/09/22: Re: Pack I/O Reg/Latches into IOBs
    27068: 00/11/09: Re: Spartan2 macros in WebPACK
    27102: 00/11/10: Re: VHDL: FFS in IOBs
    27103: 00/11/10: Re: FFT LogiCore
    27220: 00/11/15: Re: .mif and .coe files in coregen vs. green mountain 68hc11
    27682: 00/12/01: Re: DLLs driving DLLs in Virtex.
    27762: 00/12/06: Re: ADAPTIVE FILTER
    27875: 00/12/13: Re: Dual-ported RAM instantiation in Virtex-E ?
    28619: 01/01/18: Re: FAQ for this news group? (or What is an FPGA?)
    29668: 01/03/04: Re: Virtex ambit support
    29774: 01/03/08: Re: Spartan XL & Spartan II Slave Serial Configuration
    29777: 01/03/08: Re: Foundation ISE Evaluation Kit - how to order?
    30140: 01/03/25: Re: Timing analysis after implementation
    30218: 01/03/28: Re: Pinout tables
    30219: 01/03/28: Re: Pinout tables
    30223: 01/03/28: Re: Please help a poor student with virtexe
    30225: 01/03/28: Re: Pinout tables
    30414: 01/04/06: Re: Pinout tables
    30546: 01/04/13: Re: Pinout tables
    30982: 01/05/07: Re: Shannon Capacity
    31037: 01/05/09: Re: Virtex-2 - experiences ?
    32071: 01/06/12: Re: Virtex, Routing Error
    32072: 01/06/12: Re: Virtex, Routing Error
    32073: 01/06/12: Re: Video Compression on an FPGA
    32118: 01/06/14: Re: Cores needed
    32146: 01/06/15: Re: efficient CAM in Virtex or Spartan II?
    32889: 01/07/10: Re: Virtexe Config problem
    39373: 02/02/07: Re: Looking for Free EDIF/Verilog netlist - Schematic Viewer
    40675: 02/03/12: Re: cyphers
    41939: 02/04/11: Re: HDLC Controller Design
    42971: 02/05/08: Re: VHDL: FIFO
    46459: 02/08/30: Re: XNF vs. EDIF
    46636: 02/09/04: Re: Viewing Xilinx netlist
    51413: 03/01/13: Re: Celoxica's White Paper on TripleDES
    55603: 03/05/13: Re: Spartan3 DLL?
    58325: 03/07/20: Re: Instantiating pins on Virtex-II Pro
    58470: 03/07/24: Re: Multi Pass Place & Route
    58642: 03/07/29: Re: DCM delays in the TRCE report.
    64154: 03/12/18: Re: Xilinx IOSTANDARD for PCI-X 100MHz interface
    64285: 03/12/24: Re: Problems with Xilinx ISE6.1i P&Rs for Virtex II
    65646: 04/02/03: Re: how to get a vendor id of a pci
    68897: 04/04/21: Re: VCD file generation
    71602: 04/07/24: Re: PCI Core implementation in Spartan 2E FG456 package
    73228: 04/09/16: Re: Synthesis issues in Modelsim 5,7g SE for a simple ROM
    77226: 04/12/31: Re: Xilinx + Modelsim *Please Help Tonight*
Vikram Ragukumar:
    144257: 09/11/23: PCI card unrecognized
    144262: 09/11/23: Re: PCI card unrecognized
    144263: 09/11/23: Re: PCI card unrecognized
    144266: 09/11/23: Re: PCI card unrecognized
vikram.pasham@gmail.com:
    122169: 07/07/21: Re: regarding specifying clock as internal signal in chipscope
vikramp:
    23976: 00/07/19: Re: FPGA Conferences
Viktor Kesler:
    6800: 97/06/28: HELP with mcALLPROG
Viktor Steinlin:
    76454: 04/12/02: Virtex-II PRO, DDR2 SDRAM, RocketIO
    76579: 04/12/06: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO
ville:
    13540: 98/12/08: Links page from Sweden
Ville Salminen:
    81815: 05/04/01: Re: Xilinx ISE 7.1
Ville Voipio:
    65861: 04/02/09: JAM and Xilinx/Altera CPLDs
    65865: 04/02/09: Re: JAM and Xilinx/Altera CPLDs
    66004: 04/02/11: Re: JAM and Xilinx/Altera CPLDs
    66027: 04/02/11: Re: JAM and Xilinx/Altera CPLDs
Vimal:
    121049: 07/06/23: IBIS Model V5 GTP output
    121056: 07/06/24: Re: IBIS Model V5 GTP output
    121067: 07/06/24: Re: IBIS Model V5 GTP output
    121153: 07/06/26: Virtex4 ISERDES question
<vimes_ankh@yahoo.de>:
    115470: 07/02/12: Master IPIF interface
vinay p v:
    147164: 10/04/16: Help needed regarding Vertex2 FPGA
<vinayaksanthosh@gmail.com>:
    138888: 09/03/13: Re: DDR access on Spartan 3E 500 Starter Kit
Vince:
    115584: 07/02/14: CoreABC on M7A3PE600
    119844: 07/05/27: Re: ABC - Actel's PicoBlaze :) - anybody success with coreconsole?
    120869: 07/06/19: SystemC - Libero IDE
    120884: 07/06/19: Re: SystemC - Libero IDE
    125763: 07/11/03: Static PLL
    125796: 07/11/05: Re: Static PLL
Vince Dugar:
    1481: 95/06/27: Prototype Solutions (?)
    1843: 95/09/08: Aptix Experience?
Vincent:
    72609: 04/08/26: Re: Xilinx Command Prompt
    72648: 04/08/27: Re: Modelsim: ROM initialisation
    75392: 04/11/04: Re: SRL16E_1 primitive instantiation in VHDL
Vincent Clerc:
    29073: 01/02/05: Re: FPGA board with lots of SRAM?
    29094: 01/02/06: Re: who wants to work in France ????
Vincent Diepeveen:
    19400: 99/12/19: Re: Dumb question springing from a discussion about chess on a chip...
    19406: 99/12/20: Making a chessprogram in FPGA?
    19430: 99/12/21: Re: Dumb question springing from a discussion about chess on a chip...
    19454: 99/12/22: Re: Dumb question springing from a discussion about chess on a chip...
    19455: 99/12/22: Re: Dumb question springing from a discussion about chess on a chip...
    19472: 99/12/23: Re: Dumb question springing from a discussion about chess on a chip...
    19473: 99/12/23: Re: Dumb question springing from a discussion about chess on a chip...
    69912: 04/05/24: Re: Very Big numbers
    69913: 04/05/24: Re: Very Big numbers
Vincent Himpe:
    1425: 95/06/21: Looking for Orcad library for PALASM
    1458: 95/06/25: Wanted. orcad Library for PALASM.
    2158: 95/10/22: PLD in small package ?? anyone
    4460: 96/11/01: What is the fastest fpga for ...
Vincent J. Mooney:
    24249: 00/08/01: CASES 2000 FINAL Call for Participation
    26045: 00/10/01: CASES 2000 Advanced Program
Vincent Jachetta - Multidyne:
    26529: 00/10/19: FPGA DESIGNER LONG ISLAND
Vincent JADOT:
    42655: 02/04/30: Pb to write on flash with nios on excalibur
    44444: 02/06/20: Re: Multiple Nios CPU's on Altera PLD?
    44486: 02/06/21: Re: Multiple Nios CPU's on Altera PLD?
    44573: 02/06/24: Microblaze uart communication pb!!
    44631: 02/06/25: Re: Microblaze uart communication pb!!
    44633: 02/06/25: Re: Programming examples for Spartan II
    45727: 02/08/02: Which device equivalent
Vincent Ma:
    15990: 99/04/26: Re: Job Advert Netiquette?
Vincent Mack:
    32257: 01/06/21: Re: Xilinx Software free
Vincent Monroe:
    29578: 01/02/27: Programming Vertex-II FPGAs.
Vincent Mooney:
    21396: 00/03/21: CASES 2000 Call for Papers
Vincent Perron:
    78523: 05/02/02: Altera FLEX 8000
Vincent PINON:
    49745: 02/11/20: Programming Altera Flex10k under Linux
Vincent Rowley:
    933: 95/03/31: Re: Memory in xc4000 using synopsys...
    952: 95/04/02: Re: How do I connect an external crystal to a XC4000?
    1577: 95/07/20: Re: HELP!! Xilinx V5.0 doesn't work correctly with Synopsys
    1987: 95/09/28: Re: FPGA for a 20k gates micro-controller.
    4158: 96/09/19: FPGAs design tools for PC
    4571: 96/11/15: VHDL code editor for Windows NT.
Vincent Vendramini:
    41640: 02/04/04: Re: Q: Any Virtex II pro development board on market?
    42151: 02/04/17: Re: Virtex Development Board with a 4M or more gates
<vincent.perron@usherbrooke.ca>:
    78555: 05/02/03: Re: Altera FLEX 8000
<vincent.stay@gmail.com>:
    157122: 14/10/14: Re: Non-project mode Vivado simulation?
    157163: 14/10/22: Re: Non-project mode Vivado simulation?
Vincenzo Liguori:
    13044: 98/11/13: Re: DES in VHDL?
    13463: 98/12/04: JPEG Core compliance
    13466: 98/12/04: Re: JPEG Core compliance
    13615: 98/12/14: Re: Documention AHDL?
    25595: 00/09/15: Re: DCT implementation using FpgA
    29610: 01/03/01: VHDL to Verilog RTL translator available under GPL
    34725: 01/09/05: Re: Looking for a synthesizable JPEG coder core
    36666: 01/11/15: Re: speed of HW JPEG implementations
vinceserti@gmail.com:
    134543: 08/08/17: Multicore OS
vinch:
    85243: 05/06/07: Signed/unsigned divider
    85349: 05/06/08: Re: Signed/unsigned divider
vineeth sukumaran:
    146307: 10/03/11: fastest multiplier for dsps
Vinh Pham:
    60860: 03/09/24: Re: Synchronous counter enable pulse length
    60862: 03/09/24: Re: FPGA implementation in (V)HDL
    60893: 03/09/24: Re: Synchronous counter enable pulse length
    60902: 03/09/24: Re: Synchronous counter enable pulse length
    60974: 03/09/26: Re: LUT and Registers in Xilinx Virtex 2
    60975: 03/09/26: Re: Portable computer for FPGA/CPLD tools
    60984: 03/09/26: Re: How to change "X" to "0" or "1" (VHDL) ?
    60990: 03/09/26: Re: Graphics rendering
    60992: 03/09/26: Re: How to change "X" to "0" or "1" (VHDL) ?
    61025: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
    61027: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
    61030: 03/09/26: Re: Graphics rendering
    61045: 03/09/26: Re: Graphics rendering
    61046: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
    61064: 03/09/26: Re: Graphics rendering
    61068: 03/09/27: Re: Graphics rendering
    61069: 03/09/27: Re: Graphics rendering
    61074: 03/09/27: Re: Graphics rendering
    61102: 03/09/28: Re: How to change "X" to "0" or "1" (VHDL) ?
    61103: 03/09/28: Re: spam poll
    61254: 03/10/01: Re: Frustrations with Marketing
    61297: 03/10/01: Re: Frustrations with Marketing
    61298: 03/10/01: Re: Frustrations with Marketing
    61300: 03/10/01: Re: DP RAM infering
    61306: 03/10/01: Re: Digesting runs of ones or zeros "well"
    61310: 03/10/01: Re: Limitations of Xilinx coregen or limitations with using Xilinx primitives in synthesis.
    61312: 03/10/01: Re: Any word on the V2Pro-X?
    61313: 03/10/01: Re: Frustrations with Marketing
    61348: 03/10/02: Re: Digesting runs of ones or zeros "well"
    61349: 03/10/02: Re: DP RAM infering
    61378: 03/10/02: Re: Digesting runs of ones or zeros "well"
    61391: 03/10/02: Apology to Martin Erudjian
    61393: 03/10/03: Graphics rendering revisited
    61440: 03/10/03: Re: Apology to Martin Erudjian
    61443: 03/10/03: Re: Graphics rendering revisited
    61444: 03/10/03: Re: Digesting runs of ones or zeros "well"
    61446: 03/10/03: Re: Graphics rendering revisited
    61447: 03/10/04: Re: Interesting article about FPGAs
    61498: 03/10/06: Re: Digesting runs of ones or zeros "well"
    61500: 03/10/06: Re: Xilinx courses
    61503: 03/10/06: Re: Should I worry about metastability
    61505: 03/10/06: Re: Should I worry about metastability
    61545: 03/10/06: Re: Should I worry about metastability
    61546: 03/10/06: Re: Should I worry about metastability
    61600: 03/10/07: Re: Xilinx courses
    61603: 03/10/07: Re: Xilinx courses
    61794: 03/10/11: Re: Graphics rendering revisited
    61799: 03/10/12: Re: RAM in Xilinx Spartan II
    61827: 03/10/13: Re: How to select a FPGA
    61905: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
    61907: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
    61914: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
    61919: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
    61946: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
    61984: 03/10/16: Re: Electronic Dice ( 3 die ) In VHDL
    61987: 03/10/16: Re: Ph.inisheD.
    61988: 03/10/16: Re: To our future engineers, smart and otherwise...
    61989: 03/10/16: Re: To our future engineers, smart and otherwise...
    61992: 03/10/16: Re: To our future engineers, smart and otherwise...
    63783: 03/12/04: Re: Quartus generics and vhdl
    63785: 03/12/04: Re: Synchronization between CPU-clock and FPGA clock.
    63786: 03/12/04: Re: CoreGenerator
    63813: 03/12/04: Re: Ideal Development Machine Specifications
    63831: 03/12/05: Re: Ideal Development Machine Specifications
    63857: 03/12/06: Re: Synchronization between CPU-clock and FPGA clock.
    63858: 03/12/06: Re: Block RAM simulation VII
    63861: 03/12/06: Re: Floorplanning techniques
    63862: 03/12/06: Re: Ideal Development Machine Specifications
    63863: 03/12/06: Re: Ideal Development Machine Specifications
    63872: 03/12/06: Re: Block RAM simulation VII
    63877: 03/12/07: Re: Block RAM simulation VII
    63878: 03/12/07: Re: Block RAM simulation VII
    63891: 03/12/08: Re: Block RAM simulation VII
    63920: 03/12/09: Re: Block RAM simulation VII
    63937: 03/12/09: Re: Block RAM simulation VII
    64428: 04/01/04: Re: Complicated clocking in an FPGA.
    64540: 04/01/07: Re: How do you initialize signals in VHDL?
    64542: 04/01/07: Re: Is the P&R processing time proportional to the FPGA gate count or the size of my logic?
Vinitex:
    12582: 98/10/17: Re: clock divider chips
Vinod:
    69175: 04/04/29: EDK 3.2
    69177: 04/04/29: basic question, virtex 2 pro
    69249: 04/05/03: Re: EDK 3.2
    69254: 04/05/03: Re: basic question, virtex 2 pro
    69287: 04/05/04: Re: EDK 3.2
    69294: 04/05/05: Re: EDK 3.2
vinod:
    72615: 04/08/26: problem with DDR
    72638: 04/08/27: Re: problem with DDR
    72692: 04/08/29: Re: problem with DDR
    72806: 04/09/02: reg: clock generatred by combinational logic
<vinogradov.slava@gmail.com>:
    92910: 05/12/09: Re: Experiences with Actel ProAsic3E and toolchain?
Vipan Kakkar:
    22875: 00/05/29: Help with Coregen
    22546: 00/05/11: floorplanning
    22676: 00/05/17: macros for reuse
    26053: 00/10/02: Multiplication
    26165: 00/10/06: Re: Multiplication
Vips:
    147565: 10/05/03: FIFO Depth Calculation
    147566: 10/05/03: FIFO Depth Calculation
    147575: 10/05/04: Re: FIFO Depth Calculation
    147576: 10/05/04: Re: FIFO Depth Calculation
    148027: 10/06/15: How to detect a sync and start of a frame in an optimal way
    148054: 10/06/16: Re: How to detect a sync and start of a frame in an optimal way
    148397: 10/07/17: I2C Master Start stop generation
    148402: 10/07/18: Re: I2C Master Start stop generation
    149242: 10/10/11: Asynchronous Control Signals Synchronization Issues
    149324: 10/10/16: Re: Regarding Synchronization of multiple control signals
    150840: 11/02/16: Regarding passing a control signal from fast to slow cloak domain
    153502: 12/03/16: ways to find frequency of operation in early phase of the design
VIPS:
    96786: 06/02/10: Re: ModelSim # Error loading design
    120366: 07/06/06: How to Find false path in a design
    131028: 08/04/08: 32 bit multiplier
    138055: 09/02/04: help in VHDL procedure programming
    140576: 09/05/18: i2c Start and stop detection
    140622: 09/05/20: Re: i2c Start and stop detection
    141083: 09/06/04: I2C SDA LINE
Virachat Boondharigaputra 34052027:
    938: 95/03/31: Howto FPGA ????
Viral Parikh:
    56724: 03/06/12: Problem with External Memory controller in Xilinx Embedded Development Kit
    58245: 03/07/17: EDK - - -XMD: Can't establish connection with Stub
Viral Shah:
    52254: 03/02/05: Virtex-2 Timing Simulation - 5.1i Service pack-3
Virginia Horseman:
    21830: 00/04/03: HIPO - Hierarchy Input Process Output
VIRMAN:
    22199: 00/05/01: Xilinx CPLD Make file
    22356: 00/05/05: Re: How to connect JTAG to XCS10pc84 FPGA device
viron:
    105171: 06/07/16: Re: An idea for a product (FPGA/ASIC based)
    105516: 06/07/25: Re: An idea for a product (FPGA/ASIC based)
virtex II pro ddr controller(xapp608):
    86680: 05/07/04: DDR controller : problems about burst access
Virtex_User:
    60846: 03/09/23: Corrupt Xilinx 18vxx poms
Virtual:
    12758: 98/10/28: Re: Altera MAXPLUS2 V9 slow.
Virtual Storefronts:
    7617: 97/09/28: Web Hosting
VirtualSean:
    49043: 02/10/30: Getting Started: Seeking intro FPGA material
    49049: 02/10/30: Concepts: What is "Clock Edge"?
    49080: 02/10/31: Re: Concepts: What is "Clock Edge"?
Visar Zejnullahu:
    153602: 12/04/03: Re: Mandelbrot set on Spartan3
vishal shah:
    59865: 03/08/30: DSP
<vishii4u@gmail.com>:
    125001: 07/10/15: profiling in modelsim
Vishker:
    49193: 02/11/04: Re: Incremental design question
    49787: 02/11/21: Re: Global clock routing
    52226: 03/02/04: Clock Enables
    52279: 03/02/05: Re: Clock Enables
    52288: 03/02/05: Re: Clock Enables
    53727: 03/03/20: Re: fpga implementation problems
    56412: 03/06/04: Post P&R Verilog/VHDL netlist
<vishnuprasanth@gmail.com>:
    124992: 07/10/14: FIFO depth
visiblepulse:
    114530: 07/01/18: Re: Generation of Divided-by-3 clock
<visualfor@gmail.com>:
    104493: 06/06/28: DDR2 at 125MHz or lower with Cyclone2
Viswan:
    74126: 04/10/04: question on interfacing FPGA with a sensor
    74230: 04/10/06: Re: question on interfacing FPGA with a sensor
    76535: 04/12/05: doubt on configuring SPARTAN2E FPGA
viswanath:
    35424: 01/10/04: multipliers in virtex-II
    69305: 04/05/05: costal loop question
    69664: 04/05/17: question about filter design vhdl
<viswanathank@gmail.com>:
    108901: 06/09/19: Multiple External Interrupt handling in Microblaze
    109140: 06/09/21: Re: iMPACT: Problem in downloading bit file
    109141: 06/09/21: Re: DCM and domain crossing
<vit.matteo@gmail.com>:
    96166: 06/01/31: Re: Remotely updating Altera FPGA configuration
    106203: 06/08/09: Re: Open source Xilinx JTAG programmer with Digilent USB support
Vitali:
    32558: 01/06/29: XC9500 drive capability
    32639: 01/07/03: Re: Phase Locked loop implementation on FPGA
    34232: 01/08/16: Foundation Series 3.1i ---> Foundation Series ISE 3.3i
Vitaliy:
    112344: 06/11/20: Missing module : XFFT_V3_1 Verilog (not VHDL) module
    113226: 06/12/08: FFT on Virtex II Pro (how to download .dat file?)
    113229: 06/12/08: FFT on Virtex-II Pro (how to download .dat file?)
    113273: 06/12/09: Some questions about FFT implementation
    113274: 06/12/09: Writing output signals to text file (VHDL)?
    113282: 06/12/10: Re: Writing output signals to text file (VHDL)?
    113285: 06/12/10: Re: Writing output signals to text file (VHDL)?
    113286: 06/12/10: Re: Writing output signals to text file (VHDL)?
    113297: 06/12/10: Re: Some questions about FFT implementation
    113327: 06/12/11: Re: Writing output signals to text file (VHDL)?
    113836: 06/12/23: Matlab (.m) to VHDL
Vitaliy Rukhmakov:
    10188: 98/05/02: Need to duplicate Actel A1020B-PL84C
Vitaliy Tkachenko:
    29880: 01/03/15: Re: NIOS 16-Bit
    30397: 01/04/06: Re: Altera 20k programming
    30415: 01/04/07: Re: Altera 20k programming
    35618: 01/10/11: Re: High level synthesis will never work well :)
    38348: 02/01/11: Re: How do I use Altera's PLL megafunction to multiply some frequency ?
    39587: 02/02/13: Re: Making Altera development quicker
<vitalyh@hotmail.com>:
    14988: 99/03/02: LCD driver
<vitek.vitek@gmail.com>:
    124136: 07/09/12: Altera + ARM Cortex-M1
    124163: 07/09/12: Re: Ethernet Code Problem with Xilinx Spartan3E
Vitit Kantabutra:
    5927: 97/03/26: Re: 8-bit divider in FPGA
    6120: 97/04/13: Announcing new division & an fpga implementation
    6126: 97/04/14: New division algorithm
    6238: 97/05/01: Re: Announcing new division & an fpga implementation
    9559: 98/03/23: New radix-4 CORDIC for computing sine and cosine
    9578: 98/03/24: Re: New radix-4 CORDIC for computing sine and cosine
    9995: 98/04/21: carry-save adder
    9997: 98/04/21: Re: Could you help me save CLB's?
    10017: 98/04/22: Re: carry-save adder
    10018: 98/04/22: Re: Could you help me save CLB's?
    10019: 98/04/22: Re: Could you help me save CLB's?
    10021: 98/04/22: Re: carry-save adder
    10020: 98/04/22: Re: Could you help me save CLB's?
    10026: 98/04/22: Re: Could you help me save CLB's?
    10041: 98/04/23: Re: carry-save adder
    11187: 98/07/23: High-radix division
    29918: 01/03/16: SPECIAL SESSION ON LOW-POWER ELECTRONICS AT IECON 2001, DENVER
Vito P. Errico:
    13297: 98/11/24: Add-in board with FPGA Secondary Processor
vitoal18t:
    83517: 05/05/02: Reasonable Entry Level Dev. Board....
Vitolo:
    16652: 99/06/01: XILINX/ALTERA compatibility
vitosim_at_tin.it:
    10298: 98/05/10: PALCE22v10 / GAL22v10 programming algorithms needed
    10746: 98/06/15: *** PALCE22v10 / GAL22v10 programming algorithms needed
vits:
    109031: 06/09/20: i2c,ahb,apb
    109215: 06/09/21: Re: i2c,ahb,apb
    109328: 06/09/24: Re: i2c,ahb,apb
    109350: 06/09/25: I2C slaves needed
    109386: 06/09/25: Re: i2c,ahb,apb
    110112: 06/10/11: Re: ARMv6 ISA doc required plz help
    113314: 06/12/11: Re: @(posedge clk)
    127512: 07/12/31: xilinx PAR runtime and synplify synth runtime
    132026: 08/05/10: getting samples from an RF board onto the system
    133547: 08/07/03: Processor Debug interface
vittal:
    109601: 06/09/30: DDR RAM
    110096: 06/10/11: ARMv6 ISA doc required plz help
    113302: 06/12/10: @(posedge clk)
Vitus:
    77130: 04/12/24: Re: PCI doubt
    77164: 04/12/27: Re: interfacing DDR memory to a spartan-3
Viv:
    72715: 04/08/30: Delay Modelling in TVPACK
vivek:
    34952: 01/09/15: Carry Chain: Delay
    66959: 04/03/02: CASCADING DCM
    70751: 04/06/26: Newbie question -fanout of iopins in fpga
Vivek:
    54812: 03/04/18: OBUF error
    54904: 03/04/21: Xilinx XPower
    63039: 03/11/13: Xilinx Virtex2 tristate support
    71967: 04/08/04: Re: ChipScope Pro Loading Memory
    71990: 04/08/05: Verilog to VHDL conversion
    73771: 04/09/29: Chipscope Pro and VHDL
    73171: 04/09/15: CLK2X
    74426: 04/10/11: GLKP and GLKS
    74479: 04/10/12: Re: GLKP and GLKS
    74626: 04/10/15: Quartus 4.0, Excalibur Synthesis problem
Vivek Joshi:
    71391: 04/07/16: ChipScope Pro : Stimulation
    71848: 04/08/02: ChipScope Pro Loading Memory
Vivek Menon:
    103850: 06/06/13: Virtex-4 FX12: Mini module board from avnet
    103892: 06/06/14: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
    103904: 06/06/14: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
    103912: 06/06/14: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
    103926: 06/06/15: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
    103927: 06/06/15: Virtex-4 with Rocket IO capability??
    103931: 06/06/15: Re: Virtex-4 with Rocket IO capability??
    103934: 06/06/15: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
    104233: 06/06/21: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
    104234: 06/06/21: Detachable Virtex-II Pro/Virtex-4 FX module with Rocket I/O
    104237: 06/06/21: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
    104244: 06/06/21: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
    104246: 06/06/21: Re: Detachable Virtex-II Pro/Virtex-4 FX module with Rocket I/O
    104270: 06/06/22: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
    104283: 06/06/22: RS232 to access TX registers of Aurora
    104449: 06/06/27: Re: RS232 to access TX registers of Aurora using PPC (EDK)
    104455: 06/06/27: Re: RS232 to access TX registers of Aurora using PPC (EDK)
    104457: 06/06/27: Re: RS232 to access TX registers of Aurora using PPC (EDK)
    104459: 06/06/27: Re: RS232 to access TX registers of Aurora using PPC (EDK)
    104476: 06/06/28: Re: RS232 to access TX registers of Aurora using PPC (EDK)
    104483: 06/06/28: Re: RS232 to access TX registers of Aurora using PPC (EDK)
    104495: 06/06/28: Re: RS232 to access TX registers of Aurora using PPC (EDK)
    104527: 06/06/29: Re: RS232 to access TX registers of Aurora using Chapman's UART macros (xapp 223)
    104528: 06/06/29: RS232 transmitter core--Xilinx xapp223(Chapman's macro)
    104535: 06/06/29: help downloading picoblaze from xilinx
    104539: 06/06/29: Re: help downloading picoblaze from xilinx
    104540: 06/06/29: Re: RS232 transmitter core--Xilinx xapp223(Chapman's macro)
    104541: 06/06/29: Re: help downloading picoblaze from xilinx (xapp627.zip)
    104550: 06/06/29: Re: RS232 transmitter core--Xilinx xapp223(Chapman's macro)
    104594: 06/06/30: Pointers for sending data using ethernet connection from V2Pro
    104946: 06/07/10: P160 Communications module 3 with V2PRO--> EDK 7.1 errors
    104947: 06/07/10: Re: Pointers for sending data using ethernet connection from V2Pro
    105034: 06/07/12: Re: Binary Counter Core
    105099: 06/07/13: ADC08D1500 + Virtex-4
    105236: 06/07/18: Re: P160 Communications module 3 with V2PRO--> EDK 7.1 errors
    105237: 06/07/18: Re: Pointers for sending data using ethernet connection from V2Pro
    105324: 06/07/20: High-speed ADC+ Rocket I/O capability FPGA board
    105344: 06/07/20: Re: Using DCM-Virtex-II Pro
    105352: 06/07/20: Re: High-speed ADC+ Rocket I/O capability FPGA board
    105493: 06/07/24: Correlator block
    105528: 06/07/25: Correlator block along with ADC08D1500 Dev board?? Xilinx grp??
    105535: 06/07/25: FFT module with Virtex-4 xc4vlx15
    105765: 06/07/31: Information required on FPGAs and ARM evaluation boards
    105784: 06/07/31: Re: Information requested on FPGAs and ARM evaluation boards
    105943: 06/08/03: Coregen help
    105944: 06/08/03: Re: Coregen help
    105947: 06/08/03: Re: Coregen help
    105964: 06/08/03: Re: Coregen help
    105999: 06/08/04: checking the FFT cores on Xilinx FPGAs
    117742: 07/04/09: Re: PCI FPGA Dev Board Suggestions
    136029: 08/10/28: Re: I need a good reference for VHDL
    136062: 08/10/29: verilog simulation of LogiCORE Complex Multiplier v2.1
    136969: 08/12/16: Sign extension issue in Xilinx Multiplier CoreGen version10
    145434: 10/02/09: SoC benchmarks
    147730: 10/05/19: BLK_MEM_GEN_v2_8.I948.10 error when using BRAM Xilinx ISE 10.1
    147733: 10/05/19: Re: BLK_MEM_GEN_v2_8.I948.10 error when using BRAM Xilinx ISE 10.1
    147861: 10/05/27: =?windows-1252?Q?Verifying=2Fcomparing_the_FFT_output_between_Xilinx_Co?=
    147946: 10/06/03: =?windows-1252?Q?Re=3A_Verifying=2Fcomparing_the_FFT_output_between_Xilin?=
    147956: 10/06/03: =?windows-1252?Q?Re=3A_Verifying=2Fcomparing_the_FFT_output_between_Xilin?=
    151012: 11/02/28: regarding usage of IOBs and Warning XST 2036
    151014: 11/02/28: Re: regarding usage of IOBs and Warning XST 2036
    151018: 11/02/28: Re: regarding usage of IOBs and Warning XST 2036
    151952: 11/06/14: Area optimization (optimizing DSP48E usage)
    151962: 11/06/15: Determine latency of GTX links vs Aurora+LVDS
    154180: 12/08/29: =?UTF-8?Q?Simulating_fixed_point_multiplica=E2=80=8Btion_using_float?=
    155576: 13/07/23: Nios II problem with DDR core SOPC builder
    155580: 13/07/23: Re: Nios II problem with DDR core SOPC builder
    155586: 13/07/24: Re: Nios II problem with DDR core SOPC builder
    155662: 13/08/01: NiosII 8.0 make error Windows XP
    155691: 13/08/05: Re: NiosII 8.0 make error Windows XP
    155692: 13/08/05: Re: NiosII 8.0 make error Windows XP
Vivek Sagdeo:
    4555: 96/11/13: (no subject)
    4556: 96/11/13: Re: (no subject) - Comprehensive Verilog Training Dec 3-5 and Jan 7-9 - Silicon Valley
Vivek Sood:
    31110: 01/05/11: Re: SRAM fpga cell
    31282: 01/05/16: Re: FPGA based Neural Networks
vivek1609:
    148209: 10/06/29: MicroBlaze - how to instantiate/connect more BRAM to the LMB
<VIVEKEDU2003@YAHOO.CO.IN>:
    77800: 05/01/17: Re: Wallace Tree Multiplier Documentation wanted
<vivekgarg330@gmail.com>:
    92003: 05/11/18: Help Needed Regarding VPR
    97208: 06/02/18: Approximate power and area values for a 1-bit SRAM cell.
Vivian:
    30697: 01/04/24: XHWIF and Virtex Strartup
    30729: 01/04/26: Re: XHWIF and Virtex Strartup
    30752: 01/04/27: Re: XILINX Foundation UCF Problem
    30810: 01/04/30: problems with rc1000pp and xhwif
    31363: 01/05/21: Xilinx tools
    31430: 01/05/23: block diagrams
    33211: 01/07/19: SystemC
Vivian Bessler:
    94740: 06/01/17: Virtex 4 : Configuration-memory readback
    103003: 06/05/24: Re: fpga debug
    103065: 06/05/25: Re: how to readback a frame
    103073: 06/05/25: ChipScope and the FPGA Editor ILA command
    103803: 06/06/12: Re: how to readback a frame
    103886: 06/06/14: Re: how to readback a frame
    105815: 06/08/01: Re: Quick way to change Xilinx BRAM init values
    111929: 06/11/13: FPGA Debug Tool
    111940: 06/11/13: Re: FPGA Debug Tool
    111943: 06/11/13: Re: FPGA Debug Tool
    111952: 06/11/13: Re: FPGA Debug Tool
vizziee:
    141749: 09/07/06: How to interpret polyphase coefficients generated in MATLAB
    141752: 09/07/06: Re: How to interpret polyphase coefficients generated in MATLAB
    141753: 09/07/06: Re: How to interpret polyphase coefficients generated in MATLAB
    141757: 09/07/06: Re: How to interpret polyphase coefficients generated in MATLAB
    141759: 09/07/06: Re: How to interpret polyphase coefficients generated in MATLAB
    141762: 09/07/06: Re: How to interpret polyphase coefficients generated in MATLAB
    141763: 09/07/06: Re: How to interpret polyphase coefficients generated in MATLAB
    141768: 09/07/07: Re: How to interpret polyphase coefficients generated in MATLAB
    141769: 09/07/07: Re: How to interpret polyphase coefficients generated in MATLAB
    141785: 09/07/08: Re: How to interpret polyphase coefficients generated in MATLAB
    142057: 09/07/23: Re: How to interpret polyphase coefficients generated in MATLAB
    142078: 09/07/23: Re: How to interpret polyphase coefficients generated in MATLAB
<vizziee@gmail.com>:
    88566: 05/08/22: Unused pins from FPGA to LAN91C111 (through NIOS)
    89054: 05/09/04: Re: Logic??
<vizziee@yahoo.com>:
    77049: 04/12/20: Re: Problem with SOPC Builder in Quartus 4.0
    77088: 04/12/21: Re: Problem with SOPC Builder in Quartus 4.0
    77174: 04/12/28: References for FPGA implementation of OS-CFAR
    77175: 04/12/28: VHDL implementation of merge-sort
    77176: 04/12/28: Primers for Handel-C
    77190: 04/12/28: Re: Google is turning usenet into crap - was Primers for Handel-C
    77191: 04/12/28: Re: Google is turning usenet into crap - was Primers for Handel-C
    77303: 05/01/04: Re: VHDL implementation of merge-sort
<vjkaran19@gmail.com>:
    159827: 17/03/28: Re: Divide clock frequency by 1.5: output duty cycle is not 50%
    159829: 17/03/28: Re: Divide clock frequency by 1.5: output duty cycle is not 50%
<vkode77@hotmail.com>:
    29699: 01/03/05: ROM-based FSM implementation
<vkr101@gmail.com>:
    122709: 07/08/03: World's 1st FPGA Centric Portal goes LIVE!!
Vlad:
    66499: 04/02/20: Re: regarding synchronization
    66508: 04/02/20: multiple clocking in FPGA
    67402: 04/03/11: Stratix GX experience ?
<vlad@comsys.ntu-kpi.kiev.ua>:
    41345: 02/03/26: failure rate of Xilinx chips
    41389: 02/03/27: Re: failure rate of Xilinx chips
    42073: 02/04/15: JTAG cable and iMPACT
Vladan:
    77790: 05/01/17: Quartus II Command Line and Project Files
<vladan2005@gmail.com>:
    77797: 05/01/17: Re: Quartus II Command Line and Project Files
Vladimir:
    35787: 01/10/17: Could VirtexII multiplier work faster?
    51923: 03/01/26: IEEE 1149.1
vladimir:
    62213: 03/10/22: Cool test bench generator for testing some devices which describe by Verilog or VHDL
    62261: 03/10/23: Re: Cool test bench generator for testing some devices which describe by Verilog or VHDL
    62289: 03/10/24: Re: Cool test bench generator for testing some devices which describe by Verilog or VHDL
    62290: 03/10/24: Re: Subroutine in VHDL?
    62291: 03/10/24: Useful examles source code Verilog, VHDL, PLI, FLI, Tcl/Tk embedded interpreter (www.hightech-td.com)
    66111: 04/02/12: EDA tool for testing HDL designs (new update) - www.hightech-td.com
    67141: 04/03/06: New release TBGenerator (added wave form) - www.hightech-td.com
    67590: 04/03/15: New release of TBGenerator v.3.00 (new GUI, new functional possibility, new Wave Form...) www.hightech-td.com
    73570: 04/09/24: NIOS II (full sample working with DMA in HAL)?
    73642: 04/09/27: Maybe someone knows where I can get a schematic of the MJL Cyclone Development Kit board? Thx.
    75825: 04/11/16: Hello anyone! Does someone works with CS8900 under NIOSII? It's really works? Please, write works it with HAL? Thx.
    76130: 04/11/25: Help with NIOS II please.......
    76336: 04/11/30: NIOS II & CS8900?
    77196: 04/12/28: Does SPI from NIOS II work?
    77381: 05/01/05: EPCS16 & NIOS2 Custom board
Vladimir Dergachev:
    33074: 01/07/17: clock versus just a pad
    33075: 01/07/17: Re: Book Recommendation (bit different)
    33139: 01/07/18: Re: Newbie Question
    33281: 01/07/21: Re: Silo-3 Demo Program Crashes onDell 4100
Vladimir Ivanov:
    157580: 14/12/18: Re: VHDL Synchronization- two stage FF on all inputs?
    157677: 15/01/27: Artix-7 tools, ISE vs Vivado
    157681: 15/01/27: Re: Artix-7 tools, ISE vs Vivado
    157686: 15/01/28: Re: Artix-7 tools, ISE vs Vivado
Vladimir Kapitanov:
    30965: 01/05/05: Re: CompactPCI card with Virtex
Vladimir N. Zlatopolsky:
    262: 94/10/07: Presentation CAD & FPGA ICs of Actel Corp.
Vladimir Orlic:
    115778: 07/02/20: Selecting device in Project Properties : no XC2V1000?
Vladimir Ralev:
    40227: 02/03/02: turnaround cycle?
    40238: 02/03/03: Re: turnaround cycle?
    46755: 02/09/07: PCI bus problems
Vladimir Trosin:
    19362: 99/12/16: We work for you to have a rest!!!
Vladimir Vassilevsky:
    107627: 06/08/30: Re: Performance Appraisals
    107640: 06/08/30: Re: Performance Appraisals
    107964: 06/09/03: Re: Performance Appraisals
    112739: 06/11/28: Re: Digital PLL and FM demodulation
    112757: 06/11/28: Re: Digital PLL and FM demodulation
    115676: 07/02/16: Re: Building Coaxial transmission line on PCB?
    115680: 07/02/16: Re: Building Coaxial transmission line on PCB?
    115703: 07/02/17: Re: Building Coaxial transmission line on PCB?
    115709: 07/02/17: Re: Building Coaxial transmission line on PCB?
    115710: 07/02/17: Re: Building Coaxial transmission line on PCB?
    115711: 07/02/17: Re: Building Coaxial transmission line on PCB?
    115712: 07/02/16: Re: Building Coaxial transmission line on PCB?
    132866: 08/06/09: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
    137975: 09/02/03: Re: Implementation of Xilinx Aurora protocol with error correction
    139355: 09/03/27: Re: FIFO controlled loop, PLL, FLL or something else?
    141751: 09/07/06: Re: How to interpret polyphase coefficients generated in MATLAB
    141761: 09/07/06: Re: How to interpret polyphase coefficients generated in MATLAB
    148523: 10/07/29: Re: Data-path accuracy in IIR filters?
    149500: 10/10/31: Re: [O.T.] Audio DAC as AWG (test source)?
    149502: 10/10/31: Re: [O.T.] Audio DAC as AWG (test source)?
    152256: 11/07/28: Re: Bitstream compression
    152266: 11/07/29: Re: Bitstream compression
    152899: 11/10/31: Re: Fundamental DSP/speech processing patent for sale
    152900: 11/10/31: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
    152937: 11/11/02: Re: Fundamental DSP/speech processing patent for sale
    152982: 11/11/07: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
    152988: 11/11/07: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
    152991: 11/11/07: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
<vladimir@baykov.de>:
    101487: 06/05/01: 50-th Anniversary of the CORDIC Algorithm
    101555: 06/05/02: Table-lookup CORDIC
    101570: 06/05/03: Re: 50-th Anniversary of the CORDIC Algorithm
    103141: 06/05/25: Re: Cordic-based Sine Computer in MyHDL
VladimirM:
    124703: 07/10/01: Error in simple code, plz help
Vladislav Muravin:
    71366: 04/07/15: Re: Clock generation
    71381: 04/07/16: Re: Clock generation
    78894: 05/02/09: Re: virtex4 distributed RAM
    79420: 05/02/18: Re: Issues with a batch of Virtex-II chips
    79423: 05/02/18: Re: Xilinx: Pitfalls of chaining DLLs
    79638: 05/02/22: Re: virtex II register file
    79727: 05/02/23: Re: Quartus DESIGN ASSISTANT tool
    79875: 05/02/25: Re: Synthesis question
    79876: 05/02/25: Re: Prescalable counter
    79878: 05/02/25: Re: Quartus DESIGN ASSISTANT tool
    81292: 05/03/21: question about salary
    81311: 05/03/21: Re: question about salary
    81389: 05/03/22: Re: clock division using DCM, how?
    82016: 05/04/05: Re: IBUFG and BUFG +xilinx
    83655: 05/05/04: Re: Gated clock problem
    83658: 05/05/04: Re: DCM, constraints and routing (Xilinx Spartan 3)
    83774: 05/05/06: Re: Will this DCM cascade track a frequency offset clock?
    84882: 05/05/31: Re: Timing summary
    84883: 05/05/31: Re: JTAG Programming Problem
    84884: 05/05/31: Re: Xilinx ISE 6.1i - Fatal Error
    85171: 05/06/06: Re: Clock Generation : FPGA
    85300: 05/06/07: Re: VirtexII:DCM:CLKFX phase delay
    85301: 05/06/07: Re: Clock doubler to double an input 13.5 Mhz
    85303: 05/06/07: Re: FPGA/CPLD trend
    85305: 05/06/07: Re: faster Spartan III adder
    85359: 05/06/08: Re: false path on asyn. fifo
    85362: 05/06/08: Re: Clock doubler to double an input 13.5 Mhz
    85367: 05/06/08: Re: Available under the terms of the SignOnce IP License
    85417: 05/06/09: Re: [Vir2] Can I use a 18k ram as 2 single-port ram?
    85556: 05/06/10: Re: ISE7.1 PAR Warinng: excessive skew because 1 NON-CLK pins...
    85662: 05/06/13: Re: never seen XST error
    85702: 05/06/14: question - NGC & NGO files & integration
    85709: 05/06/14: Re: Problem for xilinx!!!
    85710: 05/06/14: errors during MAP
    85802: 05/06/16: Re: Deisgn partitioning issues
    85803: 05/06/16: Re: convert vhdl to edif
    85807: 05/06/16: question regarding "Add I/O buffers" option - SOS
    85885: 05/06/17: Re: question regarding "Add I/O buffers" option - SOS
    86070: 05/06/21: Re: circuit optimization - a feedbackless machine
    86071: 05/06/21: Re: Post Translate Timing
    86137: 05/06/22: Re: Area_Group
    86156: 05/06/22: Re: ISE 7.1 - block memory init value issue during simulation
    86184: 05/06/22: Re: Frequency divisors
    86229: 05/06/23: Re: Serial I/O - Delay Output
    86231: 05/06/23: using GUI and batch mode produces different results !
    86237: 05/06/23: Re: using GUI and batch mode produces different results !
    86380: 05/06/27: Re: Two Verilog FSM style compare
    86381: 05/06/27: Re: unisim for synthesis?
    86383: 05/06/27: Re: interfacing to multiple converters
    86386: 05/06/27: Re: XILINX DCMs and synthesis results
    86387: 05/06/27: Re: using GUI and batch mode produces different results !
    86417: 05/06/27: Re: Good FPGA for an encryptor
    86474: 05/06/28: INFO:Par:252 - The Map -timing placement will be discarded
    86511: 05/06/29: Re: ADPLL for NRZ
    86545: 05/06/29: Re: ADPLL for NRZ
    86726: 05/07/05: Re: Xilinx: XST synchronous FIFO using BRAMs
    86768: 05/07/06: Re: VHDL Clock Domains
    86792: 05/07/06: Re: Triggering and reseting FF
    86912: 05/07/08: Re: Timespec for DCM outputs (Spartan 3) ?
    87170: 05/07/18: pricing of Virtex-4
    87173: 05/07/18: Re: pricing of Virtex-4
    87177: 05/07/18: Re: pricing of Virtex-4
    87220: 05/07/19: Re: Xilinx equivalent of simplify constrains.
    87221: 05/07/19: Re: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1
    87222: 05/07/19: Re: pricing of Virtex-4
    87258: 05/07/20: Re: Using unregistered inputs in FSM
    87264: 05/07/20: Re: Ones Count 64 bit on Xilinx in VHDL
    87265: 05/07/20: Re: Design is too large for the device! xc3s400
    87269: 05/07/20: Re: All of the design is being optimized away and logic removed
    87313: 05/07/21: Re: All of the design is being optimized away and logic removed
    87324: 05/07/21: Re: Using unregistered inputs in FSM
    87380: 05/07/22: Re: Using unregistered inputs in FSM
    87388: 05/07/22: Re: Using unregistered inputs in FSM
    87403: 05/07/22: Re: verilog to blif(lut)
    87501: 05/07/25: Re: DCM.
    87502: 05/07/25: Re: Using unregistered inputs in FSM
    87585: 05/07/26: Re: comprehension of clck to pad,clock to setup,etc
    87626: 05/07/27: Re: Conversion of ASIC RTL to FPGA RTL
    87628: 05/07/27: question for Xilinx ppl
    87657: 05/07/27: Re: No clock signals found in this design... XST V2P
    87688: 05/07/28: Re: GLCKs on Spartan3
    87689: 05/07/28: Re: question for Xilinx ppl
    87779: 05/08/01: Re: some virtexII clock pads are useless??
    87786: 05/08/01: Re: About post synthesize
    87831: 05/08/02: Re: Conversion of Schematic to Verilog/VHDL
    87832: 05/08/02: Re: Xilinx Multiple Spartan 3
    87833: 05/08/02: Re: Xilinx Best Source for Reset
    87834: 05/08/02: Re: Bidirectional Bus problem with ModelSim.
    87838: 05/08/02: Re: some virtexII clock pads are useless??
    87967: 05/08/04: Re: Modulation Clock to set FPGA timing
    87968: 05/08/04: Re: Xilinx Multiple Spartan 3
    87969: 05/08/04: Re: About post synthesize
    88153: 05/08/10: Re: About post synthesize
    88191: 05/08/11: Re: Clocks
    88237: 05/08/12: Re: Regarding clock muxing
    88239: 05/08/12: Re: Clocks
    88326: 05/08/15: Re: Clock generation
    88327: 05/08/15: Re: 18-bit ROM in verilog
    88328: 05/08/15: Re: XST (ISE 6.1i): Error: It's interesting and surprising
    88462: 05/08/18: Re: XST Help - Device Utilization Woes
    88464: 05/08/18: Re: State Machine and BUFG
    88465: 05/08/18: Re: FPGA-Based system design project
    88466: 05/08/18: Re: Antti's last comp.arch.fpga posting
    88468: 05/08/18: Re: Antti's last comp.arch.fpga posting
    88505: 05/08/20: Re: Antti's last comp.arch.fpga posting
    88661: 05/08/24: Re: Help coding a bigger project
    88688: 05/08/25: i need some help ASAP !!! (DLL - Spartan-IIE)
    88740: 05/08/26: Re: Writing to Spartan 3 SRAM
    88741: 05/08/26: Re: i need some help ASAP !!! (DLL - Spartan-IIE)
    88866: 05/08/30: Re: Clock skew in FPGA Xilinx?
    88867: 05/08/30: Re: Should I use DCM for every FPGA design?
    88968: 05/09/01: Re: Lot of 60 XCV1000 FPGAs
    88969: 05/09/01: Re: Gated clock for FPGA (verilog)???
    89261: 05/09/09: Re: implementing the tristate bus
    89308: 05/09/12: Re: Fatal errror in ISE 6.3 i
    89400: 05/09/14: Re: FFT implementation in Xilinx Spartan 3 started kit
    89401: 05/09/14: Re: fan out capability of FPGA
    89402: 05/09/14: Re: FIFO design using Virtex-II block ram..
    89403: 05/09/14: Re: CPU benchmark for Xilinx PAR
    89407: 05/09/14: Re: reducing the number of IOBS in a design
    89419: 05/09/14: Re: FFT implementation in Xilinx Spartan 3 started kit
Vladislav Vasielnko:
    42104: 02/04/16: Re: JTAG cable and iMPACT
    42105: 02/04/16: Re: JTAG cable and iMPACT
    42108: 02/04/16: Power supply pins
Vladislav Vasilenko:
    24614: 00/08/15: About foundation 3.1
    24711: 00/08/17: Re: Permanently programming FPGAs
    24734: 00/08/17: Re: Permanently programming FPGAs
    24974: 00/08/23: about Xilinx e-mail document server
    28988: 01/02/01: PCI testbench
    31748: 01/06/05: Re: Xilinx Configuration Bitstream
    42121: 02/04/16: Re: Power supply pins
    43955: 02/06/07: Re: PowerPC Architecture
    51879: 03/01/24: SRL initialization problem
    51948: 03/01/27: XST 4.1 bug or ..?
    65921: 04/02/10: Re: FIR filter coefficient (with COE file)
    66079: 04/02/12: Re: regarding opto isolators
vladitx:
    129376: 08/02/22: Re: Reconfiguration (on the fly) using SPARTAN 3A
    131145: 08/04/12: Re: Need help on UNISIM.Vcomponents.all
    137747: 09/01/28: Re: What software do you use for PCB with FPGA ?
vlir_c8:
    102304: 06/05/14: Files.ucf QAM Demodulators for Xtreme DSP Development KIT
<vlodiya@gmail.com>:
    135366: 08/09/28: Low frequency clock generation - need help
<vlogvin@my-deja.com>:
    17768: 99/09/01: Re: Virtex BRAM Initialization
    17767: 99/09/01: virtex RANB
    18013: 99/09/23: Re: Vertex Select I/O
VLSI:
    1569: 95/07/18: ACTEL PLACE AND ROUTE
    1757: 95/08/28: Help On Fujitsu Gate Arrays
    35489: 01/10/07: IEEE 802.11 Design
vlsi:
    91876: 05/11/15: Re: Coolrunner output pins stuck at 0V
    142377: 09/08/07: diff b/w synthesis and implementation in xilinx ISE
Vlsi Champ:
    54795: 03/04/17: ISE 5.1i : Timing Analyzer
    55534: 03/05/11: Xilinx : Tools
    55799: 03/05/20: Xilinx : Tools
vlsi-student:
    73251: 04/09/16: Regarding FPGA
vlsi330:
    153326: 12/02/01: regarding tft controller
vlsi_freak:
    125556: 07/10/29: FPGA Configuration
<vlsi_kida@math.net>:
    105509: 06/07/24: EDK + Assembly Output Files + External Memory Usage
vlsi_learner:
    77555: 05/01/10: altera stratix problem
    77557: 05/01/10: Re: altera stratix problem
    77820: 05/01/17: Re: altera stratix problem
    77831: 05/01/18: Re: altera stratix problem
    77901: 05/01/19: Asynchronous memory in Stratix devices
    82638: 05/04/15: different I/O buffers available inXilinx FPGA
    82647: 05/04/15: Re: different I/O buffers available inXilinx FPGA
    83562: 05/05/03: Re: different I/O buffers available inXilinx FPGA
    115266: 07/02/05: moving data from slower to faster clock domain
    115355: 07/02/08: question abt DPRAM
    115357: 07/02/08: Re: question abt DPRAM
    115775: 07/02/20: can I convert DPRAM to SPRAM?
    115803: 07/02/21: newbie question
    118005: 07/04/16: dual port memory from single port RAM.
    118053: 07/04/16: Re: dual port memory from single port RAM.
    118068: 07/04/17: Re: dual port memory from single port RAM.
    118069: 07/04/17: Re: dual port memory from single port RAM.
    133664: 08/07/09: Can I store the output of my FPGA logic inside FPGA memory for debug
    133771: 08/07/14: Reading FPGA internal memory data
vlsiasic:
vlsichipdesigner@gmail.com:
    136983: 08/12/17: Re: SystemVerilog OOP and OVM Summary
vlsifresher:
    115781: 07/02/20: Re: can I convert DPRAM to SPRAM?
    115801: 07/02/21: Re: can I convert DPRAM to SPRAM?
vmenon:
    158048: 15/07/28: FPGA board to interface with ADC (>10 GHz) and generate 5Gbps PRBS
<vn5s-cng@asahi-net.or.jp>:
    4679: 96/11/29: Re: How to use Xilinx ?
Vo Cun To (-):
    10488: 98/05/23: Evolutionary FPGAs
Vo To:
    10184: 98/05/02: Help: 25Mhz XC4025E-2 FPGA having hold time errors during simulation
    10233: 98/05/05: How to use LogiBlox Components in FPGA Express?
    10232: 98/05/05: How to use LogiBlox Components in FPGA Express?
    10576: 98/06/02: HELP: Bidirectional I/O's in state machine
Volker:
    113453: 06/12/14: CMI Coder/ Decoder
Volker Hetzer:
    5547: 97/02/24: Re: State Diagram Tools
    6339: 97/05/16: Re: VHDL or Verilog?
Volker Kalms:
    19034: 99/11/24: ALTERA EPC2 Configuration Help needed!
    19035: 99/11/24: Configuration of ALTERA EPC2LC20 Please help!
    19187: 99/12/03: ALTERA EPC2 configuration problem
Volker Kurt Kamp:
    2676: 96/01/23: AT&T Orca vs Xilinx
    3221: 96/04/29: Synario Universal FPGA Design System
    3240: 96/05/02: Re: Synario Universal FPGA Design System
    3284: 96/05/09: Xilinx Mapping & Placing in HDL
Volker Nicolai:
    20267: 00/02/03: Crossing clock domain boundaries in digital ASICs
Volker Urban:
    21173: 00/03/09: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
Volt Services Group:
    6274: 97/05/07: US - San Jose - Firmware Engineer (Analog, Digital, DSP)
Volume WU Actual:
Von Heler:
    92343: 05/11/28: Re: AD9218, what will the negative values be in binary mode?
<voodoo98_ca@my-deja.com>:
    29220: 01/02/10: Re: verilog book
vorange:
    134440: 08/08/10: Newbie question : Xilinx Webpack examples
    134441: 08/08/10: Re: Newbie question : Xilinx Webpack examples
    134487: 08/08/12: Re: Newbie question : Xilinx Webpack examples
<vortekdoug@my-deja.com>:
    17848: 99/09/13: A mix is best
    17870: 99/09/14: Re: Lowest power FPGA
Voxer:
    77012: 04/12/20: Virtex II Pro Memory Questions
    77060: 04/12/21: DSOCM BRAM I/F Controller
    77094: 04/12/22: Re: DSOCM BRAM I/F Controller
    77966: 05/01/21: Embeddded PPC - V2Pro - Interrupts
    78061: 05/01/24: Re: Embeddded PPC - V2Pro - Interrupts
    83518: 05/05/02: OPB Intc - HELP !!!!
<voytov@ihpc.net>:
    40087: 02/02/26: EEPROM simulation
VP:
    41524: 02/04/01: Data Compression in FPGAs
    41551: 02/04/01: Re: Data Compression in FPGAs
    42142: 02/04/16: Telecom Bus info
Vp2000kit-Alvin:
    3478: 96/06/06: Mixing verilog and schematic for Altera MAX9000
VR:
    30573: 01/04/17: Clean Frequency Division
    36110: 01/10/30: Device support Foundation 3.1i SP8
    36673: 01/11/15: High Speed PWM?
    36692: 01/11/15: Re: High Speed PWM?
    36714: 01/11/17: Re: High Speed PWM?
    36793: 01/11/20: Synplicity and BlockRAM?
    36816: 01/11/21: Re: Synplicity and BlockRAM?
    36834: 01/11/21: Re: Synplicity and BlockRAM?
    36942: 01/11/27: SPI implementation details
    37175: 01/12/03: Crossing a clock domain
    37402: 01/12/10: XESS XSV-800 Gripes
    39070: 02/01/31: Re: Intel vs. AMD
    39150: 02/02/02: Re: Intel vs. AMD
vr:
    33786: 01/08/05: Re: May I connect two pins to the same net?
vragukumar:
    146801: 10/03/29: Xilinx Webpack v11.4 availability
    146857: 10/03/30: Re: Xilinx Webpack v11.4 availability
    146858: 10/03/30: Re: Xilinx Webpack v11.4 availability
    146875: 10/03/30: Migrating project from Xilinx ISE v7.1 to v11.1
    146910: 10/04/01: Predefined MACRO's in XST v11.5
    146962: 10/04/05: Re: Predefined MACRO's in XST v11.5
    147031: 10/04/09: Module wise FPGA resource utilization report
    147032: 10/04/09: Re: Predefined MACRO's in XST v11.5
<vrbvasu@gmail.com>:
    157699: 15/02/07: Topics for Projects on FPGA+Computer Archtecture
    157703: 15/02/07: Re: Topics for Projects on FPGA+Computer Archtecture
vrml3d.com:
    16875: 99/06/15: newbie -- What's the best way to get started?
VRMS:
    75195: 04/10/28: Re: Looking for FPGA design services in India or similar
<vruhou@nurb.com>:
    24959: 00/08/23: OH NO!
vsh:
    153297: 12/01/28: Design Notation VHDL or Verilog?
VSP:
    89099: 05/09/05: Strange warning "WARNING:MapLib:701 - Signal P_GPIO_3 connected to top level port P_GPIO_3 has been removed."
VSR:
    78527: 05/02/02: Trouble with XilinxCoreLib\vhdl_analyze_order
    80295: 05/03/03: How to read back!
    80489: 05/03/07: Readback
<vsrpkumar@rediffmail.com>:
    112145: 06/11/16: Hpw to remove combinational loops in quartus s/w
vssumesh:
    86488: 05/06/28: Clock buffers on the Viretx E
    86516: 05/06/29: Clock buffering in VirtexE FPGA
    86567: 05/06/30: TDI routing in Virtex E FPGA.
    86619: 05/06/30: Re: Clock buffering in VirtexE FPGA
    86627: 05/07/01: Re: Clock buffering in VirtexE FPGA
    86661: 05/07/03: Re: Clock buffering in VirtexE FPGA
    86662: 05/07/03: Re: Clock buffering in VirtexE FPGA
    86663: 05/07/03: Re: Clock buffering in VirtexE FPGA
    86683: 05/07/04: Re: Clock buffering in VirtexE FPGA
    86770: 05/07/06: Triggering and reseting FF
    86818: 05/07/07: SELV - power supply specification
    86844: 05/07/07: Re: SELV - power supply specification
    87074: 05/07/14: Doubts on Xilinx FPGA
    87108: 05/07/15: Re: Doubts on Xilinx FPGA
    87109: 05/07/15: Re: Doubts on Xilinx FPGA
    87130: 05/07/16: Re: Doubts on Xilinx FPGA
    87191: 05/07/18: Driving the FPGA output.
    87214: 05/07/19: Xilinx equivalent of simplify constrains.
    87745: 05/07/30: About post synthesize
    87746: 05/07/30: Re: Triggering and reseting FF
    87764: 05/07/31: Re: About post synthesize
    87765: 05/07/31: Re: struggling with general digital design
    87780: 05/08/01: Re: struggling with general digital design
    87781: 05/08/01: Re: About post synthesize
    87783: 05/08/01: Re: Doubts on Xilinx FPGA
    87869: 05/08/02: Re: About post synthesize
    87996: 05/08/04: Re: About post synthesize
    88007: 05/08/05: Modeling two dimensional circuits
    88019: 05/08/05: Re: Modeling two dimensional circuits
    88024: 05/08/05: Re: Modeling two dimensional circuits
    88997: 05/09/02: Multidimensional port.
    89006: 05/09/02: Re: Multidimensional port.
    89007: 05/09/02: Creating higher bit multipliers from low bit.
    89118: 05/09/06: Disconnect the FPGA I/O pads from the outside world
    89212: 05/09/07: Re: Disconnect the FPGA I/O pads from the outside world
    89246: 05/09/08: Re: Disconnect the FPGA I/O pads from the outside world
    89278: 05/09/09: Re: implementing the tristate bus
    89383: 05/09/13: fan out capability of FPGA
    89496: 05/09/16: Re: fan out capability of FPGA
    89928: 05/09/30: Prob in Synthesizing and Simulating large Mux
    89933: 05/09/30: Re: Prob in Synthesizing and Simulating large Mux
    90024: 05/10/02: Re: Prob in Synthesizing and Simulating large Mux
    90032: 05/10/03: Re: Prob in Synthesizing and Simulating large Mux
    90040: 05/10/03: Re: Prob in Synthesizing and Simulating large Mux
    90062: 05/10/04: Re: Prob in Synthesizing and Simulating large Mux
    90136: 05/10/05: Re: Prob in Synthesizing and Simulating large Mux
    90434: 05/10/12: Simulink to hdl conversion
    90511: 05/10/15: Implementing five stage pipeline
    90513: 05/10/15: Re: What is a "full custom" design?
    90579: 05/10/17: Re: What is a "full custom" design?
    90804: 05/10/21: Re: Implementing five stage pipeline
    90831: 05/10/21: Re: Implementing five stage pipeline
    91634: 05/11/10: Re: Forcing carry-ripple adder ?
    91638: 05/11/10: Re: Internal signal to drive clock resources
    96650: 06/02/08: How to gnerate VCD file with hex outputs.
    97177: 06/02/17: Re: How to gnerate VCD file with hex outputs.
    97188: 06/02/18: Xilinx development board
    97262: 06/02/20: Re: Xilinx development board
    97807: 06/02/27: Observed a bug in the Model sim V 6.0a
    98200: 06/03/06: Internal pull down on the FPGA.....
    98267: 06/03/07: how to implement a good register decoding logic
    98580: 06/03/13: Doubt on the xilinx Viretex E user guide
    98581: 06/03/13: Re: Question about multi write ports RAM in FPGA?
    98700: 06/03/14: Re: Doubt on the xilinx Viretex E user guide
    98713: 06/03/15: Re: Question about multi write ports RAM in FPGA?
    99769: 06/03/28: Re: combinatorial always blocks + for-loops in XST
    100267: 06/04/05: Re: initializing arrays with Verilog and XST
    100526: 06/04/10: To use adder and multiplier of DSP48 in V4
    100534: 06/04/11: simulation of DCM blocks
    100535: 06/04/11: Re: simulation of DCM blocks
    100603: 06/04/12: Re: To use adder and multiplier of DSP48 in V4
    100718: 06/04/17: How to apply timing constrains for large bus
    100726: 06/04/17: Re: How to apply timing constrains for large bus
    100765: 06/04/17: Re: How to apply timing constrains for large bus
    100889: 06/04/20: Synthesizer is creating unwanted global resources
    100909: 06/04/20: Re: Synthesizer is creating unwanted global resources
    100914: 06/04/20: Re: Synthesizer is creating unwanted global resources
    100958: 06/04/21: Why Edge is required to read from Block RAM of V4
    100996: 06/04/23: Re: Why Edge is required to read from Block RAM of V4
    100997: 06/04/23: Re: Why Edge is required to read from Block RAM of V4
    100998: 06/04/23: Re: Synthesizer is creating unwanted global resources
    101003: 06/04/24: Re: Synthesizer is creating unwanted global resources
    101123: 06/04/25: Re: Synthesizer is creating unwanted global resources
    101208: 06/04/27: Synplify is not translating xilinx template for block ram
    101239: 06/04/27: Re: Synplify is not translating xilinx template for block ram
    101279: 06/04/28: Re: Synplify is not translating xilinx template for block ram
    102059: 06/05/09: Routing problem in PAR.
    102062: 06/05/10: Re: Routing problem in PAR.
    103389: 06/06/01: Problem with Mig1.5 when used to generate ddr sdram controller
    103447: 06/06/02: Simulating post par simulation model
    103450: 06/06/02: Re: Simulating post par simulation model
    103451: 06/06/02: Re: Simulating post par simulation model
    103454: 06/06/02: Re: Simulating post par simulation model
    103624: 06/06/06: Re: Simulating post par simulation model
    103688: 06/06/08: Re: Block Ram vs Distributed Ram
    103990: 06/06/16: Doubts on IBUFGDP
    105577: 06/07/26: Re: How to phase align a 10MHz clock using V4LX60 DCM
    108919: 06/09/19: Re: resets on synplicity inferred RAMs
    108928: 06/09/19: Re: resets on synplicity inferred RAMs
    108929: 06/09/19: Buffering the critical path.
    108933: 06/09/19: Re: how can I decrease the time cost when synthesis and implement
    108934: 06/09/19: Re: MIG1.6 as DDR2 controller using Spartan3
    108961: 06/09/19: Re: Buffering the critical path.
    108962: 06/09/19: Re: Performance Appraisals
    108967: 06/09/19: Re: xilinx or altera?
    108995: 06/09/19: Re: Buffering the critical path.
    109009: 06/09/19: Re: xilinx or altera?
    109032: 06/09/20: Re: Buffering the critical path.
    115291: 07/02/05: Xilinx Virtex5 board
    117113: 07/03/23: Flash memmory model
    117366: 07/03/29: Re: Flash memmory model
    118179: 07/04/19: Re: dual port memory from single port RAM.
    119477: 07/05/21: Re: Timing not met but working on board
    119488: 07/05/21: Re: Timing not met but working on board
    119619: 07/05/23: Re: How the synthesizer acutally works.
    119636: 07/05/24: Re: How the synthesizer acutally works.
    119654: 07/05/24: Re: How the synthesizer acutally works.
    119715: 07/05/24: Re: How the synthesizer acutally works.
    120225: 07/06/03: Re: Some doubts in the FPGA design flow in the ISE
    121052: 07/06/24: Re: Substitute for FORK / JOIN?
    121474: 07/07/05: Re: Simulation problem
    121475: 07/07/05: Doubt in Asynchronus Circuit design
    121497: 07/07/05: Re: Doubt in Asynchronus Circuit design
    121500: 07/07/05: Re: Doubt in Asynchronus Circuit design
    121508: 07/07/06: Re: Doubt in Asynchronus Circuit design
    121517: 07/07/06: Re: New with FGPAs
    121565: 07/07/08: Re: Doubt in Asynchronus Circuit design
    135634: 08/10/10: Can i ask some DFT questions
    135645: 08/10/10: Re: Can i ask some DFT questions
    135655: 08/10/11: Re: Can i ask some DFT questions
<vssumesh@gmail.com>:
    115356: 07/02/08: Re: Xilinx Virtex5 board
<vsundaram@my-deja.com>:
    22391: 00/05/08: Re: Beginner's Guide
    22620: 00/05/14: Re: Altera Schematic
    22621: 00/05/14: Re: Do you know xilinx FPGAs well?
    22622: 00/05/14: Re: HELP - what to choose?
vsurducan@gmail.com:
    123469: 07/08/28: Re: PCB Layers
    123470: 07/08/28: Re: PCB Layers
    123492: 07/08/29: Re: Problems with PLB_DDR2 core and soft reset
    123493: 07/08/29: Re: PCB Layers
    123526: 07/08/29: PCIe question
vt2001cpe:
    107108: 06/08/24: RocketIO over cable
    107120: 06/08/24: Re: RocketIO over cable
    107235: 06/08/25: Re: RocketIO over cable
    107447: 06/08/28: Re: RocketIO over cable
    107610: 06/08/30: Aurora implementation
    121481: 07/07/05: Multiple Core generator MAC FIR Filter 5.1 Cores
    121492: 07/07/05: Re: Multiple Core generator MAC FIR Filter 5.1 Cores
    121530: 07/07/06: Re: Multiple Core generator MAC FIR Filter 5.1 Cores
    121554: 07/07/08: Re: Multiple Core generator MAC FIR Filter 5.1 Cores
    123451: 07/08/28: Re: PCB Layers
    129993: 08/03/12: Xilinx Pipelined Divider for V5?
<vt313@comsys.ntu-kpi.kiev.ua>:
    30181: 01/03/27: Re: frequency measurement?
    36209: 01/11/02: Re: Implementing Filter
    38725: 02/01/23: Re: Internal tri state buffer..
    38760: 02/01/24: Re: Internal tri state buffer..
    39357: 02/02/07: Re: Pseudorandom Bitstream
    39372: 02/02/07: Re: Pseudorandom Bitstream
    41522: 02/04/01: Re: Filter design problem
    52253: 03/02/05: Re: low pass FIR filter in FPGA
    54185: 03/04/04: Re: FFT 256pt on Spartan
VTCMich:
    5451: 97/02/17: Moving Sale
<vtxsupport@hotmail.com>:
    153351: 12/02/05: Free GUI top level integration tool for Verilog and VHDL
    153492: 12/03/12: Re: Free GUI top level integration tool for Verilog and VHDL
    153515: 12/03/20: Re: Free GUI top level integration tool for Verilog and VHDL
vu3rdd:
    123125: 07/08/16: Routing JTAG pins thru FPGA
    123145: 07/08/17: Re: Routing JTAG pins thru FPGA
vu_5421:
    109830: 06/10/05: Spartan 3 Starter Kit I/O ports
    109903: 06/10/07: Re: Spartan 3 Starter Kit I/O ports
    109908: 06/10/07: Re: Spartan 3 Starter Kit I/O ports
    109935: 06/10/08: Re: Spartan 3 Starter Kit I/O ports
    114690: 07/01/22: low speed USB interface for FPGAs
    115283: 07/02/05: Re: low speed USB interface for FPGAs
    115816: 07/02/21: nets vs. pads ; constraints question
Vulcain_75:
    49249: 02/11/06: Altera ACAP?
vvcd2@ath.forthnet.gr:
<vve@xilinx.com>:
    72553: 04/08/24: Re: Xilinx in Linux
    72554: 04/08/24: Re: [Synthesis][VHDL] HowTo prevent Removal of Registers ...
    72556: 04/08/24: Re: Edk BMM file problem in ISE
    72557: 04/08/24: Re: Xilinx Spartan3 DCM Procedure
<vwmrlu@gw1qa7t.com>:
<vysakhpillai@gmail.com>:
    129974: 08/03/11: Re: Sun open SPARC micro architecture document
vytla:
    79494: 05/02/20: beginner: running linux on xilinx ml310
    79573: 05/02/21: Re: beginner: running linux on xilinx ml310
Vyyk Draygo:
<vze24h5m@verizon.net>:
    122053: 07/07/18: Re: Xilinx XC9536 current draw ?
<vze2k9kn@verizon.net>:
    31664: 01/06/02: Re: Help requested in choosing a career


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