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Hi, A PCB has been designed to faciliate communications between Virtex4 FPGA and an infiniband(ib) chip. The v4 fpga have a powerpc and the ib chip contains a pcix module. Now i have to design a pcix module for the fpga. The purpose of the design is to ensure that the ib chip can be controlled by powerpc. I know the mater and slave function blocks in the pcix moule for fpga are needed, but i don't know what other function blocks should be implemented so that the ib chip can be correctly configured and mannaged. I hope someone can help me, any advice will be greatly appreciated. thanks :-) perryArticle: 118226
Thanks. Very clearly explained! In article <f08n7t$kk61@cnn.xsj.xilinx.com>, Austin Lesea <austin@xilinx.com> wrote: > Well, > > Specifying the IO standard pretty much identifies to the bitgen part of > the program which bits to turn on (and off) to get that drive strength > for that standard. > > Suppose you have 2.5 V Vcco, and you call for a 1.5 V 4 mA CMOS driver > -- running at 2.5 volts it will be much stronger than the 4 mA as the > bits will have enabled most of the driver "legs" to get 4 mA min at 1.5V > Vcco. It would require far fewer "legs" enabled to get 2.5 V 4 mA. > > So, the IO will function at a different voltage, it just won't meet the > data sheet specifications for that new voltage. Its behavior will be > stronger if the Vcco is larger than it thought, or weaker if smaller > than it was programmed for. Other specifications will also be affected: > delay and input impedance if differentially terminated internally. > > AustinArticle: 118227
Hi new version of actel coreconsole includes CoreABC - a tiny Fpga SoftCore with APB interface for peripherals, but I have trouble creating a SoC, i wonder if any one has worked it out ? hm.. eh, I tried to connect Fusion on chip used Flash blocks to ABC, maybe this is not supported and was the reason for problem. Still if anyone has experience with ABC, would be nice to hear:) AnttiArticle: 118228
On Apr 19, 6:46 pm, "B. Joshua Rosen" <bjro...@polybusPleaseDontSpamMe.com> wrote: > On Wed, 18 Apr 2007 21:11:50 -0700, nezhate wrote: > > On Apr 18, 9:40 pm, Andy Peters <goo...@latke.net> wrote: > >> On Apr 18, 4:24 am, nezhate <mazouz.nezh...@gmail.com> wrote: > > >> > Hi all, > >> > I'm using Ise 9.1.03i. when I try to print a code written in Ise text > >> > editor, I get this error: > >> > "Print fails because the default printer has not been selected", and > >> > when the design summary is opened I can see the window "steup > >> > printer" and my default printer is automatically selected. How to > >> > configure printer for ise text editor? thanks. > > >> Wow...somebody actually uses the ISE text editor? > > >> I thought everyone just used emacs. > > >> -a > > not everyone works under Linux. > > At home I have Linux and use emacs but in univ. they have windows and > > use Ise text editor .... what to do? > > Xemacs is available for Windows, you don't have to suffer with the ISE > editor even if you have to suffer with Windows. Xemacs is available stand > alone or as part of Cygwin. Thanks .... I will try to use xemacs.Article: 118229
Finally first picture of Darnaw1 our PGA style FPGA board is here here http://www.enterpoint.co.uk/moelbryn/darnaw1.html. More information on pricing and spec in the next couple of days will appear on the website. Those with eagle eyes can work it out the spec from the picture. First shipments will have 16Mbit SPI flash to allow programming of the FPGA but also to act as a code store for processors like MicroBlaze implemented within the FPGA. There is also SDRAM on board. Small numbers of this product will be available to ship next week. We would be interested to have feedback on this product and what you like, and what we could improve on this product and the related series of products we have planned. John Adair Enterpoint Ltd.Article: 118230
"John Adair" <g1@enterpoint.co.uk> wrote in message news:1177070132.270147.235340@b75g2000hsg.googlegroups.com... > Finally first picture of Darnaw1 our PGA style FPGA board is here here > http://www.enterpoint.co.uk/moelbryn/darnaw1.html. More information on > pricing and spec in the next couple of days will appear on the > website. Those with eagle eyes can work it out the spec from the > picture. > > We would be interested to have feedback on this product and what you > like, and what we could improve on this product and the related series > of products we have planned. > > John Adair > Hi John, There was some bloke on here a while back asking about this sort of product, I pointed him at your DIP design. Craigsomething? So, you reckon it'll work in a wire-wrap system!? I wish you luck supporting that SI hellhole. :-) Although, can you buy wirewrap boards with ground planes now? Also, the capacitor packs you're using, are they interdigitated ones? I'm interested on what other folks are using for bypass networks these days. It'd be nice to find someone else who's had experience of the X2Y caps that were discussed here a few weeks back. Finally, I hope you ripped off Xilinx's sparse chevron thingy for your pinout. It'll be a big help for your SI. Cheers, Syms. p.s. 'ripped off' <-> 'were inspired by' ;-)Article: 118231
Hi All, I have problem with clock signal in FGPA XC95288XL144. I have 3,3V signal on the output but I want get 5V signal. I say in addition that I use chip with 3.3V power supply. Should I use pull up or different operation? What do you do with clock signal in FPGA? Thank youArticle: 118232
"maroni" <maroni@interia.pl> wrote in message news:f0ae4k$qco$23@atlantis.news.tpi.pl... > Hi All, > > I have problem with clock signal in FGPA XC95288XL144. I have 3,3V signal > on the output but I want get 5V signal. I say in addition that I use chip > with 3.3V power supply. Should I use pull up or different operation? What > do you do with clock signal in FPGA? > > Thank you > Hi, If you _really_ need 5V, then buffer it. http://www.fairchildsemi.com/collateral/Tinylogiclinecard.pdf HTH, Syms.Article: 118233
Symon I don't know about wirewrap boards with ground availability but one of our thoughts with this product was the user that likes 2-4 layer low technology pcb boards they can assemble themselves. With this product we allow them to stay with the board technology they like but they can have a high performance bga based FPGA in their system. I have seen wirewrap sockets I believe from Mill-Max or Precidip if someone wants to do that. The capacitors are just conventional arrays as used throughout our product range. We have gone to the effort of making the board itself resiliant in terms of SSI but there is a limit given the target market and where it is likely to be used. If someone is after very high performance I would always integrate the FPGA into a complete board. We do often take one of our standard products as a starting point and produce a customer specific design from it. The Craignell modules are sort of complimentary to the Darnaw range but are much smaller in I/O and differ in other ways. These are also now shipping. Darnaw1 can be a very serious processing capability with it's I/O resources and onboard SDRAM and FLASH. We may uprate the SDRAM to DDR2 in issue2 but that is still to be decided. For those familiar with our OVERCOAT series it is also possible to use this technique to stack DARNAW1's if you have a reason to do so. I am hoping that a lot of products we have planned will make it to market this year given our slow output of our own product range last year. The engineering team has now grown very substantially and some resource is now going back to our own product developments. I think some of the things we are doing right now might even surprise a few people but I will leave the detail as something of tease and a surprise to come. John Adair Enterpoint Ltd. On 20 Apr, 13:43, "Symon" <symon_bre...@hotmail.com> wrote: > "John Adair" <g...@enterpoint.co.uk> wrote in message > > news:1177070132.270147.235340@b75g2000hsg.googlegroups.com...> Finally first picture of Darnaw1 our PGA style FPGA board is here here > >http://www.enterpoint.co.uk/moelbryn/darnaw1.html. More information on > > pricing and spec in the next couple of days will appear on the > > website. Those with eagle eyes can work it out the spec from the > > picture. > > > We would be interested to have feedback on this product and what you > > like, and what we could improve on this product and the related series > > of products we have planned. > > > John Adair > > Hi John, > There was some bloke on here a while back asking about this sort of product, > I pointed him at your DIP design. Craigsomething? > So, you reckon it'll work in a wire-wrap system!? I wish you luck supporting > that SI hellhole. :-) Although, can you buy wirewrap boards with ground > planes now? > Also, the capacitor packs you're using, are they interdigitated ones? I'm > interested on what other folks are using for bypass networks these days. > It'd be nice to find someone else who's had experience of the X2Y caps that > were discussed here a few weeks back. > Finally, I hope you ripped off Xilinx's sparse chevron thingy for your > pinout. It'll be a big help for your SI. > Cheers, Syms. > p.s. 'ripped off' <-> 'were inspired by' ;-)Article: 118234
On Apr 19, 5:51 pm, Austin Lesea <aus...@xilinx.com> wrote: > I do not mind one bit that he uses an Altera board to learn about FPGAs: > it will be his first job that will determine who he will get to use, it > will probably not be his choice! > > So, the more that know how to use FPGA's, the better. > > I only offer up the Digilent board because there have been tens of > thousands sold to students. The resulting ecosystem has some benefits. I think there's something special that happens when a serious get-your- feet-wet but be able to "really do something" version of a technology is available for general purchase for ~$100.Article: 118235
Hi I am experimenting on module-based partial reconfiguration for Virtex-4 (LX25-ff668). Intended functionality is that After full bitstream download on the board, LED blinks. After partial bitstream download, LED blinks with different frequency. Intended chip floorplan is that Left half is is 'reconfigurable' region and right half is 'fixed' region. I intend to generate partial bitstream for the "left half". I made 1-bit slice-based bus macro for both of Virtex-2 Pro and Virtex-4. When I tried module-based flow (xapp290) for Virtex-2 Pro on ISE 8.2.03, it works on the board, for both of full bitstream (with size of 1.4MB) and partial bitstream (with size of 50KB). I tried on Virtex-4 with ISE 8.2.03. Module based tool flow does not create any error. I checked two NCD files for partial / full bitstream on the FPGA editor. Everything seems okay. When I download full bitstream (with size of 955 KB), it works on the board. It means that the bus macro functions correctly as a wire. Problem is that -------------------- Partial bitstream size is same as full bitstream size (with 955 KB) Also when I download partial bitstream, it does not work on the board. It implies that the chip is NOT partitioned as described in UCF file and the generated partial bitstream is not PARTIAL --: -------------------- I wonder if we can generate partial bitstream using xapp290 flow for Virtex-4 ? Does anyone have these experiences? Thank you for any comment.Article: 118236
Hi all, I am developing my first FPGA LUT-Based design.Trying to make a FPGA with MRAM based design. There is anyone here who is an expert to the FPGA full custum design?Article: 118237
Hi, Is there an Altera application to count the number of equivalent gates for Logic Elements, Memory, DSP blocks, PLL etc... ? Thanks... I don't find this information..Article: 118238
Austin Lesea wrote: > http://www.xilinx.com/products/boards/files/s3e_starter_schematic.pdf > > Is the previous revision of the schematic, with page 3 shown. Actually, that schematic is newer and the USB interface page is now not just blank, it's completely gone. Pg 3 now shows something different. > If someone really wants to look at a USB to FPGA interface, not only is > there the previous revision of the board schematic, but thousands of > them out there on the web. True. Some enterprising individual has reverse-engineered the USB interface and re-written the Cypress USB firmware, as well as the CPLD code to provide an open-source USB download capability. It's not as fast as the code that ships with the S3Esk though. EricArticle: 118239
Jhoberg <jrquevedor@gmail.com> posted on 19 Apr 2007 21:39:00 -0700 in news:comp.arch.fpga : "This it is a message of Richard Staman creator of free softeare fundation and GNU on an idea to construct free hardware in FPGAs. http://lists.duskglow.com/open-graphics/2007-January/008663.html http://en.wikipedia.org/wiki/Richard_Stallman " On 2000 March 8th Richard M. Stallman has made a presentation in Trinity College Dublin. Near the end, a member of the audience has asked a question re the GPL and hardware. Richard M. Stallman has responded appreciating no relevance of freedom to hardware. Perhaps he had not been aware of code written in hardware description languages which had already been licensed according to the second version of the GPL by that time, and perhaps he has revised his opinion. Regards, Colin Paul GlosterArticle: 118240
Hi everyone, I've been reading previous posts regarding ethernet MAC layers for FPGA's but can't seem to solve my problem. I'm going to be sending a receiving UDP packets from my PC to a PHY chip and then to my FPGA with a mac layer that I wrote in VHDL. It is a point to point connection and I can successfully receive packets when I set a static IP for the PC and broadcast. This project will always be point to point, is it necessary to give my FPGA board an IP address? I'm am worried that even if this is a point to point connection certain applications may still try to access the same UDP port and corrupt the transmissions. How would I go about handshaking with the PC to let it know that there is a valid IP address on the other end of the connection? Currently I am not even checking IP and it will work when I broadcast using a UDP tester ( http://www.fpga4fun.com/files/UDP.zip ) and checking for the port only, but when I set a specific IP it won't go through...this may be more of a networking question but if anyone can help I would appreciate it. Thanks! -MattArticle: 118241
Hey Guys/Gals, I'm only fairly new to FPGA's, I've used the xilinx xc2s400e, but this was on a digilent board and the whole environment was set up for me. I'm doing my final year thesis for engineering and am highly interested in using an FPGA as the IC's I am after, well, dont exist. The main purpose of the FPGA is to replace a 32input or gate (which is made out of 4-8input or gates and 1x4 input), 32 bit mux (made out of 2x16 bit muxes and 1x2bit mux) and 32 d-latches (each latch also has to have logic on its input - ie. an extremely simple finite state machine (2 states)) I am considering using the xilinx xc2s50e... however I do have a couple of concerns... Do I actually have to 'clock' the chip? or can I have it run asynchronously like most logic gates?? I do have a few other questions, but thats the main one. Cheers MattArticle: 118242
You don't need to clock the FPGA but be aware that FPGA logic is very fast and ripple delays can cause glitches very easily. This is a much greater issue that in descrete logic chips. A clock can help to stabilse this albeit with some time penalty. John Adair Enterpoint Ltd. On 20 Apr, 16:02, "Matt Sorrensen" <mafr...@optusnet.com.au> wrote: > Hey Guys/Gals, > > I'm only fairly new to FPGA's, I've used the xilinx xc2s400e, but this was > on a digilent board and the whole environment was set up for me. > > I'm doing my final year thesis for engineering and am highly interested in > using an FPGA as the IC's I am after, well, dont exist. > > The main purpose of the FPGA is to replace a 32input or gate (which is made > out of 4-8input or gates and 1x4 input), 32 bit mux (made out of 2x16 bit > muxes and 1x2bit mux) and 32 d-latches (each latch also has to have logic > on its input - ie. an extremely simple finite state machine (2 states)) > > I am considering using the xilinx xc2s50e... however I do have a couple of > concerns... > > Do I actually have to 'clock' the chip? or can I have it run asynchronously > like most logic gates?? > > I do have a few other questions, but thats the main one. > > Cheers > MattArticle: 118243
"Matt Sorrensen" <mafroew@optusnet.com.au> wrote in message news:132hkt62dc1a9a9@corp.supernews.com... > Hey Guys/Gals, > > I'm only fairly new to FPGA's, Indeed you are, or you'd know there're not many 'Gals' on this newsgroup, more's the pity... :-) > > I've used the xilinx xc2s400e, but this was on a digilent board and the > whole environment was set up for me. > I'm doing my final year thesis for engineering and am highly interested in > using an FPGA as the IC's I am after, well, dont exist. > The main purpose of the FPGA is to replace a 32input or gate (which is > made out of 4-8input or gates and 1x4 input), 32 bit mux (made out of > 2x16 bit muxes and 1x2bit mux) and 32 d-latches (each latch also has to > have logic on its input - ie. an extremely simple finite state machine (2 > states)) > I am considering using the xilinx xc2s50e... however I do have a couple of > concerns... > Do I actually have to 'clock' the chip? or can I have it run > asynchronously like most logic gates?? > I do have a few other questions, but thats the main one. > Cheers > Matt Yep, async will work fine. I guess you have some input which 'clocks' the latches? Of course, you're almost certain to want to do something clever later on which needs a clock. I'd make provision for a oscillator module just in case. Use something > 24MHz so there are no restrictions on using the on-chip digital clock managers. Good luck, Syms.Article: 118244
Colin Paul Gloster <Colin_Paul_Gloster@ACM.org> writes: > Perhaps he had not been aware of code written in hardware > description languages which had The key word here is "code". IMHO RMS's point is that the types of freedoms that the GPL provides (use, change, share) do not apply to physical objects, because the cost of copying physical objects is non-trivial. So, you can GPL the code *in* an FPGA (software), but you can't GPL the FPGA itself (hardware). How could you copy a chip and share it with your friends? "Hey Colin, could you email me a Spartan 3?"Article: 118245
On 20 Apr., 17:17, DJ Delorie <d...@delorie.com> wrote: > Colin Paul Gloster <Colin_Paul_Glos...@ACM.org> writes: > > > Perhaps he had not been aware of code written in hardware > > description languages which had > > The key word here is "code". IMHO RMS's point is that the types of > freedoms that the GPL provides (use, change, share) do not apply to > physical objects, because the cost of copying physical objects is > non-trivial. So, you can GPL the code *in* an FPGA (software), but > you can't GPL the FPGA itself (hardware). How could you copy a chip > and share it with your friends? "Hey Colin, could you email me a > Spartan 3?" well FPGA's DO MAKE it possible to send HARDWARE per email. the only assumption is that the receiving party has some equipment with an FPGA inside. this maybe the LCD TV as example or some other equipment. so by loading the new bit file to the FPGA in his LCD TV the FPGA will transform to some hardware that did not previously exist at the premises of the receiver of the "hardware per email"... so the issue about licensing is not trivial :) AnttiArticle: 118246
"Antti" <Antti.Lukats@xilant.com> wrote in message news:1177083477.214936.26030@n76g2000hsh.googlegroups.com... > > well FPGA's DO MAKE it possible to send HARDWARE per email. > > > Antti > To be pedantic, I disagree. You're not emailing hardware, you're emailing a way of configuring hardware that someone has. Same as emailed software configures your PC. Cheers, Syms.Article: 118247
On 20 Apr., 16:09, vhdldesigner.patr...@gmail.com wrote: > Hi, > > Is there an Altera application to count the number of equivalent gates > for Logic Elements, Memory, DSP blocks, PLL etc... ? > > Thanks... > > I don't find this information.. its not available - it's called: "marketing strategy"... AnttiArticle: 118248
On 20 Apr., 16:01, Midou <mourad.elbar...@gmail.com> wrote: > Hi all, I am developing my first FPGA LUT-Based design.Trying to make > a FPGA with MRAM based design. > There is anyone here who is an expert to the FPGA full custum design? the answer to your question is: YESArticle: 118249
Thank you very much for your reply. I will read the document and have a try.
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Compare FPGA features and resources
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