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I wrote pci core and implemented it on a virtex 4 fpga, the pci core served as a slave. Now the config space can be read by host bridge correctly, but there are still some questions confusing me. I wish someone here could give me advices, thanks 1. This pci core doesn't support burst transaction. so signal TRDY was designed to be valid for one cycle and then set to 1. the problem is in a read transaction, the master device didn't get any data during this cycle though the IRDY is low. why? however, if the TRDY delayed for one cycle, that is it was valid for two cycles, the master can read data correctly. 2. In a write configuration transaction(eg: writing "FFFFFFFF" into memory base address DWORDs), there should be some 0s in the Byte Enable signal. but the fact was BE=1111, no byte was written. why the host gave such a BE? thanks allArticle: 115326
On 7 Feb, 12:32, "Pablo" <pbantu...@gmail.com> wrote: > Does anyone Know how can I compile uClinux-dist for Spartan 3E. I have > done the next: > > download uClinux-dist > download uClinux-2.4.x > cd uClinux-dist > ln -s ../uClinux-2.4.x linux-2.4.x > copy auto-config.in to arch/microblaze/platform.... > PATH=$PATH:/usr/local/microblaze-elf-tools > > make clean (an error occurr with images/CVS, I have to delete > manually) > make menuconfig > > I can pass this. I have an error in arch/microblaze/config.in > > Does I need to do something else???? Yes try make distclean... or somethink like that. if makedistclean doesn't work have a look in the makefile and look for somethink like distclean. What you should do is to say... "look I changed something in the SW and also in the HW because my config.in file is different" FrancescoArticle: 115327
On 7 Feb., 13:49, "Perry" <lipeng....@gmail.com> wrote: > I wrote pci core and implemented it on a virtex 4 fpga, the pci core > served as a slave. Now the config space can be read by host bridge > correctly, but there are still some questions confusing me. I wish > someone here could give me advices, thanks > > 1. This pci core doesn't support burst transaction. so signal TRDY was > designed to be valid for one cycle and then set to 1. the problem > is in a read transaction, the master device didn't get any data during > this cycle though the IRDY is low. why? Did it get no data or did it get the wrong data (eg. 0)? > however, if the TRDY delayed > for one cycle, that is it was valid for two cycles, the master can > read data correctly. I guess you output your data one clock cycle late. Or you did not tell the master to finish the cycle. If the master wants to burst and the slave does not agree it must do a target abort. (stop='1' IIRC) Kolja SulimmaArticle: 115328
Depending on what is happening you may want to assert a terminate with data (STOP + TRDY) if the cycles is trying to burst. On the byte enables you will see many apparently strange things happening on PCI and you need to follow the entire cycle and decode fully what it means. Shortcuts in decode will lead to problems invariably. John Adair Enterpoint Ltd. On 7 Feb, 12:49, "Perry" <lipeng....@gmail.com> wrote: > I wrote pci core and implemented it on a virtex 4 fpga, the pci core > served as a slave. Now the config space can be read by host bridge > correctly, but there are still some questions confusing me. I wish > someone here could give me advices, thanks > > 1. This pci core doesn't support burst transaction. so signal TRDY was > designed to be valid for one cycle and then set to 1. the problem > is in a read transaction, the master device didn't get any data during > this cycle though the IRDY is low. why? however, if the TRDY delayed > for one cycle, that is it was valid for two cycles, the master can > read data correctly. > > 2. In a write configuration transaction(eg: writing "FFFFFFFF" into > memory base address DWORDs), there should be some 0s in the Byte > Enable signal. but the fact was BE=1111, no byte was written. why the > host gave such a BE? > > thanks allArticle: 115329
Hi, All
I want to use UART to do the transmission between Matlab and FPGA
board. I found one from others. I made a simple test to realize
transmit data to uart and transmit back to matlab. I will write some
parts codes of my test here to make sure you know what I am doing.
entity uart-top is
port(
sys_clock : in std_logic;
PB_LEFT : in std_logic;
RS232_RTS_IN : IN std_logic;
RS232_RX_DATA : IN std_logic;
RS232_CTS_OUT : OUT std_logic;
RS232_TX_DATA : OUT std_logic
);
end uart-top;
COMPONENT uart115200
PORT(
SYSCLK : IN std_logic;
RS232_RTS_IN : IN std_logic;
RS232_RX_DATA : IN std_logic;
RESET : IN std_logic;
READ : IN std_logic;
WRITE : IN std_logic;
DATAOUT : IN std_logic_vector(7 downto 0);
RS232_CTS_OUT : OUT std_logic;
RS232_TX_DATA : OUT std_logic;
DATAIN : OUT std_logic_vector(7 downto 0);
RXRDY : OUT std_logic;
TXRDY : OUT std_logic;
parityerr : OUT std_logic;
framingerr : OUT std_logic
);
END COMPONENT;
dataout <=3D datain;
write <=3D read;
test_inst: process(sysclk)
variable rxrdy1 :=3D std_logic:=3D '0';
begin
if reset =3D '1' then
read <=3D '0';
txrdy1 :=3D '0';
elsif sysclk'event and sysclk =3D'1' then
if rxrdy1 =3D'0' and rxrdy =3D'1' then
read <=3D '1';
end if;
if rxrdy1 =3D'1' and rxrdy =3D'0' then
read <=3D '0';
end if;
rxrdy1 :=3D rxrdy;
end if;
end process;
It works well. Data are transmitted from matlab to fpga, and send
back correctly.
---------------------------------------------------------------------------=
----------------------------
Next, I want to add an Array in this test
First=EF=BC=8CData are witten into uart and saved in a tempary Array. When =
the
counter=3DNumByteData, Data are sent back to Matlab.
I don't know how to control the write signal and read signal here.
I still use the change of 'rxrdy' to control the Read signal like I
use to do it. But this time I did not connect READ with WRITE. I want
to to use index of Array to trigger WRITE signal. So I do this
est_inst: process(wrramclk)
variable rxrdy1: std_logic:=3D'0';
begin
if reset =3D '1' then
readb <=3D '0';
rxrdy1 :=3D '0';
elsif wrramclk'event and wrramclk =3D'1' then
if rxrdy1 =3D'0' and rxrdy =3D'1' then
readb <=3D '1';
end if;
if rxrdy1 =3D'1' and rxrdy =3D'0' then
readb <=3D '0';
end if;
rxrdy1 :=3D rxrdy;
end if;
end process;
countRX_inst: process(WRRAMCLK,RESET)
VARIABLE CNT : STD_LOGIC_VECTOR (4 DOWNTO 0) :=3D(others=3D>'0');
VARIABLE rd1,rd2,rd3,rd4: std_logic:=3D'0';
VARIABLE TMP: STD_LOGIC :=3D'0
begin
if (RESET =3D '1') then
CNT :=3D (OTHERS =3D>'0');
index1 <=3D0;
rd1 :=3D '0';
rd2 :=3D '0';
rd3 :=3D '0'
elsif WRRAMCLK'event and WRRAMCLK =3D '1' then
if rd4 =3D '0' and rd3 =3D '1' and rd2 =3D '1' and rd1
=3D'1' then --detect the rising edge of read
tmpH(index1)<=3Ddatain; --read data from input-register in uart to
tempary_array input register CNT :=3D CNT +
"00001"; index1 <=3D CONV_INTEGER(UNSIGNED(CNT));
writeb<=3D'0'; IF index1=3D15 THEN
index1<=3D0; writeb <=3D '1';
end if;
else index1
<=3D0; CNT :=3D (OTHERS=3D> '0');
end if; rd4 :=3D rd3;
rd3 :=3D rd2;
rd2 :=3D rd1;
rd1 :=3D readb; --delay "read" three cycles
end if; ;
END PROCESS;
--------------------
I did not write out the whole codes. But these code above have already
shown what I am thinking.
It cannot work. Does anybody tell me what the problem of my design?
Thank you.
Zhi
Article: 115330I'm having problems with Synplify and the Actel macros. As part of a project I'm using a FIFO generated by Libero's ACTgen to save processed data that I also output through the pins of the FPGA (an Actel APA300), for computer readback. ACTgen produces a VHDL file which instantiates the RAM/FIFO blocks (it creates two or more FIFO256x9SST, depending on FIFO depth) and provides an interface to make them act as one bigger FIFO, which I then instantiate in my code. I synthesize it with Synplify (both normal and Pro have the same problem) 8.0A, which is specific for Actel, and then Place&Route with Actel Designer. The timing analyzer claims to meet the desired frequency of 40MHz. The program produces a STAPL file which I use to program the FPGA. When I test it, however, the FIFO malfunctions. The data is being processed correctly (because it comes out of the pins OK, I can check that with an oscilloscope) but when I read it back from the FIFO, some of the bits change. I know the readback interface works fine as well, and I have tried on two different FPGAs of the same model, so it must be the FIFO. When I use a very small FIFO, of depth 8 or so, everything works fine, but I need a longer depth (256, 512, or so). Everything points to a timing problem caused by the FIFO logic, since a change in only the FIFO depth causes it to work or not. When I synthesize it with Synplify, it provides the following warning: @W: MT253 :"[mypath]\hdl\fifo_tc.vhd":234:3:234:4|Blackbox FIFO256x9SST is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) I searched, asked my friends, and investigated, and I found out that whenever an Actel macro is used, it gets mapped to a blackbox which, if there is timing information for it, Synplify uses to optimize paths. I also found that, when using my own custom blackboxes, I can use constraints to specify the propagation delay etc so that the synthesis uses it. I can now create a constraints file with the delays associated to the FIFO and the program will use them. My problem, of course, is that I don't know whan values to use. I assume (perhaps wrongly) that Actel provides them in one of the libraries from either Libero or Synplify (they distribute the Actel edition of the program, so I assume they make the libraries) and I haven't found a way to include it. The other option is that they don't and I need to create the constraints file with the values which hopefully Actel provides (I don't know where I would get them, otherwise). Can anybody offer any hints as to what I need to do in order to provide Synplify with the timing information?Article: 115331
I have an application where I want to keep my 2.5V sdram alive while turning off the FPGA. My V4 fpga uses 3.3V, 2.5V, and 1.2V. I want to shut off the 1.2V and the 3.3V but the 2.5V would still be powered. Will this hurt the fpga? Thanks, ClarkArticle: 115332
Hi newsgroup, I am trying to write a VHDL wrapper for a Verilog IP core which includes a "params.v" file: `define DDR2_MODE `define ROW_WIDTH 13 `define COL_WIDTH 10 `define COL_WIDTH_EQ_10 TRUE ... These parameters are used to define the port widths etc. of the IP core. How can I take over the parameter file into my VHDL wrapper ? Do I have to generate a second VHDL parameter file ? Thank you for your opinion. Rgds AndreArticle: 115333
Is the Byte Blaster Cable and Signal Tap supported on Linux and more specifically on Fedora Core 5 or 6? All of my experience has been with Xilinx tools, this will be my first use of the Altera debug tools. Xilinx's ChipScope has only marginal Linux support. There is a kernel specific driver that only runs on the RHEL version of the kernel which is so old as to be useless on a laptop. I was wondering if Altera has the same sort of limitations or if their tools are kernel independent. Thanks,Article: 115334
cpope wrote: > I have an application where I want to keep my 2.5V sdram alive while turning > off the FPGA. My V4 fpga uses 3.3V, 2.5V, and 1.2V. I want to shut off the > 1.2V and the 3.3V but the 2.5V would still be powered. Will this hurt the > fpga? > > Thanks, > Clark > > Clark, No, it will not "hurt" the FPGA. But you will lose the configuration, and have to re-configure when power is re-applied. AustinArticle: 115335
On Feb 6, 12:45 am, dim...@gmail.com wrote: > Current version of xc3sprog in SVN incorporates all of the patches > submitted > so far. I pulled them in a couple of days ago, partially in response > to this > thread. Please submit your new patches - I will try to keep the > project > up to date. I've sent you my patches to your gmail address. Please let me know if you've received them. -- mmihaiArticle: 115336
Geronimo Stempovski wrote: > I just read an interesting paper about high-speed I/O's power dissipation. > Unfortunately there is an equation I don't quite understand. Maybe someone > is in the mood for discussing and explaining the correctness of the equation > to me. > The formula I am talking about is (1) in the paper [ > http://www.ee.ucla.edu/faculty/papers/yang-ckk_ieeeTransCircSystems2_nov2006.pdf ] > > For high-common mode signaling (which standard would that be, anyway? TTL? > CMOS? SSTL?) it is assumed > P = V*Vswing/Z0 = V*Vrx/Z0*H(f) > > For low-common mode signaling (LVDS? CML? LVPECL?) it states > P = Vswing^2/2*Z0 = Vrx^2/2*Z0*H(f)^2 > > What I don't understand is the factor 2 (2*Z0) in the calculation of the > low-common mode signaling. Furthermore I'm not sure if the H(f)^2 is > correct. > > Any help is highly appreciated! Thanks a lot in advance! That does seem mangled. When in doubt, check the dimensions of the answer ? Normally where frequency is used in power calcs, it is of the form of power dissipation capacitance : W = Fo * Cp * Vcc^2 -jgArticle: 115337
Jim Granville wrote: > Geronimo Stempovski wrote: > >> I just read an interesting paper about high-speed I/O's power >> dissipation. >> Unfortunately there is an equation I don't quite understand. Maybe >> someone is in the mood for discussing and explaining the correctness >> of the equation to me. >> The formula I am talking about is (1) in the paper [ >> http://www.ee.ucla.edu/faculty/papers/yang-ckk_ieeeTransCircSystems2_nov2006.pdf >> ] >> >> For high-common mode signaling (which standard would that be, anyway? >> TTL? CMOS? SSTL?) it is assumed >> P = V*Vswing/Z0 = V*Vrx/Z0*H(f) >> >> For low-common mode signaling (LVDS? CML? LVPECL?) it states >> P = Vswing^2/2*Z0 = Vrx^2/2*Z0*H(f)^2 >> >> What I don't understand is the factor 2 (2*Z0) in the calculation of >> the low-common mode signaling. Furthermore I'm not sure if the H(f)^2 >> is correct. >> >> Any help is highly appreciated! Thanks a lot in advance! > > > That does seem mangled. > When in doubt, check the dimensions of the answer ? > > Normally where frequency is used in power calcs, it is of the form > of power dissipation capacitance : W = Fo * Cp * Vcc^2 > > -jg > it looks like its analagous to an RMS calculation, but made on an unknown dataset of a particular (hardware) flavour. its a mere proof by blatant assertion, so it'd take a fair bit of digging or maths to figure out where it came from. ya gotta love professional comics. Cheers TerryArticle: 115338
On Feb 7, 8:45 am, General Schvantzkoph <schvantzk...@yahoo.com> wrote: > Is the Byte Blaster Cable and Signal Tap supported on Linux and more > specifically on Fedora Core 5 or 6? All of my experience has been with > Xilinx tools, this will be my first use of the Altera debug tools. > Xilinx's ChipScope has only marginal Linux support. There is a kernel > specific driver that only runs on the RHEL version of the kernel which is > so old as to be useless on a laptop. I was wondering if Altera has the > same sort of limitations or if their tools are kernel independent. > > Thanks, Yes, SignalTap is supported on Linux. With regard to ByteBlaster, it is supported on 32-bit Linux but not on 64-bit Linux. But, the 64-bit Linux does however support Ethernet Blaster.Article: 115339
On Wed, 07 Feb 2007 14:50:38 -0800, rekha.arun wrote: > On Feb 7, 8:45 am, General Schvantzkoph <schvantzk...@yahoo.com> > wrote: >> Is the Byte Blaster Cable and Signal Tap supported on Linux and more >> specifically on Fedora Core 5 or 6? All of my experience has been with >> Xilinx tools, this will be my first use of the Altera debug tools. >> Xilinx's ChipScope has only marginal Linux support. There is a kernel >> specific driver that only runs on the RHEL version of the kernel which is >> so old as to be useless on a laptop. I was wondering if Altera has the >> same sort of limitations or if their tools are kernel independent. >> >> Thanks, > > Yes, SignalTap is supported on Linux. With regard to ByteBlaster, it > is supported on 32-bit Linux but not on 64-bit Linux. But, the 64-bit > Linux does however support Ethernet Blaster. Are there any kernel issues?Article: 115340
Has anyone successfully configured the two PowerPCs inside XUP2VP (virtex2Pro) using EDK?...as I know there are no features in EDK to configure both the PowerPCs. Wondering is any other way of configuring both PowerPCs using EDK....Article: 115341
Hi Pablo, Pablo wrote: > download uClinux-dist > download uClinux-2.4.x > cd uClinux-dist > ln -s ../uClinux-2.4.x linux-2.4.x > copy auto-config.in to arch/microblaze/platform.... > PATH=$PATH:/usr/local/microblaze-elf-tools Instead of this, I recommend you start using PetaLinux: http://developer.petalogix.com We've bundled together the kernel and dist sources, tools, BSP generation and hardware reference designs into a single downloadable package. There is lots of documentation and scripts to ease the process of working with Embedded Linux on the MicroBlaze platform. I hope you find it useful. Regards, John > > make clean (an error occurr with images/CVS, I have to delete > manually) > make menuconfig > > I can pass this. I have an error in arch/microblaze/config.in > > Does I need to do something else???? >Article: 115342
On Feb 6, 6:30 am, "comp.arch.fpga" <ksuli...@googlemail.com> wrote: > But as most FPGA designs have no use for the amount of hardware > multipliers available in todays FPGAs, > x*x + y*y < r*r might actually be a lot simpler. > > Kolja Sulima yes, it's lot easier and works fine... Thank you all for all your answers. i am still working on Bresenham's algorithm, just for the sake of implementing circle in a another way. Thank you again.Article: 115343
On Feb 7, 6:51 am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > "EEngineer" <mari...@gmail.com> writes: > > Is there a way of generating VHDL code from Matlab code for DSP, more > > precisely image processing using wavelet transform? > > I want to implement a small 8X8 image processing layout that will use > > wavelet transform and it is not easy to come up with the VHDL code for > > that. Any help would be highly appreciated! > > If you're targetting Xilinx AccelDSP may be of use. > > Otherwise, write a spec, and give it to a human VHDL-code-generator > :-) > > You don't say how fast you need it to run and on what image sizes - > this may affect the feasibility of the conversion. > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html I am interested in image processing of 128x128 image using wavelet transform compression, 12 bits per pixel, monochrome. Thanks, DanArticle: 115344
Hello All,
Thanks for your precious suggestion; finally the problem of
instantiating more than one MicroBlaze is being solved. Now I am
facing next set of problem, i.e. debugging my code.
I have interconnected my two MicroBlazes through FLS so as to have two
way communications. I have loaded following programs:
In MicroBlaze 0:
#include <mb_interface.h>
#include <xutil.h>
int main(void){
int i = 0;
while(i<10){
microblaze_bwrite_datafsl(i, 0);
microblaze_bread_datafsl(i, 0);
xil_printf("pong %d\n\r", i);
}
}
In MicroBlaze 1:
#include <mb_interface.h>
#include <xutil.h>
int main(void){
int i;
while(1){
microblaze_bread_datafsl(i, 0);
i++;
xil_printf("ping %d\n\r", i);
microblaze_bwrite_datafsl(i, 0);
}
}
My aim is to let them pass data through FSL. The problem is that I am
able to connect to only One Microblaze_0, I am not able to do setups
for debugging microblaze_1 through Debug -> XMD options ->
Microblaze_1 and so I am not able to connect to Microblaze_1. A blank
panel appears when followed the above mentioned path with a Tip saying
Please choose a Connection Type.
I had been told that we can connect to only one Microblaze at a time.
And for successful execution of my code in first Microblaze_0 I want
the program in Microblaze_1 to be up and running, but I am not able to
start the program in Microblaze_1.
Can anyone tell me:
1. How to start the program in Microblaze_1 so that the program in
Microblaze_0 can successfully send data to Microblaze_1, and get the
reply from the same.
2. How to connect to Microblaze_1.
3. Is it possible to have a program in any of the microblazes which
can start running automatically, soon after doing the reset of the
FPGA Board.
Please throw some light on this problem of mine.
Thanks and Regards,
Shant
Article: 115345Hi, I have one doubt : What is the need of parallelism/concurrency in the hardware description language ? I have seen some topics which says, C in its purest form is not suitable for the hardware description. The main reason is lack of parallelism in C. I am new to HDLs. It will be very nice if somebody can explain which feature of HDL really needs parallelism support. Thanks a lot. SrinivasArticle: 115346
Hi, I am creating an FPGA (Spartan 3 XCS400) based replacement for one of our old board designs which uses IDT 7201 - http://www.idt.com/products/files/4237161/7200-7202_DS.pdf. Initially I cheated a little and created a clock for the FIFOs and lined up my stimulus to that clock and worked out the bugs in my design. To actually match the original board however I need to work without a clock - the board I am replacing is controlled by another board with a 32MHz clock on it but that clock does not pass down the backplane to my board so all I have are various signals that I must act on. Most of the design seems to work fine except for a limitation in the FIFO core (I am using the Xilinx async FIFO core v6.1) - it must get few clocks from each domain after a reset otherwise it will not accept writes (or reads presumably but it's hard to tell). I did put a 50MHz clock on my board Just In Case(tm) however, obviously, it won't be synchronised with the clock on the main card so I need to sync up the incoming reset signal and then count out a few clocks to the FIFO core. I'm still working on the last part trying to get it working but since my design reads like a "How not to use an FPGA" (through no fault of my own! :) plus I am normally a software guy, it's hard going. Has anyone done this sort of thing before? (and would be willing to share their solution). I am also considering taking the 50MHz clock on my board and multiplying it up to, say, 150MHz and sychronising/one-shotting all of the signals from the other board to that. -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 115347
Hello yesterday I ' ve tried to install ISE 9.1 on a openSuSE 10.2 system. Unfortunately the installation crashs after about 60% without messages. I tried a different installation source -- same result. Has someone any experience with openSuSE 10.2 and Xilinx ISE 9.1 installation ? Best regards AndreasArticle: 115348
Hi,
You can connect to upto 8 MicroBlazes using the opb_mdm
You can only control one at the time using XMD but switch from one to
another using a command.
1.
You have to connect to target 1 or target 0 in XMD
Read chapter 12 about XMD commands in "Embedded System Tools Reference
Manual"
2.
See above, It's all in the documentation
3. Yes, You can have code initialized in the BRAM which the processors will
start to execute after reset.
Just click on your application in XPS and set "Mark to Initialize BRAMs"
Göran
"Shant" <shantchandrakar@gmail.com> wrote in message
news:1170912167.447746.46480@m58g2000cwm.googlegroups.com...
> Hello All,
>
> Thanks for your precious suggestion; finally the problem of
> instantiating more than one MicroBlaze is being solved. Now I am
> facing next set of problem, i.e. debugging my code.
>
> I have interconnected my two MicroBlazes through FLS so as to have two
> way communications. I have loaded following programs:
>
> In MicroBlaze 0:
>
> #include <mb_interface.h>
> #include <xutil.h>
> int main(void){
> int i = 0;
> while(i<10){
> microblaze_bwrite_datafsl(i, 0);
> microblaze_bread_datafsl(i, 0);
> xil_printf("pong %d\n\r", i);
> }
> }
>
>
> In MicroBlaze 1:
>
> #include <mb_interface.h>
> #include <xutil.h>
> int main(void){
> int i;
> while(1){
> microblaze_bread_datafsl(i, 0);
> i++;
> xil_printf("ping %d\n\r", i);
> microblaze_bwrite_datafsl(i, 0);
> }
> }
>
> My aim is to let them pass data through FSL. The problem is that I am
> able to connect to only One Microblaze_0, I am not able to do setups
> for debugging microblaze_1 through Debug -> XMD options ->
> Microblaze_1 and so I am not able to connect to Microblaze_1. A blank
> panel appears when followed the above mentioned path with a Tip saying
> Please choose a Connection Type.
>
> I had been told that we can connect to only one Microblaze at a time.
> And for successful execution of my code in first Microblaze_0 I want
> the program in Microblaze_1 to be up and running, but I am not able to
> start the program in Microblaze_1.
>
> Can anyone tell me:
> 1. How to start the program in Microblaze_1 so that the program in
> Microblaze_0 can successfully send data to Microblaze_1, and get the
> reply from the same.
> 2. How to connect to Microblaze_1.
> 3. Is it possible to have a program in any of the microblazes which
> can start running automatically, soon after doing the reset of the
> FPGA Board.
>
> Please throw some light on this problem of mine.
>
> Thanks and Regards,
> Shant
>
Article: 115349For ByteBlaster( II or MV), you can use the /dev/parport? driver. Be sure to have permission to use that device. In addition, there is a ByteBlaster kernel driver to speed up the access. For the USBBlaster, no additional usb driver is needed. However, a bit configuration is needed. See http://www.altera.com/support/ software/drivers/dri-usb_b-lnx.html For MasterBlaster (serial port only), /dev/ttyS? driver is used. For EthernetBlaster, it works with the TCP/IP stack. In summary, no additional kernel driver is needed for all blasters. - Subroto Datta Altera Corp. On Feb 7, 3:11 pm, General Schvantzkoph <schvantzk...@yahoo.com> wrote: > On Wed, 07 Feb 2007 14:50:38 -0800, rekha.arun wrote: > > On Feb 7, 8:45 am, General Schvantzkoph <schvantzk...@yahoo.com> > > wrote: > >> Is the Byte Blaster Cable and Signal Tap supported on Linux and more > >> specifically on Fedora Core 5 or 6? All of my experience has been with > >> Xilinx tools, this will be my first use of the Altera debug tools. > >> Xilinx's ChipScope has only marginal Linux support. There is a kernel > >> specific driver that only runs on the RHEL version of the kernel which is > >> so old as to be useless on a laptop. I was wondering if Altera has the > >> same sort of limitations or if their tools are kernel independent. > > >> Thanks, > > > Yes, SignalTap is supported on Linux. With regard to ByteBlaster, it > > is supported on 32-bit Linux but not on 64-bit Linux. But, the 64-bit > > Linux does however support Ethernet Blaster. > > Are there any kernel issues?- Hide quoted text - > > - Show quoted text -
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