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Messages from 114625

Article: 114625
Subject: Re: suggest me the right fpga
From: pbgibbrish@ludd.invalid
Date: 21 Jan 2007 13:24:42 GMT
Links: << >>  << T >>  << A >>
>      I am doing a  fpga project for my engineering course completion.
>The project is to process an image caught by a digital camera(. I have
>to store the image caught by the camera in fpga memory as a bit map
>image and will find the average color of the image and to display it in
>the lcd of fpga. I am using verilog .         now please guide me with
>the right fpga that i can go for. I hope one million gates are well
>enough for this project. But I am not sure with the amount of RAM that
>is needed. Is spartan 3 XCS 1000 of xilinx ok. I am not sure. Please
>suggest me with right fpga and amount of memory needed for this project
>and everything that i have to check before buying.

I think you should specify:
  * Image sensor resolution, desired framerate, interface.
  * What kind of processing is involved, and how fast it must complete tasks.
  * LCD resolution, desired framerate, interface.
  * Chip package constraints (BGA?).
  * Software constraints (Linux?).


Article: 114626
Subject: Re: ISE 9.1i and partial reconfiguration
From: El-Mehdi Taileb <taileb.mehdi@gmail.com>
Date: Sun, 21 Jan 2007 18:02:15 +0300
Links: << >>  << T >>  << A >>
Julian,
I already have access to EAPR.
What I would like to know is if this is finally included in the standard
ISE9.1i or if i should continue to have separate installation of ise
patched by EAPR.
Concerning the XAPP290: I thought that it wasn't applicable to Virtex-4/5
because of the absence of TBUFs. What I use is the module-based
reconfiguration.
The EAPR can be used using scripts in command mode although it is highly
recommended to use PlanAhead.

Mehdi

Julian Kain wrote:

> Mehdi,
> 
> What exactly are you looking for, in terms of partial reconfiguration
> support?  Generally, partial reconfiguration is already well supported,
> especially in Virtex-4 and Virtex-5 devices.  The early XAPP290 flow
> works, although it's a bit clunky.  However, the Early Access Partial
> Reconfiguration (access approval required) flow also works very well
> and is significantly more efficient.  Although it's not a "hard"
> requirement, you probably need PlanAhead to really employ it.
> 
> I could be wrong, but I don't think ISE 9.1i includes any "silver
> bullet" partial reconfiguration support, if you're looking for an
> automated process.  But certainly look into the EAPR flow -- it's as
> good as it gets for the time being.  I've personally experienced a high
> degree of success with it.
> 
> Julian Kain
> 
> 
> El-Mehdi Taileb wrote:
>> Hi all!
>> ISE 9.1i is finally out!
>> I read the marketing papers but didn't find any word about partial
>> reconfiguration support.
>> 
>> Mehdi


Article: 114627
Subject: project help
From: "project help" <shahmdk@gmail.com>
Date: 21 Jan 2007 09:49:54 -0800
Links: << >>  << T >>  << A >>
hi everyone

      I am doing a  fpga based project for my engineering course
completion.
camera will be connected to the kit. the kit have to process the image
caught and displaythe color in the led.

The project is to process an image caught by a digital camera(. I have
to store the image caught by the camera in fpga memory as a bit map
image and will find the average color of the image and to display it in

the led of fpga. I am using verilog hdl .  this is the camera that i
will use.

http://www.electronics123.com/s.nl/it.A/id.42/.f?sc=8&category=241
  ( i have only pdf so kindly use this link for all details)
    * Image sensor resolution , interface can be seen in the above
link.interface is surely  not USB..I am a software student and new to
this .please suggest me the *interface and *frame rate by seeing the
camera.

*speed is not a issue in my project.

image processing algorithms are to be developed yet for this project.
finding the average color of an image is the process..i dont think it
will be a big process.

   *LED is enough
No software constraints like linux.
BGA required

 now please guide me with
the right fpga that i can go for. I hope one million gates are well
enough for this project. But I am not sure with the amount of RAM that
is needed. Is spartan 3 XCS 1000 of xilinx ok. I am not sure. Please
suggest me with right fpga and amount of memory needed for this project

and everything that i have to check before buying


Article: 114628
Subject: Re: project help
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 21 Jan 2007 10:02:42 -0800
Links: << >>  << T >>  << A >>
I findit arrogant and presumptious that you don't even bother to
develop some ideas about the structure of your design, before you dump
it all on this newsgroup.
Remenber: This is a homework assignment for you, not for us!
Peter Alfke

On Jan 21, 9:49 am, "project help" <shah...@gmail.com> wrote:
> hi everyone
>
>       I am doing a  fpga based project for my engineering course
> completion.
> camera will be connected to the kit. the kit have to process the image
> caught and displaythe color in the led.
>
> The project is to process an image caught by a digital camera(. I have
> to store the image caught by the camera in fpga memory as a bit map
> image and will find the average color of the image and to display it in
>
> the led of fpga. I am using verilog hdl .  this is the camera that i
> will use.
>
> http://www.electronics123.com/s.nl/it.A/id.42/.f?sc=8&category=241
>   ( i have only pdf so kindly use this link for all details)
>     * Image sensor resolution , interface can be seen in the above
> link.interface is surely  not USB..I am a software student and new to
> this .please suggest me the *interface and *frame rate by seeing the
> camera.
>
> *speed is not a issue in my project.
>
> image processing algorithms are to be developed yet for this project.
> finding the average color of an image is the process..i dont think it
> will be a big process.
>
>    *LED is enough
> No software constraints like linux.
> BGA required
>
>  now please guide me with
> the right fpga that i can go for. I hope one million gates are well
> enough for this project. But I am not sure with the amount of RAM that
> is needed. Is spartan 3 XCS 1000 of xilinx ok. I am not sure. Please
> suggest me with right fpga and amount of memory needed for this project
> 
> and everything that i have to check before buying


From invalid@dont.spam Sun Jan 21 10:06:34 2007
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From: Phil Hays <invalid@dont.spam>
Subject: Re: Ones' complement addition
User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table)
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NNTP-Posting-Date: Sun, 21 Jan 2007 13:06:34 EST
Xref: prodigy.net comp.arch.fpga:125822

Eric Smith wrote:

> A one's complement adder does not have a "carry-in" input,

Please excuse my poor choice of words. Replaced "carry-in" with
"carry-wrapped around input to LSB", which is the same as the "carry-out"
or the "carry-wrapped around output from the MSB" after the propagation
delay from the MSB's output to the input of the LSB. So let me try again:

An example. Note that the two inputs can be anything that are inverses of
each other. The first two cases are stable.

  0111
 +1000
    +0 Carry wrapped around input to LSB
======
  1111 carry wrapped around output from MSB = 0

Note that the carry bits are 0000

or:

  0111
 +1000
    +1 Carry wrapped around input to LSB
======
  0000 carry wrapped around output from MSB = 1

Note that the carry bits are 1111

The key point here is that there are two correct answers in ones
complement to the problem:

7 - 7 = ?

And these answers are positive zero and negative zero.

With me so far?

To describe an unstable case, I'm going to show only the carry bits. The
inputs are the same as above. I'm assuming ripple carry, and that one time
step is required for propagation of carry for one bit position.

Time
0     Carry  0011
1     Carry  0110
2     Carry  1100
3     Carry  1001
4     Carry  0011
5     Carry  0110
6     Carry  1100
7     Carry  1001
8     Carry  0011
...

The sum would also not be stable.

There are multiple ways to avoid the unstable cases. A few that come to
mind with little effort:

1) Force the previous carry wrap around input into the LSB until the carry
wrap around output from the MSB is stable. This has the side effect of
making the result (positive or negative zero) depend on the previous
computation. (I think that the CDC6600 used this method)

2) If the carry look ahead shows all propagate bits are '1', then generate
a carry wrap around input into the LSB = '1' regardless of the carry wrap
around output from the MSB or any generate bits. This has the side effect
of producing only positive zeros for any add unless both operands were
negative zeros.

3) Force a carry wrap around input of '0' until the carry wrap around
output is stable. This has the side effect of never producing a positive
zero output for any add unless both operands were positive zeros. (Hand
computed examples often use this method)

4) Force a carry wrap around input of '1' until the carry wrap around
output is stable. This has the side effect of producing only positive
zeros any add unless both operands were negative zeros.

Any method that must decide between two correct answers may take forever
to come to one of the two answers.


-- 
Phil Hays (Xilinx, but posting for myself)


Article: 114629
Subject: system generator from Xilinx
From: nbg2006@gmail.com
Date: 21 Jan 2007 10:32:34 -0800
Links: << >>  << T >>  << A >>
Hello all,
I just wanted to find out how good system generator software is? I can
program in VHDL and would like to know if the SYS gen software would
make life easier for me when it comes to designing DSP filters , FFTS
or other DSP blocks.
Does Xilinx  provide IPs separately for the DSP blocks? If so then How
different is it from using Xilinx IP in the design instead of sysgen
blocks ?
Any experience on system generator software would be helpful .
Thanks,
nbg


Article: 114630
Subject: Re: project help
From: "Josep Duran" <j.duran@teleline.es>
Date: 21 Jan 2007 11:40:46 -0800
Links: << >>  << T >>  << A >>
project help wrote:
> hi everyone
>
>       I am doing a  fpga based project for my engineering course
> completion.
> camera will be connected to the kit. the kit have to process the image
> caught and displaythe color in the led.
> .........
> http://www.electronics123.com/s.nl/it.A/id.42/.f?sc=8&category=241
> .........
> .........

I am afraid you will not know the size of the FPGA you need until later
on the development cycle.
First you should study your camera, and the way you are going to
interface it.
Then you should study the algorithms you are going to use, and find the
simpler one that will get your job done.
Then you can implement it all and simulate your design using the
Webpack software.

And you are done !!!

You know for sure what FPGA fits your design, so now you can buy one of
the kits available to implement your design, just order the board, and
after a bit of soldering it should all work.

Don't expect this to be fast nor simple as it is your first time, there
are many tools you have to learn how to use.


Best regards

Josep Duran


Article: 114631
Subject: When do I need reset and clear?
From: <shitsu>
Date: Sun, 21 Jan 2007 20:03:19 -0000
Links: << >>  << T >>  << A >>
The question is about the xc9500 familiy. I understand
that if I need to connect a clock to the chip, I should
use the GCK pin. When should I use the GSR and
GTS pins? Feel free to use Verilog to demonstrate
an example.



Article: 114632
Subject: Re: digilent nexys vga glitches
From: Ben Jackson <ben@ben.com>
Date: Sun, 21 Jan 2007 14:26:17 -0600
Links: << >>  << T >>  << A >>
On 2007-01-21, Corer <corer@somewhere.net> wrote:
> I get some nasty horizontal jitter on vga display
> controlled by a vga controller (see below) running
> on a digilent nexys board.

What's the source of the clock for the VGA?  Does it look good?

-- 
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

Article: 114633
Subject: Re: digilent nexys vga glitches
From: "Corer" <corer@somewhere.net>
Date: Sun, 21 Jan 2007 22:19:16 GMT
Links: << >>  << T >>  << A >>
It looks like I was wrong and the raise time
of production vga controller is about the same as
I get out of my proto-board - HSync raise time is about
19ns 0->5v on production vga and 20ns 0->3v on
Changing DRIVE and SLEW doesn't make any difference
to the resulting picture.

My hsyncs do ring (you can not avoid that right?)
Ringing dies off in 230ns and I get four periods of a transient.
Pronounced peaks are at
3.3v+0.85v; 3.3v-0.41v; 3.3v+0.2v; 3.3v-0.2;

Ringing on the real adapter hsync dies in 200ns and transient
peaks are around 0.6/-0.5 but they look "smoother" and are
lower frequency (sorry for my terminology). Don't forget
their hsyncs are 5v high while mine is "only" 3.3

I think that the main problem I'm having is hsync to hsync jitter.
If I set my analog oscilloscope to trigger at an hsync raising
edge and then see what happens 470mks later I see a smear.
For a production vga adapter I see a solid edge that "pans"
left and right.

Corer.

"Sylvain Munaut" <tnt-at-246tNt-dot-com@youknowwhattodo.com> wrote in
message news:45B3348A.1000503@youknowwhattodo.com...
>
>
> > Looking at the hsyncs via an oscilloscope shows that
> > the pulses do actually slide left and right like crazy and
> > are really unstable (10-20ns jitter).
>
> Are they clean ? (no ringing)
> If they're clean, but just too slow rising, you can
> try to change the IOB properties of the hsync
> output, try to add things like DRIVE=24 and/or SLEW=FAST
> (I'd try the DRIVE first, at 50MHz the FAST slew doesn't
> make much sense I think)
>
> Sylvain
>



Article: 114634
Subject: Re: digilent nexys vga glitches
From: "Corer" <corer@somewhere.net>
Date: Sun, 21 Jan 2007 22:44:05 GMT
Links: << >>  << T >>  << A >>
I have a proto board from digilent
http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS&Nav1=Products&Nav2
=Programmable

Nexys board has a builtin 25/50/100MHz oscillator
which I use for my project's mclk input.
I tried to route the clock to one of the output
fpga connectors and 100MHz output doesn't look like
a square wave at all (it looks more like a sine wave).
Unfortunately it could be that oscilloscope/probe/myself
system can not deal with such a high frequency.

BTW If I display voltage of 100MHz pin driven through
fpga 2000ns after the trigger event I see a smear.
The waveform is barely distingushable after 800ns.
Is it supposed to be like this? I'm really new to the
electronics and it looks like I'm not ready to deal with
imperfections :-)

Corer

"Ben Jackson" <ben@ben.com> wrote in message
news:slrner7j39.27ps.ben@saturn.home.ben.com...
> On 2007-01-21, Corer <corer@somewhere.net> wrote:
> > I get some nasty horizontal jitter on vga display
> > controlled by a vga controller (see below) running
> > on a digilent nexys board.
>
> What's the source of the clock for the VGA?  Does it look good?
>
> --
> Ben Jackson AD7GD
> <ben@ben.com>
> http://www.ben.com/



Article: 114635
Subject: Re: Correction for hwicap_v1_00_a code
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Mon, 22 Jan 2007 09:46:12 +1000
Links: << >>  << T >>  << A >>
Hi Neil,

Neil Steiner wrote:

> I was writing a linux kernel driver for the icap, 

You mean like this one:

http://www.itee.uq.edu.au/~listarch/partial-reconfig/archive/2006/04/msg00009.html

?

It was written for MicroBlaze / uClinux, but will port trivially to PPC 
if you need to.  A paper describing the driver and some things we did 
with is here

http://eprint.uq.edu.au/archive/00001296/

> People who always write full frames will probably not have run into 
> this, but my driver had to write chunks of data as it received them from 
> the kernel, and thus not split along frame boundaries.

I think I came across similar issues - with HWICAP you must always write 
a full frame at a time which means buffering in the driver in case the 
user does something like multiple byte writes (e.g. from "cat") instead 
of a nice big block write.

Cheers,

John


Article: 114636
Subject: how to use register to save data
From: "ZHI" <threeinchnail@gmail.com>
Date: 21 Jan 2007 15:48:11 -0800
Links: << >>  << T >>  << A >>
There are Matrix 4 by 4 R and Vector 4 by 1 B generated in Matlab. I
transmitted these data to FPGA board. The 16 elements of R are saved in
a RAM and the 4 elements of B are saved in another RAM.  Now I am
thinking if it is possible to save these data in several registers.

For example:
for k=1:4
B= B*2^mdiff - R(:,k)
end

midff is a constant. It is seen that  B do update once need read R RAM
and B RAM 4 times. So i wanna to save these data in several registers.
Then  B can do one update operation in one clock cycle by reading all
the data at the same time. But if i put one register following every
element, i don't know how to index these different registers.  Does
anybody  tell me how to figuer it out? Many thanks.


Article: 114637
Subject: Re: how to use register to save data
From: "ZHI" <threeinchnail@gmail.com>
Date: 21 Jan 2007 16:04:15 -0800
Links: << >>  << T >>  << A >>
Can I try this way?

type array_type1 is array (0 to 3) of std_logic_vector (31 downto 0);
 signal  arrayb: array_type1 :=(others=>(others=>'0'));

I define the array_tpye and store the elements into the arrayb.  I
don't know if it is a proper solution.


Article: 114638
Subject: How to exclude timing violations in Xilinx *.ucf file
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 21 Jan 2007 17:07:58 -0800
Links: << >>  << T >>  << A >>
Hi,
I have 2 questions to ask for help.

1.
My a project has a module outputing AD_OE signal.

That signal drive 64 output pins:
AD(63 downto 0) <= AD_O_Pin(63 downto 0) when AD_OE   = '1' 	else
(others=>'Z');

Now AD_OE has timing violations.

In my design AD_OE signal is handled specially so that it should be
excluded in timing violation tables.

After using ChipScope tool, I found that AD_OE generates 64 registers
internally by Xilinx compiler:
AD_OE_0,
AD_OE_1,
AD_OE_2,
..
AD_OE_63.

The following equations are all wrong with Xilinx compiler:
INST "m_t_statea/ad_oe" TNM = "PCI_OE";
INST "m_t_statea/ad_oe_0" TNM = "PCI_OE";
INST "m_t_statea/ad_oe<*>" TNM = "PCI_OE";
INST "ad_oe_0" TNM = "PCI_OE";
INST "ad_oe<*>" TNM = "PCI_OE";

>From timing violation listing by using Xilinx Timing Analyzer, it shows
timing violations:
M_T_StateA/AD_OE_0 (FF)
...
M_T_StateA/AD_OE_15 (FF)

I copy those signals directly into *.ucf as above, all are compiler
errors.

What should I do now?

2. How to set default timing violation count from 3 to any number for
Xilinx Timing Analyzer?

Thank you.

Weng


Article: 114639
Subject: Using demo IP libraries?
From: zwsdotcom@gmail.com
Date: 21 Jan 2007 17:15:41 -0800
Links: << >>  << T >>  << A >>
I'm trying to build one of the sample projects (ml403_emb_ref_ppc) that
comes with the ML403. I'm running Platform Studio 7.1.02i. It's
complaining that there's no license for the 16550, the I2C and the
Ethernet MAC. Fair enough - but I thought this was supposed to include
time/byte-limited demo versions of the IP. How can I fix this silly
licensing issue so I can build and download one of the samples?

The exact error text is:

ERROR:MDT - opb_uart16550 (opb_uart16550_0) -
C:\ml403_emb_ref_ppc\system.mhs:324 - invalid license or no license
found!
INFO:coreutil - Valid license for feature opb_iic_v1 not found.
You may use the customization GUI for this core but you will
not be able to generate any implementation or simulation files.
Contact Xilinx to obtain a full license for this LogiCORE. For more
information please refer to www.xilinx.com/ipcenter/ipevaluation/
FLEXlm Error: No such feature exists (-5,21)


Article: 114640
Subject: Re: edif format
From: "quad" <fyp.quadruples@gmail.com>
Date: 21 Jan 2007 20:09:42 -0800
Links: << >>  << T >>  << A >>

Neil Steiner wrote:
> > where can i find a description of the edif format. www.edif.org doesn't
> > have the syntax
>
> I can't address the larger question, but if you just need to read and
> parse edif, BYU has two good solutions:
>

I do not necessarily need to read and parse edif. I need to write edif,
in other words, i need to construct edif using c code. Are there any
books/ebooks on edif with documentation enough to construct netlists
ourselves?


From dave@comteck.com Sun Jan 21 21:39:18 2007
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From: Dave <dave@comteck.com>
Subject: Re: project help
Date: Mon, 22 Jan 2007 00:39:18 -0500
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On Sun, 21 Jan 2007 09:49:54 -0800, project help wrote:

>     * Image sensor resolution , interface can be seen in the above
> link.interface is surely  not USB..I am a software student and new to
> this .please suggest me the *interface and *frame rate by seeing the
> camera.

So you cannot even be bothered with reading the document and determining
the resolution and interface on your own?  We have to waste our time
looking for something you should be able to tell us?  Help from the
participants in this community comes to those who put forth some effort
and ask for help on that basis. You get out of coursework what you put
into it, in your case 0.


    ~Dave~

Article: 114641
Subject: Re: frequency-Phase Detector?
From: "axalay" <axalay@gmail.com>
Date: 21 Jan 2007 23:25:44 -0800
Links: << >>  << T >>  << A >>
Thank for all. 

Vasiliy


Article: 114642
Subject: Re: how to use register to save data
From: backhus <nix@nirgends.xyz>
Date: Mon, 22 Jan 2007 08:28:57 +0100
Links: << >>  << T >>  << A >>
ZHI schrieb:
> There are Matrix 4 by 4 R and Vector 4 by 1 B generated in Matlab. I
> transmitted these data to FPGA board. The 16 elements of R are saved in
> a RAM and the 4 elements of B are saved in another RAM.  Now I am
> thinking if it is possible to save these data in several registers.
> 
> For example:
> for k=1:4
> B= B*2^mdiff - R(:,k)
> end
> 
> midff is a constant. It is seen that  B do update once need read R RAM
> and B RAM 4 times. So i wanna to save these data in several registers.
> Then  B can do one update operation in one clock cycle by reading all
> the data at the same time. But if i put one register following every
> element, i don't know how to index these different registers.  Does
> anybody  tell me how to figuer it out? Many thanks.
> 
Hi Zhi,
how do you "transmit" the data to the FPGA Board? are you using some 
tool like system designer that buids your bridge from matlab to the FPGA?

Your problem would be simple to solve, if you were designing your 
datapath yourself in VHDL or verilog. But with automated translation 
tools you have to figure out how to write matlab code in a way that will 
be interpreted in the way you intend, rather than the standard solution 
you get now.

Matlab sees every variable as a matrix. The most natural way of storing 
matrices is ram. So the disigners of your translation tool choose this 
solution for simplicity and generality. If you want something special 
e.g. to speed up your design you have to tell the tool.

My guess would be (and it's really just a guess!) that you have to 
specify a scalar variable for each matrix element, and don't use loops 
cause loops may infer a copy from ram to register machine which would 
not be what you intend.

have a nice synthesis
   Eilert

Article: 114643
Subject: Re: Different Modelsim versions disagree in same backannotation!
From: Kim Enkovaara <kim.enkovaara@iki.fi>
Date: Mon, 22 Jan 2007 09:43:28 +0200
Links: << >>  << T >>  << A >>
spectrallypure wrote:
>> #3 - Why are you set at 1ns resolution? Is this a *very* slow chip? I
>> bet your sim models are set to 1ps; I'd suspect a rounding problem somewhere.
> We also think the problem might have to do with this. I just set the
> resolution to 1ns because that is the value of the resolution of the
> SDF files, but I have experimented by changing this value and the
> timing of the waveform changes A LOT. However, I haven't been able to
> make the simulation give the expected results by tweaking this
> parameter. The operating frequency of the design is 50MHz.

You should set the resolution to what the models expect, nowadays the 
resolution is usually 1ps or 10ps. The models can behave incorrectly
if the resolution is not correct.

And also the SDF must be generated from the layout tools with the same 
or better resolution. 1ns resolution for the SDF files sounds very 
large, unless you use some exotic or old process. Even for 0.13u process 
1ps resolution is sometimes too high in STA.


>> #4 - What do you get if you enable sdf warnings & errors?
> 
> In 5.8b I get a lot (nearly 50,000) of the following warnings:
> 
> # ** Warning: (vsim-SDF-3262) ./DFM_TC_Worst.pt.sdf(<-SDF line number
> here->): Failed to find matching specify timing constraint.
> 
> ... but the simulation works. On the other hand, in 6.2e, I get this
> same error but a lot more times (something like three times more), I
> additionally I get the following error (once again, I get it a lot of
> times):
> 
> # ** Warning: (vsim-SDF-3261) ./DFM_TC_Worst.pt.sdf(<-SDF line number
> here->): Failed to find matching specify module path.

Normally you should not get any warnings or errors from the annotation.
They usually tell that the SDF is annotated to a wrong place or 
simulation models do not match the synthesis models (library version 
mismatch etc.). You should manually compare the SDF and the models to 
see why the errors are there. I have seen usually warnings in special 
analog cells, IO-testing structures etc. that are quite hard to model in 
simulation.

50k errors is too much, <100 warnings for few gigabyte SDF sounds normal 
figure. The tool might do things differently in error conditions 
depending on versions.


--Kim

Article: 114644
Subject: Re: Series DCM's and total Lock Time
From: moogyd@yahoo.co.uk
Date: 21 Jan 2007 23:56:13 -0800
Links: << >>  << T >>  << A >>

motty wrote:
> > I googled around a bit but could not find the answer.
>
>   The data sheets, user guides, and switching characteristics data
> sheets are your friend.
>
> > I am using Xilinx Spartan FPGA, with 2 DCM's in series to generate a
> > 32MHz clock (50% duty cycle) from a 75MHz input. (First DCM is divide
> > 2.5, second multiply 32 and divide 30).
> >
> > The first DCM is connected to a system reset via a user pin, and the
> > LOCKED signal of this DCM is used to reset the second DCM.
> >
> > My question : What is the total lock time i.e. When will the 32MHz
> > clock be available ?
> >
> > Thanks for any insights,
> >
> > Steven
>
> I'm sure the Spartan datasheets spec the time needed for the DLL to
> lock given a certain output frequency.  Find that number for the first
> DCM and then find the lock time for the DFS on the second DCM.  You
> should have a ballpark figure then.  You're talking about milliseconds
> (at least according to the Virtex4 data - which should be close to the
> Spartan figures).  So the delay from the lock asserting on the first
> DCM to the second DCM being enabled should be negligible.

Hi,

You are of course correct. I checked the datasheets, and the values are
there (0.48ms + 2.88ms).

Next time I will check more carefully.

Thanks,

Steven


Article: 114645
Subject: "Divide" a video line in two stripe
From: "Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com>
Date: 22 Jan 2007 00:33:28 -0800
Links: << >>  << T >>  << A >>
Here's my problem :

A have a video module (that I can't really change), that outputs a
3840x2400 image, by outputing two consecutive pixels at once (like
dual-link DVI). The problem is that the screen to display that doesn't
want dual-link DVI, it wants two independant DVI stream, one for the
left part of the screen and another for the right part of the screen.
(two "stripes" of 1920x2400).

I'm trying to come up with a solution to "transform" one into another,
without using a frame buffer nor storing more than 1 line of video.
(At 3840, in color, that already is 6 Xilinx BRAMs and I'm a little
short of those ...).

According to my calculations, It should even be possible to only store
half a line, but I prefer to have a 1 line delay than half a line
delay.
My problem is that I can't find how to do it ... Storing in BRAM has
proven to be an addressing nightmare to store and reread simultaneously
without overwriting data I haven't re-read yet ... (since I don't read
in the same order that I write).

Does anyone has done something similar or has a genius idea ? Because
I'm missing something here, that should be simple and I just don't see
it ...


Sylvain


Article: 114646
Subject: Re: edif format
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: 22 Jan 2007 09:47:17 +0100
Links: << >>  << T >>  << A >>
"quad" <fyp.quadruples@gmail.com> writes:

> in other words, i need to construct edif using c code. Are there any
> books/ebooks on edif with documentation enough to construct netlists
> ourselves?

You can buy the CD-ROM from 

http://tinyurl.com/38wyu6

Or the paper/PDF for version 2.00

http://tinyurl.com/2vqgqb

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 114647
Subject: Re: how to use register to save data
From: "ZHI" <threeinchnail@gmail.com>
Date: 22 Jan 2007 00:52:32 -0800
Links: << >>  << T >>  << A >>
I transmitted these data to FPGA board  by a serial link from Matlab. I
use the serial commond like
fwrite(s,R,'int8','async') to send the data to UART.   I did not use
the translation tools. Now I am thinking can I try this way:

type array_type1 is array (0 to 3) of std_logic_vector (31 downto 0);
     signal  arrayb: array_type1 :=(others=>(others=>'0'));

I define a new type and store these elements in the array type instead
of the RAM.


backhus wrote:
> ZHI schrieb:
> > There are Matrix 4 by 4 R and Vector 4 by 1 B generated in Matlab. I
> > transmitted these data to FPGA board. The 16 elements of R are saved in
> > a RAM and the 4 elements of B are saved in another RAM.  Now I am
> > thinking if it is possible to save these data in several registers.
> >
> > For example:
> > for k=1:4
> > B= B*2^mdiff - R(:,k)
> > end
> >
> > midff is a constant. It is seen that  B do update once need read R RAM
> > and B RAM 4 times. So i wanna to save these data in several registers.
> > Then  B can do one update operation in one clock cycle by reading all
> > the data at the same time. But if i put one register following every
> > element, i don't know how to index these different registers.  Does
> > anybody  tell me how to figuer it out? Many thanks.
> >
> Hi Zhi,
> how do you "transmit" the data to the FPGA Board? are you using some
> tool like system designer that buids your bridge from matlab to the FPGA?
>
> Your problem would be simple to solve, if you were designing your
> datapath yourself in VHDL or verilog. But with automated translation
> tools you have to figure out how to write matlab code in a way that will
> be interpreted in the way you intend, rather than the standard solution
> you get now.
>
> Matlab sees every variable as a matrix. The most natural way of storing
> matrices is ram. So the disigners of your translation tool choose this
> solution for simplicity and generality. If you want something special
> e.g. to speed up your design you have to tell the tool.
>
> My guess would be (and it's really just a guess!) that you have to
> specify a scalar variable for each matrix element, and don't use loops
> cause loops may infer a copy from ram to register machine which would
> not be what you intend.
> 
> have a nice synthesis
>    Eilert


Article: 114648
Subject: Re: "Divide" a video line in two stripe
From: "jbnote" <jbnote@gmail.com>
Date: 22 Jan 2007 01:25:47 -0800
Links: << >>  << T >>  << A >>
Hello,

The simplest scheme would certainly be to use two async fifos of
half-a-line each (one for each DVI output stream). The input stream
feeds alternatively the first and the second fifo. You synchronize the
get of the fifos when both have data: this allows you to get two
synchronized output DVI streams with one line buffering.

If you can desynchronize the DVI output streams, then a quarter line
fifo for each output stream is sufficient (you don't have to wait for
the other fifo to have elements in it to start emptying it, so by te
time the input stream gets back to you, you already have half-emptied
your first fifo).

JB


Article: 114649
Subject: what happened to modular design in ISE9
From: backhus <nix@nirgends.xyz>
Date: Mon, 22 Jan 2007 10:31:42 +0100
Links: << >>  << T >>  << A >>
Hi,
while Iwere reading some chapters of the new ISE9 Development System 
Reference guide I happened to notice that the chapters about Incremental 
Design and Modolar Design are gone.

What happened? Have these approaches been dropped? If so, I would like 
to know the reasons. Is there some new (better) approach? Or have these 
chapters just moved to some yet unpublished ISE9 document? (I know they 
are still available in the ISE8 doc files.)

Best regards
   Eilert



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