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Messages from 114675

Article: 114675
Subject: Re: edif format
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Mon, 22 Jan 2007 11:03:16 -0800
Links: << >>  << T >>  << A >>
quad wrote:
> Neil Steiner wrote:
>>> where can i find a description of the edif format. www.edif.org doesn't
>>> have the syntax
>> I can't address the larger question, but if you just need to read and
>> parse edif, BYU has two good solutions:
>>
> 
> I do not necessarily need to read and parse edif. I need to write edif,
> in other words, i need to construct edif using c code. Are there any
> books/ebooks on edif with documentation enough to construct netlists
> ourselves?
> 

If I recall correctly you had posted earlier this month about creating a
C-to-EDIF program that would create (aka synthesize) designs to be used
in a FPGA.  If this is still your intent then I would suggest you simply
take a look at some example EDIF files for the particular vendor and device
that you are going to target and just emulate what is in them.

The EDIF format structure is very simple, but not all possible keywords
and styles are supported by every vendor.  Your best shot is to start
with known working examples (with hierarchy) and just output the same
for your design netlists. The format itself is a trivial task, outputting
a correct design netlist will all of the right design entry primitives,
ports and attributes is the hard part.

Good luck.

Ed McGettigan
--
Xilinx Inc.


Article: 114676
Subject: Re: Clock constraints
From: "Gabor" <gabor@alacron.com>
Date: 22 Jan 2007 11:07:55 -0800
Links: << >>  << T >>  << A >>

skyworld wrote:
> Hi,
> I will input a differential clock to DCM, how should I set contraints?
> Should I set constraint on IBUFGDS input or should I set constraint on
> its output? And should I set constraints on DCM outputs? Thanks.

Normally for pin-to-pin constraints you just use the positive pin
of the differential input and the constraints otherwise work as
they would for a single-ended clock.  If you put constraints on
a DCM input or on the input pin that feeds the DCM, you
shouldn't need constraints on the output of the DCM as well.  In
fact often constraints on the outputs of DCM's are ignored
in this case, because the timing analyzer uses the input
constraints that were "pushed through" the DCM instead.

HTH,
Gabor


Article: 114677
Subject: Re: edif format
From: Mike Treseler <mike_treseler@comcast.net>
Date: Mon, 22 Jan 2007 11:43:46 -0800
Links: << >>  << T >>  << A >>
> quad wrote:

>> I do not necessarily need to read and parse edif. I need to write edif,
>> in other words, i need to construct edif using c code. 


See also an XST or Quartus technology schematic
for a graphical view of the luts'n'flops netlist.

      -- Mike Treseler


Article: 114678
Subject: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
From: "radarman" <jshamlet@gmail.com>
Date: 22 Jan 2007 11:48:45 -0800
Links: << >>  << T >>  << A >>

Austin Lesea wrote:
> Antti,
>
> No problem.  We have to release our software on a regular schedule, so
> there is no holding it back.
>
> I would caution that whatever is revealed in the software may be updated
> or changed in the future, so the recommendation to work with our FAEs
> (if you really want to use a product before its release) is still valid.
>
> Austin

Are there any plans for a non-volatile version of the Spartan 3e?


Article: 114679
Subject: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
From: "Antti" <Antti.Lukats@xilant.com>
Date: 22 Jan 2007 11:55:51 -0800
Links: << >>  << T >>  << A >>
Austin Lesea schrieb:

> Antti,
>
> No problem.  We have to release our software on a regular schedule, so
> there is no holding it back.
>
> I would caution that whatever is revealed in the software may be updated
> or changed in the future, so the recommendation to work with our FAEs
> (if you really want to use a product before its release) is still valid.
>
> Austin
Huh.
tnx.

I just pointed out to some info that is revealed by the WP 9.1, things
that are to my understanding command knowledge as of today.

The fact that actual product release announce are not in sync with
software updates is a bit confusing. For me at least, but I guess that
explains why I failed so miserable on brainbench online examps for:
"SCM: Software Configuration Management".

At the moment I can only say that S3AN looks like REALLY REALLY nice
FPGA! A real nice one.
And I can only whish that package options would include
VQ64
DIP40
QFN48
;) kidding.
but really, a package with outline 8by8 mm or less would be really
nice.
Altera is currently leading in this regard the MAX II has 0.5mm 100
ball BGA with measueres 6by6mm !

thats a real dream package.
ok, I can little relax the specs, S3AN in 8bx8 mm microFPGA would be
close to a truedream as well.

Antti


Article: 114680
Subject: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
From: "Antti" <Antti.Lukats@xilant.com>
Date: 22 Jan 2007 12:09:58 -0800
Links: << >>  << T >>  << A >>
radarman schrieb:

> Austin Lesea wrote:
> > Antti,
> >
> > No problem.  We have to release our software on a regular schedule, so
> > there is no holding it back.
> >
> > I would caution that whatever is revealed in the software may be updated
> > or changed in the future, so the recommendation to work with our FAEs
> > (if you really want to use a product before its release) is still valid.
> >
> > Austin
>
> Are there any plans for a non-volatile version of the Spartan 3e?
Rick,
if you look at the datasheet of S3-A then you should be able answer
your question yourself.

NO.

S3-A is re-engineered to have features needed for non-volatile on chip
storage.

This is mainly the feature to self-reinit the a re-confiugration from
random address and optionally from different configuration interface.
That is S3A (and AN) is first Xilinx that can force itself to be
reconfigured in an config mode defined by user app. S3E and V-5 have
both limited multi-boot functionality
S3-E can init "second config only in BPI mode"
Virtex-5 can restart config from any user defined offset in same mode
(eg cant over-ride mode pin setting)
S-3A/N can restart config from user defined offsert in user defined
mode.

from the above you can see that for sure, S3E will not have
non-volatile version - it does not make sense.

Antti


Article: 114681
Subject: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
From: "-jg" <Jim.Granville@gmail.com>
Date: 22 Jan 2007 12:57:57 -0800
Links: << >>  << T >>  << A >>
Antti wrote:
> With Spartan-3AN is Xilinx making its entry in the non-volatile FPGA
> arena.
>
> I am glad that this can now be discussed in open, as WebPack 9.1
> includes already support for S3-AN.
> So my speculations, about "Why S3-A if its not volatile" was justified,
> with the only difference that S3-A has 2 derivates, with and without
> integrated non-volatile storage.

 So this is a dual-die release ? - makes it a fairly incremental
advance,
and perhaps able to give more illusion of security.

 Will it cost less than an external multisourced SPI that follows the
industry price curve ? - very unlikely.

 Or maybe they chose to use more bond wires, for
better load times, and usefull execute-from-flash speeds ?

 With Soft CPU deployment more common, the config memory size is
no longer as defined as it was, so matching the bundled EE to the
users needs is a challenge.

-jg


Article: 114682
Subject: Re: digilent nexys vga glitches
From: "Corer" <corer@somewhere.net>
Date: Mon, 22 Jan 2007 21:32:54 GMT
Links: << >>  << T >>  << A >>
Thanks for the info... I think I tried driving it from
50MHz and didn't make any appreciable difference.
Could it be my oscillator is that bad?
Are you using j8 connector?
Do you see anything wrong with my vhdl? (first
message in this thread)

I do not really know whether it is at all possible,
but could share your code, so I could try and run
it on my nexys? It would be just great.

I tried to look at http://www.derepas.com/fabrice/hard/
it doesn't seem to work (at least right now). I'll try again
later

Corer.

"RedskullDC" <RedskullDC@SPAM.yahoo.com.au> wrote in message
news:rZCdnZar4oMIKSnYnZ2dnUVZ_vShnZ2d@giganews.com...
> Hi Corer,
>
> "Corer" <corer@somewhere.net> wrote in message
> news:GlDsh.2913$O02.2241@newssvr11.news.prodigy.net...
> > Newbie problem:
> > I get some nasty horizontal jitter on vga display
> > controlled by a vga controller (see below) running
> > on a digilent nexys board. It looks like all scan lines
> > jitter relative to each other (couple of pixels left/right).
> > The problem is worse on the first 1/16th of the screen
> > and it is getting better below (still jitters on the bottom
> > though).
> >
> > Looking at the hsyncs via an oscilloscope shows that
> > the pulses do actually slide left and right like crazy and
> > are really unstable (10-20ns jitter).
> >
> > I tried to look at the output of a production vga adapter
> > and it looks more stable (do not jitter as much) and the
> > edges of the pulses are much more "square" (raise time is
> > much smaller). Another difference is with the voltage -
> > nexys uses 3.3v and it looks like the vga adapter I tried
> > has 5v output.
> >
> > I looked all over the internet and it doesn't seem like
> > anybody else has this problem. Have anybody tried
> > to get a nice and stable picture via nexys vga?
> > What am I doing wrong? Is it supposed to be that
> > "imperfect"? How do I fix it?
>
> No probs using the Nexys this end. I have the VGA adapter card aswell.
> Tried it with 640x480 and 800x600, 60Hz.
>
> Couldn't get 1024x768 working properly, but that will be a job
> for a rainy weekend.
>
> I was using a 25MHz pixel clock though, as in the "squares"
> example from:
> http://www.derepas.com/fabrice/hard/
>
> 25 or 50MHz inputs on MCLK instead of the 100MHz you are
> using may be more forgiving.
>
> Cheers,
> Red
>
>
>



Article: 114683
Subject: Re: edif format
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: 23 Jan 2007 00:16:58 +0100
Links: << >>  << T >>  << A >>
Ed McGettigan <ed.mcgettigan@xilinx.com> writes:

> The EDIF format structure is very simple, but not all possible keywords
> and styles are supported by every vendor.  Your best shot is to start

Yes, even if you have the EDIF spec you can't know that your Xilinx
targeted netlist is more or less useless without a (property init
(string "XX")) where XX is the lut value.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 114684
Subject: Re: Ones' complement addition
From: Eric Smith <eric@brouhaha.com>
Date: 22 Jan 2007 15:37:55 -0800
Links: << >>  << T >>  << A >>
Phil Hays wrote:
> Please excuse my poor choice of words. Replaced "carry-in" with
> "carry-wrapped around input to LSB", which is the same as the "carry-out"
> or the "carry-wrapped around output from the MSB" after the propagation
> delay from the MSB's output to the input of the LSB. So let me try again:

My apologies for misunderstanding your point.

> There are multiple ways to avoid the unstable cases. A few that come to
> mind with little effort:

After further consideration, I believe you are correct that the cases
where the result is numerically zero can be unstable, unless a method
to precondition at least one stage of the carry chain is used (as done
in your suggestions).

> 1) Force the previous carry wrap around input into the LSB until the carry
> wrap around output from the MSB is stable. This has the side effect of
> making the result (positive or negative zero) depend on the previous
> computation. (I think that the CDC6600 used this method)

When I find a bit of spare time, I'll look into what method was used
by the PDP-1.  As a guess, I suspect the design probably is such that
the initial state of the carry signals is zero, in which case the
result is stable even for operands that add to zero.

Eric

Article: 114685
Subject: Re: Xilinx ISE 8.2
From: Eric Smith <eric@brouhaha.com>
Date: 22 Jan 2007 15:42:38 -0800
Links: << >>  << T >>  << A >>
"bgshea" <bgshea@gmail.com> writes:
> I'm looking for POSITIVE feedback on Xilinx ISE.

As compared to what?

Xilinx ISE is the best development software for Xilinx FPGAs that
I've ever used.

Article: 114686
Subject: Re: Clock constraints
From: "skyworld" <chenyong20000@gmail.com>
Date: 22 Jan 2007 15:45:47 -0800
Links: << >>  << T >>  << A >>
thanks.


"Gabor =D0=B4=B5=C0=A3=BA
"
> skyworld wrote:
> > Hi,
> > I will input a differential clock to DCM, how should I set contraints?
> > Should I set constraint on IBUFGDS input or should I set constraint on
> > its output? And should I set constraints on DCM outputs? Thanks.
>
> Normally for pin-to-pin constraints you just use the positive pin
> of the differential input and the constraints otherwise work as
> they would for a single-ended clock.  If you put constraints on
> a DCM input or on the input pin that feeds the DCM, you
> shouldn't need constraints on the output of the DCM as well.  In
> fact often constraints on the outputs of DCM's are ignored
> in this case, because the timing analyzer uses the input
> constraints that were "pushed through" the DCM instead.
>=20
> HTH,
> Gabor


Article: 114687
Subject: Re: "Divide" a video line in two stripe
From: "Rob" <robnstef@frontiernet.net>
Date: Tue, 23 Jan 2007 03:20:34 GMT
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

------=_NextPart_000_003B_01C73E73.E1F6D680
Content-Type: text/plain;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Sylvain


I'm not familiar with Xilinx's memory architecture; but if their memory =
blocks have the option of being run in dual-port mode it could make this =
problem much easier to deal with. =20

=20

In the past I've taken advantage of other mfg's mixed-port =
read-during-write mode.  This mode is used when a RAM has one port =
reading and the other port writing to the same address location with the =
same clock. The memory block outputs the old data at the specified =
address when there is a simultaneous read during write to the same port. =
You then could set up two blocks (one for each half of the image) a line =
deep.



First fill the memory blocks with line 1



fill block a

*reset wraddr_a back to addr 0 and wait for block b to fill

fill block b

reset wraddr_b back to addr 0

now you read through the two blocks simultaneously while writing to the =
same address for block_a

reset wraddr_b back to addr 0

repeat *



You'll have two pointers for each memory block, one read and one write =
pointer.



I haven't done any work with DVI so I may be missing something specific =
to that interface.  If so, my apologies.



Take care,

Rob



"Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com> wrote in =
message news:1169454808.249472.167130@a75g2000cwd.googlegroups.com...
> Here's my problem :
>=20
> A have a video module (that I can't really change), that outputs a
> 3840x2400 image, by outputing two consecutive pixels at once (like
> dual-link DVI). The problem is that the screen to display that doesn't
> want dual-link DVI, it wants two independant DVI stream, one for the
> left part of the screen and another for the right part of the screen.
> (two "stripes" of 1920x2400).
>=20
> I'm trying to come up with a solution to "transform" one into another,
> without using a frame buffer nor storing more than 1 line of video.
> (At 3840, in color, that already is 6 Xilinx BRAMs and I'm a little
> short of those ...).
>=20
> According to my calculations, It should even be possible to only store
> half a line, but I prefer to have a 1 line delay than half a line
> delay.
> My problem is that I can't find how to do it ... Storing in BRAM has
> proven to be an addressing nightmare to store and reread =
simultaneously
> without overwriting data I haven't re-read yet ... (since I don't read
> in the same order that I write).
>=20
> Does anyone has done something similar or has a genius idea ? Because
> I'm missing something here, that should be simple and I just don't see
> it ...
>=20
>=20
> Sylvain
>
------=_NextPart_000_003B_01C73E73.E1F6D680
Content-Type: text/html;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2900.3020" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY><FONT size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial; mso-bidi-font-size: 7.5pt; =
mso-fareast-font-family: 'Times New Roman'; mso-ansi-language: EN-US; =
mso-fareast-language: EN-US; mso-bidi-language: AR-SA">
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">Sylvain<BR></SPAN></P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">I'm not familiar with =
Xilinx's=20
memory architecture; but if their memory blocks have the option of being =
run in=20
dual-port mode it could make this problem much easier to deal =
with.&nbsp;=20
<?xml:namespace prefix =3D o ns =3D =
"urn:schemas-microsoft-com:office:office"=20
/><o:p></o:p></SPAN></P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial">&nbsp;<o:p></o:p></SPAN></P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial; mso-bidi-font-size: =
12.0pt">In the=20
past I've taken advantage of other mfg's mixed-port read-during-write=20
mode.&nbsp; </SPAN><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial; mso-bidi-font-size: =
7.5pt">This mode=20
is used when a RAM&nbsp;has one port reading and the other port writing =
to the=20
same address location with the same clock. The memory block outputs the =
old data=20
at the specified address when there is a simultaneous read during write =
to the=20
same port. You then&nbsp;could set up two blocks (one for each half of =
the=20
image) a line deep.</SPAN></P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial; mso-bidi-font-size: =
7.5pt"></SPAN>&nbsp;</P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial; mso-bidi-font-size: =
7.5pt">First=20
fill the memory blocks with line 1</SPAN></P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial; mso-bidi-font-size: =
7.5pt"></SPAN>&nbsp;</P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial; mso-bidi-font-size: =
7.5pt">fill=20
block a</SPAN></P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial; mso-bidi-font-size: =
7.5pt">*reset=20
wraddr_a back to addr 0 and wait for block b to fill</SPAN></P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial; mso-bidi-font-size: =
7.5pt">fill=20
block b</SPAN></P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial; mso-bidi-font-size: =
7.5pt">reset=20
wraddr_b back to addr 0</SPAN></P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt">now you read through =
the two=20
blocks simultaneously while writing to the same address for block_a</P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt">reset wraddr_b back =
to addr 0</P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt">repeat *</P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt">&nbsp;</P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt">You'll have two =
pointers for each=20
memory block, one read and one write pointer.</P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt">&nbsp;</P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"></SPAN></FONT><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial; mso-bidi-font-size: =
7.5pt"><FONT=20
face=3DArial size=3D2>I haven't done any work with DVI so I may be =
missing something=20
specific to that interface.&nbsp; If so, my apologies.</FONT></SPAN></P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial; mso-bidi-font-size: =
7.5pt"></SPAN>&nbsp;</P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial; mso-bidi-font-size: =
7.5pt">Take=20
care,</SPAN></P>
<P class=3DMsoNormal style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial; mso-bidi-font-size: =
7.5pt">Rob</SPAN></P>
<DIV><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial; mso-bidi-font-size: =
7.5pt"><FONT=20
face=3DArial size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial; mso-bidi-font-size: =
7.5pt"><FONT=20
face=3DArial size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>"Sylvain Munaut &lt;</FONT><A=20
href=3D"mailto:SomeOne@SomeDomain.com"><FONT face=3DArial=20
size=3D2>SomeOne@SomeDomain.com</FONT></A><FONT face=3DArial =
size=3D2>&gt;"=20
&lt;</FONT><A href=3D"mailto:246tnt@gmail.com"><FONT face=3DArial=20
size=3D2>246tnt@gmail.com</FONT></A><FONT face=3DArial size=3D2>&gt; =
wrote in message=20
</FONT><A=20
href=3D"news:1169454808.249472.167130@a75g2000cwd.googlegroups.com"><FONT=
=20
face=3DArial=20
size=3D2>news:1169454808.249472.167130@a75g2000cwd.googlegroups.com</FONT=
></A><FONT=20
face=3DArial size=3D2>...</FONT></DIV><FONT face=3DArial size=3D2>&gt; =
Here's my problem=20
:<BR>&gt; <BR>&gt; A have a video module (that I can't really change), =
that=20
outputs a<BR>&gt; 3840x2400 image, by outputing two consecutive pixels =
at once=20
(like<BR>&gt; dual-link DVI). The problem is that the screen to display =
that=20
doesn't<BR>&gt; want dual-link DVI, it wants two independant DVI stream, =
one for=20
the<BR>&gt; left part of the screen and another for the right part of =
the=20
screen.<BR>&gt; (two "stripes" of 1920x2400).<BR>&gt; <BR>&gt; I'm =
trying to=20
come up with a solution to "transform" one into another,<BR>&gt; without =
using a=20
frame buffer nor storing more than 1 line of video.<BR>&gt; (At 3840, in =
color,=20
that already is 6 Xilinx BRAMs and I'm a little<BR>&gt; short of those=20
...).<BR>&gt; <BR>&gt; According to my calculations, It should even be =
possible=20
to only store<BR>&gt; half a line, but I prefer to have a 1 line delay =
than half=20
a line<BR>&gt; delay.<BR>&gt; My problem is that I can't find how to do =
it ...=20
Storing in BRAM has<BR>&gt; proven to be an addressing nightmare to =
store and=20
reread simultaneously<BR>&gt; without overwriting data I haven't re-read =
yet ...=20
(since I don't read<BR>&gt; in the same order that I write).<BR>&gt; =
<BR>&gt;=20
Does anyone has done something similar or has a genius idea ? =
Because<BR>&gt;=20
I'm missing something here, that should be simple and I just don't =
see<BR>&gt;=20
it ...<BR>&gt; <BR>&gt; <BR>&gt; Sylvain<BR>&gt;</FONT></BODY></HTML>

------=_NextPart_000_003B_01C73E73.E1F6D680--


Article: 114688
Subject: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP
From: "nagaraj" <nagarajputti@gmail.com>
Date: 22 Jan 2007 21:44:31 -0800
Links: << >>  << T >>  << A >>
Hi,

I m looking for differences between rocketio MGT and GTP (both
architectural as well as the way they are used).

please reply if anybody knows anything in this regard.


Thanks,
Nagaraj


Article: 114689
Subject: Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology
From: chris.hallahan@nuvation.com
Date: 22 Jan 2007 22:25:47 -0800
Links: << >>  << T >>  << A >>
Hello Anand,
Our company is a leading engineering services firm with a seasoned team
of algorithm acceleration specialists. There are numerous ways to
achieve your goal depending on your algorithm, budget, and tool
comfort.  For example, there are new FPGA solutions that can plug into
quad-Opteron sockets and co-process over a very high-speed, low-latency
bus such as Hypertransport.  These FPGA daughtercards can plug & play
but your algorithm will require a nontrivial effort for setup,
integration, analysis, and optimization.  Knowing C and HDL is
important, along with the associated tool flows (MATLAB, SysGen or DSP
Builder, ModelSim, Quartus or ISE, etc).  You might also consider some
of the hybrid FPGA-MCU devices from IPFlex, Stretch, and others.  And
there is always the embedded systems approach of using FPGAs, DSPs,
MCUs -- or a combination of such devices to achieve your
cost-performance goals.  On average, 40x acceleration is not uncommon.

If you are interested in engaging a professional firm, I am confident
that our team can architect a solution and help optimize your
algorithms to the fabric.  Feel free to contact us if we can be of
service.  www.nuvation.com
Kind regards,
Chris Hallahan


anand wrote:
> What are some of the considerations while migrating from a pure SW
> based bio-medical simulation to a HW based simulation/acceleration
> solution? Insights on both the business & technical considerations
> would be appreciated
> 
> Thanks
> Anand


Article: 114690
Subject: low speed USB interface for FPGAs
From: "vu_5421" <nugentoffer@gmail.com>
Date: 22 Jan 2007 23:29:25 -0800
Links: << >>  << T >>  << A >>
Hello all,

I am a college student experimenting with VHDL and currently using the
Spartan 3 starter kit. This particular kit (unlike the Spartan3e) does
not come with an onboard usb connector. I was hoping to add one and
bring in the D+ and D- lines directly into the FPGA I/O pins. I realize
that these signals are RS485 differential, and that the FPGA would
require LVTTL input.

I plan to hook a device like a usb mouse to this board, which would
only use USB1.1 standard, and I expect the swing to be somewhere around
3.3 to 3.6V, and the the tolerance would be safe enough to bring into
the FPGA. Is this something that can be done? I am still fumbling
around the thick USB manual, but I believe that it is possible.

Assuming that I am stuck with the current Spartan3 board, how can I
allow a low speed device like a mouse to interface with the FPGA? Thank
you very much for any insight you can offer.


Article: 114691
Subject: Re: how to use register to save data
From: backhus <nix@nirgends.xyz>
Date: Tue, 23 Jan 2007 08:37:31 +0100
Links: << >>  << T >>  << A >>

> backhus wrote:
>> ZHI schrieb:
>>> There are Matrix 4 by 4 R and Vector 4 by 1 B generated in
>>> Matlab. I transmitted these data to FPGA board. The 16 elements
>>> of R are saved in a RAM and the 4 elements of B are saved in
>>> another RAM.  Now I am thinking if it is possible to save these
>>> data in several registers.
>>> 
>>> For example: for k=1:4 B= B*2^mdiff - R(:,k) end
>>> 
>>> midff is a constant. It is seen that  B do update once need read
>>> R RAM and B RAM 4 times. So i wanna to save these data in several
>>> registers. Then  B can do one update operation in one clock cycle
>>> by reading all the data at the same time. But if i put one
>>> register following every element, i don't know how to index these
>>> different registers.  Does anybody  tell me how to figuer it out?
>>> Many thanks.
>>> 
>> Hi Zhi, how do you "transmit" the data to the FPGA Board? are you
>> using some tool like system designer that buids your bridge from
>> matlab to the FPGA?
>> 
>> Your problem would be simple to solve, if you were designing your 
>> datapath yourself in VHDL or verilog. But with automated
>> translation tools you have to figure out how to write matlab code
>> in a way that will be interpreted in the way you intend, rather
>> than the standard solution you get now.
>> 
>> Matlab sees every variable as a matrix. The most natural way of
>> storing matrices is ram. So the disigners of your translation tool
>> choose this solution for simplicity and generality. If you want
>> something special e.g. to speed up your design you have to tell the
>> tool.
>> 
>> My guess would be (and it's really just a guess!) that you have to 
>> specify a scalar variable for each matrix element, and don't use
>> loops cause loops may infer a copy from ram to register machine
>> which would not be what you intend.
>> 
>> have a nice synthesis Eilert
> 
> ZHI schrieb: I transmitted these data to FPGA board  by a serial link
> from Matlab. I use the serial commond like fwrite(s,R,'int8','async')
> to send the data to UART.   I did not use the translation tools. Now
> I am thinking can I try this way:
> 
> type array_type1 is array (0 to 3) of std_logic_vector (31 downto 0);
>  signal  arrayb: array_type1 :=(others=>(others=>'0'));
> 
> I define a new type and store these elements in the array type
> instead of the RAM.
> 
> 
Hi Zhi,
OK, so you are just feeding the matlab data to the FPGA and write your 
algorithm in VHDL yourself.

If you are defining an array type as described above it depends on the 
rest of your code whether your synthesis tool creates a ram or not.

if yo access all elements of the array at the same time, the synthesis 
tool will be forced to produce some parallel hardware using registers

e.g.

for i in arrayb'range loop
   arrayb(i) <= calculation_function(i);
end loop

You may use this loop inside a clocked process and all the calculations 
will happen in one clock cycle. This can only be done if the synthesis 
tool creates registers. If your calculations become more complex you 
should be aware of pipelining effects. Study the reader-driver model of 
VHDL for a better understanding (e.g. search this newsgroup about this 
topic)

have a nice synthesis
   Eilert

Article: 114692
Subject: Re: what happened to modular design in ISE9
From: backhus <nix@nirgends.xyz>
Date: Tue, 23 Jan 2007 08:40:04 +0100
Links: << >>  << T >>  << A >>
Hi Tim,
I read about partitions in the Tcl chapter of the ISE9 documentation, 
but haven't seen any further explanation about that flow yet. Do you 
have a link?
best regards
   Eilert

Tim Verstraete schrieb:
> i think they were replaced with the partitions flow (ISE8.2i)? or am i
> wrong?
> 
> backhus schreef:
>> Hi,
>> while Iwere reading some chapters of the new ISE9 Development System
>> Reference guide I happened to notice that the chapters about Incremental
>> Design and Modolar Design are gone.
>>
>> What happened? Have these approaches been dropped? If so, I would like
>> to know the reasons. Is there some new (better) approach? Or have these
>> chapters just moved to some yet unpublished ISE9 document? (I know they
>> are still available in the ISE8 doc files.)
>>
>> Best regards
>>    Eilert
> 

Article: 114693
Subject: Re: low speed USB interface for FPGAs
From: "Jon Beniston" <jon@beniston.com>
Date: 23 Jan 2007 00:49:22 -0800
Links: << >>  << T >>  << A >>

> I am a college student experimenting with VHDL and currently using the
> Spartan 3 starter kit. This particular kit (unlike the Spartan3e) does
> not come with an onboard usb connector. I was hoping to add one and
> bring in the D+ and D- lines directly into the FPGA I/O pins. I realize
> that these signals are RS485 differential, and that the FPGA would
> require LVTTL input.
>
> I plan to hook a device like a usb mouse to this board, which would
> only use USB1.1 standard, and I expect the swing to be somewhere around
> 3.3 to 3.6V, and the the tolerance would be safe enough to bring into
> the FPGA. Is this something that can be done? I am still fumbling
> around the thick USB manual, but I believe that it is possible.
>
> Assuming that I am stuck with the current Spartan3 board, how can I
> allow a low speed device like a mouse to interface with the FPGA? Thank
> you very much for any insight you can offer.

USB transceivers are cheap:

http://www.nxp.com/pip/isp1106.html

USB HDL can be found here:

http://www.opencores.org/projects.cgi/web/usbhostslave/overview

Cheers,
Jon


Article: 114694
Subject: Re: Different Modelsim versions disagree in same backannotation!
From: "Duth" <premduth@gmail.com>
Date: 23 Jan 2007 00:52:22 -0800
Links: << >>  << T >>  << A >>
Hi,

I agree with Kim. You should not get any of the warnings that you are
getting in 6.2e and 5.8 either. Ensure that the annotation is happening
at the correct instantiation.

Additionally, have you tired to run the simulation using the -novopt
switch? The one major difference is that vopt is on by default in 6.2
versions.

I would not say that this is necessarily a bad thing to have vopt on,
although there could be some issues in the vopt algorithm and a simple
test to look at this is to disable the vopt, by using the -novopt in
both compilation and simulation commands.

Thanks
Duth


Kim Enkovaara wrote:
> spectrallypure wrote:
> >> #3 - Why are you set at 1ns resolution? Is this a *very* slow chip? I
> >> bet your sim models are set to 1ps; I'd suspect a rounding problem somewhere.
> > We also think the problem might have to do with this. I just set the
> > resolution to 1ns because that is the value of the resolution of the
> > SDF files, but I have experimented by changing this value and the
> > timing of the waveform changes A LOT. However, I haven't been able to
> > make the simulation give the expected results by tweaking this
> > parameter. The operating frequency of the design is 50MHz.
>
> You should set the resolution to what the models expect, nowadays the
> resolution is usually 1ps or 10ps. The models can behave incorrectly
> if the resolution is not correct.
>
> And also the SDF must be generated from the layout tools with the same
> or better resolution. 1ns resolution for the SDF files sounds very
> large, unless you use some exotic or old process. Even for 0.13u process
> 1ps resolution is sometimes too high in STA.
>
>
> >> #4 - What do you get if you enable sdf warnings & errors?
> >
> > In 5.8b I get a lot (nearly 50,000) of the following warnings:
> >
> > # ** Warning: (vsim-SDF-3262) ./DFM_TC_Worst.pt.sdf(<-SDF line number
> > here->): Failed to find matching specify timing constraint.
> >
> > ... but the simulation works. On the other hand, in 6.2e, I get this
> > same error but a lot more times (something like three times more), I
> > additionally I get the following error (once again, I get it a lot of
> > times):
> >
> > # ** Warning: (vsim-SDF-3261) ./DFM_TC_Worst.pt.sdf(<-SDF line number
> > here->): Failed to find matching specify module path.
>
> Normally you should not get any warnings or errors from the annotation.
> They usually tell that the SDF is annotated to a wrong place or
> simulation models do not match the synthesis models (library version
> mismatch etc.). You should manually compare the SDF and the models to
> see why the errors are there. I have seen usually warnings in special
> analog cells, IO-testing structures etc. that are quite hard to model in
> simulation.
>
> 50k errors is too much, <100 warnings for few gigabyte SDF sounds normal
> figure. The tool might do things differently in error conditions
> depending on versions.
> 
> 
> --Kim


Article: 114695
Subject: Re: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 23 Jan 2007 08:58:56 -0000
Links: << >>  << T >>  << A >>
"nagaraj" <nagarajputti@gmail.com> wrote in message 
news:1169531071.292150.65370@v45g2000cwv.googlegroups.com...
> Hi,
>
> I m looking for differences between rocketio MGT and GTP (both
> architectural as well as the way they are used).
>
> please reply if anybody knows anything in this regard.
>
>
> Thanks,
> Nagaraj
>
The spelling's different.
Syms.

RTFM. 



Article: 114696
Subject: Re: low speed USB interface for FPGAs
From: "Antti" <Antti.Lukats@xilant.com>
Date: 23 Jan 2007 01:01:50 -0800
Links: << >>  << T >>  << A >>
vu_5421 schrieb:

> Hello all,
>
> I am a college student experimenting with VHDL and currently using the
> Spartan 3 starter kit. This particular kit (unlike the Spartan3e) does
> not come with an onboard usb connector. I was hoping to add one and
> bring in the D+ and D- lines directly into the FPGA I/O pins. I realize
> that these signals are RS485 differential, and that the FPGA would
> require LVTTL input.
>
> I plan to hook a device like a usb mouse to this board, which would
> only use USB1.1 standard, and I expect the swing to be somewhere around
> 3.3 to 3.6V, and the the tolerance would be safe enough to bring into
> the FPGA. Is this something that can be done? I am still fumbling
> around the thick USB manual, but I believe that it is possible.
>
> Assuming that I am stuck with the current Spartan3 board, how can I
> allow a low speed device like a mouse to interface with the FPGA? Thank
> you very much for any insight you can offer.

it has been done by japanese, there is an project that has specialized
tiny processor that implements the mouse host usb stuff

Antti


Article: 114697
Subject: Re: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP
From: "nagaraj" <nagarajputti@gmail.com>
Date: 23 Jan 2007 01:05:45 -0800
Links: << >>  << T >>  << A >>

Symon wrote:
> "nagaraj" <nagarajputti@gmail.com> wrote in message
> news:1169531071.292150.65370@v45g2000cwv.googlegroups.com...
> > Hi,
> >
> > I m looking for differences between rocketio MGT and GTP (both
> > architectural as well as the way they are used).
> >
> > please reply if anybody knows anything in this regard.
> >
> >
> > Thanks,
> > Nagaraj
> >
> The spelling's different.
> Syms.
>
> RTFM.




Sorry I didn't get u....!

let me be clear first.

I mean difference between virtex 4 Multi gigabit Tranceiver and its
virtex 5 counter part.


thanks,
nagaraj


Article: 114698
Subject: XdmHelpers:662
From: "skyworld" <chenyong20000@gmail.com>
Date: 23 Jan 2007 01:09:44 -0800
Links: << >>  << T >>  << A >>
Hi,

when I use ISE8.2 to do synthesis and P&R for my fpga (Virtex 4)
design, I got such message:

  WARNING:XdmHelpers:662 - Period specification
   "TS_u_DigRF_top_u_v4_clkgen_clk26_buf" references the TNM group
   "u_DigRF_top_u_v4_clkgen_clk26_buf", which contains both pads and
synchronous
   elements. The timing analyzer will ignore the pads for this
specification.
   You might want to use a qualifier (e.g. "FFS") on the TNM property
to remove
   the pads from this group.

Does anybody knows what it mean and how to solve it? thanks very much.


Article: 114699
Subject: iMPACT dont shows erase write options with fpga
From: "blisca" <bliscachiocciolinatiscali.it>
Date: Tue, 23 Jan 2007 10:25:08 +0100
Links: << >>  << T >>  << A >>
Hi to all

i'm a beginner tryin to build some application with a scraped xc2v3000

after generating a bit file with the ISE,i try to configure the FPGA ;iMPACT
recognizes it but it looks that there is no erase or write option active

consider that:
my board is home made
the device is a virtex2 that as you know better than me it has a 1,5V
core,but my programming cable (digilent) is rated down to 1,8V

thank you

Diego





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