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Brandon Jasionowski wrote: > Btw, what is the default IOSTANDARD, if not specified in the UCF, for > differential and single-ended pins. I thought I remember reading it > somewhere, but I can't find that reference anymore. For single-ended pins it's LVCMOS25. Not sure for differential signals, but I would assume it's LVDS25. -- My email address is only valid until the end of the month. Go figure what the address is going to be after that...Article: 114451
Just tell us what incoming frequency you have available, and which frequencies you want to generate. That would simplify the discussion. BTW: it is MHz, named after Heinrich Hertz. Peter Alfke ======== On Jan 16, 12:56 am, "axalay" <axa...@gmail.com> wrote: > I am generate 2.048 MGz with jitter ~5ns if FPGA. I need to reduse > jitter and vander using the digital filter. Tell me please what tipes > of filters will solve this problems. > > And next question. I whant generate 19.44 MGz (whith good gitter and > vander) from that 2.048 MGz whith use external VCO. I see 2 ways: > > 1) use digital faze detector, which generate 2 signais : charge and > discharge the external capasitor (to operate the VCO). > 2) use digital PI regulator, which generate PWM. ANd use external > filter. > > Ho from 2 ways better?Article: 114452
I'm working on modifying a design in order to meet my needs and am having trouble coming up with a workable soltuion. It mainly centers around some different clock domains. This design is for a Virtex-4 SX55 FPGA. The base design that I am starting from has 4 ADC inputs which come in with individual source synchronous clocks. They are registered using BUFIO/BUFR region clock paths and then stored into a FIFO upon receipt of an asynchronous pulse from another clock domain. The same pulse is received by all four of the ADC regional clock domains, which are all the same frequency with some fixed phase offset. Therefore, depending on when the pulse arrives at each of the domains, one, two, or three of the ADC data streams will get stored at a one clock offset from the other ones. The captures seem to occur properly ~ 50% of the time, indicating that all of the clocks are phase offset within half of the clock period. What I'd like to do is ensure that all four of the the data streams are captured at the proper point in time every single capture. I had thought that all each of the IOB FF's to be clocked by the individual BUFIOs and then selecting one clock signal to be a BUFG which would feed all of the logic after the input buffers would be the right way to go (trial and error would decide which of the 4 individual clocks would get data that is aligned properly in time, since the phase offsets are fixed, one of the four clocks should always give proper data). Unfortunately, when I try this design, it fails to route the new global clock path (both with and without a DCM in the chain). Does anybody have any idea what might be a good solution to this problem? In summary: Current design (4 ADs, 4 Clocks -> 4 BUFIOs -> 4 BUFRs -> logic in 4 clock domains and 1 asynchronous capture pulse to all) Attempted design (4 ADs 4 Clocks -> 4 BUFIOs -> 1 BUFG (selected from 4 BUFIOs) -> logic in 1 clock domain so asynchronous capture pulse is guaranteed to go at the same clock for all four data streams) Thanks for your help! JohnArticle: 114453
Dear all, I am new to both FPGA and CPU design. I am supposed to implement a CPU on FPGA. The CPU is described in www.homebrewcpu.com. It needs to be exactly the same. Currently I am working on translating the microcodes into verilog. It just seems too complex currently and I do not know where I can seek for more information on how to do this. Any advice or guidance will be much appreciated. Thanks! CHeers, JalenArticle: 114454
Jalen.Ong@gmail.com wrote:
> I am new to both FPGA and CPU design. I am supposed to implement a CPU
> on FPGA. The CPU is described in www.homebrewcpu.com. It needs to be
> exactly the same.
That strikes me as a very unimaginative assignment.
I would drop the class and find something
more creative and interesting.
-- Mike Treseler
Article: 114455thought it was an interesting article... <http://www.playfuls.com/news_05850_HP_Engineers_Defy_Moores_Law_New_Nano_Chip_Prototype_in_2008.html> <http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=JK1JAR34VQSMIQSNDLOSKHSCJUNN2JVN?articleID=196901012> <http://ej.iop.org/links/rZ4GbW1Ei/Iovyg5-l2xG7v7HLav5vpA/nano7_3_035204.pdf>Article: 114456
Dale, What are you trying to do with MGTs? I have recently got two V4 FPGAs (one CES2, another CES4) streaming to each other at 3.36 Gbps using simplex Aurora cores. The learning curve wasn't easy, but in the end everything worked as a charm! /Mikhail "Dale" <dale.prather@gmail.com> wrote in message news:1168541088.454548.159100@i39g2000hsf.googlegroups.com... > Is it just me or is the documentation for the RocketIO (MGT) for the > Xilinx Virtex4 very bad? I'm trying to find duty cycle requirements > for the MGT clock. Is it OK to use a clock with a 40% duty cycle? > > Also, if anyone can point me to some better RocketIO (MGT) > documentation for the hardware guys I'd appreciate it. I already have > ug076. > > Thanks, > Dale >Article: 114457
Yes, it is (interesting). The one big problem that I see is that 20% of the connections don't work, and the defects are random. So, the chip has to also be able to provide self-healing, or self-routing that is self-testing, or something like that in order to function. Timing closure is yet another issue with random wires and faults. HP was also pretty harsh: "multi-core is an admission of failure" is pretty nasty to be saying about Intel's strategy. Not sure who reviewed that press release. There is a long way to go until there is a product that makes use of this technology, but it means that as an IC designer, I am likely to stay employed. AustinArticle: 114458
skyworld wrote: > Hi, > I need to generate four clocks with DCM in VIRTEX4. The frequency is > 312MHz. I can't get any output from clk_90 and clk_270. I contacted > Xilinx's FAE and they told me there is no output from 90/270 phase > shift when DCM works at high speed mode. Does anybody know how to > generate these four clocks with equal phase shift in VIRTEX 4? thanks > very much. Multiple DCM's? Phase shift capabilities of DCM's? ChipSync? To name a few.... What's 312 MHz for?Article: 114459
Austin Lesea wrote: > Yes, it is (interesting). > > The one big problem that I see is that 20% of the connections don't > work, and the defects are random. > > So, the chip has to also be able to provide self-healing, or > self-routing that is self-testing, or something like that in order to > function. Timing closure is yet another issue with random wires and faults. > > HP was also pretty harsh: "multi-core is an admission of failure" is > pretty nasty to be saying about Intel's strategy. Not sure who reviewed > that press release. > > There is a long way to go until there is a product that makes use of > this technology, but it means that as an IC designer, I am likely to > stay employed. > > Austin > > The author said it might be available as soon as *2020*. In terms of electronics, that is several lifetimes away. It might as well be science fiction. Most of us will be contemplating retirement before that "optimistic" date arrives, and somehow I doubt that the design landscape will even resemble what it is now.Article: 114460
hey guys... can u please tell me a method to reduce the clock frequency of the FPGA using counters puneetArticle: 114461
Use a DCM(xilinx) or PLL (altera), or keep the clock frequency the same and use clock enables to run this logic at a lower rate, or use a counter to reduce the clock frequency. What are you trying to do? psgandhi@gmail.com wrote: > hey guys... > > can u please tell me a method to reduce the clock frequency of the FPGA > using counters > > puneetArticle: 114462
Hi motty, I need four equally-spaced sample phases to sample input data so that jitter will not cause any problem. The input data rate is 312MHz. So I need clk0, clk90, clk180 and clk270 with 312MHz working frequency. The DCM can be used to generate these four phase clocks, but it can't support such high frequency in Virtex 4. With Phase shift capabilities of DCM's, ChipSync, I am not familiar to them. Can you explain it more detail? thanks. "motty =D0=B4=B5=C0=A3=BA " > skyworld wrote: > > Hi, > > I need to generate four clocks with DCM in VIRTEX4. The frequency is > > 312MHz. I can't get any output from clk_90 and clk_270. I contacted > > Xilinx's FAE and they told me there is no output from 90/270 phase > > shift when DCM works at high speed mode. Does anybody know how to > > generate these four clocks with equal phase shift in VIRTEX 4? thanks > > very much. > > Multiple DCM's? Phase shift capabilities of DCM's? ChipSync? >=20 > To name a few.... >=20 > What's 312 MHz for?Article: 114463
>From my experience in college project related courses the instructor would encourage the students to come up with their own ideas but if they don't come up with acceptable proposals for projects they have a list for alternative projects. I found the type of projects on the alternative list usually were of the type that would encourage me find my own. Another possibility is it is early in the semester or quarter and this could be example of an introductory project and the instructor found something about it that he can use as a vehicle for later work. And instructors are required to teach using a specific type of project and they have to change the specifics so that students don't re-use prior work or projects found on the web. Besides how many examples do we really need of PDP-8, PDP-11, DLX and MIPS processors? Mike Treseler wrote: > Jalen.Ong@gmail.com wrote: > > > I am new to both FPGA and CPU design. I am supposed to implement a CPU > > on FPGA. The CPU is described in www.homebrewcpu.com. It needs to be > > exactly the same. > > That strikes me as a very unimaginative assignment. > I would drop the class and find something > more creative and interesting. > > -- Mike TreselerArticle: 114464
skyworld wrote: > Hi motty, > > I need four equally-spaced sample phases to sample input data so that > jitter will not cause any problem. The input data rate is 312MHz. So I > need clk0, clk90, clk180 and clk270 with 312MHz working frequency. The > DCM can be used to generate these four phase clocks, but it can't > support such high frequency in Virtex 4. With Phase shift capabilities > of DCM's, ChipSync, I am not familiar to them. Can you explain it more > detail? thanks. > Is your 312 MHz clock input to the FPGA or is it derived internally using a DCM clocked from some other input clock? Is the data phase-related to the clock? If it is realted to the 312 clock, then how BAD is the jitter? How closed will the data eye be? The DCM's feature a finite phase shifting capability. I can't remember the frequency limits associated with using it, but that info can be found in the Virtex4 documentation. There would likely be issues with aligning the clocks from different DCM's. If you really need 4 phases at that speed it may be better using the IDELAY's that are available on the FPGA I/O's. You'd have to input as many data streams as you need phases for though. Instead of using multiple clocks, you'd use multiple time-offset data streams. Each option has its technical problems and challenges associated with it. Again, all the information on the technolgy can be found in the Virtex4 documentation, applications notes, etc.Article: 114465
Ray Andraka wrote: > The author said it might be available as soon as *2020*. In terms of > electronics, that is several lifetimes away. It might as well be > science fiction. Most of us will be contemplating retirement before > that "optimistic" date arrives, and somehow I doubt that the design > landscape will even resemble what it is now. I did see earlier notes on beam cross-bars, which sounded real, but the HP stuff is 100% vaporware, as they have only simulated it. It will be impressive if, when they finally build it (~end 2007), it works as simulated :) No comments on OTP or Reprogrammable, but either way, defect coverage sounds like expensive testing time. Why is HP researching this stuff ? -jgArticle: 114466
well, the 312MHz clock is a input to FPGA. I do need four phases to sample the data so that data jitter could be reduce. It is very interesting that DCM could not output clk90 and clk270 when set it to high speed mode -- i got this information from Xilinx FAE and simulated this with ModelSim, but their datasheet and user guide doesn't mention this. My design has based on these four pahse clock and DCM performance and my PCB is ready for this. I have to find a way to solve this. by the way, what do you mean by that "IDELAY"? thanks. "motty =D0=B4=B5=C0=A3=BA " > skyworld wrote: > > Hi motty, > > > > I need four equally-spaced sample phases to sample input data so that > > jitter will not cause any problem. The input data rate is 312MHz. So I > > need clk0, clk90, clk180 and clk270 with 312MHz working frequency. The > > DCM can be used to generate these four phase clocks, but it can't > > support such high frequency in Virtex 4. With Phase shift capabilities > > of DCM's, ChipSync, I am not familiar to them. Can you explain it more > > detail? thanks. > > > > Is your 312 MHz clock input to the FPGA or is it derived internally > using a DCM clocked from some other input clock? Is the data > phase-related to the clock? If it is realted to the 312 clock, then > how BAD is the jitter? How closed will the data eye be? > > The DCM's feature a finite phase shifting capability. I can't remember > the frequency limits associated with using it, but that info can be > found in the Virtex4 documentation. There would likely be issues with > aligning the clocks from different DCM's. > > If you really need 4 phases at that speed it may be better using the > IDELAY's that are available on the FPGA I/O's. You'd have to input as > many data streams as you need phases for though. Instead of using > multiple clocks, you'd use multiple time-offset data streams. > > Each option has its technical problems and challenges associated with > it. Again, all the information on the technolgy can be found in the > Virtex4 documentation, applications notes, etc.Article: 114467
Mike Treseler wrote: > Jalen.Ong@gmail.com wrote: > > > I am new to both FPGA and CPU design. I am supposed to implement a CPU > > on FPGA. The CPU is described in www.homebrewcpu.com. It needs to be > > exactly the same. > > That strikes me as a very unimaginative assignment. > I would drop the class and find something > more creative and interesting. > > -- Mike Treseler I wouldn't call it very unimaginative, but I can see that it would severely test the average noob undergrad, with their narrow experience. I had a quick look at the design, and it uses a very TTL centric approach, even to deploying FIVE x 8 bit PROMs to do both Opcode and Strobe work. Nifty in TTL days, but I fear too much for a HDL coder to grasp. I could not see a clean opcode listing, but a better assignment might be to take the Lattice open source Mico8, and port it to cover the CPU above. -jgArticle: 114468
jonas@mit.edu schrieb: > Has anyone found or could recommend a small(ish) processor for more > complex state machine tasks that is: > > 1. ~1000 LUTs or so (smaller is better) > 2. available under a free license (say, GPL, LPGL, BSD) > 3. available in vhdl? > > Ideally something like picoblaze would probably do what I want, except > that it's not under any of the available licenses, and pacoblaze is > vhdl (and potentially an IP nightmare). I've found a bunch of small > processors on opencores and the like but many of them look > half-finished. Any recommendations? These state machines are driving me > mad! > > Thanks! > > ...Eric there is "avalon micro sequencer" at altera website. and there exists a statemachine compiler from russia, I translated the docs to english but then new release did come out and I havent looked at changes or updated the docs. this sequences does come with its own compiler, that generates the microcode. AnttiArticle: 114469
"""Peter Alfke ΠΙΣΑΜ(Α): """ > Just tell us what incoming frequency you have available, and which > frequencies you want to generate. > That would simplify the discussion. > BTW: it is MHz, named after Heinrich Hertz. > Peter Alfke I do SDH (STM1-STM16) synchronization circuit. :) and sorry for my bad englishArticle: 114470
> Has anyone use the PLB DDR controller for the PowerPC in the EDK 7.1? > I have implented it in my design and it takes 150 clock counts for the > PowerPC to read or write data in the DDR memory. I think its too slow! Probably you don't have the burst option enabled. It will cost a few more LUTs, but as you've seen, performance is disastrous without it. Cheers, Peter MontaArticle: 114471
>Jhlw <james.h.w@gmail.com> >Jhlw wrote: > Hello All, > > I figured out how to run an application from external memory in Xilinx. > I have EDK ver 8.2.01i and an ML403 board. > What you do is "Mark to init BRAMs" on the default bootloop app in > the Applications window pane, update your bitstream and then load > it into the board using iMPACT. > Change your linker script using "Generate Link Script" for your > large application and set the .text section to SRAM. Rebuild your > app. > I have done upto this in ML402 board.But I am not able to run program from external memory. > You also have to set the .boot section (0x00000010) to SRAM. How to set the .boot section? Have I to create a new section and select memory as SRAM.But it shows "0 bytes" and I couldn't select the address - 0x00000010.And I am not able to run application from external memory.Pls.advice me.Thanks Regards, R.BalArticle: 114472
"""Andrew FPGA =D0=BF=D0=B8=D1=81=D0=B0=D0=BB(=D0=B0):
"""
> Use a DCM(xilinx) or PLL (altera),
> or keep the clock frequency the same and use clock enables to run this
> logic at a lower rate,
> or use a counter to reduce the clock frequency.
>
Example (in Verilog):
Generate 8.192 (2.048 * 4) MHz from 19.44 MHz workin on 155.52 (19.44 *
8) MHz
This metod generete parazitic jitter.
//=C3=8C=C3=AE=C3=A4=C3=B3=C3=AB=C3=BC =C3=B4=C3=AE=C3=B0=C3=AC=C3=A8=C3=B0=
=C3=B3=C3=A5=C3=B2 =C3=A8=C3=A7 155.52 =C3=8C=C3=83=C3=B6 8.192 =C3=8C=C3=
=83=C3=B6
//=C3=84=C3=AB=C3=BF =C3=BD=C3=B2=C3=AE=C3=A3=C3=AE =C3=AD=C3=A5=C3=AE=C3=
=A1=C3=B5=C3=AE=C3=A4=C3=A8=C3=AC=C3=AE =C3=A2=C3=BB=C3=A4=C3=A0=C3=B2=C3=
=BC 126 =C3=B0=C3=A0=C3=A7 10
=C3=AF=C3=A5=C3=B0=C3=A8=C3=AE=C3=A4=C3=AE=C3=A2 =C3=A8 130 =C3=B0=C3=A0=C3=
=A7 9 =C3=AF=C3=A5=C3=B0=C3=A8=C3=AE=C3=A4=C3=AE=C3=A2
//4 =C3=AB=C3=A8=C3=B8=C3=AD=C3=A8=C3=B5 9 =C3=AF=C3=A5=C3=B0=C3=A8=C3=AE=
=C3=A4=C3=AE=C3=A2 =C3=A2=C3=BB=C3=A4=C3=A0=C3=A5=C3=AC =C3=AD=C3=A0 1-=C3=
=A9, 64-=C3=A9,
128-=C3=A9 =C3=A8 193-=C3=A9 =C3=B0=C3=A0=C3=A7=C3=BB
module divide_clk (RESET, iCLK, oCLK);
input RESET;
input iCLK;
output oCLK; reg oCLK;
reg [7:0] aCOUNT; //=C3=91=C3=B7=C3=A5=C3=B2=C3=B7=C3=A8=C3=AA
reg [4:0] bCOUNT; //=C3=91=C3=B7=C3=A5=C3=B2=C3=B7=C3=A8=C3=AA =C3=
=A8=C3=AD=C3=B2=C3=A5=C3=B0=C3=A2=C3=A0=C3=AB=C3=A0 9 =C3=A8=C3=AB=C3=A8
10 CLK
always @(posedge iCLK) begin
if (!RESET) begin
oCLK =3D 0;
aCOUNT =3D 0;
bCOUNT =3D 0;
end //if
else begin
if (aCOUNT <=3D 63 || (aCOUNT >=3D 128 && aCOUNT <=3D 191))
begin
if (aCOUNT =3D=3D 0 || aCOUNT =3D=3D 128 || aCOUNT[=
0]
=3D=3D 1) begin
if (bCOUNT < 17) begin
if (bCOUNT =3D=3D 8) oCLK =3D 1;
bCOUNT =3D bCOUNT + 1;
end
else begin
oCLK =3D 0;
bCOUNT =3D 0;
aCOUNT =3D aCOUNT + 1;
end
end //if
else if (aCOUNT[0] =3D=3D 0) begin
if (bCOUNT < 19) begin
if (bCOUNT =3D=3D 9) oCLK =3D 1;
bCOUNT =3D bCOUNT + 1;
end
else begin
oCLK =3D 0;
bCOUNT =3D 0;
aCOUNT =3D aCOUNT + 1;
end
end //else if
end //if
else begin
if (aCOUNT[0] =3D=3D 1) begin
if (bCOUNT < 19) begin
if (bCOUNT =3D=3D 9) oCLK =3D 1;
bCOUNT =3D bCOUNT + 1;
end
else begin
oCLK =3D 0;
bCOUNT =3D 0;
aCOUNT =3D aCOUNT + 1;
end
end //if
else begin
if (bCOUNT < 17) begin
if (bCOUNT =3D=3D 8) oCLK =3D 1;
bCOUNT =3D bCOUNT + 1;
end
else begin
oCLK =3D 0;
bCOUNT =3D 0;
aCOUNT =3D aCOUNT + 1;
end
end //else
end //else
end //else=20
end //always=20
endmodule //divide_clk
Article: 114473Thanks Joel Joel Kolstad wrote: > "Ian" <ian.shee1@gmail.com> wrote in message > news:1168923096.202584.258410@v45g2000cwv.googlegroups.com... > > "The core's synchronous input control signals > > (START, ND, BYPASS, CE) are not registered inside thecore. > > It is assumed these will be registered external to the core if > > required" > > > > What is the difference between a core with REGISTERED Input and > > one WITHOUT REGISTERED input? > > It means the control signals mentioned are coming out of a flip-flop that's > clocked off the same clock that's running to the core. > > > Does one have the advantage over the other? > > Well, if you don't synchronize your control signals to the core's clock, you > potentially end up with metastability problems (when you inadvertently > violate the set-up and hold times of the core's internal flip-flops) and the > core will just generate garabge data for you! Granted, for signals like > BYPASS, CE, etc., it'll probably recover sooner or later, but the idea is > that without synchronization there's no guarantee the thing works at all. > > The only disadvantages of the core registering the inputs itself would be > that (1) it uses up additionally flip-flops and (2) it introduces another > clock cycle of latency. In many cases this is a negligible difference, but > since many people already have synchronous control signals running around > anyway, Xilinx figures they'll go for the ever-so-slightly higher > performance/lower gate count solution. > > > Would adding a Delay Flip-flop do? > > Just add a regular old flip-flop. Assuming the core came with a timing > constrains file, place and route will automatically, uh... place and route > the flip-flops such that the set-up and hold times are met on the control > signals. > > ---JoelArticle: 114474
Hi everyone, it happened to me that by chance I interrupted ModelSim not properly (to be honest I cannot say what happened) and on the next start it showed me this message: Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use I tried to remove the file, thinking (uncorrectly I suppose) that the program would have generate a new one, but it didn't work. I found on some forums that is a problem of license but I have a Libero web license, so if it was so I would have had problems with Libero and Synplify as well (they are all under the same license). Could you please explain me what happened? Thanks a lot Al -- Alessandro Basili CERN, PH/UGC Hardware Designer
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