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Messages from 114225

Article: 114225
Subject: Re: (-1)*xn operation in FPGA
From: "Thomas Stanka" <usenet_10@stanka-web.de>
Date: 8 Jan 2007 00:33:10 -0800
Links: << >>  << T >>  << A >>
Hi,

SunLei schrieb:
>     in C programming,it's easy to get a negative value of any variables, as
> minus -xn; in FPGA, suppose it's 16bit 2's complement number format, how to
> compute a negative value of a given number 'xn'? I mean, there must be a
> solution to get the result easily, not "reverse every 16-bits first,and add
> 1" to get the result.
>     I am confused about this, there must be something wrong with my
> understandings.

The sollution of inverting every single bit is easy in (V)HDL (unlike
to C).
a <= not a;

There is _no_ general negative value of any variable. Unless you
specify the variable to be  of type signed (not in the code, but in
your brain).
A variable stands for a  number of registers assigned together. The
semantic of this registerbank is up to you. you could use a 32 bit
register as a representation of a signed integer, than it is easy to
invert by bitwise negation and adding of -1. If your register
represents a unsigned value there is no negative specified. But the
value could also be a IEEE floating point which requires only a
inversion of the sign bit to get the negative value.

On bit level you use the NOT function, on all other level you need to
specify the datatype for yourself.

bye Thomas


Article: 114226
Subject: Re: Use Multi-cycle Path or Pipeline?
From: "Hans" <hans64@ht-lab.com>
Date: Mon, 08 Jan 2007 09:56:07 GMT
Links: << >>  << T >>  << A >>

"Davy" <zhushenli@gmail.com> wrote in message 
news:1168222080.317023.115720@v33g2000cwv.googlegroups.com...
> Hi all,
>
> In normal design we'd like to pipeline large comb logic to pipelined
> design. But I heard there is Multi-cycle Path and need more complex
> control logic.

The only logic required is to tell when the output is valid. This can for 
example be a simple counter/shift register/fsm etc controlling a FF enable 
pin.

>
> I have some questions according to it.
> 1. Is most design style don't recommend Multi-cycle Path?

It has nothing to do with recommendations, it is a design issue. If you have 
a large combinatorial block and the output is not required every clock cycle 
then why pipeline it? Adding an MCP constraint is much quicker and might 
also helps your backend tool meeting timing.

> 2. Can I change all Multi-cycle Path to Pipelined Path?

without any further details, yes.

> 3. Can I change all Pipelined Path to Multi-cycle Path?

without any further details, yes.

> 4. In what circumstance shall we need Multi-cycle Path?

As above, also if you use the enable input of a FF then you might already 
have a MCP and not be aware of it :-)

>
> Any recommending reading material is welcome!

I would suggest the Design compiler reference manual (you can find this on 
the web) which has some example of MCP's, also have a look at 
http://www.fishtail-da.com/

Hans
www.ht-lab.com


>
> Best regards,
> Davy
> 



Article: 114227
Subject: Re: Ones' complement addition
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Mon, 08 Jan 2007 02:18:02 -0800
Links: << >>  << T >>  << A >>
Koen Van Renterghem wrote:

> glen herrmannsfeldt wrote:

(snip regarding ones complement adder)

>  > You need the end-around carry.  It is pretty easy with a carry
>  > lookahead adder to wire the carry out back to the carry in.
>  > (snip)

>  > You should only need a 16 bit adder with carry in/carry out.

>  > assign {carry,result} = a+b+carry;

>  > The worst case is where the carry propagates 16 bits.
>  > (Well, the full width.)  It never goes farther than that.

> I previously tried this approach, but that resulted in synplify and 
> xilinx complaining about a combinatorial loop created by connecting the
> carry-out to the carry-in of the adder. That is why I started using a
> dedicated 16 bit adder to calculate the carry. This carry is then
> applied to a second adder.

The delay will be at most one trip around the carry loop, but
the tools don't know that.  It might be that there is a way
to tell the system the delay.  You will have to include the
end-around carry through the routing fabric, which will depend
on the routing.

> The statement you suggested will save area, but is there a proper way to
> constrain it? Right now the combinatorial loop seems to be ignored in 
> timing analysis :

It is nice that it figures out that there is a loop, and to ignore
it.  Unless it can specifically recognize ones complement adders,
I don't think there is anything else it could do.  That might be
one to ask synplify.

-- glen


Article: 114228
Subject: CREATE FPGA-PC CONNECTION (LWIP, XILNET)
From: "Pablo" <pbantunez@gmail.com>
Date: 8 Jan 2007 02:20:06 -0800
Links: << >>  << T >>  << A >>
Can anyone tell me some code to probe socket connection between PC and
my Spartan 3E?. I have created projects with Xilnet and LWIP but I have
not finished anyone. I only want to send and receive information with
PC but every code is designed to create a html server. With LWIP I have
used RAW_API.


Article: 114229
Subject: Re: (-1)*xn operation in FPGA
From: "KJ" <kkjennings@sbcglobal.net>
Date: Mon, 8 Jan 2007 07:13:12 -0500
Links: << >>  << T >>  << A >>

"SunLei" <iamsunlei@gmail.com> wrote in message 
news:enssgp$24b$1@news.cn99.com...
> Hi,
>
>    in C programming,it's easy to get a negative value of any variables, as
> minus -xn; in FPGA, suppose it's 16bit 2's complement number format, how 
> to
> compute a negative value of a given number 'xn'? I mean, there must be a
> solution to get the result easily, not "reverse every 16-bits first,and 
> add
> 1" to get the result.
>    I am confused about this, there must be something wrong with my
> understandings.
>

-xn works the same way in VHDL as it is does in C.  The signal (or variable) 
xn being defined to be the appropriate type:

signal xn, something: signed (15 downto 0);    -- Example 1
signal xn, something: integer range -32768 to 32767;    -- Example 2

....

something <= -xn;    -- Valid for either Example 1 or 2.

Kevin Jennings



Article: 114230
Subject: Re: Use Multi-cycle Path or Pipeline?
From: Jerome <jeje@.com>
Date: Mon, 08 Jan 2007 13:41:39 +0100
Links: << >>  << T >>  << A >>


Davy a écrit :
> Hi all,
>
> In normal design we'd like to pipeline large comb logic to pipelined
> design. But I heard there is Multi-cycle Path and need more complex
> control logic.
>
> I have some questions according to it.
> 1. Is most design style don't recommend Multi-cycle Path?
No, there is no such recommendation.
> 2. Can I change all Multi-cycle Path to Pipelined Path?
> 3. Can I change all Pipelined Path to Multi-cycle Path?
> 4. In what circumstance shall we need Multi-cycle Path?
For the previous points perhaps, but you really have to describe your
design as it is.
For example, a configuration register, going in logic using the same
clock, is a real multicycle path.
>
> Any recommending reading material is welcome!
>
> Best regards,
> Davy
>

Article: 114231
Subject: Re: Build an FPGA programmer cable
From: "Guenter" <GHEDWHCVEAIS@spammotel.com>
Date: 8 Jan 2007 05:27:35 -0800
Links: << >>  << T >>  << A >>
Timo Schneider wrote:
[...]
>
> So I wondered if it is possible to just use a chaep FPGA chip like this
> one: http://tinyurl.com/y33nh5 and just solder some led's + buttons to
> the IO-pins.
> It is a xilinx chip, so I could use the free Webpack ISE for generating
> the bitstream I guess. But the problem is: How do I actually configure
> the FPGA? I have read a Xilinx datasheets (http://tinyurl.com/ykxojk)
> and got the impression that the actual configuration process isn't that
> difficult in slave searial mode.
> The problem is that I don't know much about electronics. So I wondered
> if I could build such a FPGA-paralell-port-programmer by myself? Are
> there any hidden traps? (The software side is no problem, writing and
> reading bits to/from parport is easy.)
[...]

Hi Timo,

It first always sounds so simple to just put together just what you
need. But once you go into detail it ends up taking more than you
expected.

The question will be whether you are willing to do all the electronics
work necessary to get it going. The Spartan 3 has quite some voltage
requirements. So just to get it going byitself will take some
components. The next step is the programming. Adding some components to
do the programming is one side. The other is how to get the bit stream
from the PC to the components. You could use an AVR for example. With
the serial port of the AVR connecting to the PC. However, if I remember
right the Spartan 3 binary is quite bigger than that of the Spartan 2,
so the programming process might take some time.

There is actually a way to hook up an USB interface direct to the FPGA.
I have an old Spartan 2 board from digilent and they have a library
that allows to download the FPGA image over their USB interface. This
does not work with my Spartan 2, but it is supposed to work with the
Spartan 3.

I think the USB FPGA project on sourceforge uses the same approach:

http://sourceforge.net/projects/usbp
http://atrandomresearch.com/usbp/

Actually, maybe that board has just what you are looking for. I think
the small version also uses a X3S50.

What I like about it is, that you can even customize the USB firmware
if you need so. Also the code is freely available from sourceforge.

Cheers,

Guenter


Article: 114232
Subject: Re: First Picture of Craignell Modules
From: "Dave Pollum" <vze24h5m@verizon.net>
Date: 8 Jan 2007 06:29:52 -0800
Links: << >>  << T >>  << A >>

-jg wrote:
> John Adair wrote:
> > For those asking first photo of DIL FPGA modules Craignell1/2/3 are now
> > on our website. Modules have a very tiny packaged Spartan-3E and we
> > have made them 5V tolerant and capable of reaching 5V CMOS levels with
> > pullup resistors.
> >
> > John Adair
> > Enterpoint Ltd.
>
> No Link ?  ( some of us are lazy..)
> -jg

Not from John,but -- http://www.enterpoint.co.uk/
John, have you set prices yet for the Craignell boards?
-Dave Pollum


Article: 114233
Subject: Generate ACE File: *.elf does not contain start address
From: "Peter Kampmann" <peter.kampmann@googlemail.com>
Date: 8 Jan 2007 07:10:43 -0800
Links: << >>  << T >>  << A >>
Hi everyone,

I'm trying to put Linux on the XUPV2P Board, therefore I use the
Tutorial from the  Brigham Young University (BYU,
http://splish.ee.byu.edu/projects/LinuxFPGA/configuring.htm).

In this Tutorial you are told to build an ACE File with the following
command:



    xmd -tcl genace.tcl -opt xupGenace.opt

where the file xupGenace.opt contains the following:

-jprog
-board user
-target ppc_hw
-hw implementation/download.bit
-elf TestApp_memory/executable.elf
-configdevice devicenr 1 idcode 0x1127e093 irlength 14 partname xc2vp30
-debugdevice devicenr 1 cpunr 1
-ace system.ace

When I adjust the paths to my application and execute the command
mentioned above, I get an error:
*.elf does not contain start address ...

In the Xilinx Answer Database, there is an entry for this issue:
Xilinx Answer Record #23192,
http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=23192

But when I change the code according to this record, the problem
remains.

I'm using EDK 8.2.02i, does anybody know what to do?

Thanks and Regards,
Peter


Article: 114234
Subject: Re: what are your current SoC design for ?
From: "Peter Y" <yiannac@gmail.com>
Date: 8 Jan 2007 07:12:00 -0800
Links: << >>  << T >>  << A >>

As a PhD student researching soft cores, I'd love to hear a little more
of the 100-long list of advantages.  Also if you have any insight into
"typical uses" of a soft core that would also be very insightful.

Thanks.


On Dec 17 2006, 11:46 pm, "Daniel S."
<digitalmastrmind_no_s...@hotmail.com> wrote:
> rpons...@gmail.com wrote:
> > I don't need your IP secrecies...
>
> > This is for my students : what, in your current design, requires using
> > a fpga + softcore, in place of a COTS micro controler ?
> > less IC -> lower footprint, lower power cons., parallelism,...
>
> > thanks,
> > raphFewer ICs? Yes - why have a $3 I2C PROM and a $5 microcontroller with
> the extra manufacturability programming bother when they can be emulated
> using a spare BRAM or two and 200 slices in a $40 FPGA that's already
> there for high-bandwidth signal processing?
>
> Lower power? Yes - sort of: more in the form of not needing an extra
> power regulator, clock source and other such items for the external
> microcontroller
>
> Parallelism? No - a soft core sounds like a pretty lousy choice for pure
> software parallelism... you might need to fill an XC5V330LX with
> microblazes to match modern CPUs. High-performance algorithms in FPGAs
> are much better served with pipelined parallelized logic implementations.
>
> Other reasons?
> - Cost: if the microcontroller core fits, it is practically free
> - Cost: an integrated microcontroler does not need IOs to interface with
> internal logic
> - Simplicity: an integrated microcontroller is easier to interface (no
> need to manage tristate IOs)
> - Simplicity: an integrated microcontroller can be customized
> - Simplicity: auxiliary microcontroller functions can be implemented in
> logic
> - Flexibility: all of the above
> - Flexibility: No compromising with multi-function pins
> - Performance, bandwidth, latency, etc.
> - If I had time, I could probably list over 100 reasons
>
> I have often been very frustrated with multi-function pins on
> off-the-shelf chips where two features I want often end up being
> mutually exclusive on most reasonably sized devices. With soft cores,
> nobody ever has to face this irritating limitation of hard-wired logic.


Article: 114235
Subject: Re: how do we connect internals signals(not ports) of submodules in the top level design to trigger ports of the ila core?
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 8 Jan 2007 15:15:24 -0000
Links: << >>  << T >>  << A >>
"CMOS" <manusha@millenniumit.com> wrote in message 
news:1168180397.430509.305110@11g2000cwr.googlegroups.com...
> hi,
> how do we connect internals signals(not ports)  of submodules in the
> top level design to trigger ports of the ila core? With core inserter,
> it is possible to connect signals from many submodules to the same
> trigger port, but how is this done when you use core generater and
> manually setup connections of icon and ila cores?
>
> thank you.
>
You can get round this problem by using the Chipscope inserter. This method 
allows you access to all the signals in the design and you don't need to add 
anything to your source code.
HTH, Syms. 



Article: 114236
Subject: Re: dynamically created blockRAM contents?
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 8 Jan 2007 15:18:21 -0000
Links: << >>  << T >>  << A >>
"matteo" <matt.fischler@gmail.com> wrote in message 
news:1168023629.092115.51520@51g2000cwl.googlegroups.com...
>I have some Verilog code that generates an array of blockRAMs to any
> dimensions that I want. For example, if I set LENGTH=3 and HEIGHT=4
> then 12 blockRAMs get synthesized. I have a separate script written in
> Ruby that creates the initial blockRAM contents according to the
> position of each blockRAM in the array. What I'd like to do is be able
> to pass in the blockRAM init parameters dynamically as each blockRAM is
> generated.
>
> I'm looking for suggestions on how to do this. Can XST execute and
> interact with scripts from the command line?
>
Does this help?
http://www.google.com/search?en&q=data2mem
Probably not, but just checking.
Cheers, Syms. 



Article: 114237
Subject: Re: Use Multi-cycle Path or Pipeline?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Mon, 08 Jan 2007 07:30:07 -0800
Links: << >>  << T >>  << A >>
Hans wrote:

> As above, also if you use the enable input of a FF then you might already 
> have a MCP and not be aware of it :-)

Yes, and synthesis can most often arrange
to meet single cycle timing in this case.
I don't *need* to think about timing constraints
unless static timing fails.

If such a path were to fail,
and I happen to know for *sure*
that good data is never needed on
the first tick, then I have a choice.
I can add a constraint or change the design.
This is a matter of style unless my device is full.

   -- Mike Treseler

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From: Phil Hays <spampostmaster@comcast.net>
Subject: Re: Ones' complement addition
Date: Mon, 08 Jan 2007 07:44:32 -0800
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glen herrmannsfeldt wrote:

> Koen Van Renterghem wrote:
> 
>> glen herrmannsfeldt wrote:
> 
> (snip regarding ones complement adder)
> 
>>  > You need the end-around carry.  It is pretty easy with a carry
>>  > lookahead adder to wire the carry out back to the carry in. (snip)
> 
>>  > You should only need a 16 bit adder with carry in/carry out.
> 
>>  > assign {carry,result} = a+b+carry;
> 
>>  > The worst case is where the carry propagates 16 bits. (Well, the
>>  > full width.)  It never goes farther than that.
> 
>> I previously tried this approach, but that resulted in synplify and
>> xilinx complaining about a combinatorial loop created by connecting the
>> carry-out to the carry-in of the adder. That is why I started using a
>> dedicated 16 bit adder to calculate the carry. This carry is then
>> applied to a second adder.
> 
> The delay will be at most one trip around the carry loop, but the tools
> don't know that.

It looks to me like there is a chance of a pulse running around the carry
loop for a multiple times, perhaps even forever.

The case of interest is a calculation that should result in an answer of
zero. Note that there are two representations of zero in one's complement
notation, all '1's and all '0's, often called negative zero and positive
zero.

If there is a carry, the answer is all '0's, or positive zero. If there is
no carry, the answer will be all '1's, or negative zero.

Now suppose my adder is half in the state with a carry, and half in the
state without a carry. The carry, and not carry will both propagate up the
carry chain to the msb and around to the lsb again, chasing each other,
and it is a race. If carry is faster than the not carry, then the final
result will be all '0's. If not carry is faster than the carry, then the
final result will be all '1's. Assuming you wait long enough, of course.
If carry propagates at exactly the same speed as the not carry, then the
circuit will never produce either of the two correct results. If you check
before the end of the race, then you will get an incorrect result, that is
something other than negative zero or positive zero.

In other words, this circuit has a metastable state when the answer is
zero. It may take forever to to produce a correct answer, if it must
decide between negative zero and positive zero.


-- 
Phil Hays (Xilinx, but posting for myself)


Article: 114238
Subject: Re: Generate ACE File: *.elf does not contain start address
From: "Peter Kampmann" <peter.kampmann@googlemail.com>
Date: 8 Jan 2007 08:05:21 -0800
Links: << >>  << T >>  << A >>
hmmm, I think I have solved the problem:

add the following line to the xupGenace.opt - File:

-start_address 0xFFFFFFFC

the start address, I've chosen here, points to the boot-section that's
in the linker-script.

Regards,
Peter

On 8 Jan., 16:10, "Peter Kampmann" <peter.kampm...@googlemail.com>
wrote:
> Hi everyone,
>
> I'm trying to put Linux on the XUPV2P Board, therefore I use the
> Tutorial from the  Brigham Young University (BYU,http://splish.ee.byu.edu/projects/LinuxFPGA/configuring.htm).
>
> In this Tutorial you are told to build an ACE File with the following
> command:
>
>     xmd -tcl genace.tcl -opt xupGenace.opt
>
> where the file xupGenace.opt contains the following:
>
> -jprog
> -board user
> -target ppc_hw
> -hw implementation/download.bit
> -elf TestApp_memory/executable.elf
> -configdevice devicenr 1 idcode 0x1127e093 irlength 14 partname xc2vp30
> -debugdevice devicenr 1 cpunr 1
> -ace system.ace
>
> When I adjust the paths to my application and execute the command
> mentioned above, I get an error:
> *.elf does not contain start address ...
>
> In the Xilinx Answer Database, there is an entry for this issue:
> Xilinx Answer Record #23192,http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=23192
>
> But when I change the code according to this record, the problem
> remains.
>
> I'm using EDK 8.2.02i, does anybody know what to do?
> 
> Thanks and Regards,
> Peter


Article: 114239
Subject: Variable clock using Virtex 4?
From: John <null@null.com>
Date: Mon, 8 Jan 2007 09:17:09 -0800
Links: << >>  << T >>  << A >>
Is there a way to create a variable clock that behaves like a VCO using the Virtex 4? If not clock, how about variable analog voltage?

Article: 114240
Subject: Re: Build an FPGA programmer cable
From: Timo Schneider <timos@perlplexity.org>
Date: Mon, 8 Jan 2007 17:40:21 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2007-01-08, Guenter <GHEDWHCVEAIS@spammotel.com> wrote:

Hi!

>> So I wondered if it is possible to just use a chaep FPGA chip like this
>> one: http://tinyurl.com/y33nh5 and just solder some led's + buttons to
>> the IO-pins.
>> It is a xilinx chip, so I could use the free Webpack ISE for generating
>> the bitstream I guess. But the problem is: How do I actually configure
>> the FPGA? I have read a Xilinx datasheets (http://tinyurl.com/ykxojk)
>> and got the impression that the actual configuration process isn't that
>> difficult in slave searial mode.
>> The problem is that I don't know much about electronics. So I wondered
>> if I could build such a FPGA-paralell-port-programmer by myself? Are
>> there any hidden traps? (The software side is no problem, writing and
>> reading bits to/from parport is easy.)

> It first always sounds so simple to just put together just what you
> need. But once you go into detail it ends up taking more than you
> expected.

Yes, that's what I expected. :-) Do you have some tips which problems
could occour?

> The question will be whether you are willing to do all the electronics
> work necessary to get it going.

If it is not too complicated, I would like to do so. Learning by doing.

> The Spartan 3 has quite some voltage
> requirements. So just to get it going byitself will take some
> components. The next step is the programming. Adding some components to
> do the programming is one side. The other is how to get the bit stream
> from the PC to the components. You could use an AVR for example. With
> the serial port of the AVR connecting to the PC.

My first idea was too hook up the paralell port of the pc directly to
the fpga-programming pins, adding resistors and a z-diode to get the
voltage right.
Is this completely wrong or why should I use an AVR in between the pc
paralell-port and the fpga?

> I think the USB FPGA project on sourceforge uses the same approach:
>
> http://sourceforge.net/projects/usbp
> http://atrandomresearch.com/usbp/
>
> Actually, maybe that board has just what you are looking for. I think
> the small version also uses a X3S50.

Mm, but this board is just as expensive as the Spartan3E Starter Kit.

Regards,
Timo

Article: 114241
Subject: Re: Build an FPGA programmer cable
From: "Antti" <Antti.Lukats@xilant.com>
Date: 8 Jan 2007 10:03:37 -0800
Links: << >>  << T >>  << A >>
Timo Schneider schrieb:

> On 2007-01-08, Guenter <GHEDWHCVEAIS@spammotel.com> wrote:
>
> Hi!
>
> >> So I wondered if it is possible to just use a chaep FPGA chip like this
> >> one: http://tinyurl.com/y33nh5 and just solder some led's + buttons to
> >> the IO-pins.

Timo,

it all depends on your skills and willingness to play around.

if you have any Xilinx FPGA then it is rather easy to make from
it an devkit, some while ago I purchased some big Virtex FPGA
from ebay for 49$ and made a devboard, the chip was in BGA but
thats also doable with some patentience, just place the chip balls
up and solder directly to the balls.

with the JTAG programming, just use series resistors that all.
usually works.

so all you need to worry are the voltage regulators for the aux and
core

Antti


Article: 114242
Subject: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
From: Ray Andraka <ray@andraka.com>
Date: Mon, 08 Jan 2007 13:13:19 -0500
Links: << >>  << T >>  << A >>
Bob Perlman wrote:

> On Sun, 7 Jan 2007 20:00:54 +0800, "SunLei" <iamsunlei@gmail.com>
> wrote:
> 
> 
>>The FFT result output, implemented in a FPGA, is a complex number with
>>16-bit real part and 16-bit imaginary part. In the application, I only care
>>about the FFT result magnitude, Mag = sqrt(Re*Re+Im*Im).So I wonder if there
>>is an approximate estimation about this operation. and even more, the
>>decibel algorithm. I think the decibel algorithm can be easily implemented
>>by a looking-up-table scheme, but I still have no idea about simple complex
>>magnitude algorithm. I appreciate your suggestions.
>>
>>Sun Lei.
> 
> 
> I don't know what precision you need, so the following may be totally
> unsuitable.  But it's worth mentioning, if only as a history lesson.
> 
> Back in the 70's, when life was cheap and digital hardware was
> expensive, I was designing parts of radar signal processors.  Most of
> these things had an FFT in the front end, and at some point we had to
> produce a magnitude from I and Q.  In those days a 12-by-16 multiplier
> took an entire circuit board of AMD 25S05 2-by-4 multipliers, which
> seemed kind of excessive for such a function.
> 
> We got pretty good results by comparing the magnitudes of I and Q,
> then adding the larger plus half the smaller.  The average result
> error is around 8.6 percent.  There are variations on this theme that
> use different coefficients, i.e. alpha*|larger| + beta*|smaller|, and
> produce much lower average and peak errors.  You can read more about
> this at:
> 
> http://dspguru.com/comp.dsp/tricks/alg/mag_est.htm
> 
> If you're using one of those new-fangled FPGAs with a zillion
> multipliers on it, this isn't the solution for you.  Still, it's
> interesting how much performance designers used to squeeze out of not
> all that much logic.  And coffee was only a quarter.  And the music
> was better.  I could go on.
> 
> Bob Perlman
> Cambrian Design Works
> http://www.cambriandesign.com


And if you are using dB output only, the larger plus half smaller yields 
a max error of less than 1 dB, so if you don't have the luxury of 
multipliers at a reasonable cost, a dB output using larger plus half 
smaller is very workable in many situations.

My experience is similar to Bob's regarding radar systems.  In a former 
job, we frequently used larger plus half smaller and a simple look-up to 
get dB output, also in radar systems dating from the mid 70's, when DSP 
was done with boards full of TTL devices, high speed meant clocks as 
high as *gasp* 12 MHz (and that was a significant feat while meeting the 
mil environment specs).  Debug was done with an oscilloscope and if you 
were real lucky you got access to a storage scope.  Still, the stuff we 
do today is cooler, but it also doesn't require as much magic to pull it 
off.

Article: 114243
Subject: Re: Build an FPGA programmer cable
From: Vangelis <>
Date: Mon, 8 Jan 2007 10:20:37 -0800
Links: << >>  << T >>  << A >>
Here is a simple schematic for the parallel cable programmer:

 <http://toolbox.xilinx.com/docsan/3_1i/data/common/jtg/dppb/appb.htm>

Article: 114244
Subject: Re: Variable clock using Virtex 4?
From: Austin Lesea <austin@xilinx.com>
Date: Mon, 08 Jan 2007 10:29:38 -0800
Links: << >>  << T >>  << A >>
John,

Well, in Virtex 4, it is a simple matter to instantiate an accumulator
with feedback, which is then a digitally controlled oscillator (a direct
digital synthesizer).  The frequency is from nearly 0 to 1/2 the clock
at which the DDS is run with.

The resolution of the DDS is just how many bits you use.  For example,
16 bits is 1/65,536.  48 bits is ~ 3.5E-15.

To generate an analog voltage, pulse width modulation, or pulse position
modulation may be used with any output.  A RC filter is needed to smooth
out the result, and provide a nice clean analog signal.  Rate
multipliers are often used to spread out the corrections, and make the
steps smaller in time (no long periods without any pulses at all) so
that a small RC may be used.

Rise and fall time of the IO is one factor in causing error.

If the Vcco of the bank with that IO pin is referenced to a voltage
standard, the accuracy of such a circuit may be as much as 14 bits, but
it will not be very fast (D/A good up to perhaps ~ 10 KHz?).  I would
say that 8 to 10 bits of control would be all I would expect.

Austin

Article: 114245
Subject: Re: Build an FPGA programmer cable
From: Timo Schneider <timos@perlplexity.org>
Date: Mon, 8 Jan 2007 19:51:36 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2007-01-08, Vangelis <> wrote:

Hi!

> Here is a simple schematic for the parallel cable programmer:
>
> <http://toolbox.xilinx.com/docsan/3_1i/data/common/jtg/dppb/appb.htm>

Ah, thats great! And it looks easy to build. But what do I need the jtag
header for? It seems the paralell port is directly connected to the fpga
pins. Or is it just usefull to have a jtag header on the board so that I
can use a jtag cable later on?

Regards,
Timo

Article: 114246
Subject: Re: First Picture of Craignell Modules
From: "-jg" <Jim.Granville@gmail.com>
Date: 8 Jan 2007 13:24:43 -0800
Links: << >>  << T >>  << A >>

Dave Pollum wrote:
> Not from John,but -- http://www.enterpoint.co.uk/
> John, have you set prices yet for the Craignell boards?
> -Dave Pollum

Thanks, but on the home page Craignell Modules does not appear,
and google for Craignell Modules finds nothing, also news has only
quite old infos, and not until I take a guess, and dig into
BoardProducts
do I see Craignell mentioned, and finally here find a link

http://www.enterpoint.co.uk/component_replacements/craignell.html

Tip for John:
Post photos in two resolutions: Lower for fast loading, and then
click-on
any photo, to allow higher res.

There seem to be 3 variants, but all labeled FD2 ?, and these all seem
to have two
'Pin1 Square pad convention' - also no photo of the PCB rear ?
I can see a compact flash card, but no mention of how that relates to
Craignell Modules - is there a CF socket on the rear ?

-jg


Article: 114247
Subject: Re: dynamically created blockRAM contents?
From: "KJ" <kkjennings@sbcglobal.net>
Date: Mon, 08 Jan 2007 22:02:51 GMT
Links: << >>  << T >>  << A >>

"matteo" <matt.fischler@gmail.com> wrote in message 
news:1168023629.092115.51520@51g2000cwl.googlegroups.com...
>I have some Verilog code that generates an array of blockRAMs to any
> dimensions that I want. For example, if I set LENGTH=3 and HEIGHT=4
> then 12 blockRAMs get synthesized. I have a separate script written in
> Ruby that creates the initial blockRAM contents according to the
> position of each blockRAM in the array. What I'd like to do is be able
> to pass in the blockRAM init parameters dynamically as each blockRAM is
> generated.
>
> I'm looking for suggestions on how to do this. Can XST execute and
> interact with scripts from the command line?
>

Is there some reason why the code that generates the initial contents is 
written in Ruby?  More to the point, is there some reason that this Ruby 
program can not be converted to VHDL or Verilog bundled up as a function 
that will return the memory contents?

Kevin Jennings 



Article: 114248
Subject: Re: Problem with unused pin on Spartan 2E
From: Mounard Le Fougueux <blinkingCursor@NonEventHorizon.com>
Date: Mon, 08 Jan 2007 18:55:29 -0500
Links: << >>  << T >>  << A >>
kayrock66@yahoo.com wrote:
> It sounds like that pin isn't actually a no-connect, but is used since
> you are expecting a particular behavoiour.  As one poster mentioned
> (and increased my knowledge) the tools will do whatever they want with
> a pin that it figures are unconnected.  If you have a specific
> behaviour you need, you need to tell it so.  Sounds like you lucked out
> in a manner of sorts that it drove the pin to the same logic state of
> the other driver on that net in previous builds.
> 
> 
> Mounard Le Fougueux wrote:
> 
>>I have a mature design on a spartan2300E. It has some unused pin - by
>>that I mean there are no references to thoses pins in either the UCF or
>>port map of the VHDL code - nor has there ever been.
>>
>>Here's the problem:
>>
>>Last rev of the fw, the unused pins acted as I expected - high
>>impedence. There fore there way never any contention with other devices
>>conneected to that unused pin on a backplane.
>>
>>So far so good.
>>
>>I then need to make a small change to the VHDL code that had NO IMPACT
>>on either the ports or the UCF. The PAR report has the pin as "UNUSED".
>>I had to do an overnight MPPR (Mutipass place and route) to meet timing
>>constraints (as I normally had to on all previous revs).
>>
>>However with this new rev, the FPGA is clearly driving the pin to 3.3V
>>through a low imppendance, and in fact is contending with anotehr device
>>which is driving the same line to 0V resulting in a net ~1V contended
>>signal result. This happen on every board that i've tried this new rev
>>on - therefore it is not a board issue but a FPGA configuration issue.
>>
>>Shouldn't an unused FPGA pin default to some high impedence state? My
>>solution to the problem is to explicitely USE the pins as inputs.
>>
>>However what would be the explaination for an unused input looking like
>>a driven 3.3V output?????
>>
>>Thanks
> 
> 
my guess is that it decided to use that "unused" IOB for some internal 
routing purposes to meet explicit constraints.

I am now using the FPGA editor (post route) to verify that fact.

Inthe xilinx 6.3.3 tools, there is an option for unused pins under 
Configuration properies, but I belive that only applies to configuration 
pins, such as JTAG or M0 -M2 pins only.

Article: 114249
Subject: Quartus II 6.1 Remove Duplicate Logic option removed
From: Wilhelm.Klink@gmail.com
Date: 8 Jan 2007 16:16:11 -0800
Links: << >>  << T >>  << A >>
The remove duplicate logic option has been removed from Quartus II 6.1.
 I tried searching the manual to find which setting is meant to replace
it, but all I could find was a brief note in the document revision
history "Removed section on obsoleted logic option Remove Duplicate
Logic".  Does anyone know which setting replaces it?




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