Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On 5 Jan 2007 11:39:28 -0800, "Frank" <FrankTDai@gmail.com> wrote: >I've been looking all over for a board with a Xilinx V4 LX160 or 200 >FPGA >and 2 10/100 Ethernet PHYs. Closest I got was a board from Avnet that >only had 1 PHY. > >Know where to find one? Please let me know. Avnet sell a "memory/communications board" which would plug into 2 of the on-board 140-pin connectors on that board, and add at least one more PHY. I don't regard add-on boards as ideal, but check it out in case it's usable for your project. - BrianArticle: 114176
i have to admit at first i was not really convinced but by writing more and more DSP related VHDL where i need signed/unsigned values i am learning a lot of the inefficiency of certain libraries and packages ... Mike Treseler wrote: > Jonathan Bromley wrote: >> On 4 Jan 2007 07:14:21 -0800, "Tim Verstraete" >> <tim.verstraete@barco.com> wrote: >> >> [Also posted to comp.lang.vhdl] >> >>> ok, your right, now i know why it works on this code and not mine, in >>> the template i used the following libraries: >>> >>> LIBRARY ieee; >>> USE ieee.std_logic_1164.ALL; >>> use ieee.std_logic_arith.all; >>> use ieee.std_logic_signed.all; >>> >>> and in mine i used >>> >>> library IEEE; >>> use IEEE.STD_LOGIC_1164.ALL; >>> use IEEE.STD_LOGIC_ARITH.ALL; >>> use IEEE.STD_LOGIC_UNSIGNED.ALL; >> And that is PRECISELY why I keep banging on about why >> STD_LOGIC_(UN)SIGNED is such a very, very bad thing. >> >> If you had used only STD_LOGIC_ARITH or (better) >> NUMERIC_STD, then you would have been forced into >> declaring the objects as SIGNED or UNSIGNED, and you >> would know what you were doing. Having an arbitrary >> numeric representation imposed on std_logic_vector >> by a use clause is IMO certifiably insane. >> >> Thanks for providing more ammunition for my rant :-) > > These newsgroups provide plenty > of this sort of ammunition. > The source, it seems to me, > is the training examples and > editor templates from brand X and brand S. > > The result is that most designers of > VHDL synthesis code are convinced that > using signed and unsigned types is a waste of time, > and that only "purists" think otherwise. > > This state of affairs is only a problem > for me when I use or supply entities to > other designers. My workaround in this case > is to declare [un]signed variables for use > in my entity and implicit type conversion > for port input and output assignments > from the omnipresent std_logic_vector type. > > -- Mike Treseler >Article: 114177
rao wrote: > Hi, > I am trying to make 7:1 LVDS Tx for a display solution (XGA and SXGA) > and trying to use > the approach as specified in xilinx app note XAPP704 (virtex-4 high > speed single data rate > LVDS transceiver). The reference design that xilinx provided is for > 4:1 (4 parallel data goes > to 1 channel of LVDS) and it works fine but when I try to change the > parameters to operate > as 7:1 the design doesn't work (the serial data output doesn't > correspond to parallel data input). > > As the maximum bit per channel for a xilinx OSERDES is 6 I have to > use two OSERDES in > seires (as master and slave) to make a 7:1 channel. > > I would like to know if any worked on this aspect before and I do > appreciate if any one can > provide some helpful info to proceed. > > Regards > rao > why not use <http://direct.xilinx.com/bvdocs/appnotes/xapp265.pdf>?Article: 114178
Yes, thank you for pointing out the availability of PREADY in APB version 3.0 I had read about that in a different message thread. Unfortunately, as one may expect I am limited by the fact that I am interfacing to an AMBA 2.0 system. Marco. Jon Beniston wrote: > marco wrote: > > Hello. > > > > I have a peripheral with an AMBA APB interface. > > The issue that I am facing is that of clock domain crossing. > > The processing logic in the peripheral is required to operate at a > > relatively slow clock frequency, but the clock frequency of the APB > > interface can be 4 to 5 times that of the slow clock domain. > > I have been considering the two clock domains as asynchronous with > > respect to each other, even though the faster clock is generated from > > the slow clock by means of a PLL; therefore, the phase relationship > > between the two clock should be constant. > > > > My problems lies in the fact that APB has no signal to hold the bus in > > the case where the data from a write cycle to the slow clock domain has > > not yet been registered by the slow clock when a second write cycle > > starts to happen. > > AMBA APB version 3 has such a signal I believe, pready. > > Cheers, > JonArticle: 114179
I have a mature design on a spartan2300E. It has some unused pin - by that I mean there are no references to thoses pins in either the UCF or port map of the VHDL code - nor has there ever been. Here's the problem: Last rev of the fw, the unused pins acted as I expected - high impedence. There fore there way never any contention with other devices conneected to that unused pin on a backplane. So far so good. I then need to make a small change to the VHDL code that had NO IMPACT on either the ports or the UCF. The PAR report has the pin as "UNUSED". I had to do an overnight MPPR (Mutipass place and route) to meet timing constraints (as I normally had to on all previous revs). However with this new rev, the FPGA is clearly driving the pin to 3.3V through a low imppendance, and in fact is contending with anotehr device which is driving the same line to 0V resulting in a net ~1V contended signal result. This happen on every board that i've tried this new rev on - therefore it is not a board issue but a FPGA configuration issue. Shouldn't an unused FPGA pin default to some high impedence state? My solution to the problem is to explicitely USE the pins as inputs. However what would be the explaination for an unused input looking like a driven 3.3V output????? ThanksArticle: 114180
Mounard Le Fougueux wrote:
> However with this new rev, the FPGA is clearly driving the pin to 3.3V
> through a low impedance, and in fact is contending with another device
> which is driving the same line to 0V resulting in a net ~1V contended
> signal result.
> Shouldn't an unused FPGA pin default to some high impedance state?
That is a common expectation, but the usual default
for unused FPGA pins is low impedance drive to power or ground,
for lower noise, or even to a random internal node to save a route.
This will vary by device and sometimes by software revision.
> My solution to the problem is to explicitly USE the pins as inputs.
That works, but I prefer to declare the unused pin
drive explicitly in the place and route settings file
to keep the source code clean and easy to sim.
There are almost always other device constraints
like pin numbers that don't really belong in
the source code either. When a design is final,
I like to tie the remaining unused IOs to ground.
-- Mike Treseler
Article: 114181Hi Joe, > Hello, I'm looking to implement an Ethernet Controller to support > 1000Base-T on a Stratix II GX and would like to know if anyone could > suggest an IP Core? I've been looking over the Atlera IP web site and > have found some IP's, but I wanted to see what other people were using. In my region there's two popular choices: the IFI GMAC and LGMAC cores (www.ifi-pld.de) and the MoreThanIP GMAC (www.morethanip.com). I believe that the current Gigabit MAC that Altera sells is a sublicensed version of the MoreThanIP GMAC. Best regards, BenArticle: 114182
"Mounard Le Fougueux" <blinkingCursor@NonEventHorizon.com> wrote in message news:r9ydnYJyMNj4SQLYnZ2dnUVZ_q-vnZ2d@adelphia.com... > > Here's the problem: > > Last rev of the fw, the unused pins acted as I expected - high impedence. > There fore there way never any contention with other devices conneected to > that unused pin on a backplane. > > > I then need to make a small change to the VHDL code that had NO IMPACT on > either the ports or the UCF. The PAR report has the pin as "UNUSED". I had > to do an overnight MPPR (Mutipass place and route) to meet timing > constraints (as I normally had to on all previous revs). > > However with this new rev, the FPGA is clearly driving the pin to 3.3V > through a low imppendance, and in fact is contending with anotehr device > which is driving the same line to 0V resulting in a net ~1V contended > signal result. This happen on every board that i've tried this new rev > on - therefore it is not a board issue but a FPGA configuration issue. > My guess is that the two designs were run with different versions of the synthesis/place & route software. The earlier version of the software defaulted unused I/O pins to be tri-state; the newer version actively drives them. Solutions are: - Use the older software for the new design. This is not necessarily a 'good' idea to be using out of date software which is less likely to be supported). - Define the 'unused' pins as explicit inputs as you've done to come up with something that works. While this is a workable solution you're gumming up the design a bit by defining pins as input signals that you have no intention of using...which is probably making you feel a bit leary about this approach (as it should). It does work though. - Find the setting that you need that sets unused I/O pins to tri-state (if such an option is available in whatever version you happen to be using). This would usually be the 'best' approach since used be using fully supported software and you're not adding artificial tweaks just to please the tool. Usually the only trouble comes in when you want some of those 'unused' pins to really be a high and others to be low for some reason. If that's the situation though then whatever process tha was followed that got the PCBA design into this type of situation needs to be reviewed since it is clearly not acceptable to have two different pins that 'should' be no connects tied to different voltages. If this is the case, then you're kind of stuck with the previous bullet about explicitly defining the pins as inputs as you've done. > Shouldn't an unused FPGA pin default to some high impedence state? > However what would be the explaination for an unused input looking like a > driven 3.3V output????? Not necessarily. Actively driving an 'unused' pin tends to decrease simultaneous switching noise for the actively used outputs of the FPGA so from the perspective of the part itself it would rather not have these open or weakly driven. As parts get faster and faster over time this becomes more of an issue to keep in mind. Kevin JenningsArticle: 114183
premrajan wrote: > iam using mentor graphics modelsim6.2d for running verilog codes,can > anyone tell me how to use code coverage in batch > http://www.google.com/search?q=vsim+%22-coverage%22Article: 114184
Mounard Le Fougueux wrote: > I have a mature design on a spartan2300E. It has some unused pin - by > that I mean there are no references to thoses pins in either the UCF or > port map of the VHDL code - nor has there ever been. > > Here's the problem: > > Last rev of the fw, the unused pins acted as I expected - high > impedence. There fore there way never any contention with other devices > conneected to that unused pin on a backplane. > > So far so good. > > I then need to make a small change to the VHDL code that had NO IMPACT > on either the ports or the UCF. The PAR report has the pin as "UNUSED". > I had to do an overnight MPPR (Mutipass place and route) to meet timing > constraints (as I normally had to on all previous revs). > > However with this new rev, the FPGA is clearly driving the pin to 3.3V > through a low imppendance, and in fact is contending with anotehr device > which is driving the same line to 0V resulting in a net ~1V contended > signal result. This happen on every board that i've tried this new rev > on - therefore it is not a board issue but a FPGA configuration issue. > > Shouldn't an unused FPGA pin default to some high impedence state? My > solution to the problem is to explicitely USE the pins as inputs. > > However what would be the explaination for an unused input looking like > a driven 3.3V output????? > > Thanks To all who answered: I USED THE EXACT SAME VERSION FOR BOTH REVS - ISE V6.3 ThanksArticle: 114185
Mounard Le Fougueux wrote:
> To all who answered:
> I USED THE EXACT SAME VERSION FOR BOTH REVS - ISE V6.3
Something was different.
-- Mike Treseler
Article: 114186Since I started posting to this list under my current adress, I am receivin tons of spam mails every day. I thought, the email was protected by the system but obviously is not. How can this be explained? What could be done to protect the mail, but maintain to be reachable for serious questions? Regularly changing mail adress ?Article: 114187
fpgauser wrote: > Since I started posting to this list under my current adress, I am > receivin tons of spam mails every day. I thought, the email was > protected by the system but obviously is not. > How can this be explained? This is a public newsgroup, not a closed mailing list you have to register for. All messages can even be searched with Google. Everything that's in these messages (including email addresses) might just as well be published on a website. There's no protection whatsoever. > What could be done to protect the mail, but maintain to be reachable > for serious questions? > > Regularly changing mail adress ? That's one approach. I use email-addresses that change every month, but every human should be smart enough to construct the currently valid address. The scripts and bots that scan newsgroups for addresses aren't that clever (yet), so that works quite well. Other people here only post their addresses in some sort of coded way, and use an invalid address as the From:-address. That means you can't just hit the reply-button, but have to manually put in the correct email-address. Another way is to just put a link to a website in your posts, and if somewone wants to contact you, he/she needs to fill out a contact form on that website. All depends on how much trouble you're willing to go through and how many hoops you want people to have to jump through to reach you. cu, Sean -- My email address is only valid until the end of the month. Go figure what the address is going to be after that...Article: 114188
fpgauser wrote:
> What could be done to protect the mail, but maintain to be reachable
> for serious questions?
Also
get thunderbird (it's free)
and turn on the junk mail controls (they work well)
-- Mike Treseler
Article: 114189If you use VHDL, you can initialize block RAMs during synthesis. Check the "Initializing RAM" section in XST User Guide for examples. Cheers, Jim http://home.comcast.net/~jimwu88/tools/ matteo wrote: > I have some Verilog code that generates an array of blockRAMs to any > dimensions that I want. For example, if I set LENGTH=3 and HEIGHT=4 > then 12 blockRAMs get synthesized. I have a separate script written in > Ruby that creates the initial blockRAM contents according to the > position of each blockRAM in the array. What I'd like to do is be able > to pass in the blockRAM init parameters dynamically as each blockRAM is > generated. > > I'm looking for suggestions on how to do this. Can XST execute and > interact with scripts from the command line?Article: 114190
I am developing a EDK 8.2 component with a PLB master based DMA interface. It sure would be nice to use the coreconnect bus functional models such as PLB slave and PLB bus monitor to develop this core, but all I have for simulation is MXE. Does anyone know if this is possible? I downloaded and installed bfm_8_2.exe and can see source for all the BFM components; but the EDK "compile simulation library" command complains that I have MXE instead of PE/EE. I don't care about simulating other stuff in EDK, and normally I would simulate stand-alone but I get the feeling the BFM components are only meant for EDK. Had anyone here done anything like this? Searching the xilinx database has not returned a straight answer. Closest I can come is answer 19326 which refers to this: (Xilinx Answer 16359) - 3.1/3.2 EDK - Does EDK support the ModelSim XE simulator? but answer 16359 does not seem to exist. thanks, -JeffArticle: 114191
Jeff Cunningham wrote: > I am developing a EDK 8.2 component with a PLB master based DMA > interface. It sure would be nice to use the coreconnect bus functional > models such as PLB slave and PLB bus monitor to develop this core, but > all I have for simulation is MXE. Does anyone know if this is possible? > I downloaded and installed bfm_8_2.exe and can see source for all the > BFM components; but the EDK "compile simulation library" command > complains that I have MXE instead of PE/EE. I don't care about > simulating other stuff in EDK, and normally I would simulate stand-alone > but I get the feeling the BFM components are only meant for EDK. Had > anyone here done anything like this? > > Searching the xilinx database has not returned a straight answer. > > Closest I can come is answer 19326 which refers to this: > > (Xilinx Answer 16359) - 3.1/3.2 EDK - Does EDK support the ModelSim XE > simulator? > > but answer 16359 does not seem to exist. > > thanks, > -Jeff I used the bus functional models from the IBM CoreConnect toolkit with EDK 7.1. EDK generated all the scripts to compile and run the test bench for me, but I did not run ModelSim from within EDK. Having EDK generate the scripts was nice, but is something that you can do yourself. The BFMs did not have any Swift models in them, so you do not need that feature. If I remember correctly, both VHDL and Verilog BFMs are provided, so as long as your code is all one or the other you do not need the mixed language feature. Some of the files are large, over 50K lines I think, so if there is a line limit on the MXE version that might be a problem. Regards, John McCaskill www.fastertechnology.comArticle: 114192
Jonathan Bromley wrote: Snip > > Even if you could assemble BGA at home, you would > then have to worry about inspection or test. As far > as I'm aware, JTAG testing software is still not widely > used by amateurs, and X-ray inspection tools are > even rarer. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.bromley@MYCOMPANY.com > http://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. For JTAG testing software, take a look at the onTAP software by Flynn systems at www.flynn.com. It is less than $1000 USD. I use it, and have been very happy with it. Regards, John McCaskill www.fastertechnology.comArticle: 114193
The FFT result output, implemented in a FPGA, is a complex number with 16-bit real part and 16-bit imaginary part. In the application, I only care about the FFT result magnitude, Mag = sqrt(Re*Re+Im*Im).So I wonder if there is an approximate estimation about this operation. and even more, the decibel algorithm. I think the decibel algorithm can be easily implemented by a looking-up-table scheme, but I still have no idea about simple complex magnitude algorithm. I appreciate your suggestions. Sun Lei.Article: 114194
"SunLei" <iamsunlei@gmail.com> wrote in message news:enqq36$voc$1@news.cn99.com... > The FFT result output, implemented in a FPGA, is a complex number with > 16-bit real part and 16-bit imaginary part. In the application, I only > care > about the FFT result magnitude, Mag = sqrt(Re*Re+Im*Im).So I wonder if > there > is an approximate estimation about this operation. and even more, the > decibel algorithm. I think the decibel algorithm can be easily implemented > by a looking-up-table scheme, but I still have no idea about simple > complex > magnitude algorithm. I appreciate your suggestions. > > Sun Lei. > If you are using an Altera part, code it exactly the same. There are both SQR and SQRT megafunctions which can be pipelined and get extremely high throughput at 16 bits resolution. Using schematics the algorithm is trivial, don't know about VHDL/Verilog implementation though. LorneArticle: 114195
I am using a Xilinx one. There is a IP core in the ISE envirement, but it cost too resources and running time. Regards, Sun Lei "Peppermint Pumpkin" <pepperpump@make.a.mint> 写入消息新闻:45a0e342$0$8715$ed2619ec@ptn-nntp-reader02.plus.net... > > "SunLei" <iamsunlei@gmail.com> wrote in message > news:enqq36$voc$1@news.cn99.com... >> The FFT result output, implemented in a FPGA, is a complex number with >> 16-bit real part and 16-bit imaginary part. In the application, I only >> care >> about the FFT result magnitude, Mag = sqrt(Re*Re+Im*Im).So I wonder if >> there >> is an approximate estimation about this operation. and even more, the >> decibel algorithm. I think the decibel algorithm can be easily >> implemented >> by a looking-up-table scheme, but I still have no idea about simple >> complex >> magnitude algorithm. I appreciate your suggestions. >> >> Sun Lei. >> > > If you are using an Altera part, code it exactly the same. There are both > SQR and SQRT megafunctions which can be pipelined and get extremely high > throughput at 16 bits resolution. > > Using schematics the algorithm is trivial, don't know about VHDL/Verilog > implementation though. > > Lorne >Article: 114196
hi, how do we connect internals signals(not ports) of submodules in the top level design to trigger ports of the ila core? With core inserter, it is possible to connect signals from many submodules to the same trigger port, but how is this done when you use core generater and manually setup connections of icon and ila cores? thank you.Article: 114197
On Sun, 7 Jan 2007 20:00:54 +0800, "SunLei" <iamsunlei@gmail.com> wrote: >The FFT result output, implemented in a FPGA, is a complex number with >16-bit real part and 16-bit imaginary part. In the application, I only care >about the FFT result magnitude, Mag = sqrt(Re*Re+Im*Im).So I wonder if there >is an approximate estimation about this operation. and even more, the >decibel algorithm. I think the decibel algorithm can be easily implemented >by a looking-up-table scheme, but I still have no idea about simple complex >magnitude algorithm. I appreciate your suggestions. There are many possibilities, but to narrow down the choice we need to know more about your specification. What accuracy do you need? How much time do you have available to process each result? The complex FFT takes some time to process, so presumably you have some time to get the result? CORDIC may be a good solution; it gives nice accuracy with small hardware, but it needs either many clock cycles to do the calculation, or bigger hardware so that the calculation is pipelined. Tell us more. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. You are right that conversion from magnitude to dB can be done using a lookup table, or a combination of LUT and interpolation, or by using normalisation as a first step.Article: 114198
"SunLei" <iamsunlei@gmail.com> wrote in message news:enqq36$voc$1@news.cn99.com... > The FFT result output, implemented in a FPGA, is a complex number with > 16-bit real part and 16-bit imaginary part. In the application, I only care > about the FFT result magnitude, Mag = sqrt(Re*Re+Im*Im).So I wonder if there > is an approximate estimation about this operation. and even more, the > decibel algorithm. I think the decibel algorithm can be easily implemented > by a looking-up-table scheme, but I still have no idea about simple complex > magnitude algorithm. I appreciate your suggestions. > > Sun Lei. > > > > I assume the data is serialized going into your FFT block (i.e. comes from one ADC), so it should be a simple matter to serialize the bins coming out of your FFT. All you need then is a cordic coregen function (which is tiny compared to an FFT block so you'll have the space) and then a BRAM look up table to convert from magnitude to dB. Unless you serialize the cordic I think you need 1 stage per output bit so I would expect 16 stages times 32 registers = 512 registers (256 slices) and then 2^16*8 bits magnitude (about .5 dB accuracy) or 512 kbits memory. Though there is probably a more efficient way to calculate the log10. Maybe take the log2 by converting to floating point and then just use LUT on the mantissa and scaling. -ClarkArticle: 114199
I can infer blockRAMs and initialize their contents with a file using
the $readmemh system task from an initial block. The problem now is how
do I dynamically load a different file based on the parameters that get
passed from an upper module? The syntax is
initial $readmemh("data.txt",Mem,0,7);
where 0 is the start address and 7 would be the end address if the
depth was 8. Say I have a set of files for different blockram contents:
data0.txt
data1.txt
data2.txt
the # comes in as a parameter. Is there a way that I can convert it to
a string?
Matt
On Jan 6, 2:50 pm, "Jim Wu" <jimwu88NOOOS...@yahoo.com> wrote:
> If you use VHDL, you can initialize block RAMs during synthesis. Check
> the "Initializing RAM" section in XST User Guide for examples.
>
> Cheers,
> Jimhttp://home.comcast.net/~jimwu88/tools/
>
> matteo wrote:
> > I have some Verilog code that generates an array of blockRAMs to any
> > dimensions that I want. For example, if I set LENGTH=3 and HEIGHT=4
> > then 12 blockRAMs get synthesized. I have a separate script written in
> > Ruby that creates the initial blockRAM contents according to the
> > position of each blockRAM in the array. What I'd like to do is be able
> > to pass in the blockRAM init parameters dynamically as each blockRAM is
> > generated.
>
> > I'm looking for suggestions on how to do this. Can XST execute and
> > interact with scripts from the command line?
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z