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Messages from 114350

Article: 114350
Subject: Re: xc3sprog
From: Andrew Rogers <andrew@_NO_SPAM_rogerstech.co.uk>
Date: Fri, 12 Jan 2007 12:43:18 GMT
Links: << >>  << T >>  << A >>
Andrew Rogers wrote:
> Hi,
> 
> ...
> What I would like to do is to incorporate the many suggestions and 
> patches into the next release of xc3sprog if people are still using it.
> 
> I would be particularly interested in modifications to xc3sprog for USB 
> programmers. My laptop does not have a parallel port:(
> 
> Regards
> Andrew Rogers

Sorry, I forgot to mention that emails sent to me should include 
[XC3SPROG] in the subject field. This helps me to filter them from the 
150 SPAMs I get a day.

Happy New Year!
Andrew Rogers

-- 
Spartan3 configuration JTAG download tool for GNU/Linux available from
http://www.rogerstech.co.uk/xc3sprog/

Article: 114351
Subject: Re: Xilinx Floorplanner 'Replace All With Placement' and still logic left over!
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Fri, 12 Jan 2007 12:45:42 +0000
Links: << >>  << T >>  << A >>
On 11 Jan 2007 12:11:07 -0800, "Craig Yarbrough" <hyarbr01@harris.com>
wrote:

>Ok, it's been a while (a few versions) since I've had to use the Xilinx
>Floorplanner. But I don't recall this happening before. Virtex 5, after
>place and route I'm in the FPGA Editor and I switch the filter to
>'Unplaced Components.' None there! I load the same design in
>Floorplanner and execute 'Replace All with Placement.' Some symbols do
>get placed, but not all of them. I'm seeing some symbols including FG's
>left over in the Design Hierarchy window. What gives??? Is there an
>optimization step between .ngd/.ncd and final place/route where these
>rogues are taken out?

Take a look at the unplaced components ... I'm guessing they are all
route-throughs (will have _rt at the end of their name).

The PAR tools should place them correctly later on - though if you have
occupied the "right" place with another component you will get
conflicts.

Just one of the odd things Floorplanner has done since version 3.1...

- Brian

Article: 114352
Subject: Re: Medwedjew - who was that guy?
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Fri, 12 Jan 2007 13:08:23 +0000
Links: << >>  << T >>  << A >>
On Fri, 12 Jan 2007 10:28:37 +0100, backhus <nix@nirgends.xyz> wrote:

>Hi everybody,
>it may seem a little off topic, but during a discussion with my 
>colleague about state machines we came across this name, and wondered 
>when he lived and worked on his state machine theory. First thing was to 
>search the net, but besides politics and genetics etc. there was not 
>even his first name mentioned, not to speak of when or where he lived 
>and worked.
>
>Anyone has an idea/reference?

Russian names are spelled differently in different languages, so...
possibly Fyodor Andreevich Medvedev (19231994)
http://www.ltn.lv/~podnieks/gt2.html#Medvedev1982

Is this the guy?

I haven't found a whole lot online either,as you can see!

- Brian


Article: 114353
Subject: Too many warnings in Modelsim?
From: "Frai" <maybetooparanoid@gmail.com>
Date: 12 Jan 2007 05:11:52 -0800
Links: << >>  << T >>  << A >>
Hello, I am developing a solution using Xilinx ISE 8.2 and Modelsim
6.1. When I start the Post Place & Route simulation, I receive many
warnings, since at the beginning some signals are in a incoherent
state, like the Digital Clock Manager which is not locked yet.

I would like to know what the experts do when they simulate complex
circuits. Do you ignore those warnings? Do you try to eliminate them?
Is there any way to filter innocuous warnings?

Regards.

PD: these are some of the warnings I receive:

# ** Warning: /X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.042 ns; Observed := 0.025 ns; At : 1.397 ns
#    Time: 1397 ps  Iteration: 3  Instance:
/tim_top_tb/i_tim_top/g_dsp_n_1_i_dsp_n_g_global_bus_i_global_bus_link_i_global_bus_v241i875_q7

# ** Warning: CAS# Setup time violation -- tCMS
#    Time: 5 ns  Iteration: 1  Instance: /tim_top_tb/dspa_sdram0_inst
# ** Warning: RAS# Setup time violation -- tCMS


Article: 114354
Subject: Re: Too many warnings in Modelsim?
From: tgschwind@tiscalinet.ch
Date: 12 Jan 2007 05:19:36 -0800
Links: << >>  << T >>  << A >>
Let the simulation settle first, make it run for a few clock cycles and
see if the warning still appear.


Frai wrote:
> Hello, I am developing a solution using Xilinx ISE 8.2 and Modelsim
> 6.1. When I start the Post Place & Route simulation, I receive many
> warnings, since at the beginning some signals are in a incoherent
> state, like the Digital Clock Manager which is not locked yet.
>
> I would like to know what the experts do when they simulate complex
> circuits. Do you ignore those warnings? Do you try to eliminate them?
> Is there any way to filter innocuous warnings?
> 
> Regards.
>


Article: 114355
Subject: Re: Too many warnings in Modelsim?
From: "Frai" <maybetooparanoid@gmail.com>
Date: 12 Jan 2007 05:29:35 -0800
Links: << >>  << T >>  << A >>
After some cycles the warning doesn't appear any longer. I wonder if
there is any way to eliminate those warnings, or at least filter them.


Article: 114356
Subject: Stratix RAM limitations
From: "Peter Y" <yiannac@gmail.com>
Date: 12 Jan 2007 06:06:23 -0800
Links: << >>  << T >>  << A >>

I have a design needing a RAM which Quartus is putting into 2 VERY
under-utilized Mega-RAMs instead of the M4Ks I want it to be built
with.  When I try to force it in the M4Ks I get the message:

Error: Can't use port A width with port B width in altsyncram
megafunction

I initially instantiated altsyncram manually but when I got the error I
used the memory compiler to generate it (which also let me force it in
the M4Ks) and still got the same thing.

The RAM parameters are:

- Bidirection dual port mode
- Port A: Read/Write, 32-bits wide, 256 entries, 4-bits of byte enable
- Port B: Write only, 128-bits wide, 64 entries, no byte enable
- no output registers for either ports
- Each of port A and B has its own separate clock

Does anyone know why this is happening or how I can fix it?  I could
just string up 8 M4Ks myself but doing this manually may be painful as
I expect these parameters to change a lot.

Peter


Article: 114357
Subject: FIFO LogiCore with ISE 8.2 ??
From: "Matthieu Cattin" <matthieu.cattin@cern.ch>
Date: Fri, 12 Jan 2007 16:36:02 +0100
Links: << >>  << T >>  << A >>
Hi all,

I've created 2 different FIFO with Xilinx Core Generator.

I insert the first one in my design, everything is ok. But when I try to 
insert the second one, ISE told me that;
"Only one design unit  of this type is allowed for the same top module"

How can I put my to FIFO in my design?

Thanks
Matthieu 



Article: 114358
Subject: Re: Stratix RAM limitations
From: "Hans" <hans64@ht-lab.com>
Date: Fri, 12 Jan 2007 15:55:58 GMT
Links: << >>  << T >>  << A >>

"Peter Y" <yiannac@gmail.com> wrote in message 
news:1168610783.587445.282160@38g2000cwa.googlegroups.com...
>
> I have a design needing a RAM which Quartus is putting into 2 VERY
> under-utilized Mega-RAMs instead of the M4Ks I want it to be built
> with.  When I try to force it in the M4Ks I get the message:
>
> Error: Can't use port A width with port B width in altsyncram
> megafunction
>
> I initially instantiated altsyncram manually but when I got the error I
> used the memory compiler to generate it (which also let me force it in
> the M4Ks) and still got the same thing.
>
> The RAM parameters are:
>
> - Bidirection dual port mode
> - Port A: Read/Write, 32-bits wide, 256 entries, 4-bits of byte enable
> - Port B: Write only, 128-bits wide, 64 entries, no byte enable
> - no output registers for either ports
> - Each of port A and B has its own separate clock
                                                          ^^^^^^^^^^^^^^^
This might be the problem, from the datasheets "Mixed-port read-during-write 
is not supported when two different clocks
are used in a dual-port RAM", see page 2-35 Stratix-II device handbook,

Just a thought,

Hans
www.ht-lab.com



>
> Does anyone know why this is happening or how I can fix it?  I could
> just string up 8 M4Ks myself but doing this manually may be painful as
> I expect these parameters to change a lot.
>
> Peter
> 



Article: 114359
Subject: Re: inserting text into a video stream (from a pre-existing video source)
From: "wallge" <wallge@gmail.com>
Date: 12 Jan 2007 08:23:28 -0800
Links: << >>  << T >>  << A >>
> You wont be able to be video-format-agnostic for a number of
> reasons :
>
> To properly CHAR insert you need to phase-lock to the incomming Line
> Sync
> (often called GenLock) - if you do not do this, the chars jitter about
> as you
> have two clock domains.

No, in my design all the video processing is done in a processing clock
domain
that is bridged to the input video clock domain by asynchronous FIFOs.
What you are describing should not be a problem in my system.
Each pixel carries three flags: frame start, line start, and valid
data.
Video timing counters increment as appropriate when each of these flags
is observed in
a given video processing block.

>
> You also need to Sync to Frame, and count lines, to decide when to
> start the CHAR insert-stream.

I realize that lines need to be counted, and position in the current
frame kept track of,
and thus you need to know the number of valid/blank pixels and lines
and count them while
the system is online.
But these parameters could be set as generics or package constants or
even passed in
to registers at run time (if we wanted the char-gen scheme to be
resolution and timing agnostic).

This is the kind of block I am looking for. But it looks as if no-one
knows of something like this floating around on the web.


Article: 114360
Subject: Re: Transport Delays in Modelsim
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Fri, 12 Jan 2007 10:35:09 -0700
Links: << >>  << T >>  << A >>
Jonathan Bromley wrote:
> On Thu, 11 Jan 2007 12:04:50 -0700, Kevin Neilson
> <kevin_neilson@removethiscomcast.net> wrote:
> 
> [Jonathan]
>>> If you want transport delay in your own Verilog model, use
>>> intra-assignment nonblocking delays - try tnis...
>>>   always @(sig_in) sig_out <= #4 sig_in;
> 
>> That is wonderful.  It totally works.  I wish I'd known this before.
> 
> Lots of people say that when we tell them :-)
> 
> It can do other magic too.  The #N transport delay can be replaced
> with an event control:
> 
>   sig_out <= @(posedge clk) sig_in;
> 
> in other words, evaluate sig_in right now, and schedule it for
> assignment to sig_out on the next posedge; and, even more
> fun,
> 
>   sig_out <= repeat (4) @(posedge clk) sig_in;
> 
> which makes a very efficient, very compact model of a
> 4-stage pipeline delay.  Note that the assignment is nonblocking
> so therefore the statement itself executes in zero time - execution
> proceeds immediately - even though the assignment takes place
> some considerable time later.
> 
>>  I would like to 
>> be able to adjust  the delay on-the-fly, in order to model pad/trace 
>> delays that change over time, but I don't think that's possible.
> 
> It's panto time... Oh yes it is!!!!
> 
> The numeric value in the delay expression is evaluated each time the
> statement executes; it can be any run-time expression, unlike the 
> delay in a continuous assign which must be an elaboration-time
> constant.  The only thing to note is that any expression needs to 
> be enclosed in parentheses.  So...
> 
>   sig_out <= #(base_delay + fudge_factor * temperature) sig_in;
> 
> Take care, though.  This means that later assignments can overtake
> earlier assignments, if the time delay is sufficiently different: 
> consider this...
> 
>   initial begin
>     S <= #10 expr1;   // will update S at time=10
>     #5                       // delay until time=5
>     S <= #2 expr2;    // will update S at time=7
> 
> so you get the somewhat counterintuitive result that S takes on
> the value expr2 at time 7, and then expr1 at time 10.
> 
> There's one piece of really bad news about this, though.
> I am not aware of *any* reliable way, in Verilog, of revoking 
> a future nonblocking assignment once you've committed it.
> Disabling the code block that did the assignment *may*
> revoke its pending nonblocking assignments - some simulators
> do that - but it's explicitly left undefined in the LRM.

This is great stuff.  I replaced all of my adjustable delay lines, which 
consisted of long shift registers clocked by a 10GHz clock so I could 
achive 100ps resolution.  This was slowing down the simulation 
drastically.  I guess it is panto time--whatever that might be.  -Kevin

From invalid@dont.spam Fri Jan 12 09:37:59 2007
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From: Phil Hays <invalid@dont.spam>
Subject: Re: Ones' complement addition
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glen herrmannsfeldt wrote:

> Phil Hays wrote:
> 
> (snip regarding carry and ones complement adders)
> 
>> The case of interest is a calculation that should result in an answer
>> of zero. Note that there are two representations of zero in one's
>> complement notation, all '1's and all '0's, often called negative zero
>> and positive zero.
> 
>> If there is a carry, the answer is all '0's, or positive zero. If there
>> is no carry, the answer will be all '1's, or negative zero.

> If this were really a problem I don't believe Cray would have built ones
> complement machines when he was trying to build them as fast as
> possible.

There is a reason why ones complement isn't done on recent computers. Even
Cray didn't use it in his later machines. For example, a google search
found me this:

http://docs.cray.com/books/004-2179-001/html-004-2179-001/rvc5mrwh.html

There are solutions to this problem. From example, hold the last carry
until there is a stable next carry. The carry was faster than the sum,
as it was generated by a carry lookahead, and the sum required carry
ripple between several bits. From memory cells not refreshed since about
1975 or so, the CDC6600 did something like this. I just wrote some simple
programs on one, perhaps someone who knows more about the details will
comment.


> As far as I know (never having actually tried to build a ones complement
> machine) it is more usual to use a subtractor than adder. The reason I
> always thought it was done was to reduce the negative zero results. Does
> a subtractor still have this effect?

Why would a subtractor produce more or less negative zero results?


> Also, a Xilinx implementation will have the wraparound carry much slower
> than the others.

Which doesn't help. It is still a loop.


> Is real logic symmetric in propagation time for zero and one?

It can be.

CMOS logic is inverting. A carry value of "zero" or "one" must be both a
physical low and a physical high at different stages of the circuit. While
the high to low transition may be faster than the low to high transition,
the next stage is the inverse, so some or all of the difference cancels
out.


-- 
Phil Hays (Xilinx, but speaking for myself)



Article: 114361
Subject: Re: Stratix RAM limitations
From: "Peter Y" <yiannac@gmail.com>
Date: 12 Jan 2007 10:23:27 -0800
Links: << >>  << T >>  << A >>

I should have mentioned that, but the read-during-write is set to
DONT_CARE so that's not it.  Setting it to OLD_DATA gives errors about
that, however the error I've been getting is about the widths, and
everything I've seen so far in the Handbook tells me this should be
allowed.  Also, this is a Stratix I part (a 1S80) that I'm targetting.

Peter


Article: 114362
Subject: Re: RocketIO, MGT documentation. Does MGT clcok have to be 50% duty
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Fri, 12 Jan 2007 11:03:37 -0800
Links: << >>  << T >>  << A >>
Dale wrote:
> Is it just me or is the documentation for the RocketIO (MGT) for the
> Xilinx Virtex4 very bad?  I'm trying to find duty cycle requirements
> for the MGT clock.  Is it OK to use a clock with a 40% duty cycle?
> 
> Also, if anyone can point me to some better RocketIO (MGT)
> documentation for the hardware guys I'd appreciate it.  I already have
> ug076.

There is no duty cycle specification for the RocketIO reference
clock as this only feeds the PLL with the MGT.  The important
characteristics for this source are the jitter specifications.
A 40/60 duty cycle would be fine so long as the jitter of the
edges meets the requirements.

Ed McGettigan
--
Xilinx Inc.

Article: 114363
Subject: Re: picoblaze RS-232 using 62.5 MHz
From: "Eric Crabill" <eric.crabill@xilinx.com>
Date: Fri, 12 Jan 2007 11:23:06 -0800
Links: << >>  << T >>  << A >>
Hi,

I have used a similar approach with Ken Chapman's UARTs, where I wanted to 
run at 115200 baud with a 25 MHz reference clock.  This particular 
combination has significant mismatch with an integer enable count, so I did 
this:

always @(posedge clk)
begin
if (en_16_x_startover) en_16_x_cntr <= 0;
else en_16_x_cntr <= en_16_x_cntr + 1;
end

assign en_16_x_startover = (en_16_x_cntr == 26);
assign en_16_x_baud = (en_16_x_cntr == 26) || (en_16_x_cntr == 13);

It's always 16 enables per bit, but the enables come every 14, 13, 14, 13... 
cycles.  That was good enough to solve my problem.

Eric

"-jg" <Jim.Granville@gmail.com> wrote in message 
news:1168571655.100170.198640@s34g2000cwa.googlegroups.com...
>
> Some of the better UARTS support fractional baud define, where
> they do not always use 16 clks per bit, but can rate-multiply
> between 15 or 16, over the Rx bits. That gives you more Xtal
> freedom, and you can get closer to the precise baud rate,
> or higher baudrates.
>
> -jg 



Article: 114364
Subject: XST bug inferring dynamic shift register
From: Eric Brombaugh <ebrombaugh.invalid.@earthlink.net>
Date: Fri, 12 Jan 2007 19:25:07 GMT
Links: << >>  << T >>  << A >>
Hi,

I've got the following Verilog code which selects a variable tap from a 
delay line:

	wire [2:0] idly;							
	reg signed [dsz-1:0]	d0, d1, d2, d3,	
				d4, d5, d6, d7;
	reg signed [dsz-1:0] id;

	always @(posedge clk)
	begin
		d0 <= in;
		d1 <= d0;
		d2 <= d1;
		d3 <= d2;
		d4 <= d3;
		d5 <= d4;
		d6 <= d5;
		d7 <= d6;
	end

	always @(*)
		case(idly)
			3'b000: id = d3;
			3'b001: id = d2;
			3'b010: id = d1;
			3'b011: id = d0;
			3'b100: id = d7;
			3'b101: id = d6;
			3'b110: id = d5;
			3'b111: id = d4;
		endcase

Note that the delay amount is not equal to the idly value - this is 
intentional to give a 2's complement interpretation of the delay.

When using XST from ISE 8.2.02i, a dynamic shift register is inferred 
here, but the 2's complement nature is ignored, resulting in a mismatch 
between simulation and synthesis. To correct this, I had to make the 
following modification to the mux logic:

	wire [2:0] sel;
	assign sel = idly^3'b100;	// invert msb
	always @(*)
		case(sel)
			3'b000: id = d7;
			3'b001: id = d6;
			3'b010: id = d5;
			3'b011: id = d4;
			3'b100: id = d3;
			3'b101: id = d2;
			3'b110: id = d1;
			3'b111: id = d0;
		endcase

This works correctly. Has anyone else seen this? Is this a known bug in 
XST 8.2.02i? A quick search through the Xilinx answers doesn't show it, 
but I often have trouble with the search engine there.

Eric

Article: 114365
Subject: Re: xc3sprog
From: Eli Hughes <emh203@psu.edu>
Date: Fri, 12 Jan 2007 15:08:00 -0500
Links: << >>  << T >>  << A >>

I use Xilinx Tools on Linux.   What does your tool do that I can't 
already do with my setup now? (Xilinx Foundation with EDK and USB 
programming cable)

-Eli

Andrew Rogers wrote:
> Andrew Rogers wrote:
>> Hi,
>>
>> ...
>> What I would like to do is to incorporate the many suggestions and 
>> patches into the next release of xc3sprog if people are still using it.
>>
>> I would be particularly interested in modifications to xc3sprog for 
>> USB programmers. My laptop does not have a parallel port:(
>>
>> Regards
>> Andrew Rogers
> 
> Sorry, I forgot to mention that emails sent to me should include 
> [XC3SPROG] in the subject field. This helps me to filter them from the 
> 150 SPAMs I get a day.
> 
> Happy New Year!
> Andrew Rogers
> 

Article: 114366
Subject: Re: 16-bit DDR memory controller in EDK
From: "cpope" <cepope@nc.rr.com>
Date: Fri, 12 Jan 2007 15:36:02 -0500
Links: << >>  << T >>  << A >>

<sheikh.m.farhan@gmail.com> wrote in message
news:1168595277.938053.28500@a75g2000cwd.googlegroups.com...
> Hi,
> I need to know is it possible to have a 16-bit PLB DDR memory
> controller in EDK 8.x for a custom made board. So far what I have seen
> is EDK supports 32 and 64-bits PLB DDR controller for third party base
> systems.
> Has anyone tried to port Linux 2.4.x successfully on PPC running on
> Virtex 4? Any issues.......
>
> Farhan
>

I'm pretty sure that a 16-bit DDR interface has to go on OPB, PLB won't
support it.

I have Linux 2.6 running on my V4 right now. Linux is the easy part. Getting
all you peripherals and drivers work is the time consuming part.

If you want a pre-rolled solution see Monta Vista. But there are plenty of
do it yourself info on the web.

-Clark



Article: 114367
Subject: Re: Transport Delays in Modelsim
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Fri, 12 Jan 2007 22:27:16 +0000
Links: << >>  << T >>  << A >>
On Fri, 12 Jan 2007 10:35:09 -0700, Kevin Neilson
<kevin_neilson@removethiscomcast.net> wrote:

>Jonathan Bromley wrote:
>> It's panto time... Oh yes it is!!!!

>  I guess it is panto time--whatever that might be.

Sorry, I should have taken note of your timezone.

Someone else please explain :-)
-- 
Jonathan Bromley, Consultant

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Article: 114368
Subject: Re: xc3sprog
From: "mmihai" <iiahim@yahoo.com>
Date: 12 Jan 2007 14:43:45 -0800
Links: << >>  << T >>  << A >>
Andrew Rogers wrote:

> It's been over two years since I released xc3sprog. Since then Xilinx
> has released ISEWebPack for GNU/Linux. Many people have sent me
> modifications for various additions to xc3sprog.
>
> A lot has happenned to me in two years. I moved house (the Xilinx kit is
> still in the loft). Have completeted my Ph.D. except the thesis which
> seems to take for ever.
>
> What I would like to do is to incorporate the many suggestions and
> patches into the next release of xc3sprog if people are still using it.
>
> I would be particularly interested in modifications to xc3sprog for USB
> programmers. My laptop does not have a parallel port:(

I think I've tried to contact you via email more than one year ago and
got no answer.

It looks like several people (me included) made use of xc3sprog and
updated it (I have patches to compile under FreeBSD, program XCF01S and
other misc enhancements).

There is a project started on sourceforge (named xc3sprog) which also
adds USB connectivity option (I'll be testing it soon).

Last December I've migrated my changes to this source base since it
seemed more active; however, reading the posts regarding xc3sprog on
this newsgroup and sourceforge you'll find people trying to commit
changes and not being able to. May be you can try to get in touch with
the sourceforge project owner and help with managing new patches (I'll
be more than happy to submit my changes if somehow is possible).

I think having tools to do JTAG programming in userland is quite
valuable since they are more portable than closed source, proprietary
kernel which is required by IMPACT.

I am more than happy using xc3sprog under FreeBSD (xst FPGA fitting
runs under FreeBSD w/ linux emulation as well). It looks like people
are looking more after free stuff than open source (see RealPlayer,
jtag programming, ATI/NVIDIA drivers, etc, for which the development of
opensource sw is quite slow).

--

mmihai


Article: 114369
Subject: How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 12 Jan 2007 16:59:38 -0800
Links: << >>  << T >>  << A >>
Hi,
I would like to ask for your help with a problem I met in simulation
with ModelSim.

I generated single port distributed ram with initial file *.mif
successfully with Xilinx chip Vertex II.

When I started debugging the design, I found all single port
distributed ram were not initialized. All their outputs are 'X'.

I changed my design to make its inputs signal are constant, the results
are still 'X'.

I changed initial file name and when running ModelSim it showed errors.
It shows ModelSim reads the initial file.

What should I do with ModelSim single port distributed ram initial file
problem?

Thank you.

Weng


Article: 114370
Subject: Re: How to get correct initial values from Xilinx Vertex II single
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 12 Jan 2007 17:23:04 -0800
Links: << >>  << T >>  << A >>
Weng Tianxiang wrote:

> When I started debugging the design, I found all single port
> distributed ram were not initialized. All their outputs are 'X'.

That is normal for a RAM model.
To make a RAM output valid the testbench
must perform a write and read cycle to the
same address.
Maybe a ROM is what you want.

 -- Mike Treseler

Article: 114371
Subject: Re: Stratix RAM limitations
From: "Rob" <robnstef@frontiernet.net>
Date: Sat, 13 Jan 2007 03:21:49 GMT
Links: << >>  << T >>  << A >>
Peter,



>From the datasheet:

The widest bit configuration of the M4K and M-RAM blocks in true dualport

mode is 256  16-bit ( 18-bit with parity) and 8K  64-bit ( 72-bit

with parity), respectively. The 128  32-bit ( 36-bit with parity)

configuration of the M4K block and the 4K  128-bit ( 144-bit with parity)

configuration of the M-RAM block are unavailable because the number of

output drivers is equivalent to the maximum bit width of the respective

memory block. Because true dual-port RAM has outputs on two ports,

the maximum width of the true dual-port RAM equals half of the total

number of output drivers.



It seems to me that your 32bit port A is forcing this into MRAM.  And I 
believe the reason it is using 2 MRAM's is due to your 128 port B.



Rob


"Peter Y" <yiannac@gmail.com> wrote in message 
news:1168610783.587445.282160@38g2000cwa.googlegroups.com...
>
> I have a design needing a RAM which Quartus is putting into 2 VERY
> under-utilized Mega-RAMs instead of the M4Ks I want it to be built
> with.  When I try to force it in the M4Ks I get the message:
>
> Error: Can't use port A width with port B width in altsyncram
> megafunction
>
> I initially instantiated altsyncram manually but when I got the error I
> used the memory compiler to generate it (which also let me force it in
> the M4Ks) and still got the same thing.
>
> The RAM parameters are:
>
> - Bidirection dual port mode
> - Port A: Read/Write, 32-bits wide, 256 entries, 4-bits of byte enable
> - Port B: Write only, 128-bits wide, 64 entries, no byte enable
> - no output registers for either ports
> - Each of port A and B has its own separate clock
>
> Does anyone know why this is happening or how I can fix it?  I could
> just string up 8 M4Ks myself but doing this manually may be painful as
> I expect these parameters to change a lot.
>
> Peter
> 



Article: 114372
Subject: Re: xc3sprog
From: Andrew Rogers <andrew@_NO_SPAM_rogerstech.co.uk>
Date: Sat, 13 Jan 2007 12:38:36 GMT
Links: << >>  << T >>  << A >>
mmihai wrote:
> Andrew Rogers wrote:
> 
> 
>>It's been over two years since I released xc3sprog. Since then Xilinx
>>has released ISEWebPack for GNU/Linux. Many people have sent me
>>modifications for various additions to xc3sprog.
>>
>>A lot has happenned to me in two years. I moved house (the Xilinx kit is
>>still in the loft). Have completeted my Ph.D. except the thesis which
>>seems to take for ever.
>>
>>What I would like to do is to incorporate the many suggestions and
>>patches into the next release of xc3sprog if people are still using it.
>>
>>I would be particularly interested in modifications to xc3sprog for USB
>>programmers. My laptop does not have a parallel port:(
> 
> 
> I think I've tried to contact you via email more than one year ago and
> got no answer.
> 
> It looks like several people (me included) made use of xc3sprog and
> updated it (I have patches to compile under FreeBSD, program XCF01S and
> other misc enhancements).
> 
> There is a project started on sourceforge (named xc3sprog) which also
> adds USB connectivity option (I'll be testing it soon).
> 
> Last December I've migrated my changes to this source base since it
> seemed more active; however, reading the posts regarding xc3sprog on
> this newsgroup and sourceforge you'll find people trying to commit
> changes and not being able to. May be you can try to get in touch with
> the sourceforge project owner and help with managing new patches (I'll
> be more than happy to submit my changes if somehow is possible).
> 
> I think having tools to do JTAG programming in userland is quite
> valuable since they are more portable than closed source, proprietary
> kernel which is required by IMPACT.
> 
> I am more than happy using xc3sprog under FreeBSD (xst FPGA fitting
> runs under FreeBSD w/ linux emulation as well). It looks like people
> are looking more after free stuff than open source (see RealPlayer,
> jtag programming, ATI/NVIDIA drivers, etc, for which the development of
> opensource sw is quite slow).
> 
> --
> 
> mmihai
> 

Found it at:

http://sourceforge.net/projects/xc3sprog/

Great to see so many changes added to it. Once I worked out how to drive 
  sourceforge.net, ie. to upload changes, etc. I have a few updates myself.

Thanks
Andrew Rogers

Article: 114373
Subject: Will FPGAs suit my need?
From: NickHolby@googlemail.com
Date: 13 Jan 2007 07:04:45 -0800
Links: << >>  << T >>  << A >>
Hi all,

I'm an electronics hobbyist; my projects are generally quite small.
They generally consist of me using 7400 chips, and in some cases the
PIC microcontroller. However, I'm wanting to stretch out a little. What
I'm after is nothing more than a chip that contains thousands of 7400
chips, no clock, no onboard memory etc... Just a microchip which is in
essence thousands of 7400 chips. I would like actual control of the
connections between the chips, so I can say what gates link with what
without me doing something so general as 1+1 and the programmer
figuring out what to put.

I thought FPGAs might be suitable, but they all appear to try to offer
more than just something like that. Can anybody point me in some rough
direction?

Thanks for your time,
Nick


Article: 114374
Subject: Re: Will FPGAs suit my need?
From: "Icky Thwacket" <it@it.it>
Date: Sat, 13 Jan 2007 15:51:02 -0000
Links: << >>  << T >>  << A >>

<NickHolby@googlemail.com> wrote in message 
news:1168700683.831757.179720@l53g2000cwa.googlegroups.com...
> Hi all,
>
> I'm an electronics hobbyist; my projects are generally quite small.
> They generally consist of me using 7400 chips, and in some cases the
> PIC microcontroller. However, I'm wanting to stretch out a little. What
> I'm after is nothing more than a chip that contains thousands of 7400
> chips, no clock, no onboard memory etc... Just a microchip which is in
> essence thousands of 7400 chips. I would like actual control of the
> connections between the chips, so I can say what gates link with what
> without me doing something so general as 1+1 and the programmer
> figuring out what to put.
>
> I thought FPGAs might be suitable, but they all appear to try to offer
> more than just something like that. Can anybody point me in some rough
> direction?
>
> Thanks for your time,
> Nick
>

You will be better off starting out with a CPLD.
These are stand alone devices that do not require an external configuration 
memory and are generally much cheaper than FPGA's, typically under $5.

Have a look at
http://www.altera.com/products/devices/cpld/max2/mx2-index.jsp

Download Alteras' free software and start experimenting!
Altera software supports schematic entry and the included libraries include 
most of the 7400 series to get you started.
https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp

Good luck!

Icky 





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