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On 26 Feb., 19:48, Austin Lesea <aus...@xilinx.com> wrote: > Cat out of the bag? > > Well, sure looks like the website folks are going to have some > embarrassment from this. > > Yes, that link is certainly broken. > > As for 3AN, I have to wait until the release to talk about it, unless > you were already one of the "early adopters" and are under NDA. =C2=A0In = that > case, you already know everything. > > Austin !? email from Xilinx: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D The new Spartan=E2=84=A2-3AN FPGA platform signifies a breakthrough marriage of uncompromised SRAM FPGA and leading-edge Flash technologies. With highly advanced on-chip security features, the Spartan-3AN platform provides a cost-effective solution to help prevent reverse- engineering, cloning, and unauthorized overbuilding. Furthermore, designers can achieve superior system flexibility with up to 11Mb of integrated user Flash. Built on industry=E2=80=99s most successful cost- effective and production-proven 90nm technology, the Spartan-3AN platform provides unmatched performance, integration and cost. It is ideal for space-critical or secure applications as well as low cost embedded controllers. Register Now! =E2=80=94 for Webcast By attending the Introducing Spartan-3AN FPGAs =E2=80=93 Non-volatile Secure Platform for Highest System Integration Webcast you will learn how to: Implement a low-cost security solution Lower system cost Achieve higher system flexibility Improve design margins Reduce power consumption Accelerate your time to market Spartan-3AN FPGA Advantages =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D I assume this means S-3AN ___ARE__ officially launched or whatelse should I understand from the above mailing? was the email sent too early as accident? I assume not. AnttiArticle: 115951
Antti, Too early? Accident? Just don't know (yet). Obviously the email has detailed many of the features. But, so far, I have heard nothing from my inquiries here. AustinArticle: 115952
Does anyone have any info on the new non-volatile Spartan parts?Article: 115953
"Antti" <Antti.Lukats@xilant.com> wrote: >http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3an_fpgas/index.htm > >This is the link that makes the clicking sound when opened in >webbrowser. The page redirects to itself - doh. --Article: 115954
Hi Andrea, Let me add some more things to this: 1. The "opb_bram" core allows for smaller memory blocks. It lets you add controllers for the smaller sizes and thus make available more memory. 2. For me, the EDK 8.2 SP3 "data2mem" functionality does not work correctly with contiguous segments. I can assign different linker segments to different bram (controllers), but a linker segment cannot cross a bram border. Unfortunately all C code is compiled to a single TEXT segment, so the maximum code size for your project would be 32KB. Only the data, bss, stack, init, boot, etc segments can be moved to the additional bram controllers. 3. You can always implement your own bram controller, with only 63K used. Regards, MarcArticle: 115955
On 26 Feb., 20:18, Austin Lesea <aus...@xilinx.com> wrote: > Antti, > > Too early? Accident? Just don't know (yet). > > Obviously the email has detailed many of the features. > > But, so far, I have heard nothing from my inquiries here. > > Austin must be the (ro)bots have taken control at 2100 Logic Dr. ;) I was so happily surprised to see the Xilin official announcement in my mail (actually 2 copies of it) that I assumed it really is officially launched as of today and now. but its still working hours at eastcoast, so maybe things to get cleared up. AnttiArticle: 115956
Antti, Found out what happened: got sent out too soon (I suppose that is obvious...). Now we have to figure out 'how' it got sent out too soon (less obvious). Sorry for the inconvenience. AustinArticle: 115957
You had gotten a "sneak preview" per e-mail. Please give our guys one more day to get the website running properly. Apparently there is lots of (well-deserved) excitement... Good! Peter Alfke On Feb 26, 10:12 am, "Antti" <Antti.Luk...@xilant.com> wrote: > finally announced! > > so now can talk about them - well still not documents on Xilinx > website, but hopefully they will be available shortly > > AnttiArticle: 115958
Hello,
I'm trying to register some data coming from an ADC at 4ns period. I
currently have the following in my UCF:
<SNIP>
NET "adc_clk_p" TNM_NET = "TG_adc_clk_p";
TIMESPEC "TS_adc_clk_p" = PERIOD "TG_adc_clk_p" 4 ns HIGH 50%;
NET "adc?_db_p<*>" OFFSET = IN 1.0 ns BEFORE "adc_clk_p";
NET "adc?_db_n<*>" OFFSET = IN 1.0 ns BEFORE "adc_clk_n";
</SNIP>
However, the adc data arrives 2.59 ns +- (jitter) after the rising
edge of the clock. Is there anyway I can specify this in the TIMESPEC?
The PHASE attribute of TIMESPEC appears to only be valid for clock
relationships, correct?
I meet the constraints just fine, but when I inspect the registers in
chipscope, the adc output looks noisy:
http://img442.imageshack.us/my.php?image=adctimeif2.jpg (time domain)
http://img58.imageshack.us/my.php?image=adcfreqtp5.jpg (freq domain)
Here's the output from Timing Analyzer:
<SNIP>
================================================================================
Timing constraint: COMP "adc1_db_n<0>" OFFSET = IN 1 ns BEFORE COMP
"adc_clk_n";
1 item analyzed, 0 timing errors detected. (0 setup errors, 0 hold
errors)
Minimum allowable offset is 0.824ns.
--------------------------------------------------------------------------------
Slack: 0.176ns (requirement - (data path - clock path
- clock arrival + uncertainty))
Source: adc1_db_n<0> (PAD)
Destination: adc1_iface/ibuf_out_r_0 (FF)
Destination Clock: adc_clk rising at 0.000ns
Requirement: 1.000ns
Data Path Delay: 1.389ns (Levels of Logic = 2)
Clock Path Delay: 0.745ns (Levels of Logic = 4)
Clock Uncertainty: 0.180ns
Data Path: adc1_db_n<0> to adc1_iface/ibuf_out_r_0
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tiopp 1.206 adc1_db_n<0>
net (fanout=1) 0.000 adc1_iface/
array_gen[0].diffend_gen.ibufds_inst/SLAVEBUF.DIFFIN
Tiodi 0.000 adc1_iface/
array_gen[0].diffend_gen.ibufds_inst/IBUFDS
net (fanout=1) 0.054 adc1_iface/ibuf_out<0>
Tidock 0.129 adc1_iface/ibuf_out_r_0
---------------------------- ---------------------------
Total 1.389ns (1.335ns logic, 0.054ns route)
(96.1% logic, 3.9% route)
</SNIP>
I believe I want adc_clk rising at 0.000 ns to be adc_clk rising at
4.0-2.59 ns = 1.41 ns?
Article: 115959On 26 Feb., 21:01, "Peter Alfke" <p...@xilinx.com> wrote: > You had gotten a "sneak preview" per e-mail. > Please give our guys one more day to get the website running properly. > Apparently there is lots of (well-deserved) excitement... > Good! > Peter Alfke > > On Feb 26, 10:12 am, "Antti" <Antti.Luk...@xilant.com> wrote: > > ROTFL actually I got 2 "sneak previews" maybe i should have sold he other one on ebay! hehe - but YES the excitment is well-deserved ! Antti_smileArticle: 115960
Hi all I am working on partial reconfiguration and I am stuck. Say I have an INIT value of "8000" and I am changing it to "8800" the third input seems to be redundant and is removed from the routing process[xilinx]. Is there a way to overcome this. I want all the inputs to be routed irrespective of its redundant nature. Thanks in advance Mr.BArticle: 115961
Ray Andraka wrote: > It would be better to set the BRAMs up as 16Kx1, using as many as you > need for bits and then a simple 2:1 mux to select between two banks for > the 32K size. This eliminates a lot of the external logic by using more > of the internal decode. As a result you get considerably better timing > and power dissipation. Also, it turns out it is much easier to route > because each BRAM has only one read data and one write data rather than > the full width of the BRAM. Just a note for the archive: I agree with Ray, but if power consumption is a consideration, you need to experiment with both implementations. Some architectures have power burn strongly affected by the number of enabled BRAMs.Article: 115962
Antti wrote: > On 26 Feb., 21:01, "Peter Alfke" <p...@xilinx.com> wrote: >> You had gotten a "sneak preview" per e-mail. >> Please give our guys one more day to get the website running properly. >> Apparently there is lots of (well-deserved) excitement... >> Good! >> Peter Alfke >> >> On Feb 26, 10:12 am, "Antti" <Antti.Luk...@xilant.com> wrote: >> >> > ROTFL > actually I got 2 "sneak previews" maybe i should have sold he other > one on ebay! > > hehe - but YES the excitment is well-deserved ! > > Antti_smile > > > It's about gosh darn time these FPGA's have some flash built in. I have been waiting for this for awhile now. This will certainly think about moving away from Actel devices.... I have heard the "an external PROM is not a big deal" line for too long now. Its like telling MCU people "you don't need integrated FLASH". An external FLASH device is not a big deal. Sure, its just another external chip but it is 2007.Article: 115963
Just curious if anyone knows any facts/rumors about any eval boards (like, say an ML403) that are 10G capable?Article: 115964
"Peter Alfke" <peter@xilinx.com> wrote: >You had gotten a "sneak preview" per e-mail. >Please give our guys one more day to get the website running properly. >Apparently there is lots of (well-deserved) excitement... >Good! >Peter Alfke > The mail Antti got looks good. Maybe I can slip the Spartan 3AN into a current design if it is not too different from a regular Spartan 3. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 115965
Eli Hughes wrote: > > It's about gosh darn time these FPGA's have some flash built in. I have > been waiting for this for awhile now. This will certainly think about > moving away from Actel devices.... > > I have heard the "an external PROM is not a big deal" line for too long now. > > Its like telling MCU people "you don't need integrated FLASH". An > external FLASH device is not a big deal. Sure, its just another > external chip but it is 2007. I think these are dual-die solutions - so they are not going to be 'instant on', like the Actel devices. ( relative load times anyone ? ) More interesting will be how wide the flash bus is. A vanilla serial device is cheapest to put in, but that's likely to be more costly than an external serial flash device. If they have added a security layer, you will be paying for that. -jgArticle: 115966
On 26 Feb., 22:45, n...@puntnl.niks (Nico Coesel) wrote: > "Peter Alfke" <p...@xilinx.com> wrote: > >You had gotten a "sneak preview" per e-mail. > >Please give our guys one more day to get the website running properly. > >Apparently there is lots of (well-deserved) excitement... > >Good! > >Peter Alfke > > The mail Antti got looks good. Maybe I can slip the Spartan 3AN into a > current design if it is not too different from a regular Spartan 3. > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U opwww.adresboekje.nl consider them "as" S-3A, so look at S-3A and that what you get in S-3AN as well. only add the nonvolatile part... AnttiArticle: 115967
The LOCK_PINS attribute worked for me. Do a newsgroup search on LOCK_PINS and you'll find a conversation from a couple months ago along the same lines. "Mr B" <bharadwaj.sr@gmail.com> wrote in message news:1172521908.914352.77720@h3g2000cwc.googlegroups.com... > Hi all > > I am working on partial reconfiguration and I am stuck. Say I have an > INIT value of "8000" and I am changing it to "8800" the third input > seems to be redundant and is removed from the routing process[xilinx]. > Is there a way to overcome this. I want all the inputs to be routed > irrespective of its redundant nature. > > Thanks in advance > > Mr.B >Article: 115968
Hi Prasad, prasad.anirudh@gmail.com wrote: > Could some one give some information on ICAP.I have read thru the > documentation on www.xilinx.com on dynamic reconfiguration,I still > have not understood how would I access the ICAP port?I am basically > trying to use the PowerPC on the virtex 4 to dynamically reconfigure > the FPGA.I am also looking to synthesize a Microblaze softcore and > make it do the reconfiguration. > > So in short Here is my specific Question > > .How do I access the ICAP?Does it have a port address?Say I write a C+ > + program running on the microblaze,my intension is to change the > bitstream dynamically by using the ICAP. Look at the opb_hwicap peripheral distributed with Xilinx EDK. It is a simple OPB interface to the ICAP primitive. You can also find a Linux device driver (microblaze / ppc) for this core here: http://www.itee.uq.edu.au/~listarch/partial-reconfig/archive/2006/04/msg00009.html Regards, JohnArticle: 115969
self wrote: > Hello All, > > I have a Xilinx ML501 board and I want to use the Xilinx XCF32P > platform flash to configure the XC5VLX50. > > I can program the LX50 directly accross the JTAG chain and the design > runs correctly (flashing LED's). > > Also the XCF32P does show up on the chain and Impact lets me program > it. Unfortunately, when I hit the program button my design does not > come up. The done LED goes true after a delay as if the part is > programming from some other source. > > There is a 8 position dip switch on the board, SW15, that apparently > controls the configuration source but the documentation is not clear > about how to set that switch for platform flash. I have all zeros > selected now. > > Can anyone just tell me how to set SW15 to configure from the platform > flash on the ML501? > This is documented on page 28 of the ML501 User Guide (ug226). Ed McGettigan -- Xilinx Inc.Article: 115970
On Feb 26, 10:12 am, "Antti" <Antti.Luk...@xilant.com> wrote: > finally announced! > > so now can talk about them - well still not documents on Xilinx > website, but hopefully they will be available shortly > > Antti I am pleased to announce that the Spartan-3AN FPGA family is now officially out in the open. Full technical literature is now available on the Xilinx web site. Spartan-3AN Non-Volatile FPGA Family http://www.xilinx.com/spartan3an Spartan-3AN Technical Literature Page http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=Publications/FPGA+Device+Families/Spartan-3AN -- Steve KnappArticle: 115971
On Feb 26, 1:53 pm, "-jg" <Jim.Granvi...@gmail.com> wrote: > I think these are dual-die solutions - so they are not going to be > 'instant on', > ( relative load times anyone ? ) You are correct that Spartan-3AN FPGAs are not "instant on", as some devices claim to be. Spartan-3AN FPGAs configure from internal In- System Flash memory. There is enough Flash for two FPGA configuration bitstreams (a primary, and a "MultiBoot" image), plus still more room for nonvolatile application data. The Flash architecture also supports Flash memory blocks down to 264 bytes. The FPGA configuration time depends on the FPGA device size. Assuming that power is already stable, the smallest part, the XC3S50AN, configures in about 45. ms, worst-case. The largest part, the XC3S1400AN, configures in about 310 ms, worst-case. > More interesting will be how wide the flash bus is. A vanilla serial > device is cheapest to put in The In-System Flash essentially uses an internal SPI serial bus that operates up to 66 MHz. If you only use the In-System Flash for configuration, then you can completely ignore the details. However, the Flash is available to the FPGA application after configuration. The FPGA application has direct access to the Flash using a new design primitive called SPI_ACCESS. There is a separate user guide that delves into the details. UG333: Spartan-3AN In-System Flash User Guide http://direct.xilinx.com/bvdocs/userguides/ug333.pdf --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3 Generation FPGAs http://www.xilinx.com/spartan3a http://www.xilinx.com/spartan3an http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 115972
On Feb 26, 2:32 am, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> wrote: > While both Device/package combinations are listed in the datasheets, I have > not seen any of these devices "out in the wild" (means available with > Digikey(*)/Nuhorizons/Avnet). I bothered Xilinx people at both Electronica > 2006 and Embedded World 2007 about availability/plans for availability for > these devices, but never heared back. > > Does anybody have more information about these device/package combination? > > Thanks > > (*) Digikey list the XC3S4004PQ208C as available on demand with minimum > order of 120 pieces. > > -- > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Hi Uwe, Thanks for bringing this to our attention. I've passed this on to our distribution manager and he's working to remedy the situation. Both the XC3S400 and the XC3S500E FPGAs are most definitely available. The working theory is that the PQ208 package option is not the highest running product combinations. Consequently, our distributors aren't stocking them. I fully understand the attraction of the QFP package, however. -- Steve KnappArticle: 115973
can it be done? where do I look for information? RichArticle: 115974
Hi, I am doing FPGA design with xilinx spartan 3e. When I finished P&R, I checked the timing report. Everything is ok, and there is no timing violations. But when I run post simulation, the modelsim reports some timing errors for some registers with $recovery(...). I checked the time when these errors occur. They happened to be the time when reset is de-assertion. I tried to change reset period, but this time other register report $recovery/$setup/$hold errors. It is very strange because I have passed P&R, there is no timing violations, why does these errors orrur? Can anybody help me? thanks very much.
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