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Threads Starting Nov 2003

62548: 03/11/01: <sc01@hotmail.com>: Convert verilog to VHDL??
    62550: 03/11/01: Glen Herrmannsfeldt: Re: Convert verilog to VHDL??
    62556: 03/11/01: Valentin Tihomirov: Re: Convert verilog to VHDL??
    62562: 03/11/02: David R Brooks: Re: Convert verilog to VHDL??
62549: 03/11/01: <sc01@hotmail.com>: WinCE driver for Wildcard from Annapolis Micro System?
    62571: 03/11/01: Will: Re: WinCE driver for Wildcard from Annapolis Micro System?
62563: 03/11/01: jerry1111: Nios & external RAM
    62566: 03/11/01: jerry1111: Re: Nios & external RAM
62564: 03/11/01: :: Gabster ::: Using unused space on a PROM (configuration device) as an EEPROM
    62573: 03/11/02: Glen Herrmannsfeldt: Re: Using unused space on a PROM (configuration device) as an EEPROM
62569: 03/11/01: Ljubisa Bajic: Video decoder and encoder IC's
    62570: 03/11/02: Khim Bittle: Re: Video decoder and encoder IC's
62576: 03/11/02: Seb K: Xilinx Weback 6.1i - Java Exception
    62580: 03/11/02: Marc Guardiani: Re: Xilinx Weback 6.1i - Java Exception
        62584: 03/11/02: Seb K: Re: Xilinx Weback 6.1i - Java Exception
    62601: 03/11/03: Klaus Falser: Re: Xilinx Weback 6.1i - Java Exception
        62603: 03/11/03: Seb K: Re: Xilinx Weback 6.1i - Java Exception
62578: 03/11/02: blisca: help ;lattice synario error
62582: 03/11/02: Amstel: VHDL Xilinx Flow Engine ERROR
    62583: 03/11/02: Bob Perlman: Re: VHDL Xilinx Flow Engine ERROR
62585: 03/11/02: Rajeshwary: Spartan II with Digilab board, IO communication
62588: 03/11/02: Tullio Grassi: Power-On-Reset from a xilinx
    62589: 03/11/02: Martin Euredjian: Re: Power-On-Reset from a xilinx
    62606: 03/11/03: Simon Peacock: Re: Power-On-Reset from a xilinx
        62614: 03/11/03: Amontec Team, Laurent Gauch: Re: Power-On-Reset from a xilinx
62591: 03/11/03: John Williams: Vendor supplied symbol/part models?
    62592: 03/11/03: Hal Murray: Re: Vendor supplied symbol/part models?
        62594: 03/11/03: Martin Euredjian: Re: Vendor supplied symbol/part models?
            62596: 03/11/03: John Williams: Re: Vendor supplied symbol/part models?
                62598: 03/11/03: Hal Murray: Re: Vendor supplied symbol/part models?
                62652: 03/11/04: Brian Drummond: Re: Vendor supplied symbol/part models?
        62615: 03/11/03: mikegw: Re: Vendor supplied symbol/part models?
        62618: 03/11/03: Martin Thompson: Re: Vendor supplied symbol/part models?
        62629: 03/11/03: Symon: Re: Vendor supplied symbol/part models?
        62639: 03/11/04: John Williams: Re: Vendor supplied symbol/part models?
            62649: 03/11/04: Martin Thompson: Re: Vendor supplied symbol/part models?
    62657: 03/11/04: rob d: Re: Vendor supplied symbol/part models?
    62669: 03/11/04: Leon Heller: Re: Vendor supplied symbol/part models?
62597: 03/11/03: mikegw: Building the 'uber processor'
    62605: 03/11/03: Simon Peacock: Re: Building the 'uber processor'
        62612: 03/11/03: mikegw: Re: Building the 'uber processor'
            62655: 03/11/04: Mario Trams: Re: Building the 'uber processor'
            62660: 03/11/04: Kolja Sulimma: Re: Building the 'uber processor'
                62740: 03/11/06: mikegw: Re: Building the 'uber processor'
            62662: 03/11/04: kryten_droid: Re: Building the 'uber processor'
    62616: 03/11/03: john jakson: Re: Building the 'uber processor'
    62640: 03/11/04: John Williams: Re: Building the 'uber processor'
        62650: 03/11/04: mikegw: Re: Building the 'uber processor'
            62653: 03/11/04: Don Taylor: Re: Building the 'uber processor'
            62700: 03/11/05: Thomas Stanka: Re: Building the 'uber processor'
        62664: 03/11/04: Ron Huizen: Re: Building the 'uber processor'
    62648: 03/11/03: Antti Lukats: Re: Building the 'uber processor'
        62686: 03/11/05: David R Brooks: Re: Building the 'uber processor'
    62654: 03/11/04: Philip Freidin: Re: Building the 'uber processor'
        62693: 03/11/04: john jakson: Re: Building the 'uber processor'
            62718: 03/11/05: Jonathan Bromley: Re: Building the 'uber processor'
                62727: 03/11/05: john jakson: Re: Building the 'uber processor'
                    62733: 03/11/06: Goran Bilski: Re: Building the 'uber processor'
                        62762: 03/11/06: john jakson: Re: Building the 'uber processor'
                            62777: 03/11/07: Goran Bilski: Re: Building the 'uber processor'
                                62821: 03/11/08: john jakson: Re: Building the 'uber processor'
                                    62847: 03/11/10: Goran Bilski: Re: Building the 'uber processor'
                            62785: 03/11/07: Mario Trams: Re: Building the 'uber processor'
                                62822: 03/11/08: john jakson: Re: Building the 'uber processor'
                                62830: 03/11/09: jetmarc: Re: Building the 'uber processor'
    63073: 03/11/13: Marc Van Riet: Re: Building the 'uber processor'
        63095: 03/11/14: Thomas Womack: Re: Building the 'uber processor'
62600: 03/11/03: Lockie: Xilinx - Multi Volt Interfacing
    62643: 03/11/04: Sandeep Kulkarni: Re: Xilinx - Multi Volt Interfacing
        62658: 03/11/04: Lockie: Re: Xilinx - Multi Volt Interfacing
            62666: 03/11/04: Nial Stewart: Re: Xilinx - Multi Volt Interfacing
            62670: 03/11/04: Peter Alfke: Re: Xilinx - Multi Volt Interfacing
                62688: 03/11/05: Lockie: Re: Xilinx - Multi Volt Interfacing
62602: 03/11/03: Rotem Gazit: Altera "my support" :-(
    62626: 03/11/03: Marc: Re: Altera "my support" :-(
    62627: 03/11/03: Mike Treseler: Re: Altera "my support" :-(
    62642: 03/11/03: Jerry: Re: Altera "my support" :-(
    62755: 03/11/06: Joe Thompson: Re: Altera "my support" :-(
        62772: 03/11/07: rickman: Re: Altera "my support" :-(
            62794: 03/11/07: Austin Lesea: Re: Altera "my support" :-(
62611: 03/11/03: <moonygals@yahoo.com>: synplify Pro 7.3.1
62617: 03/11/03: Vazquez: Using the Virtex Block Select RAM+ Features
    62633: 03/11/03: Peter Alfke: Re: Using the Virtex Block Select RAM+ Features
62619: 03/11/03: Nick: Defect and Fault Tolerance Material
    62644: 03/11/04: Sandeep Kulkarni: Re: Defect and Fault Tolerance Material
62623: 03/11/03: Taufik Siswanto: 5 input LUT in virtex
62645: 03/11/03: Nagaraj: Tools Tree
    62685: 03/11/04: Mike Treseler: Re: Tools Tree
        62704: 03/11/05: Nagaraj: Re: Tools Tree
            62706: 03/11/05: fe: Re: Tools Tree
                62751: 03/11/06: Hans: Re: Tools Tree
                    62752: 03/11/06: Nicholas C. Weaver: Re: Tools Tree
            62870: 03/11/10: Neeraj Varma: Re: Tools Tree
62647: 03/11/04: Basuki Endah Priyanto: Re: Searching for 802.11a/g implementations
62651: 03/11/04: H. Peter Anvin: Prototyping board with 4+ MB SRAM?
    62656: 03/11/04: Philip Freidin: Re: Prototyping board with 4+ MB SRAM?
    62675: 03/11/04: Jon Beniston: Re: Prototyping board with 4+ MB SRAM?
        62720: 03/11/05: Dave Vanden Bout: Re: Prototyping board with 4+ MB SRAM?
62661: 03/11/04: wolfgang: DCM recover after interruption of input clock
    62665: 03/11/04: Alvin Andries: Re: DCM recover after interruption of input clock
    62667: 03/11/04: Austin Lesea: Re: DCM recover after interruption of input clock
    62684: 03/11/04: Martin Euredjian: Re: DCM recover after interruption of input clock
62671: 03/11/04: Thomas Womack: I/O on current FPGAs - deserialise first ??
    62674: 03/11/04: Peter Alfke: Re: I/O on current FPGAs - deserialise first ??
    62676: 03/11/04: Uwe Bonnes: Re: I/O on current FPGAs - deserialise first ??
    62705: 03/11/05: Jeff Cunningham: Re: I/O on current FPGAs - deserialise first ??
        62710: 03/11/05: Mike Treseler: Re: I/O on current FPGAs - deserialise first ??
            62732: 03/11/06: Jeff Cunningham: Re: I/O on current FPGAs - deserialise first ??
62672: 03/11/04: Nicholas C. Weaver: Silly ML300 question...
62673: 03/11/04: Ted Lechman: help with 120MHz comparator
    62678: 03/11/04: Daniel Lang: Re: help with 120MHz comparator
        62681: 03/11/04: Austin Lesea: Re: help with 120MHz comparator
    62679: 03/11/04: Hal Murray: Re: help with 120MHz comparator
62677: 03/11/04: Timothy Miller: Voila: Nedit macro to produce verilog module instantiations
    62680: 03/11/04: Joerg Fischer: Re: Voila: Nedit macro to produce verilog module instantiations
        62708: 03/11/05: Timothy Miller: Re: Voila: Nedit macro to produce verilog module instantiations
            62753: 03/11/06: Joerg Fischer: Re: Voila: Nedit macro to produce verilog module instantiations
    62702: 03/11/05: vijay: Re: Voila: Nedit macro to produce verilog module instantiations
        62709: 03/11/05: Bob Perlman: Re: Voila: Nedit macro to produce verilog module instantiations
62682: 03/11/04: Scott Connors: Video Scan Conversion Rate - Camera Input to DVI Display Output
    62683: 03/11/04: Jim Lewis: Re: Video Scan Conversion Rate - Camera Input to DVI Display Output
    62687: 03/11/04: Symon: Re: Video Scan Conversion Rate - Camera Input to DVI Display Output
    62691: 03/11/05: Bob Feng: Re: Video Scan Conversion Rate - Camera Input to DVI Display Output
    62707: 03/11/05: daica: Re: Video Scan Conversion Rate - Camera Input to DVI Display Output
    62714: 03/11/05: daica: Re: Video Scan Conversion Rate - Camera Input to DVI Display Output
    62715: 03/11/05: Pete Fraser: Re: Video Scan Conversion Rate - Camera Input to DVI Display Output
    63990: 03/12/10: Julian Hu: Re: Video Scan Conversion Rate - Camera Input to DVI Display Output
62689: 03/11/05: John Williams: Xilinx platform flash VCCO/VCCJ
62690: 03/11/05: 2Penny: device progamming hardware found; device programming software sought
62692: 03/11/04: The Big Bear: FPGA Prototyping Board
    62694: 03/11/05: Ralph Mason: Re: FPGA Prototyping Board
        62696: 03/11/05: mikegw: Re: FPGA Prototyping Board
            62725: 03/11/05: Eric Crabill: Re: FPGA Prototyping Board
    62697: 03/11/05: Leon Heller: Re: FPGA Prototyping Board
        62723: 03/11/05: The Big Bear: Re: FPGA Prototyping Board
            62726: 03/11/05: Leon Heller: Re: FPGA Prototyping Board
    62859: 03/11/10: Sergej: Re: FPGA Prototyping Board
62695: 03/11/05: Frank: microblaze exceptions
62698: 03/11/05: luigi raffo: parameter in top module in XILINX ISE 6.1.02
62699: 03/11/05: Atif: Problem in Implementation Costraints
    62703: 03/11/05: Ian Poole: Re: Problem in Implementation Costraints
62711: 03/11/05: David Gesswein: Virtex II DCM & ZBT SRAM
    62722: 03/11/05: Martin Euredjian: Re: Virtex II DCM & ZBT SRAM
        62756: 03/11/06: David Gesswein: Re: Virtex II DCM & ZBT SRAM
            62770: 03/11/07: Martin Euredjian: Re: Virtex II DCM & ZBT SRAM
    62766: 03/11/06: Brian Davis: Re: Virtex II DCM & ZBT SRAM
        62788: 03/11/07: Brian Davis: Re: Virtex II DCM & ZBT SRAM
    62814: 03/11/08: Marc Randolph: Re: Virtex II DCM & ZBT SRAM
62716: 03/11/05: Michelle: Linux and FPGA compatibility
    62728: 03/11/06: Glen Herrmannsfeldt: Re: Linux and FPGA compatibility
        62931: 03/11/11: Michelle: Re: Linux and FPGA compatibility
    62729: 03/11/05: Alan Nishioka: Re: Linux and FPGA compatibility
        62932: 03/11/11: Michelle: Re: Linux and FPGA compatibility
    62734: 03/11/05: john jakson: Re: Linux and FPGA compatibility
        62933: 03/11/11: Michelle: Re: Linux and FPGA compatibility
            62948: 03/11/11: Michelle: Re: Linux and FPGA compatibility
                62949: 03/11/11: H. Peter Anvin: Re: Linux and FPGA compatibility
                62966: 03/11/11: Petter Gustad: Re: Linux and FPGA compatibility
62717: 03/11/05: Konrad Eisele: Announcement
    62719: 03/11/05: Andras Tantos: Re: Announcement
        62737: 03/11/06: Antti Lukats: Re: Announcement
            62763: 03/11/06: john jakson: Re: Announcement
                62781: 03/11/07: Jon Beniston: Re: Announcement
                62787: 03/11/07: Konrad Eisele: Re: Announcement
                    62808: 03/11/07: Jon Beniston: Re: Announcement
            62780: 03/11/07: Jon Beniston: Re: Announcement
        62779: 03/11/07: Jon Beniston: Re: Announcement
            62906: 03/11/10: Eric Smith: Re: Announcement
62721: 03/11/05: Kent Ross: Programmer's unpaid overtime.
    62730: 03/11/06: Kevin Neilson: Re: Programmer's unpaid overtime.
        62741: 03/11/06: Phil Hays: Re: Programmer's unpaid overtime.
            62789: 03/11/07: Nial Stewart: Re: Programmer's unpaid overtime.
                62791: 03/11/07: Ken Land: Re: Programmer's unpaid overtime.
                    62803: 03/11/07: Kevin Neilson: Re: Programmer's unpaid overtime.
                        62812: 03/11/07: The Real Bev: Re: Programmer's unpaid overtime.
                            62816: 03/11/07: H. Peter Anvin: Re: Programmer's unpaid overtime.
                            62962: 03/11/11: linux user: Re: Programmer's unpaid overtime. ==> I would suggest here some prudence
62724: 03/11/05: Anil Khanna: Infer DDR registers from RTL?
    63639: 03/11/26: praveen: Re: Infer DDR registers from RTL?
62731: 03/11/05: Rajeshwary: ISE : Synthesis process hangs
    62750: 03/11/06: Symon: Re: Synthesis process hangs
62735: 03/11/06: Giaccaglini Giorgio: Smart card ISO 7816 and NIOS Altera
62738: 03/11/06: Terrence Mak: Virtex2Pro--ppc405-FPGA communication
62739: 03/11/06: Denis Gleeson: latch and shift 15 bits.
    62743: 03/11/06: Mirza Luqman: Re: latch and shift 15 bits.
    62748: 03/11/06: Chuck Levin: Re: latch and shift 15 bits.
        62783: 03/11/07: Denis Gleeson: Re: latch and shift 15 bits.
            62806: 03/11/07: Ben Twijnstra: Re: latch and shift 15 bits.
            62826: 03/11/08: Nate Goldshlag: Re: latch and shift 15 bits.
62742: 03/11/06: Vazquez: Creating a vector out of other vectors
    62744: 03/11/06: Jan De Ceuster: Re: Creating a vector out of other vectors
62745: 03/11/06: Morten Leikvoll: Crossing/muxing clocks thru TBUF mux (w/DLL "stunts")
    62746: 03/11/06: Austin Lesea: Re: Crossing/muxing clocks thru TBUF mux (w/DLL "stunts")
        62749: 03/11/06: Mike Treseler: Re: Crossing/muxing clocks thru TBUF mux (w/DLL "stunts")
        62765: 03/11/07: Marc Randolph: Re: Crossing/muxing clocks thru TBUF mux (w/DLL "stunts")
        62786: 03/11/07: Philip Freidin: Re: Crossing/muxing clocks thru TBUF mux (w/DLL "stunts")
            62793: 03/11/07: Austin Lesea: Re: Crossing/muxing clocks thru TBUF mux (w/DLL "stunts")
62754: 03/11/06: Kevin Becker: Arithmetics with carry
    62757: 03/11/06: Peter Alfke: Re: Arithmetics with carry
    62758: 03/11/06: Francisco Rodriguez: Re: Arithmetics with carry
        62796: 03/11/07: Kevin Becker: Re: Arithmetics with carry
            62800: 03/11/07: Glen Herrmannsfeldt: Re: Arithmetics with carry
                62811: 03/11/07: Peter Alfke: Re: Arithmetics with carry
            62807: 03/11/07: Francisco Rodriguez: Re: Arithmetics with carry
    62767: 03/11/07: Glen Herrmannsfeldt: Re: Arithmetics with carry
    62817: 03/11/07: H. Peter Anvin: Re: Arithmetics with carry
        62819: 03/11/08: Glen Herrmannsfeldt: Re: Arithmetics with carry
            62823: 03/11/08: Kevin Becker: Re: Arithmetics with carry -- got it :-)
            62971: 03/11/11: H. Peter Anvin: Re: Arithmetics with carry
                62985: 03/11/12: Glen Herrmannsfeldt: Re: Arithmetics with carry
62761: 03/11/06: Petter Gustad: Impact, SVF, assumed TCK frequency?
    62792: 03/11/07: Amontec Team: Re: Impact, SVF, assumed TCK frequency?
        62809: 03/11/07: Petter Gustad: Re: Impact, SVF, assumed TCK frequency?
    63022: 03/11/12: Neil Glenn Jacobson: Re: Impact, SVF, assumed TCK frequency?
62764: 03/11/06: Yu Jun: ASIC speed
    62778: 03/11/07: Jon Beniston: Re: ASIC speed
        62804: 03/11/07: Ljubisa Bajic: Re: ASIC speed
    62795: 03/11/07: Austin Lesea: Re: ASIC speed
        62820: 03/11/07: john jakson: Re: ASIC speed
62768: 03/11/07: Qiang He: ispLSI-2064 -- how to decompile jedec file to ldf file?
62774: 03/11/07: Barth?l?my von Haller: xhwif for admxrc2 board (alpha data)
62782: 03/11/07: Anjan: spartan 3 queries
62784: 03/11/07: <se10110@yahoo.com>: FPGA & handling reset of a logic block while running
    62797: 03/11/07: John_H: Re: FPGA & handling reset of a logic block while running
    62799: 03/11/07: Mike Treseler: Re: FPGA & handling reset of a logic block while running
62798: 03/11/07: Tom Hawkins: External Modules and FPGA Primitives
62802: 03/11/07: Muthu: PCI - X Boot up
    62810: 03/11/07: Eric Crabill: Re: PCI - X Boot up
62805: 03/11/07: Fernando: FPGAs and DRAM bandwidth
    62818: 03/11/07: john jakson: Re: FPGAs and DRAM bandwidth
        62824: 03/11/08: Fernando: Re: FPGAs and DRAM bandwidth
    62825: 03/11/08: Phil Hays: Re: FPGAs and DRAM bandwidth
        62829: 03/11/09: Fernando: Re: FPGAs and DRAM bandwidth
            62832: 03/11/09: Marc Randolph: Re: FPGAs and DRAM bandwidth
            62833: 03/11/09: Nicholas C. Weaver: Re: FPGAs and DRAM bandwidth
            62842: 03/11/10: Jeff Cunningham: Re: FPGAs and DRAM bandwidth
            62844: 03/11/09: Robert Sefton: Re: FPGAs and DRAM bandwidth
                62846: 03/11/10: Martin Euredjian: Re: FPGAs and DRAM bandwidth
                    62873: 03/11/10: John_H: Re: FPGAs and DRAM bandwidth
            62865: 03/11/10: Fernando: Re: FPGAs and DRAM bandwidth
                62866: 03/11/10: Nicholas C. Weaver: Re: FPGAs and DRAM bandwidth
                    62896: 03/11/11: Erez Birenzwig: Re: FPGAs and DRAM bandwidth
                        62897: 03/11/10: Nicholas C. Weaver: Re: FPGAs and DRAM bandwidth
                    62959: 03/11/11: Fernando: Re: FPGAs and DRAM bandwidth
                62977: 03/11/11: Erik Widding: Re: FPGAs and DRAM bandwidth
                    62993: 03/11/12: Fernando: Re: FPGAs and DRAM bandwidth
62813: 03/11/07: Gerardo Sosa: Capturing Video with RC200E board of Celoxica
62815: 03/11/08: Jim Granville: 0.13u device with 5V I/O
    62827: 03/11/08: Eric Crabill: Re: 0.13u device with 5V I/O
        62828: 03/11/09: Jim Granville: Re: 0.13u device with 5V I/O
            62838: 03/11/09: Eric Crabill: Re: 0.13u device with 5V I/O
                62851: 03/11/11: Jim Granville: Re: 0.13u device with 5V I/O
                    62876: 03/11/10: Eric Crabill: Re: 0.13u device with 5V I/O
                        62880: 03/11/11: Jim Granville: Re: 0.13u device with 5V I/O
                        62887: 03/11/10: Larry Doolittle: Re: 0.13u device with 5V I/O
                            62903: 03/11/10: Eric Crabill: Re: 0.13u device with 5V I/O
        62834: 03/11/09: Garden Gnome: Re: 0.13u device with 5V I/O
            62837: 03/11/09: Eric Crabill: Re: 0.13u device with 5V I/O
                62840: 03/11/09: Garden Gnome: Re: 0.13u device with 5V I/O
                62841: 03/11/09: Hal Murray: Re: 0.13u device with 5V I/O
                    62869: 03/11/10: rickman: Re: 0.13u device with 5V I/O
                    62874: 03/11/10: Eric Crabill: Re: 0.13u device with 5V I/O
                        62980: 03/11/12: Hal Murray: Re: 0.13u device with 5V I/O
                            63000: 03/11/12: rickman: Re: 0.13u device with 5V I/O
                            63001: 03/11/12: Nial Stewart: Re: 0.13u device with 5V I/O
                            63027: 03/11/12: Eric Crabill: Re: 0.13u device with 5V I/O
62835: 03/11/10: newbie: ASIC vs FPGA
    62839: 03/11/09: Rene Tschaggelar: Re: ASIC vs FPGA
    62850: 03/11/10: Nagaraj: Re: ASIC vs FPGA
62836: 03/11/09: Bruce P.: Home grown CPU core legal?
    62860: 03/11/10: Kolja Sulimma: Re: Home grown CPU core legal?
        62861: 03/11/10: Goran Bilski: Re: Home grown CPU core legal?
            62864: 03/11/10: Symon: Re: Home grown CPU core legal?
                62868: 03/11/10: Goran Bilski: Re: Home grown CPU core legal?
                    62878: 03/11/11: Ralph Mason: Re: Home grown CPU core legal?
                        62879: 03/11/10: Goran Bilski: Re: Home grown CPU core legal?
                62881: 03/11/11: Jim Granville: Re: Home grown CPU core legal?
                    62884: 03/11/10: Nicholas C. Weaver: Re: Home grown CPU core legal?
                        62891: 03/11/11: John Williams: Re: Home grown CPU core legal?
                    62885: 03/11/10: Goran Bilski: Re: Home grown CPU core legal?
                    63002: 03/11/12: Jerry D. Harthcock: Re: Home grown CPU core legal?
        62863: 03/11/10: Nicholas C. Weaver: Re: Home grown CPU core legal?
        62872: 03/11/10: Bruce P.: Re: Home grown CPU core legal?
        62877: 03/11/10: Jake Janovetz: Re: Home grown CPU core legal?
            62883: 03/11/10: Austin Lesea: Re: Home grown CPU core legal?
                62886: 03/11/10: Georg Acher: Re: Home grown CPU core legal?
                    62890: 03/11/11: John Williams: Re: Home grown CPU core legal?
            62892: 03/11/10: Bruce P.: Re: Home grown CPU core legal?
                62950: 03/11/11: H. Peter Anvin: Re: Home grown CPU core legal?
                    62952: 03/11/11: Glen Herrmannsfeldt: Re: Home grown CPU core legal?
                        62954: 03/11/11: H. Peter Anvin: Re: Home grown CPU core legal?
                            62956: 03/11/11: rickman: Re: Home grown CPU core legal?
                                62958: 03/11/12: Erez Birenzwig: Re: Home grown CPU core legal?
                                    62968: 03/11/11: Petter Gustad: Re: Home grown CPU core legal?
                                62964: 03/11/11: Peter Alfke: Re: Home grown CPU core legal?
                                    62967: 03/11/11: H. Peter Anvin: Re: Home grown CPU core legal?
                            62965: 03/11/12: Jim Granville: Re: Home grown CPU core legal?
                                62969: 03/11/11: H. Peter Anvin: Re: Home grown CPU core legal?
                                    62972: 03/11/12: Jim Granville: Re: Home grown CPU core legal?
                                    63013: 03/11/12: Nicholas C. Weaver: Re: Home grown CPU core legal?
                            62973: 03/11/12: Jim Granville: Re: Home grown CPU core legal?
                                62974: 03/11/11: rickman: Re: Home grown CPU core legal?
                                    62976: 03/11/11: Peter Alfke: Re: Home grown CPU core legal?
                                        62979: 03/11/11: Bruce P.: Re: Home grown CPU core legal?
                                            62999: 03/11/12: rickman: Re: Home grown CPU core legal?
                                        62983: 03/11/11: H. Peter Anvin: Re: Home grown CPU core legal?
                                        62998: 03/11/12: rickman: Re: Home grown CPU core legal?
                                        63014: 03/11/12: Nicholas C. Weaver: Re: Home grown CPU core legal?
                                62982: 03/11/11: H. Peter Anvin: Re: Home grown CPU core legal?
                                    63018: 03/11/12: Symon: Re: Home grown CPU core legal?
62843: 03/11/09: colin hankins: ISE 5.2 to 6.1
    62848: 03/11/10: Muthu: Re: ISE 5.2 to 6.1
    62849: 03/11/10: Anjan: Re: ISE 5.2 to 6.1
    62854: 03/11/10: Giuseppe: Re: ISE 5.2 to 6.1
    62856: 03/11/10: Jake Janovetz: Re: ISE 5.2 to 6.1
    62867: 03/11/11: KD: Re: ISE 5.2 to 6.1
        62908: 03/11/11: Marc Guardiani: Re: ISE 5.2 to 6.1
62845: 03/11/10: #YU WEI#: CF card problem in Virtex-II Multimedia Board
62852: 03/11/10: Sean Durkin: VirtexII-Pro: Why is ICAP slower than SelectMAP?
    62858: 03/11/10: Austin Lesea: Re: VirtexII-Pro: Why is ICAP slower than SelectMAP?
        62862: 03/11/10: Sean Durkin: Re: VirtexII-Pro: Why is ICAP slower than SelectMAP?
    62875: 03/11/10: PO Laprise: Re: VirtexII-Pro: Why is ICAP slower than SelectMAP?
        62911: 03/11/11: Sean Durkin: Re: VirtexII-Pro: Why is ICAP slower than SelectMAP?
    62939: 03/11/11: PO Laprise: Re: VirtexII-Pro: Why is ICAP slower than SelectMAP?
62853: 03/11/10: Vazquez: How to create a look up table for a RAM application
    62893: 03/11/11: Erez Birenzwig: Re: How to create a look up table for a RAM application
    62900: 03/11/10: Hul Tytus: Re: How to create a look up table for a RAM application
62855: 03/11/10: Morten Leikvoll: Unconstrained net to DLL's
    62882: 03/11/10: Marc Randolph: Re: Unconstrained net to DLL's
62857: 03/11/10: Vazquez: Enumeration by Host Controller
62871: 03/11/10: Brad Eckert: Xilinx SelectMAP configuration
62888: 03/11/11: Erez Birenzwig: Implementing a very fast counterin VirtexII
    62895: 03/11/10: Peter Alfke: Re: Implementing a very fast counterin VirtexII
        62898: 03/11/11: Erez Birenzwig: Re: Implementing a very fast counterin VirtexII
            62901: 03/11/10: Peter Alfke: Re: Implementing a very fast counterin VirtexII
                62904: 03/11/11: Erez Birenzwig: Re: Implementing a very fast counterin VirtexII
                    62913: 03/11/11: Uwe Bonnes: Re: Implementing a very fast counterin VirtexII
                    62945: 03/11/11: Peter Alfke: Re: Implementing a very fast counterin VirtexII
                        62955: 03/11/12: Jim Granville: Re: Implementing a very fast counterin VirtexII
                            62957: 03/11/12: Erez Birenzwig: Re: Implementing a very fast counterin VirtexII
                                62960: 03/11/12: Jim Granville: Re: Implementing a very fast counterin VirtexII
                                    62963: 03/11/12: Erez Birenzwig: Re: Implementing a very fast counterin VirtexII
                                62961: 03/11/11: Peter Alfke: Re: Implementing a very fast counterin VirtexII
                                62970: 03/11/11: Francisco Rodriguez: Re: Implementing a very fast counterin VirtexII
                                    62975: 03/11/11: Peter Alfke: Re: Implementing a very fast counterin VirtexII
            62941: 03/11/11: John_H: Re: Implementing a very fast counterin VirtexII
    62907: 03/11/10: fe: Re: Implementing a very fast counterin VirtexII
    62910: 03/11/11: Goran Bilski: Re: Implementing a very fast counterin VirtexII
    63005: 03/11/12: Morten Leikvoll: Re: Implementing a very fast counterin VirtexII
        63008: 03/11/12: Peter Alfke: Re: Implementing a very fast counterin VirtexII
62889: 03/11/10: Rastislav Struharik: Reverse engineering an EDIF file?
    62894: 03/11/10: Jim Lewis: Re: Reverse engineering an EDIF file?
        63613: 03/11/26: Frank Raffaeli: Re: Reverse engineering an EDIF file?
        64413: 04/01/02: Joonas Timo Taavetti Kekoni: Re: Reverse engineering an EDIF file?
    62902: 03/11/11: Allan Herriman: Re: Reverse engineering an EDIF file?
        62942: 03/11/11: <rasti123@eunet.yu>: Re: Reverse engineering an EDIF file?
            62978: 03/11/12: Allan Herriman: Re: Reverse engineering an EDIF file?
    62946: 03/11/11: B. Joshua Rosen: Re: Reverse engineering an EDIF file?
    63638: 03/11/26: Muthu: Re: Reverse engineering an EDIF file?
62899: 03/11/10: Bill Smith: "clean" or "unprotected" versions of AHDL2X, SYNTHX from Xilinx (ABL2XNF sub tools)
62905: 03/11/10: Jason Berringer: Layout examples
    62929: 03/11/11: Martin Thompson: Re: Layout examples
        62940: 03/11/11: John_H: Re: Layout examples
            62944: 03/11/11: Jonathan Bromley: Re: Layout examples
                62947: 03/11/11: John_H: Re: Layout examples
                62989: 03/11/12: Hal Murray: Re: Layout examples
            62991: 03/11/12: Martin Thompson: Re: Layout examples
            62992: 03/11/12: Nial Stewart: Re: Layout examples
        63028: 03/11/13: Martin Euredjian: Re: Layout examples
            63030: 03/11/13: Martin Thompson: Re: Layout examples
                63036: 03/11/13: Martin Euredjian: Re: Layout examples
                    63086: 03/11/14: Simon Peacock: Re: Layout examples
                        63092: 03/11/14: Martin Euredjian: Re: Layout examples
                63143: 03/11/17: Hal Murray: Re: Layout examples
                    63148: 03/11/17: Martin Thompson: Re: Layout examples
62909: 03/11/11: Valentin Tihomirov: fitting Xilinx CPLD - I/O Pin Termination
    63045: 03/11/13: Klaus Falser: Re: fitting Xilinx CPLD - I/O Pin Termination
62912: 03/11/11: Jiang: Are modules that are not floorplanned still functional?
    62953: 03/11/12: Erez Birenzwig: Re: Are modules that are not floorplanned still functional?
        62995: 03/11/12: Jiang: Re: Are modules that are not floorplanned still functional?
62914: 03/11/11: Vazquez: Transforming vector position to binary value
    62915: 03/11/11: Jonathan Bromley: Re: Transforming vector position to binary value
        62923: 03/11/11: Jonathan Bromley: Re: Transforming vector position to binary value
        62928: 03/11/11: Vazquez: Re: Transforming vector position to binary value
            62930: 03/11/11: Jonathan Bromley: Re: Transforming vector position to binary value
                62938: 03/11/11: John_H: Re: Transforming vector position to binary value
                    62943: 03/11/11: Peter Alfke: Re: Transforming vector position to binary value
                        62987: 03/11/11: Vazquez: Re: Transforming vector position to binary value
                            63009: 03/11/12: Peter Alfke: Re: Transforming vector position to binary value
                                63037: 03/11/13: Martin Euredjian: Re: Transforming vector position to binary value
                                    63038: 03/11/13: Jonathan Bromley: Re: Transforming vector position to binary value
                                        63217: 03/11/18: Jonathan Bromley: Re: Transforming vector position to binary value
                                            63267: 03/11/19: Martin Euredjian: Re: Transforming vector position to binary value
                                                63308: 03/11/19: Peter Alfke: Re: Transforming vector position to binary value
                                                    63346: 03/11/20: Martin Euredjian: Re: Transforming vector position to binary value
                                    63051: 03/11/13: John_H: Re: Transforming vector position to binary value
                                    63058: 03/11/13: Peter Alfke: Re: Transforming vector position to binary value
                                        63061: 03/11/13: Martin Euredjian: Re: Transforming vector position to binary value
                                            63063: 03/11/13: Austin Lesea: Re: Transforming vector position to binary value
                                                63066: 03/11/13: Martin Euredjian: Re: Transforming vector position to binary value
                                                    63072: 03/11/13: Peter Alfke: Re: Transforming vector position to binary value
            63029: 03/11/13: Martin Euredjian: Re: Transforming vector position to binary value
    62919: 03/11/11: Valentin Tihomirov: Re: Transforming vector position to binary value
62918: 03/11/11: takkaya: Multiple clock domains in a FPGA (using DLL's)
    62927: 03/11/11: Nial Stewart: Re: Multiple clock domains in a FPGA (using DLL's)
62920: 03/11/11: Jeroen: Code for accessing CF cards on Cyclone dev.board
    63006: 03/11/12: Jesse Kempa: Re: Code for accessing CF cards on Cyclone dev.board
    63079: 03/11/13: James: Re: Code for accessing CF cards on Cyclone dev.board
62921: 03/11/11: lenz: Logic implementation in SRAM/OTP FPGAs
    62986: 03/11/12: Mario Trams: Re: Logic implementation in SRAM/OTP FPGAs
62924: 03/11/11: : XILINX Foundation Series 3_1i Problem with installation...
    62936: 03/11/11: Morten Leikvoll: Re: XILINX Foundation Series 3_1i Problem with installation...
        62988: 03/11/12: : Re: XILINX Foundation Series 3_1i Problem with installation...
            63097: 03/11/14: Steve Lass: Re: XILINX Foundation Series 3_1i Problem with installation...
                63108: 03/11/15: Uwe Bonnes: Re: XILINX Foundation Series 3_1i Problem with installation...
                    63109: 03/11/15: Nicholas C. Weaver: Re: XILINX Foundation Series 3_1i Problem with installation...
                        63111: 03/11/15: Uwe Bonnes: Re: XILINX Foundation Series 3_1i Problem with installation...
                63112: 03/11/15: ?????? ?????: Re: XILINX Foundation Series 3_1i Problem with installation...
                    63113: 03/11/15: : Re: XILINX Foundation Series 3_1i Problem with installation...
62925: 03/11/11: #YU WEI#: How to visit the files in CF cards
    62981: 03/11/11: ram: Re: How to visit the files in CF cards
    63208: 03/11/17: ram: Re: How to visit the files in CF cards
62926: 03/11/11: Andyman: DCM input clock
    62934: 03/11/11: Austin Lesea: Re: DCM input clock
62984: 03/11/11: Atif: About the purchase of XCF01s
    63088: 03/11/14: Simon Peacock: Re: About the purchase of XCF01s
62994: 03/11/12: #YU WEI#: None
62996: 03/11/12: Jan Panteltje: Trying to digitize video with CTT differential input, but webpack wont't cooperate...:-)
62997: 03/11/12: Fred: Need to verify an ATA/ATAPI-6 device
63003: 03/11/12: Morten Leikvoll: Putting TNM on a FF inside vhdl
63004: 03/11/12: Vazquez: Local nodes are not visible anymore after simulation (Altera Quartus II )
    63007: 03/11/12: Christos: Re: Local nodes are not visible anymore after simulation (Altera Quartus II )
        63091: 03/11/14: ALuPin: Re: Local nodes are not visible anymore after simulation (Altera Quartus II )
63010: 03/11/12: Si: System generator and Microblaze
    63026: 03/11/13: John Williams: Re: System generator and Microblaze
63011: 03/11/12: Pete Fraser: VHDL code for an mj2 parser.
63012: 03/11/12: Jan Panteltje: Trying to digitize video with CTT differential input, but webpack wont't cooperate...:-)
    63015: 03/11/12: Jonathan Bromley: Re: Trying to digitize video with CTT differential input, but webpack wont't cooperate...:-)
        63062: 03/11/13: Jan Panteltje: Re: Trying to digitize video with CTT differential input, but webpack wont't cooperate...:-)
63016: 03/11/12: Gazelle: Frequency Doubler - VHDL/Verilog
    63017: 03/11/12: Kevin Neilson: Re: Frequency Doubler - VHDL/Verilog
    63020: 03/11/12: Peter Alfke: Re: Frequency Doubler - VHDL/Verilog
        63024: 03/11/12: Hal Murray: Re: Frequency Doubler - VHDL/Verilog
            63025: 03/11/12: Peter Alfke: Re: Frequency Doubler - VHDL/Verilog
                63064: 03/11/13: Jan Panteltje: Re: Frequency Doubler - VHDL/Verilog
                    63071: 03/11/13: Peter Alfke: Re: Frequency Doubler - VHDL/Verilog
    63046: 03/11/13: Arash Salarian: Re: Frequency Doubler - VHDL/Verilog
        63053: 03/11/13: Symon: Re: Frequency Doubler - VHDL/Verilog
        63055: 03/11/13: Peter Alfke: Re: Frequency Doubler - VHDL/Verilog
    63077: 03/11/14: Jim Granville: Re: Frequency Doubler - VHDL/Verilog
63019: 03/11/12: Chris Carlen: Will XPLA3 phase out?
    63023: 03/11/12: Amontec Team, Laurent Gauch: Re: Will XPLA3 phase out?
63031: 03/11/13: Tom: linker script
    63057: 03/11/13: Jon Beniston: Re: linker script
63032: 03/11/13: Holger: SystemC Implementation
63034: 03/11/13: Jock: Archiving Projects
    63078: 03/11/14: Marc Guardiani: Re: Archiving Projects
63035: 03/11/13: Isaac: Reading O value
    63043: 03/11/13: Jonathan Bromley: Re: Reading O value
        63049: 03/11/13: Brent Hayhoe: Re: Reading O value
63039: 03/11/13: Vivek: Xilinx Virtex2 tristate support
    63040: 03/11/13: Uwe Bonnes: Re: Xilinx Virtex2 tristate support
    63047: 03/11/13: John_H: Re: Xilinx Virtex2 tristate support
    63052: 03/11/13: Peter Alfke: Re: Xilinx Virtex2 tristate support
63044: 03/11/13: Kay Schubert: unknown devices in JTAG chain
    63048: 03/11/13: Chen Wei Tseng: Re: unknown devices in JTAG chain
        63056: 03/11/13: Amontec Team, Laurent Gauch: Re: unknown devices in JTAG chain
    63068: 03/11/13: Mark van de Belt: Re: unknown devices in JTAG chain
        63158: 03/11/17: <--Kay-->: Re: unknown devices in JTAG chain
63050: 03/11/13: enq_semi: How to bring PLL's output to Pin_F1
    63060: 03/11/13: Hal Murray: Re: How to bring PLL's output to Pin_F1
    63065: 03/11/13: Marc Randolph: Re: How to bring PLL's output to Pin_F1
63054: 03/11/13: Yttrium: VIRTEXII IO problem
63067: 03/11/13: john orlando: Xilinx UART Macro ERROR???
    63075: 03/11/13: Peter Alfke: Re: Xilinx UART Macro ERROR???
        63076: 03/11/13: Mike Treseler: Re: Xilinx UART Macro ERROR???
    63107: 03/11/14: Brian Davis: Re: Xilinx UART Macro ERROR???
    63153: 03/11/17: Ken Chapman: Re: Xilinx UART Macro ERROR???
        63250: 03/11/18: john orlando: Re: Xilinx UART Macro ERROR???
63069: 03/11/13: Mark van de Belt: Writing Blockrams in VHDL
    63074: 03/11/13: Peter Alfke: Re: Writing Blockrams in VHDL
        63103: 03/11/14: Mark van de Belt: Re: Writing Blockrams in VHDL
63080: 03/11/13: Joe Fox: Altera MAX3000 device required.
    63085: 03/11/14: Rene Tschaggelar: Re: Altera MAX3000 device required.
63081: 03/11/14: moe: Reading back SRAM content via JTAG?
    63089: 03/11/14: Jim Wu: Re: Reading back SRAM content via JTAG?
        63101: 03/11/14: moh@speakhard.net: Re: Reading back SRAM content via JTAG?
            63139: 03/11/16: Jim Wu: Re: Reading back SRAM content via JTAG?
63082: 03/11/13: Sudip Saha: FPGA Device Utilization
63084: 03/11/13: Eman: getting started in FPGA
    63114: 03/11/15: Garrett Mace: Re: getting started in FPGA
    63128: 03/11/15: Mike Treseler: Re: getting started in FPGA
    63133: 03/11/16: Alex Gibson: Re: getting started in FPGA
    63146: 03/11/17: Jean Nicolle: Re: getting started in FPGA
        63602: 03/11/26: Vaughn Betz: Re: getting started in FPGA
            63773: 03/12/03: Martin Schoeberl: Re: getting started in FPGA
63087: 03/11/14: Anders Hellerup Madsen: Color STN LCD controller
    63094: 03/11/14: Lasse Langwadt Christensen: Re: Color STN LCD controller
        63149: 03/11/17: Anders Hellerup Madsen: Re: Color STN LCD controller
            63154: 03/11/17: Iwo Mergler: Re: Color STN LCD controller
    63100: 03/11/14: Gerd B.: Re: Color STN LCD controller
63090: 03/11/14: Hui Li: PCI Slot Expansion
    63096: 03/11/14: Hal Murray: Re: PCI Slot Expansion
        63116: 03/11/15: Hui Li: Re: PCI Slot Expansion
            63124: 03/11/15: TC: Re: PCI Slot Expansion
            63141: 03/11/16: Hal Murray: Re: PCI Slot Expansion
            63168: 03/11/17: MM: Re: PCI Slot Expansion
63093: 03/11/14: Krzysztof Szczepanski: Stratix & PLL
    63126: 03/11/15: Subroto Datta: Re: Stratix & PLL
63098: 03/11/14: Tom Hawkins: Inferring Dual Port Block RAM
    63102: 03/11/14: Mike Treseler: Re: Inferring Dual Port Block RAM
    63104: 03/11/14: Mark van de Belt: Re: Inferring Dual Port Block RAM
63110: 03/11/15: Jan Panteltje: Do I need to connect all Vref in a bank together?
    63118: 03/11/15: Marc Randolph: Re: Do I need to connect all Vref in a bank together?
    63166: 03/11/17: Austin Lesea: Re: Do I need to connect all Vref in a bank together?
        63183: 03/11/17: Jan Panteltje: Re: Do I need to connect all Vref in a bank together?
            63190: 03/11/17: Austin Lesea: Re: Do I need to connect all Vref in a bank together?
            63193: 03/11/18: Jim Granville: Re: Do I need to connect all Vref in a bank together?
                63252: 03/11/18: Jan Panteltje: Re: Do I need to connect all Vref in a bank together?
                    63259: 03/11/19: Jim Granville: Re: Do I need to connect all Vref in a bank together?
            63203: 03/11/18: Hal Murray: Re: Do I need to connect all Vref in a bank together?
                63238: 03/11/18: Jan Panteltje: Re: Do I need to connect all Vref in a bank together?
            63216: 03/11/18: Jonathan Bromley: Re: Do I need to connect all Vref in a bank together?
                63239: 03/11/18: Jan Panteltje: Re: Do I need to connect all Vref in a bank together?
                63246: 03/11/18: Jan Panteltje: Re: Do I need to connect all Vref in a bank together?
63115: 03/11/15: Naveed: Altera's EPCS programming algorithm
    63117: 03/11/15: Gerd B.: Re: Altera's EPCS programming algorithm
        63127: 03/11/15: Naveed: Re: Altera's EPCS programming algorithm
            63136: 03/11/16: Gerd B.: Re: Altera's EPCS programming algorithm
            63137: 03/11/16: Naveed: Re: Altera's EPCS programming algorithm
63119: 03/11/15: Jan Panteltje: More basic questions about Spartan 2 IOB
    63125: 03/11/15: Hal Murray: Re: More basic questions about Spartan 2 IOB
        63130: 03/11/15: Jan Panteltje: Re: More basic questions about Spartan 2 IOB
            63138: 03/11/16: Markus Meng: Re: More basic questions about Spartan 2 IOB
63120: 03/11/15: Mole: Newbie Question about Block Ram & Xilinx ECS
    63121: 03/11/15: Phil Hays: Re: Newbie Question about Block Ram & Xilinx ECS
        63122: 03/11/15: Mole: Re: Newbie Question about Block Ram & Xilinx ECS
63131: 03/11/15: Jerry: standalone IMPACT
    63132: 03/11/16: Simon Peacock: Re: standalone IMPACT
    63140: 03/11/16: Matt: Re: standalone IMPACT
63142: 03/11/16: Dave: ISE 6.1 with synplify : pin assignments
    63144: 03/11/17: Erez Birenzwig: Re: ISE 6.1 with synplify : pin assignments
63145: 03/11/17: Jay: Vertex-II configuration in slave SelectMap mode
63147: 03/11/17: Hans-Juergen Dorn: SRL16 as synchronizer
    63171: 03/11/17: Symon: Re: SRL16 as synchronizer
        63173: 03/11/17: Peter Alfke: Re: SRL16 as synchronizer
            63195: 03/11/17: John_H: Re: SRL16 as synchronizer
                63196: 03/11/18: David R Brooks: Re: SRL16 as synchronizer
                63200: 03/11/18: Hans-Juergen Dorn: Re: SRL16 as synchronizer
                    63232: 03/11/18: Peter Alfke: Re: SRL16 as synchronizer
                        63241: 03/11/18: John_H: Re: SRL16 as synchronizer
            63197: 03/11/18: Hans-Juergen Dorn: Re: SRL16 as synchronizer
    63172: 03/11/17: Mike Treseler: Re: SRL16 as synchronizer
63150: 03/11/17: Jay: ISE5.2 on solaris, can't use promgen
    63152: 03/11/17: Alan Fitch: Re: ISE5.2 on solaris, can't use promgen
        63188: 03/11/17: Petter Gustad: Re: ISE5.2 on solaris, can't use promgen
            63201: 03/11/18: Jay: Re: ISE5.2 on solaris, can't use promgen
63155: 03/11/17: Allan Herriman: Active-HDL 6.1 pricing
    63156: 03/11/17: Allan Herriman: Re: Active-HDL 6.1 pricing
        63163: 03/11/17: Stratus Engineer: Re: Active-HDL 6.1 pricing
            63194: 03/11/18: Allan Herriman: Re: Active-HDL 6.1 pricing
                63198: 03/11/17: rickman: Re: Active-HDL 6.1 pricing
                    63206: 03/11/18: Allan Herriman: Re: Active-HDL 6.1 pricing
                        63226: 03/11/18: Peter Sommerfeld: Re: Active-HDL 6.1 pricing
                            63272: 03/11/19: rickman: Re: Active-HDL 6.1 pricing
                        63227: 03/11/18: Peter Sommerfeld: Re: Active-HDL 6.1 pricing
                            63262: 03/11/19: Allan Herriman: Re: Active-HDL 6.1 pricing
                    63242: 03/11/18: Valentin Tihomirov: Re: Active-HDL 6.1 pricing
                        63263: 03/11/19: Allan Herriman: Re: Active-HDL 6.1 pricing
                            63268: 03/11/19: Valeri Serebrianski: Re: Active-HDL 6.1 pricing
    63157: 03/11/17: fred: Re: Active-HDL 6.1 pricing
63159: 03/11/17: Vazquez: Altera synthesis of registered signals ???
    63162: 03/11/17: Stratus Engineer: Re: Altera synthesis of registered signals ???
    63184: 03/11/17: Subroto Datta: Re: Altera synthesis of registered signals ???
63160: 03/11/17: Peter Sommerfeld: Altera's altsyncram MAXIMUM_DEPTH
    63174: 03/11/17: =?iso-8859-15?Q?Manfred_M=FCcke?=: Re: Altera's altsyncram MAXIMUM_DEPTH
        63253: 03/11/18: Peter Sommerfeld: Re: Altera's altsyncram MAXIMUM_DEPTH
    63178: 03/11/17: Subroto Datta: Re: Altera's altsyncram MAXIMUM_DEPTH
        63321: 03/11/19: Subroto Datta: Re: Altera's altsyncram MAXIMUM_DEPTH
            63356: 03/11/20: =?iso-8859-15?Q?Manfred_M=FCcke?=: Re: Altera's altsyncram MAXIMUM_DEPTH
                63386: 03/11/20: Mike Treseler: Re: Altera's altsyncram MAXIMUM_DEPTH
                    63429: 03/11/21: =?iso-8859-15?Q?Manfred_M=FCcke?=: Re: Altera's altsyncram MAXIMUM_DEPTH
                        63489: 03/11/22: H. Peter Anvin: Re: Altera's altsyncram MAXIMUM_DEPTH
            63869: 03/12/06: =?iso-8859-15?Q?Manfred_M=FCcke?=: Re: Altera's altsyncram MAXIMUM_DEPTH
                63886: 03/12/07: Subroto Datta: Re: Altera's altsyncram MAXIMUM_DEPTH
                63946: 03/12/09: Ben Twijnstra: Re: Altera's altsyncram MAXIMUM_DEPTH
63161: 03/11/17: Ken: Synplify Pro/ISE adder carry chain - interrupted
    63170: 03/11/17: Symon: Re: Synplify Pro/ISE adder carry chain - interrupted
        63187: 03/11/17: Ken: Re: Synplify Pro/ISE adder carry chain - interrupted
63164: 03/11/17: Jon: Architecture desing using national serializer and deserialiser
    63276: 03/11/19: Swarna Kumar: Re: Architecture desing using national serializer and deserialiser
    63335: 03/11/19: Daniel Lang: Re: Architecture desing using national serializer and deserialiser
63165: 03/11/17: Song: Tool for connecting modules,download free,quick demo
63169: 03/11/17: JKB: ISE 4.2 sp3 (Solaris)
63177: 03/11/17: Mike Silva: Is this a good starter kit?
    63182: 03/11/17: MM: Re: Is this a good starter kit?
    63191: 03/11/17: Thomas Womack: Re: Is this a good starter kit?
    63336: 03/11/20: Alex Gibson: Re: Is this a good starter kit?
        63448: 03/11/21: Mike Silva: Re: Is this a good starter kit?
            63452: 03/11/21: MM: Re: Is this a good starter kit?
                63461: 03/11/21: Mike Silva: Re: Is this a good starter kit?
                    63468: 03/11/22: MM: Re: Is this a good starter kit?
                        63482: 03/11/22: Mike Silva: Re: Is this a good starter kit?
            63476: 03/11/22: Thomas Womack: Re: Is this a good starter kit?
    63477: 03/11/22: db: Re: Is this a good starter kit?
        63481: 03/11/22: Mike Silva: Re: Is this a good starter kit?
63179: 03/11/17: MM: Virtex II multipler performance
    63185: 03/11/17: Symon: Re: Virtex II multipler performance
        63189: 03/11/17: MM: Re: Virtex II multipler performance
            63192: 03/11/17: Symon: Re: Virtex II multipler performance
    63186: 03/11/17: Chris Ebeling: Re: Virtex II multipler performance
63181: 03/11/17: Kumaran: Acek 1K - Quartus II - timing issues
    63212: 03/11/18: Manfred Balik: Re: Acek 1K - Quartus II - timing issues
        63240: 03/11/18: Kumaran: Re: Acek 1K - Quartus II - timing issues
            63271: 03/11/19: rickman: Re: Acek 1K - Quartus II - timing issues
                63352: 03/11/19: Vaughn Betz: Re: Acek 1K - Quartus II - timing issues
                    63384: 03/11/20: Kumaran: Re: Acek 1K - Quartus II - timing issues
                        63550: 03/11/25: Vaughn Betz: Re: Acek 1K - Quartus II - timing issues
63199: 03/11/17: Symon: Re: Xilinx Design entry via Schematic Capture - What tool to use ?
    63202: 03/11/18: Jay: Re: Xilinx Design entry via Schematic Capture - What tool to use ?
        63211: 03/11/18: JoeG: Re: Xilinx Design entry via Schematic Capture - What tool to use
    63210: 03/11/18: JoeG: Re: Xilinx Design entry via Schematic Capture - What tool to use
        63223: 03/11/18: Brian Drummond: Re: Xilinx Design entry via Schematic Capture - What tool to use ?
        63235: 03/11/18: Symon: Re: Xilinx Design entry via Schematic Capture - What tool to use ?
63204: 03/11/17: Dan DeConinck: Xilinx Design entry via Schematic Capture - What tool to use ?
    63214: 03/11/18: Uwe Bonnes: Re: Xilinx Design entry via Schematic Capture - What tool to use ?
    63224: 03/11/18: Jake Janovetz: Re: Xilinx Design entry via Schematic Capture - What tool to use ?
63205: 03/11/17: Josh Pfrimmer: Memory Initialization: mif, coe, hex, etc,
    63236: 03/11/18: Mike Treseler: Re: Memory Initialization: mif, coe, hex, etc,
        63244: 03/11/18: Josh Pfrimmer: Re: Memory Initialization: mif, coe, hex, etc,
            63363: 03/11/20: Tero Rissa: Re: Memory Initialization: mif, coe, hex, etc,
                63394: 03/11/20: Josh Pfrimmer: Re: Memory Initialization: mif, coe, hex, etc,
                    63402: 03/11/21: Hal Murray: Re: Memory Initialization: mif, coe, hex, etc,
    63417: 03/11/21: Robert Baumgartner: Re: Memory Initialization: mif, coe, hex, etc,
        63453: 03/11/21: Mike Treseler: Re: Memory Initialization: mif, coe, hex, etc,
    63490: 03/11/22: H. Peter Anvin: Re: Memory Initialization: mif, coe, hex, etc,
63207: 03/11/17: Robert Sefton: xilinx platform flash question
    63254: 03/11/18: Barry Brown: Re: xilinx platform flash question
63209: 03/11/17: Dan DeConinck: using multilinx from ISE to download a bit file
    63219: 03/11/18: Sean Durkin: Re: using multilinx from ISE to download a bit file
63213: 03/11/18: Frank: microblaze as submodule
    63215: 03/11/18: Goran Bilski: Re: microblaze as submodule
    63218: 03/11/18: Erik Hansen: Re: microblaze as submodule
        63222: 03/11/18: Frank: Re: microblaze as submodule
63220: 03/11/18: #YU WEI#: None
    63230: 03/11/18: Eric Crabill: Re: None
63221: 03/11/18: Nick: %age occupation of interconnect resources
63225: 03/11/18: Peter Schmand: HDL-Designer 2002: cannot edit generic mapping in Block-Diagram-view
    63233: 03/11/18: Mike Treseler: Re: HDL-Designer 2002: cannot edit generic mapping in Block-Diagram-view
        63234: 03/11/18: Mike Treseler: Re: HDL-Designer 2002: cannot edit generic mapping in Block-Diagram-view
            63277: 03/11/19: Peter Schmand: Re: HDL-Designer 2002: cannot edit generic mapping in Block-Diagram-view
63228: 03/11/18: Dan Schaffer: SPI 4.2 Core perceptions and Power
    63264: 03/11/18: Robert Sefton: Re: SPI 4.2 Core perceptions and Power
63229: 03/11/18: David Collier: PCI interface with attached PLD
    63231: 03/11/18: Eric Crabill: Re: PCI interface with attached PLD
    63237: 03/11/18: Uwe Bonnes: Re: PCI interface with attached PLD
    63282: 03/11/19: Alan Hall: Re: PCI interface with attached PLD
    63445: 03/11/21: Chuck Levin: Re: PCI interface with attached PLD
        63454: 03/11/21: Uwe Bonnes: Re: PCI interface with attached PLD
            63457: 03/11/21: Uwe Bonnes: Re: PCI interface with attached PLD
                63470: 03/11/21: Chuck Levin: Re: PCI interface with attached PLD
            63466: 03/11/21: Chuck Levin: Re: PCI interface with attached PLD
    63501: 03/11/24: Nial Stewart: Re: PCI interface with attached PLD
63245: 03/11/18: Mois?s: Problems Configurating MicroBlaze into RC200 board
    63290: 03/11/19: Tony: Re: Problems Configurating MicroBlaze into RC200 board
        63323: 03/11/19: Mois?s: Re: Problems Configurating MicroBlaze into RC200 board
63247: 03/11/18: Valentin Tihomirov: CPLD : Generating reset signal
    63248: 03/11/18: Valentin Tihomirov: NB! I do not use *Keeper* feature for I/O pin termination.
        63306: 03/11/19: tbiggs: Re: NB! I do not use *Keeper* feature for I/O pin termination.
    63249: 03/11/18: Valentin Tihomirov: Mysterious observations. Puzzle 2.
    63260: 03/11/19: Valentin Tihomirov: Thank you all for the replays.
        63265: 03/11/19: Jim Granville: Re: Thank you all for the replays.
    63316: 03/11/19: Bruce P.: Re: CPLD : Generating reset signal
        63400: 03/11/20: Arthur: Re: CPLD : Generating reset signal
63251: 03/11/18: EH-2004: CFP: EH-2004 Second Call for Abstracts
63255: 03/11/18: Barry Brown: Xilinx DCM LOCKED signal valid after input clock returns?
    63256: 03/11/18: Austin Lesea: Re: Xilinx DCM LOCKED signal valid after input clock returns?
63257: 03/11/18: erojr: Altera Stratix synthesis error
    63465: 03/11/21: Ben Twijnstra: Re: Altera Stratix synthesis error
        63480: 03/11/22: erojr: Re: Altera Stratix synthesis error
63258: 03/11/18: Kevin O'Mara: XILINX Foundation F1.5 Build 3.1.1.35 with XCS10PC84 and Digilab XLA
    63472: 03/11/22: Philip Freidin: Re: XILINX Foundation F1.5 Build 3.1.1.35 with XCS10PC84 and Digilab XLA
    63514: 03/11/24: Kevin O'Mara: Re: XILINX Foundation F1.5 Build 3.1.1.35 with XCS10PC84 and Digilab XLA
63261: 03/11/18: Symon: Anyone use HDL as design tool for PCBs?
    63266: 03/11/19: Allan Herriman: Re: Anyone use HDL as design tool for PCBs?
        63269: 03/11/19: Matt: Re: Anyone use HDL as design tool for PCBs?
            63288: 03/11/19: erojr: Re: Anyone use HDL as design tool for PCBs?
                63350: 03/11/20: Matt: Re: Anyone use HDL as design tool for PCBs?
        63304: 03/11/19: Symon: Re: Anyone use HDL as design tool for PCBs?
            63313: 03/11/19: rickman: Re: Anyone use HDL as design tool for PCBs?
            63314: 03/11/19: Larry Doolittle: Re: Anyone use HDL as design tool for PCBs?
            63334: 03/11/20: Jim Granville: Re: Anyone use HDL as design tool for PCBs?
    63285: 03/11/19: Valentin Tihomirov: How do you keep layout info in VHDL?
        63287: 03/11/19: Jonathan Bromley: Re: How do you keep layout info in VHDL?
        63302: 03/11/19: Duane Clark: Re: How do you keep layout info in VHDL?
            63310: 03/11/19: Symon: Re: How do you keep layout info in VHDL?
                63325: 03/11/19: Mike Treseler: Re: How do you keep layout info in VHDL?
63270: 03/11/18: apple: Does anyone know anything about DC-FPGA?
    63413: 03/11/21: Jay: Re: Does anyone know anything about DC-FPGA?
63273: 03/11/18: praveen: regarding clock routing
    63280: 03/11/19: Jonathan Bromley: Re: regarding clock routing
    63312: 03/11/19: Peter Alfke: Re: regarding clock routing
        63354: 03/11/19: praveen: Re: regarding clock routing
            63383: 03/11/20: Peter Alfke: Re: regarding clock routing
                63432: 03/11/21: Muthu: Re: regarding clock routing
63274: 03/11/19: Simone Winkler: SDRAM-Controller XAPP134
    63275: 03/11/19: Swarna Kumar: Re: SDRAM-Controller XAPP134
    63281: 03/11/19: rickman: Re: SDRAM-Controller XAPP134
        63283: 03/11/19: Simone Winkler: Re: SDRAM-Controller XAPP134
            63347: 03/11/20: Martin Euredjian: Re: SDRAM-Controller XAPP134
    63309: 03/11/19: Robert Sefton: Re: SDRAM-Controller XAPP134
63278: 03/11/19: Hui Li: Where and How to get Nvidia Geforce 5600 public desigh graph
    63621: 03/11/26: Ken Ryan: Re: Where and How to get Nvidia Geforce 5600 public desigh graph
63279: 03/11/19: arkaitz: XPS - Compiliing Core Generator's components
63284: 03/11/19: Frank: interrupt handler for microblaze system
63286: 03/11/19: Richard: Xilinx microblaze : SRAM external mem controller
    63357: 03/11/20: Erik Hansen: Re: Xilinx microblaze : SRAM external mem controller
        63409: 03/11/20: Antti Lukats: Re: Xilinx microblaze : SRAM external mem controller
            63412: 03/11/21: Goran Bilski: Re: Xilinx microblaze : SRAM external mem controller
63289: 03/11/19: King: Embedded Development Kit + performance
    63317: 03/11/19: Erik Widding: Re: Embedded Development Kit + performance
63291: 03/11/19: Jeff Peterson: 400 Mb/s ADC
    63293: 03/11/19: Nik Simpson: Re: 400 Mb/s ADC
        63324: 03/11/19: Jeff Peterson: Re: 400 Mb/s ADC
            63327: 03/11/19: MM: Re: 400 Mb/s ADC
            63328: 03/11/19: Nik Simpson: Re: 400 Mb/s ADC
                63341: 03/11/19: Jeff Peterson: Re: 400 Mb/s ADC
                    63345: 03/11/19: Nik Simpson: Re: 400 Mb/s ADC
                    63353: 03/11/20: Larry Doolittle: Re: 400 Mb/s ADC
                    63485: 03/11/22: Peter Desnoyers: Re: 400 Mb/s ADC
            63344: 03/11/19: Symon: Re: 400 Mb/s ADC
    63295: 03/11/19: MM: Re: 400 Mb/s ADC
        63342: 03/11/19: Jeff Peterson: Re: 400 Mb/s ADC
            63351: 03/11/20: MM: Re: 400 Mb/s ADC
                63393: 03/11/20: Jan Panteltje: Re: 400 Mb/s ADC
    63320: 03/11/19: glen herrmannsfeldt: Re: 400 Mb/s ADC
    63358: 03/11/20: Kolja Sulimma: Re: 400 Mb/s ADC
        63359: 03/11/20: Maxim S. Shatskih: Re: 400 Mb/s ADC
            63373: 03/11/20: Kolja Sulimma: Re: 400 Mb/s ADC
                63390: 03/11/20: Maxim S. Shatskih: Re: 400 Mb/s ADC
                    63391: 03/11/20: Nik Simpson: Re: 400 Mb/s ADC
        63411: 03/11/20: Jeff Peterson: Re: 400 Mb/s ADC
            63518: 03/11/25: John Williams: Re: 400 Mb/s ADC
    63380: 03/11/20: Ulf Samuelsson: Re: 400 Mb/s ADC
        63396: 03/11/20: Steve Prokosch: Re: 400 Mb/s ADC
        63410: 03/11/20: Jeff Peterson: Re: 400 Mb/s ADC
        63438: 03/11/21: Paul Smith: Re: 400 Mb/s ADC
            63440: 03/11/21: Ulf Samuelsson: Re: 400 Mb/s ADC
            63521: 03/11/24: Peter C. Wallace: Re: 400 Mb/s ADC
        63478: 03/11/22: Morten Leikvoll: Re: 400 Mb/s ADC
            63487: 03/11/22: dMon: Re: 400 Mb/s ADC
                63958: 03/12/10: Ray Andraka: Re: 400 Mb/s ADC
    63443: 03/11/21: trythis: Re: 400 Mb/s ADC
63292: 03/11/19: stan: State Machines....
    63294: 03/11/19: MM: Re: State Machines....
        63385: 03/11/20: Nial Stewart: Re: State Machines....
    63296: 03/11/19: Jonathan Bromley: Re: State Machines....
    63298: 03/11/19: Bob Perlman: Re: State Machines....
    63300: 03/11/19: Amontec Team, Laurent Gauch: Re: State Machines....
    63301: 03/11/19: Robert Sefton: Re: State Machines....
        63319: 03/11/19: Peter Alfke: Re: State Machines....
            63330: 03/11/19: Antonio Pasini: Re: State Machines....
                63332: 03/11/19: Nicholas C. Weaver: Re: State Machines....
            63337: 03/11/19: rickman: Re: State Machines....
                63338: 03/11/19: Peter Alfke: Re: State Machines....
                    63339: 03/11/19: Robert Sefton: Re: State Machines....
                    63340: 03/11/20: Jim Granville: Re: State Machines....
                        63388: 03/11/20: Mike Treseler: Re: State Machines....
                            63389: 03/11/20: Goran Bilski: Re: State Machines....
                                63398: 03/11/21: Jim Granville: Re: State Machines....
                                    63414: 03/11/21: Goran Bilski: Re: State Machines....
                            63418: 03/11/21: Hal Murray: Re: State Machines....
                                63484: 03/11/22: Mike Treseler: Re: State Machines....
                                    63486: 03/11/22: Hal Murray: Re: State Machines....
                                        63517: 03/11/24: Mike Treseler: Re: State Machines....
                    63343: 03/11/19: rickman: Re: State Machines....
                    63355: 03/11/20: Hal Murray: Re: State Machines....
                        63375: 03/11/20: Marc Randolph: Re: State Machines....
                    63360: 03/11/20: Ulf Samuelsson: Re: State Machines....
    63331: 03/11/19: Mike Treseler: Re: State Machines....
63297: 03/11/19: Ken: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
    63307: 03/11/19: Symon: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
        63326: 03/11/19: Francisco Rodriguez: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
            63371: 03/11/20: Ken: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
        63362: 03/11/20: Ken: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
            63367: 03/11/20: Marc Randolph: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
                63370: 03/11/20: Ken: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
                    63376: 03/11/20: Marc Randolph: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
                        63377: 03/11/20: Ken: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
            63404: 03/11/20: Brian Davis: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
                63424: 03/11/21: Ken: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
                    63439: 03/11/21: Brian Davis: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
                        63960: 03/12/10: Ray Andraka: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
63303: 03/11/19: Dave Wilson: Apex power calculator
    63349: 03/11/20: Marc Guardiani: Re: Apex power calculator
    63464: 03/11/21: Ben Twijnstra: Re: Apex power calculator
63305: 03/11/19: Al Clark: Small PLD choices
    63311: 03/11/19: Mikeandmax: Re: Small PLD choices
    63315: 03/11/19: rickman: Re: Small PLD choices
    63318: 03/11/19: Khim Bittle: Re: Small PLD choices
        63441: 03/11/21: Dan: Re: Small PLD choices
    63333: 03/11/20: Jim Granville: Re: Small PLD choices
    63379: 03/11/20: Steve Prokosch: Re: Small PLD choices
    63382: 03/11/20: Ulf Samuelsson: Re: Small PLD choices
63329: 03/11/19: Robert Finch: Xilinx UCF file conditional includes ?
    63348: 03/11/20: Martin Euredjian: Re: Xilinx UCF file conditional includes ?
63361: 03/11/20: PanJuHwa: Virtex Benchmarks
63364: 03/11/20: Mastupristi: avoiding GCLK
    63369: 03/11/20: Martin Kellermann: Re: avoiding GCLK
    63381: 03/11/20: Mastupristi: Re: avoiding GCLK
    63395: 03/11/20: John_H: Re: avoiding GCLK
    63397: 03/11/20: Mark van de Belt: Re: avoiding GCLK
63365: 03/11/20: Wing Fong Wong: Altera Max 7000 cpld's
    63405: 03/11/21: Carl: Re: Altera Max 7000 cpld's
        63408: 03/11/21: Wing Fong Wong: Re: Altera Max 7000 cpld's
63366: 03/11/20: Dirk Ziegelmeier: Xilinx Microblaze SDRAM burst access
    63610: 03/11/26: steven derrien: Re: Xilinx Microblaze SDRAM burst access
63368: 03/11/20: Vazquez: Quartus II Node Finder
    63449: 03/11/21: Subroto Datta: Re: Quartus II Node Finder
63372: 03/11/20: sudip saha: vhdl construct problem
    63374: 03/11/20: Jonathan Bromley: Re: vhdl construct problem
63378: 03/11/20: Tim Forcer: Xilinx legacy situation
    63387: 03/11/20: Peter Alfke: Re: Xilinx legacy situation
        63419: 03/11/21: Tim Forcer: Re: Xilinx legacy situation
            63423: 03/11/21: Jim Granville: Re: Xilinx legacy situation
            63428: 03/11/21: Tim: Re: Xilinx legacy situation
                63436: 03/11/21: Jonathan Bromley: Re: Xilinx legacy situation
                63451: 03/11/21: Eric Crabill: Re: Xilinx legacy situation
    63392: 03/11/20: Steve Lass: Re: Xilinx legacy situation
    63401: 03/11/20: Neil Glenn Jacobson: Re: Xilinx legacy situation
        63425: 03/11/21: Tim Forcer: Re: Xilinx legacy situation
            63426: 03/11/21: Karl Olsen: Re: Xilinx legacy situation
            63446: 03/11/21: Neil Glenn Jacobson: Re: Xilinx legacy situation
                63498: 03/11/24: Tim Forcer: Re: Xilinx legacy situation
    63505: 03/11/24: B. Joshua Rosen: Re: Xilinx legacy situation
        63507: 03/11/24: Tim Forcer: Re: Xilinx legacy situation
            63510: 03/11/24: Peter Alfke: Re: Xilinx legacy situation
63399: 03/11/20: naveen: How to set 'set up time' in a Quartus Tool for a PCI Device
    63529: 03/11/24: Vaughn Betz: Re: How to set 'set up time' in a Quartus Tool for a PCI Device
        63542: 03/11/25: Nial Stewart: Re: How to set 'set up time' in a Quartus Tool for a PCI Device
63403: 03/11/20: walala: graphic card accelarator vs. FPGA: which is better for the following task?
    63447: 03/11/21: Andras Tantos: Re: graphic card accelarator vs. FPGA: which is better for the following task?
        63574: 03/11/25: walala: Re: graphic card accelarator vs. FPGA: which is better for the following task?
            63583: 03/11/25: Andras Tantos: Re: graphic card accelarator vs. FPGA: which is better for the following task?
    63603: 03/11/26: Kolja Sulimma: Re: graphic card accelarator vs. FPGA: which is better for the following task?
        63670: 03/11/27: walala: Re: graphic card accelarator vs. FPGA: which is better for the following task?
    63664: 03/11/27: Roger Larsson: [RFC] FPGA in AGP x8 slot?
63406: 03/11/20: pradeep: verification vs validation
    63407: 03/11/21: rickman: Re: verification vs validation
        63430: 03/11/21: pradeep: Re: verification vs validation
            63435: 03/11/21: Marc Randolph: Re: verification vs validation
                63500: 03/11/24: Ian Poole: Re: verification vs validation
63415: 03/11/21: Klaus Falser: XC9500 design does not fit into Coolrunner
    63421: 03/11/21: Uwe Bonnes: Re: XC9500 design does not fit into Coolrunner
        63444: 03/11/21: Dan: Re: XC9500 design does not fit into Coolrunner
        63535: 03/11/25: Klaus Falser: Re: XC9500 design does not fit into Coolrunner
            63537: 03/11/25: Uwe Bonnes: Re: XC9500 design does not fit into Coolrunner
                63565: 03/11/25: Arthur: Re: XC9500 design does not fit into Coolrunner
            63629: 03/11/26: Robert Sefton: Re: XC9500 design does not fit into Coolrunner
    63647: 03/11/27: Iwo Mergler: Re: XC9500 design does not fit into Coolrunner
        63701: 03/12/01: Klaus Falser: Re: XC9500 design does not fit into Coolrunner
            63702: 03/12/01: Jim Granville: Re: XC9500 design does not fit into Coolrunner
63416: 03/11/21: Mastupristi: ERROR:Pack:1107 - ISE 6.1
63420: 03/11/21: Sergey Yemets: Undocumented units in Virtex (I assume in Spartan-II too)
    63427: 03/11/21: Sean Durkin: Re: Undocumented units in Virtex (I assume in Spartan-II too)
63422: 03/11/21: Silvano Bettinzana: Virtex2Pro Internal Config. Access Port
63431: 03/11/21: Fred: Xlilinx (xc2vp30-5fg676)
    63433: 03/11/21: Fred: New ASCII-figure
        63434: 03/11/21: Fred: Re: New ASCII-figure
            63475: 03/11/22: Philip Freidin: Re: New ASCII-figure
63437: 03/11/21: Marek Ponca: FC II & Generic
63442: 03/11/21: PM: Implementing submodules with their own constraint files
63450: 03/11/21: Martin Sauer: Xilinx WebPack and Linux/WINE
    63455: 03/11/21: Uwe Bonnes: Re: Xilinx WebPack and Linux/WINE
63456: 03/11/21: Symon: Differential terminations in Virtex2 Pro.
    63458: 03/11/21: Peter Alfke: Re: Differential terminations in Virtex2 Pro.
        63459: 03/11/21: Symon: Re: Differential terminations in Virtex2 Pro.
            63471: 03/11/22: Allan Herriman: Re: Differential terminations in Virtex2 Pro.
                63530: 03/11/25: Allan Herriman: Re: Differential terminations in Virtex2 Pro.
                    63557: 03/11/25: Austin Lesea: Re: Differential terminations in Virtex2 Pro.
        63460: 03/11/21: Symon: Re: Differential terminations in Virtex2 Pro.
    63462: 03/11/21: Austin Lesea: Re: Differential terminations in Virtex2 Pro.
        63463: 03/11/21: Symon: Re: Differential terminations in Virtex2 Pro.
            63467: 03/11/21: Austin Lesea: Re: Differential terminations in Virtex2 Pro.
63469: 03/11/21: sree: Generating core using .mif file
63473: 03/11/22: Wang Feng: any FPGA design for video frame memory control?
    63525: 03/11/24: Ray Andraka: Re: any FPGA design for video frame memory control?
    63558: 03/11/25: Gerd B.: Re: any FPGA design for video frame memory control?
63474: 03/11/22: Nadeem Douba: LF: Affordable Development Board
    63479: 03/11/22: MM: Re: Affordable Development Board
    63483: 03/11/22: Jean Nicolle: Re: Affordable Development Board
        63635: 03/11/26: Vaughn Betz: Re: Affordable Development Board
63488: 03/11/22: Johnson: Aurora_401 reference allows 8B/10B bypass?
    63492: 03/11/23: Philip Freidin: Re: Aurora_401 reference allows 8B/10B bypass?
        63495: 03/11/24: Marc Randolph: Re: Aurora_401 reference allows 8B/10B bypass?
63491: 03/11/23: Hans: Laptop without serial/parallel port
    63494: 03/11/24: Matt: Re: Laptop without serial/parallel port
    63496: 03/11/24: Amontec Team, Laurent Gauch: Re: Laptop without serial/parallel port
        63499: 03/11/24: louis lin: Re: Laptop without serial/parallel port
            63554: 03/11/25: Hans: Re: Laptop without serial/parallel port
                63596: 03/11/26: Matt: Re: Laptop without serial/parallel port
    63519: 03/11/25: John Williams: Re: Laptop without serial/parallel port
63493: 03/11/24: Peng Cong: Xilinx ISE 6.1i+SP2 And Modelsim 5.8
    63511: 03/11/24: Mike Treseler: Re: Xilinx ISE 6.1i+SP2 And Modelsim 5.8
63497: 03/11/24: Tom: store program in external sdram
    63512: 03/11/24: Mike Treseler: Re: store program in external sdram
63502: 03/11/24: PM: Has anyone had any luck complining examples for a Virtex-II multimedia board
    154485: 12/11/14: yossarian69: RE: Has anyone had any luck complining examples for a Virtex-II multimedia board
63503: 03/11/24: Frank: MDD file
63504: 03/11/24: enq_semi: How many dedicated clock pins EP20K1500EBC652 device?
    63528: 03/11/24: Vaughn Betz: Re: How many dedicated clock pins EP20K1500EBC652 device?
        63551: 03/11/25: enq_semi: Re: How many dedicated clock pins EP20K1500EBC652 device?
            63601: 03/11/26: Vaughn Betz: Re: How many dedicated clock pins EP20K1500EBC652 device?
                63607: 03/11/26: enq_semi: Re: How many dedicated clock pins EP20K1500EBC652 device?
                    63633: 03/11/26: Vaughn Betz: Re: How many dedicated clock pins EP20K1500EBC652 device?
63506: 03/11/24: Tobias =?iso-8859-1?Q?M=F6glich?=: Dual port RAM for Xilinx
    63533: 03/11/25: Erik Markert: Re: Dual port RAM for Xilinx
        63665: 03/11/27: Mark van de Belt: Re: Dual port RAM for Xilinx
    63534: 03/11/25: Peng Cong: Re: Dual port RAM for Xilinx
    63540: 03/11/25: pradeep: Re: Dual port RAM for Xilinx
        63705: 03/12/01: Tobias =?iso-8859-1?Q?M=F6glich?=: Re: Dual port RAM for Xilinx
            63815: 03/12/04: Mark van de Belt: Re: Dual port RAM for Xilinx
63508: 03/11/24: Symon: Differential terminations in Virtex2 Pro.Attempt II!
    63509: 03/11/24: Austin Lesea: Re: Differential terminations in Virtex2 Pro.Attempt II!
        63515: 03/11/24: Symon: Re: Differential terminations in Virtex2 Pro.Attempt II!
63513: 03/11/24: Kresten Nrgaard: Reconstructing source code from JED file
    63516: 03/11/25: Jim Granville: Re: Reconstructing source code from JED file
63520: 03/11/25: Jim Granville: 5V I/O with 1.8V Core
    63522: 03/11/24: Symon: Re: 5V I/O with 1.8V Core
        63526: 03/11/25: Jim Granville: Re: 5V I/O with 1.8V Core
            63555: 03/11/25: Austin Lesea: Re: 5V I/O with 1.8V Core
    63564: 03/11/25: Nicholas C. Weaver: Re: 5V I/O with 1.8V Core
        63573: 03/11/26: Jim Granville: Re: 5V I/O with 1.8V Core
            63577: 03/11/25: Austin Lesea: Re: 5V I/O with 1.8V Core
                63578: 03/11/26: Jim Granville: Re: 5V I/O with 1.8V Core
                    63579: 03/11/25: Austin Lesea: Re: 5V I/O with 1.8V Core
                        63581: 03/11/26: Jim Granville: Re: 5V I/O with 1.8V Core
                            63605: 03/11/26: Austin Lesea: Re: 5V I/O with 1.8V Core
                63623: 03/11/27: John Williams: Re: 5V I/O with 1.8V Core
                    63625: 03/11/26: Peter Alfke: Re: 5V I/O with 1.8V Core
                        63626: 03/11/27: Jim Granville: Re: 5V I/O with 1.8V Core
                        63656: 03/11/27: Nicholas C. Weaver: Re: 5V I/O with 1.8V Core
                            63657: 03/11/27: Hal Murray: Re: 5V I/O with 1.8V Core
                                63660: 03/11/27: Nicholas C. Weaver: Re: 5V I/O with 1.8V Core
                                    63671: 03/11/28: Jim Granville: Re: 5V I/O with 1.8V Core
                                        63680: 03/11/28: Nicholas C. Weaver: Re: 5V I/O with 1.8V Core
                                        63708: 03/12/01: Austin Lesea: Re: 5V I/O with 1.8V Core
            63582: 03/11/26: Nicholas C. Weaver: Re: 5V I/O with 1.8V Core
        63594: 03/11/26: Tullio Grassi: Re: 5V I/O with 1.8V Core
        63616: 03/11/26: Peter Alfke: Re: 5V I/O with 1.8V Core
63524: 03/11/25: Michael Gallen: ANN: Tyd-IP Code Generator ....VHDL for DSP
63527: 03/11/25: valentin tihomirov: Slightly unmatched UART frequencies
    63531: 03/11/25: rickman: Re: Slightly unmatched UART frequencies
        63532: 03/11/25: valentin tihomirov: Re: Slightly unmatched UART frequencies
            63544: 03/11/25: GPG: Re: Slightly unmatched UART frequencies
                63546: 03/11/25: Ulf Samuelsson: Re: Slightly unmatched UART frequencies
                63563: 03/11/25: Joel Kolstad: Re: Slightly unmatched UART frequencies
            63590: 03/11/26: rickman: Re: Slightly unmatched UART frequencies
    63536: 03/11/25: Joel Kolstad: Re: Slightly unmatched UART frequencies
        63539: 03/11/25: Hal Murray: Re: Slightly unmatched UART frequencies
            63541: 03/11/25: Jim Granville: Re: Slightly unmatched UART frequencies
            63560: 03/11/25: Joel Kolstad: Re: Slightly unmatched UART frequencies
                63591: 03/11/26: rickman: Re: Slightly unmatched UART frequencies
                63593: 03/11/26: rickman: Re: Slightly unmatched UART frequencies
                    63595: 03/11/25: Joel Kolstad: Re: Slightly unmatched UART frequencies
                63822: 03/12/04: Eric Smith: Re: Slightly unmatched UART frequencies
                    63825: 03/12/05: Allan Herriman: Re: Slightly unmatched UART frequencies
        63821: 03/12/04: Eric Smith: Re: Slightly unmatched UART frequencies
            63826: 03/12/04: Joel Kolstad: Re: Slightly unmatched UART frequencies
    63538: 03/11/25: juergen sauermann: Re: Slightly unmatched UART frequencies
        63547: 03/11/25: Philip Freidin: Re: Slightly unmatched UART frequencies
            63552: 03/11/25: juergen Sauermann: Re: Slightly unmatched UART frequencies
                63570: 03/11/25: glen herrmannsfeldt: Re: Slightly unmatched UART frequencies
                    63575: 03/11/25: Peter Alfke: Re: Slightly unmatched UART frequencies
                        63587: 03/11/25: GPG: Re: Slightly unmatched UART frequencies
                63614: 03/11/26: Philip Freidin: Re: Slightly unmatched UART frequencies
            63553: 03/11/25: Tim: Re: Slightly unmatched UART frequencies
            63572: 03/11/26: Jim Granville: Re: Slightly unmatched UART frequencies
                63824: 03/12/04: Eric Smith: Re: Slightly unmatched UART frequencies
        63823: 03/12/04: Eric Smith: Re: Slightly unmatched UART frequencies
    63584: 03/11/26: Allan Herriman: Re: Slightly unmatched UART frequencies
    63640: 03/11/27: Jean Nicolle: Re: Slightly unmatched UART frequencies
        63644: 03/11/27: glen herrmannsfeldt: Re: Slightly unmatched UART frequencies
    63651: 03/11/27: Watson A.Name - Watt Sun, Dark Remover: Re: Slightly unmatched UART frequencies
        63692: 03/11/30: valentin tihomirov: Re: Slightly unmatched UART frequencies
            63696: 03/12/01: Jim Granville: Re: Slightly unmatched UART frequencies
            63699: 03/12/01: Simon Peacock: Re: Slightly unmatched UART frequencies
                63700: 03/11/30: Joel Kolstad: Re: Slightly unmatched UART frequencies
                    63723: 03/12/02: Simon Peacock: Re: Slightly unmatched UART frequencies
                        63724: 03/12/01: Joel Kolstad: Re: Slightly unmatched UART frequencies
                            63787: 03/12/04: Simon Peacock: Re: Slightly unmatched UART frequencies
63543: 03/11/25: sai a: Soft-core processor construction
63545: 03/11/25: PawelT: programmable fir and simulation
    63706: 03/12/01: PawelT: Re: programmable fir and simulation
    63715: 03/12/01: Marc Randolph: Re: programmable fir and simulation
63548: 03/11/25: Frank: using xilkernel
    63567: 03/11/25: mohan: Re: using xilkernel
63549: 03/11/25: Frank: running from external memory (microblaze)
    63568: 03/11/25: mohan: Re: running from external memory (microblaze)
        63608: 03/11/26: Frank: Re: running from external memory (microblaze)
            63615: 03/11/26: mohan: Re: running from external memory (microblaze)
63556: 03/11/25: A.y: area constraints
    63561: 03/11/25: Martin Euredjian: Re: area constraints
        63597: 03/11/25: A.y: Re: area constraints
            63599: 03/11/26: Martin Euredjian: Re: area constraints
    63562: 03/11/25: Steve Lass: Re: area constraints
        63598: 03/11/25: A.y: Re: area constraints
            63612: 03/11/26: Steve Lass: Re: area constraints
                63645: 03/11/27: A.y: Re: area constraints
                    63658: 03/11/27: Martin Euredjian: Re: area constraints
                        63674: 03/11/27: A.y: Re: area constraints
63559: 03/11/25: Sujatha: Can there be 2 loops in one process
    63569: 03/11/25: Symon: Re: Can there be 2 loops in one process
63566: 03/11/25: bhb: memory
63571: 03/11/25: T. Irmen: XVPI
63576: 03/11/25: walala: what is the fastest speed that FPGA deals with CPU?
    63620: 03/11/26: Kolja Sulimma: Re: what is the fastest speed that FPGA deals with CPU?
        63624: 03/11/26: walala: Re: what is the fastest speed that FPGA deals with CPU?
            63636: 03/11/26: Muthu: Re: what is the fastest speed that FPGA deals with CPU?
                63668: 03/11/27: walala: Re: what is the fastest speed that FPGA deals with CPU?
            63646: 03/11/27: Kolja Sulimma: Re: what is the fastest speed that FPGA deals with CPU?
                63669: 03/11/27: walala: Re: what is the fastest speed that FPGA deals with CPU?
    63654: 03/11/27: Paul Hartke: Re: what is the fastest speed that FPGA deals with CPU?
63585: 03/11/25: Chris Carlen: Quote from Xilinx re: XPLA3
    63586: 03/11/26: Al Clark: Re: Quote from Xilinx re: XPLA3
        63712: 03/12/01: Dave Greenfield: Re: Quote from Xilinx re: XPLA3
            63714: 03/12/01: Peter Alfke: Re: Quote from Xilinx re: XPLA3
63588: 03/11/26: Jay: Input pins without Vcco supply-- Virtex-II
    63606: 03/11/26: Austin Lesea: Re: Input pins without Vcco supply-- Virtex-II
        63637: 03/11/27: Jay: Re: Input pins without Vcco supply-- Virtex-II
63589: 03/11/26: Larry Doolittle: Re: Soft-core processor construction
    63622: 03/11/26: Sumit Gupta: Re: Soft-core processor construction
63592: 03/11/25: Thad Smith: Re: Soft-core processor construction
63600: 03/11/26: Tom: external sdram and gdb tool
    63611: 03/11/26: Ryan Laity: Re: external sdram and gdb tool
        63648: 03/11/27: Tom: Re: external sdram and gdb tool
            63649: 03/11/27: Tom: Re: external sdram and gdb tool
63609: 03/11/26: steven derrien: IDE Ultra DMA on a SPARTAN II
    63617: 03/11/26: noone: Re: IDE Ultra DMA on a SPARTAN II
        63619: 03/11/26: steven derrien: Re: IDE Ultra DMA on a SPARTAN II
    63650: 03/11/27: nomanland: Re: IDE Ultra DMA on a SPARTAN II
63618: 03/11/26: steven derrien: IDE Ultra DMA on a SPARTAN II (corrected version)
63627: 03/11/27: Gavin Melville: Xilinx ISE 6.1 external editor
    63630: 03/11/27: Peng Cong: Re: Xilinx ISE 6.1 external editor
63628: 03/11/26: Anup Raghavan: Phy IP for Giga ethernet for Virtex -II Pro
63631: 03/11/27: Jian Ju: overshoot problem of EPM7128S
    63643: 03/11/27: Krzysztof Szczepanski: Re: overshoot problem of EPM7128S
    63795: 03/12/04: Ben Twijnstra: Re: overshoot problem of EPM7128S
63632: 03/11/26: Dean Armstrong: PCI LogiCORE with ISE 5.2
    63666: 03/11/27: Mark van de Belt: Re: PCI LogiCORE with ISE 5.2
    63686: 03/11/29: Eric Crabill: Re: PCI LogiCORE with ISE 5.2
63634: 03/11/26: Muthu: Xilinx FPGA Clock Skew
63652: 03/11/27: Ian: modular design flow in Xilinx ISE 6.1.
    63710: 03/12/01: Steve Lass: Re: modular design flow in Xilinx ISE 6.1.
63653: 03/11/27: valentin tihomirov: Any integesting article about PLD for short presentation
    63667: 03/11/27: MM: Re: Any integesting article about PLD for short presentation
        63672: 03/11/28: valentin tihomirov: Re: Any integesting article about PLD for short presentation
63655: 03/11/27: Yttrium: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
    63659: 03/11/27: Martin Euredjian: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
        63662: 03/11/27: Marc Randolph: Re: [VirtexII + DCM + newbie] problems with the clocksignals from
            63663: 03/11/27: Martin Euredjian: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
            63679: 03/11/28: Yttrium: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
        63678: 03/11/28: Yttrium: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
            63681: 03/11/28: Martin Euredjian: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
                63683: 03/11/29: Yttrium: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
                    63687: 03/11/29: Martin Euredjian: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
    63661: 03/11/27: John_H: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
63673: 03/11/28: Allan Herriman: Timing Analyzer - delay to die pad or package pin?
    63697: 03/12/01: Allan Herriman: Re: Timing Analyzer - delay to die pad or package pin?
63675: 03/11/28: Davide Canina: problem with RS485 or RS232
    63677: 03/11/28: MARTIN jm: Re: problem with RS485 or RS232
    63694: 03/11/30: valentin tihomirov: Re: problem with RS485 or RS232
    63725: 03/12/02: Mario Trams: Re: problem with RS485 or RS232
63676: 03/11/28: Alfredo: how to create timing report for all nets?
    63695: 03/12/01: Erez Birenzwig: Re: how to create timing report for all nets?
63682: 03/11/28: GN: Digilent Inc.
    63684: 03/11/30: Alex Gibson: Re: Digilent Inc.
    63685: 03/11/29: Jan Panteltje: Re: Digilent Inc.
    63688: 03/11/29: Peter Alfke: Re: Digilent Inc.
    63703: 03/12/01: GN: Re: Digilent Inc.
63689: 03/11/29: algous: what's the problem?
    63771: 03/12/03: Andy Peters: Re: what's the problem?
63690: 03/11/29: algous: MPEG2 decoder
63693: 03/11/30: Tullio Grassi: jitter in Virtex2 DCM
    63709: 03/12/01: Austin Lesea: Re: jitter in Virtex2 DCM
        63767: 03/12/03: Austin Lesea: Re: jitter in Virtex2 DCM
    63756: 03/12/03: Tullio Grassi: Re: jitter in Virtex2 DCM
63698: 03/11/30: deadflower: about digilent board
    63716: 03/12/01: Jan Panteltje: Re: about digilent board
    64020: 03/12/12: Tonny: Re: about digilent board
    76982: 04/12/17: <janbeck@gmail.com>: Re: about digilent board


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