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Messages from 63475

Article: 63475
Subject: Re: New ASCII-figure
From: Philip Freidin <philip@fliptronics.com>
Date: Sat, 22 Nov 2003 09:10:52 GMT
Links: << >>  << T >>  << A >>
On Fri, 21 Nov 2003 13:44:18 GMT, Fred <none@nowhere.no> wrote:
>Crap. This was supposed to be a follow up on
>my other thread. Sorry for the inconvenience...
>
>-Fred
>
>P.S. If anyone has a good news-client to
>recommend, please do :p

Unfortunately, with your spam blocking email address, I could
not reply off-list.

I have used Forte Agent for several years for both email and
news groups, and it meets all my needs. A free version with
somewhat less features is also available. Best of all, it
does not understand HTML, and so it is totally tolerant of
viruses, worms, etc.

    http://www.forteinc.com/main/homepage.php

Philip



Article: 63476
Subject: Re: Is this a good starter kit?
From: Thomas Womack <twomack@chiark.greenend.org.uk>
Date: 22 Nov 2003 13:56:10 +0000 (GMT)
Links: << >>  << T >>  << A >>
In article <20619edc.0311211127.77c8c0a@posting.google.com>,
Mike Silva <snarflemike@yahoo.com> wrote:
>"Alex Gibson" <alxx/*nospam*/@@/*nospam*/ihug./*nospam*/com./remove/au> wrote in message news:<bphg4m$dlu$1@lust.ihug.co.nz>...
>> I got myself a similar combo but with the dio1
>> and a couple of the breadboards
>> http://www.digilentinc.com/Catalog/digilab  io1.html
>> http://www.digilentinc.com/Catalog/digilab breadboard   wire-wrap.html
>> the lack of memory is a bit annoying sometimes
>> 
>> Have you had a look at http://www.burched.biz/
>> http://www.burched.biz/b5xsvp.html
>
>Well, there's clear consensus that I'll be wanting RAM!  I did look at
>the burched.biz stuff, but the 2.5X price put me off.

xess.com has a board for the same price as the digilab, with RAM,
though the FPGA is a good deal smaller and you'd have to use
prototyping board for the blinkylights.  I'd have thought that
building interfaces to blinkylights and push-buttons was easier than
building interfaces to RAM (no need to worry about signal integrity
...) but I've built neither.

Tom

Article: 63477
Subject: Re: Is this a good starter kit?
From: javaguy11111@yahoo.com (db)
Date: 22 Nov 2003 06:18:48 -0800
Links: << >>  << T >>  << A >>
snarflemike@yahoo.com (Mike Silva) wrote in message news:<20619edc.0311171148.4b9d44f5@posting.google.com>...
> This Digilent combo package looks to me like an excellent way to learn
> FPGAs (but then, I don't know anything yet!):
> 
> http://www.digilentinc.com/Catalog/digilab_2_dio2.html
> 
> Do more experienced eyes see any gotchas with this setup?  I realize
> the FPGA is bigger than a beginner needs, but the price seems good,
> and I gather the part is from a mainstream FPGA family.
> 
> Thanks.

This is the same setup I started with. I started with smaller projects
but after about 3 or 4 months of working my way up I was able to get
an openrisc processor running with uclinux. I did have to design my
own little DRAM board for this.
Still there is more than enough onboard memory to run an 8bit or 32
bit cpu and do some basic testing.
If you order this board be sure to ask for the  300k Spartan II rather
than the 200k. The extra 100k gates only costs about $10 more. When I
had the full openrisc up and running with uclinux I used 94% of the
300k Spartan.

Article: 63478
Subject: Re: 400 Mb/s ADC
From: "Morten Leikvoll" <m-leik@online.nospam>
Date: Sat, 22 Nov 2003 15:50:45 +0100
Links: << >>  << T >>  << A >>

"Ulf Samuelsson" <ulf@NOSPAMatmel.com> wrote in message
news:bpis10$q70$1@public2.atmel-nantes.fr...
>
> If you want to get some real speed, then maybe something like the Atmel
> TS8308500 (500 Mspl/s), TS8388B (1 Gspl/s) or TS83102G0B (Gspl/s) could be
> of interest.
> Going up to Giga Samples per second, would make your problem worse though
> :-)

Maxim also has the MAX104 (1 Ghz,) and MAX108 (1.5Ghz) and other lower
speeds in the range 500Mhz and up.




Article: 63479
Subject: Re: Affordable Development Board
From: "MM" <mbmsv@yahoo.com>
Date: Sat, 22 Nov 2003 10:00:32 -0500
Links: << >>  << T >>  << A >>
Check the archive starting from November 17th, there was a thread called "Is
this a good prototype kit?"...

/Mikhail


"Nadeem Douba" <ndouba@connectmail.carleton.ca> wrote in message
news:bpn68h$1nh$1@driftwood.ccs.carleton.ca...
> Hi everybody,
>
> I was wondering if anyone knew where I could get my hands on a cheap fpga
> development board... I'm a university student at Carleton U. in Ottawa so
I
> can't afford anything to fancy (tuition fees drained my pocket).
Anyways...
> if anyone can direct me to someone or some merchant I would greatly
> appreciate it.
>
> Thanks
>
> Nadeem
>
>



Article: 63480
Subject: Re: Altera Stratix synthesis error
From: erojr <janos.nojunk.nospam.ero@cern.nojunk.nospam.ch>
Date: Sat, 22 Nov 2003 11:06:07 -0500
Links: << >>  << T >>  << A >>
Ben Twijnstra wrote:
> erojr wrote:

>> > Error: Groups cannot be assigned to nodes
> 
> 
> 
> Doesn't sound like a familiar message. Can you post some code that
> instantiates the altsyncram?

Thanks for your efforts. Yes, here you can see below.

Janos Ero

------------------------------------------------------------------------------

LIBRARY IEEE;
LIBRARY altera_mf;

USE     IEEE.STD_LOGIC_1164.all;
USE     IEEE.Numeric_std.all;
USE     altera_mf.altera_mf_components.all;
USE     work.dttf_pack.all;


ENTITY my_rom IS
   GENERIC (
     lpm_width                : POSITIVE;
     lpm_widthad              : POSITIVE;
     lpm_file                 : STRING
     );
   PORT (
     address  : IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);
     outclock : IN STD_LOGIC;
     q        : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
     );

END my_rom;

ARCHITECTURE rom_unit OF my_rom IS

COMPONENT altsyncram
   GENERIC (
         -- PORT A PARAMETERS
         width_a                            :  INTEGER := 1;
         widthad_a                          :  INTEGER := 1;
         numwords_a                         :  INTEGER := 1;
         outdata_reg_a                      :  STRING  := "UNREGISTERED";
         address_aclr_a                     :  STRING  := "NONE";
         outdata_aclr_a                     :  STRING  := "NONE";
         indata_aclr_a                      :  STRING  := "NONE";
         wrcontrol_aclr_a                   :  STRING  := "NONE";
         byteena_aclr_a                     :  STRING  := "NONE";
         width_byteena_a                    :  INTEGER := 1;

         -- PORT B PARAMETERS
         width_b                            :  INTEGER := 1;
         widthad_b                          :  INTEGER := 1;
         numwords_b                         :  INTEGER := 1;
         rdcontrol_reg_b                    :  STRING  := "CLOCK1";
         address_reg_b                      :  STRING  := "CLOCK1";
         outdata_reg_b                      :  STRING  := "UNREGISTERED";
         outdata_aclr_b                     :  STRING  := "NONE";
         rdcontrol_aclr_b                   :  STRING  := "NONE";
         indata_reg_b                       :  STRING  := "CLOCK1";
         wrcontrol_wraddress_reg_b          :  STRING  := "CLOCK1";
         byteena_reg_b                      :  STRING  := "CLOCK1";
         indata_aclr_b                      :  STRING  := "NONE";
         wrcontrol_aclr_b                   :  STRING  := "NONE";
         address_aclr_b                     :  STRING  := "NONE";
         byteena_aclr_b                     :  STRING  := "NONE";
         width_byteena_b                    :  INTEGER := 1;

         -- GLOBAL PARAMETERS
         operation_mode                 :  STRING  := "BIDIR_DUAL_PORT";
         byte_size                          :  INTEGER := 8;
         read_during_write_mode_mixed_ports :  STRING  := "DONT_CARE";
         ram_block_type                     :  STRING  := "AUTO";
         init_file                          :  STRING  := "UNUSED";
         init_file_layout                   :  STRING  := "UNUSED";
         maximum_depth                      :  INTEGER := 0;
         intended_device_family             :  STRING  := "Stratix";

         lpm_hint                           :  STRING  := "UNUSED";
         lpm_type                           :  STRING  := "altsyncram"
         );

-- PORT DECLARATION
     PORT (
         -- INPUT PORT DECLARATION
         wren_a    : in std_logic := '0'; -- Port A write/read enable inp
         wren_b    : in std_logic := '0'; -- Port B write enable input
         rden_b    : in std_logic := 'Z'; -- Port B read enable input
         data_a    : in std_logic_vector(width_a - 1 downto 0) :=
                                                        (others => '0');
         data_b    : in std_logic_vector(width_b - 1 downto 0) :=
                                                        (others => '0');
         address_a : in std_logic_vector(widthad_a - 1 downto 0) :=
                                                        (others => '0');
         address_b : in std_logic_vector(widthad_b - 1 downto 0) :=
                                                        (others => '0');

         clock0    : in std_logic := '1';
         clock1    : in std_logic := '1';

         clocken0  : in std_logic := '1';
         clocken1  : in std_logic := '1';

         aclr0     : in std_logic := '0';
         aclr1     : in std_logic := '0';

         byteena_a : in std_logic_vector( (width_byteena_a) - 1 downto 0)
                                                     := (others => 'Z');
         byteena_b : in std_logic_vector( (width_byteena_b) - 1 downto 0)
                                                     := (others => 'Z');

         -- OUTPUT PORT DECLARATION
         q_a       : out std_logic_vector(width_a - 1 downto 0);
         q_b       : out std_logic_vector(width_b - 1 downto 0)
         );

END COMPONENT;

BEGIN

rom_comp : altsyncram
   GENERIC MAP (
   -- PORT A PARAMETERS
         width_a                  =>   lpm_width,
         widthad_a                =>    lpm_widthad,
         outdata_reg_a            => "clock0",

   -- GLOBAL PARAMETERS
         operation_mode           => "ROM",
         ram_block_type           => "AUTO",
         init_file                => lpm_file
         )
   PORT MAP (
         -- INPUT PORT DECLARATION
         address_a                => address,
         clock0                   => outclock,

        -- OUTPUT PORT DECLARATION
         q_a                      => q
   );

END rom_unit;




Article: 63481
Subject: Re: Is this a good starter kit?
From: snarflemike@yahoo.com (Mike Silva)
Date: 22 Nov 2003 10:44:05 -0800
Links: << >>  << T >>  << A >>
javaguy11111@yahoo.com (db) wrote in message news:<903bda3b.0311220618.3267ab2a@posting.google.com>...
> 
> This is the same setup I started with. I started with smaller projects
> but after about 3 or 4 months of working my way up I was able to get
> an openrisc processor running with uclinux. I did have to design my
> own little DRAM board for this.
> Still there is more than enough onboard memory to run an 8bit or 32
> bit cpu and do some basic testing.
> If you order this board be sure to ask for the  300k Spartan II rather
> than the 200k. The extra 100k gates only costs about $10 more. When I
> had the full openrisc up and running with uclinux I used 94% of the
> 300k Spartan.

Excellent tip on the larger part, thanks!

Mike

Article: 63482
Subject: Re: Is this a good starter kit?
From: snarflemike@yahoo.com (Mike Silva)
Date: 22 Nov 2003 10:46:21 -0800
Links: << >>  << T >>  << A >>
"MM" <mbmsv@yahoo.com> wrote in message news:<bpmrer$1paa7s$1@ID-204311.news.uni-berlin.de>...
> Mike,
> 
> > Just looking for a system to learn about FPGAs in my spare time.  In
> > all honesty I probably will never use more than a few percent of the
> > device.  Plenty of blinking lights is clearly the most important
> > feature. :)
> 
> Well, then it sounds like this board has all that you will need...
> 
> > > You will need to build a little board with a proper connector. This will
> > > probably cost you at least as much as the difference in the prices
>  between
> > > the boards you looked at... Have you checked with Digilent? They might
>  be
> > > offering expansion boards...
> >
> > Well, I can buy a couple of 128Kx8 SRAMs for 12 bucks, and another $12
> > for a proto board that's designed to plug into the FPGA board.  For a
> > little effort I still save $250.
> 
> The problem with this approach is signal integrity.... It will work in
> principle but it might not work at the board's full speed (at whatever the
> clock rate is there). However, it doesn't sound as you will need extra RAM
> anytime soon anyway...

Yep, I agree that's a consideration.  Hand-wiring was so much easier
in the days of 500ns memory...

Article: 63483
Subject: Re: Affordable Development Board
From: "Jean Nicolle" <j.nicolle@sbcglobal.net>
Date: Sat, 22 Nov 2003 20:28:03 GMT
Links: << >>  << T >>  << A >>
Take a look at this one
http://www.fpga4fun.com/board_pluto.html

Jean

"Nadeem Douba" <ndouba@connectmail.carleton.ca> wrote in message
news:bpn68h$1nh$1@driftwood.ccs.carleton.ca...
> Hi everybody,
>
> I was wondering if anyone knew where I could get my hands on a cheap fpga
> development board... I'm a university student at Carleton U. in Ottawa so
I
> can't afford anything to fancy (tuition fees drained my pocket).
Anyways...
> if anyone can direct me to someone or some merchant I would greatly
> appreciate it.
>
> Thanks
>
> Nadeem
>
>



Article: 63484
Subject: Re: State Machines....
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sat, 22 Nov 2003 14:00:23 -0800
Links: << >>  << T >>  << A >>


Hal Murray wrote:

> But one of the reasons for putting a big state machine
> in a ROM is so that you can treat it as a software problem.

I would prefer to write the "software"
in vhdl, and have synthesis fit it to
the block rom when appropriate.

            -- Mike


Article: 63485
Subject: Re: 400 Mb/s ADC
From: Peter Desnoyers <pjd@fred.cambridge.ma.us>
Date: Sat, 22 Nov 2003 22:52:00 GMT
Links: << >>  << T >>  << A >>
In article <369b6e8b.0311191630.15ece843@posting.google.com>, Jeff Peterson wrote:
> we will take about 64K samples, then can pause while processing...
> however all the time we are pausing we are losing data.  so we do want to
> keep the duty cycle up.  50% duty cyle is not a problem. 5% would be.

It sounds like you *really* want to do the FFTs on PCs, rather than on
an outboard DSP.  (for your application that might make sense, as you're
only building one or a few of these things, and software development
will be hugely easier)  You might try "striping" the data across
multiple PCs.  After the ADC, block the data into 64K "packets", and
have 2 or 3 links to FPGA "NICs" that receive blocks of 64k samples
(plus maybe a sequence number) and DMA them over PCI.

Even if you do try to convert to SCSI or Fibre Channel and use standard
adapters, you might still want to consider the striping idea.

-- 
.....................................................................
 Peter Desnoyers           (617) 661-1979    pjd@fred.cambridge.ma.us
 162 Pleasant St.
 Cambridge, Mass. 02139


Article: 63486
Subject: Re: State Machines....
From: hmurray@suespammers.org (Hal Murray)
Date: Sat, 22 Nov 2003 23:15:31 -0000
Links: << >>  << T >>  << A >>
>I would prefer to write the "software"
>in vhdl, and have synthesis fit it to
>the block rom when appropriate.

How big does a state machine have to get
before you want to think of it as software?

How about 100 lines of PIC/AVR code?  That's pretty
simple as software goes.

How many lines of VHDL/Verilog does it take per state?

Would you be happy with a reverse assembler?  That is a
program that would translate the (special) assmebler
language into your VHDL?

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 63487
Subject: Re: 400 Mb/s ADC
From: dMon <fragnet@excite.com>
Date: Sat, 22 Nov 2003 23:32:55 -0500
Links: << >>  << T >>  << A >>
On Sat, 22 Nov 2003 15:50:45 +0100, "Morten Leikvoll"
<m-leik@online.nospam> wrote:

>
>"Ulf Samuelsson" <ulf@NOSPAMatmel.com> wrote in message
>news:bpis10$q70$1@public2.atmel-nantes.fr...
>>
>> If you want to get some real speed, then maybe something like the Atmel
>> TS8308500 (500 Mspl/s), TS8388B (1 Gspl/s) or TS83102G0B (Gspl/s) could be
>> of interest.
>> Going up to Giga Samples per second, would make your problem worse though
>> :-)
>
>Maxim also has the MAX104 (1 Ghz,) and MAX108 (1.5Ghz) and other lower
>speeds in the range 500Mhz and up.
>
>

I worked on something similar that never got built. We wanted to
record the output of multiple  200MHz 12 Bit ADC and store it in a
harddrive. There was some company that sold an optical interface
harddrive that could manage the speed but we had decided to use
multiple harddrive and split the data among the drives to achieve the
desired throughput similar to what RAID drives do. As for FFT's they
are done way faster in a FPGA than in any processor including DSP
processors. The only problem is the cost of the FPGA if you need
really big FFT's (4K 24 bit wide). The card I was working on was
basically an RF spectrum analyzer for a missile so things needed to be
done in a hurry. The harddrive thing was for a prototype so we wanted
to store the RF we were seeing without processing it.

Ray


Article: 63488
Subject: Aurora_401 reference allows 8B/10B bypass?
From: wangxiao@eecis.udel.edu (Johnson)
Date: 22 Nov 2003 21:30:45 -0800
Links: << >>  << T >>  << A >>
I am currently using version 1.7 of the VHDL Aurora 401 reference
design for Xilinx Vertex II Pro RocketIO interface and trying to find
a way to bypass 8B/10B. What I do is to change the configurations of
ports and attributes of GT_CUSTOM as suggested in RocketIO transceiver
User Guide (page 59 to 61 for Ver2.1). Those ports/attributes are:

TXBYPASS8B10B
RX_DECODE_USE
TXCHARDISPMODE
RXCHARDISPVAL

It turns out that CHANNEL_UP is never asserted. The protocol engine
seems sending the Sync sequence, but the link is nerver initialized.
Does anybody know if Aurora_401 allows bypassing 8B/10B by some easy
reconfiguration? If not, is there any sample codes in VHDL using
GT_CUSTOM for RocketIO and bypassing 8B/10B? Thanks!

Best Regards,

Johnson
Univeristy of Delaware

Article: 63489
Subject: Re: Altera's altsyncram MAXIMUM_DEPTH
From: H. Peter Anvin <hpa@zytor.com>
Date: 22 Nov 2003 22:27:04 -0800
Links: << >>  << T >>  << A >>
Followup to:  <opryznd7oggdoir8@news.inode.at>
By author:    =?iso-8859-15?Q?Manfred_M=FCcke?= <manfred.getmuecke@ridgmxof.thisat>
In newsgroup: comp.arch.fpga
> 
> True as long as the size of the memory/FIFO is smaller than the memory 
> blocks available in the device. A Cyclone for example uses M4K memory 
> blocks with 4096bit each (as the name suggests). So for RAM/FIFOs <4096bit 
> you will always pay with a full M4K (as long as tey are implemented in 
> memory blocks), but for RAM/FIFOs >4096bits the M4K-block is the smallest 
> building unit, allowing you to implement a RAM/FIFO using 3*4096=12288bits 
> from 3 M4K-blocks (depending on the FIFO width). Because address decoding 
> is easier when aligning by depth an to improve speed, it can make sense to 
> use more (four in our example) M4K-blocks wasting some memory, but it is by 
> no ways a necessity.
> 

There is another issue, which is that the RAMs are actually 4608 bits,
not 4096.  I have seen Quartus refuse to use those extra bits in
situations where it could have, because it prefers to organize by
depth, and apparently no way to work around this.

I would really like to see:

(a) support of non-power-of-two memory sizes;
(b) ability to optimize for RAM consumption at the expense of timing.

This in particular was an issue when I tried to create a 16384 x 9 bit
ROM, and yes, I needed all 9 bits...

	-hpa
-- 
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
If you send me mail in HTML format I will assume it's spam.
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64

Article: 63490
Subject: Re: Memory Initialization: mif, coe, hex, etc,
From: H. Peter Anvin <hpa@zytor.com>
Date: 22 Nov 2003 22:31:36 -0800
Links: << >>  << T >>  << A >>
Followup to:  <bpc2nt$1m9fjq$1@ID-132015.news.uni-berlin.de>
By author:    "Josh Pfrimmer" <yeah_spam_me@thisaddress.com>
In newsgroup: comp.arch.fpga
> 
> I'd prefer a solution that only requires students to edit one file to
> change the program for both the hardware implementation (I've noticed that
> CoreGen puts the correct data in the EDIF file) AND the simulation.  It's a
> pretty challenging lab as it is, without the extra pitfall of having
> mismatching simulation/hardware programs.
> 

I usually find these kinds of situations are excellent excuses to
write a couple of Perl scripts.

Oh yes, am I the only one who thinks it's somewhat bizarre that almost
none of these tools can deal with a plain old binary file?

	-hpa
-- 
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
If you send me mail in HTML format I will assume it's spam.
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64

Article: 63491
Subject: Laptop without serial/parallel port
From: "Hans" <hansydelm@no-spam-ntlworld.com>
Date: Sun, 23 Nov 2003 09:30:28 -0000
Links: << >>  << T >>  << A >>
Hi All,

I have recently received a new all singing all dancing (well nearly :-)
laptop but unfortunately it no longer has a serial or parallel port (Dell
5150). In order to use my serial and parallel download/program cables I need
one of those USB to serial/parallel converters.

Do they work (i.e. simulate a real parallel/serial port) or am I asking for
trouble?

What about a PCMCIA parallel/serial card?

Thanks

Hans

www.ht-lab.com



Article: 63492
Subject: Re: Aurora_401 reference allows 8B/10B bypass?
From: Philip Freidin <philip@fliptronics.com>
Date: Sun, 23 Nov 2003 13:56:42 GMT
Links: << >>  << T >>  << A >>
On 22 Nov 2003 21:30:45 -0800, wangxiao@eecis.udel.edu (Johnson) wrote:
>I am currently using version 1.7 of the VHDL Aurora 401 reference
>design for Xilinx Vertex II Pro RocketIO interface and trying to find
>a way to bypass 8B/10B. What I do is to change the configurations of
>ports and attributes of GT_CUSTOM as suggested in RocketIO transceiver
>User Guide (page 59 to 61 for Ver2.1). Those ports/attributes are:
>
>TXBYPASS8B10B
>RX_DECODE_USE
>TXCHARDISPMODE
>RXCHARDISPVAL
>
>It turns out that CHANNEL_UP is never asserted. The protocol engine
>seems sending the Sync sequence, but the link is nerver initialized.
>Does anybody know if Aurora_401 allows bypassing 8B/10B by some easy
>reconfiguration? If not, is there any sample codes in VHDL using
>GT_CUSTOM for RocketIO and bypassing 8B/10B? Thanks!
>
>Best Regards,
>
>Johnson
>Univeristy of Delaware

If you are bypassing the 8B/10B encoder on transmit, are you doing
something in your logic that guarantees that you are still sending
a balanced code? what about max run length of "0" and "1"?

If you have disabled 10B/8B at the receiver, are you still sending
it comma characters for it to sync to (K28.5 I think).

I suspect the intention of the 8B/10B bypass is for an occasional
character in a transmit stream that is predominantly valid 8B/10B
encodes, with the bypass being used to achieve something that is
very non-standard. While you could use it to send 100 10B characters
of "0000000000", I would not expect a receiver to tolerate this.

What is you reason for wanting to bypass the 8B/10B encoder.

Philip Freidin


Philip Freidin
Fliptronics

Article: 63493
Subject: Xilinx ISE 6.1i+SP2 And Modelsim 5.8
From: "Peng Cong" <pc_dragon@sohu.com>
Date: Mon, 24 Nov 2003 09:12:52 +0800
Links: << >>  << T >>  << A >>
Hi all
    I have a problem with Modelsim simulation.
    When I use Modelsim 5.7f, I creat a project under ISE 6.1i+SP2, set
Simulator value to Modelsim,
it's fine. But yesterday after I upgrade Modelsim to version 5.8, when I
open the project, it said
that "This project was last saved with the project property 'Simulator' set
an unvalid value of 'Modelsim'".
    How can I solve this problem?
    Thanks for any advance



Article: 63494
Subject: Re: Laptop without serial/parallel port
From: "Matt" <bielstein2002@comcast.net>
Date: Mon, 24 Nov 2003 02:30:26 GMT
Links: << >>  << T >>  << A >>
My experience is that they do work. (USB converters) I have a Compaq Evo
N800v. I hate having to take them along but they appear to work as
advertised. I have heard of others having trouble though.



"Hans" <hansydelm@no-spam-ntlworld.com> wrote in message
news:m3%vb.5609$4Y6.5546@newsfep4-winn.server.ntli.net...
> Hi All,
>
> I have recently received a new all singing all dancing (well nearly :-)
> laptop but unfortunately it no longer has a serial or parallel port (Dell
> 5150). In order to use my serial and parallel download/program cables I
need
> one of those USB to serial/parallel converters.
>
> Do they work (i.e. simulate a real parallel/serial port) or am I asking
for
> trouble?
>
> What about a PCMCIA parallel/serial card?
>
> Thanks
>
> Hans
>
> www.ht-lab.com
>
>



Article: 63495
Subject: Re: Aurora_401 reference allows 8B/10B bypass?
From: Marc Randolph <mrand@my-deja.com>
Date: Mon, 24 Nov 2003 03:49:39 GMT
Links: << >>  << T >>  << A >>
Philip Freidin wrote:
> On 22 Nov 2003 21:30:45 -0800, wangxiao@eecis.udel.edu (Johnson) wrote:
> 
>>I am currently using version 1.7 of the VHDL Aurora 401 reference
>>design for Xilinx Vertex II Pro RocketIO interface and trying to find
>>a way to bypass 8B/10B. What I do is to change the configurations of
>>ports and attributes of GT_CUSTOM as suggested in RocketIO transceiver
>>User Guide (page 59 to 61 for Ver2.1). Those ports/attributes are:
>>
>>TXBYPASS8B10B
>>RX_DECODE_USE
>>TXCHARDISPMODE
>>RXCHARDISPVAL
>>
>>It turns out that CHANNEL_UP is never asserted. The protocol engine
>>seems sending the Sync sequence, but the link is nerver initialized.
>>Does anybody know if Aurora_401 allows bypassing 8B/10B by some easy
>>reconfiguration? If not, is there any sample codes in VHDL using
>>GT_CUSTOM for RocketIO and bypassing 8B/10B? Thanks!

Whenever I see stuff discussing a channel being "up", I usually assume 
it refers to connections that use 8B/10B unless it says otherwise.... 
so... are you sure that CHANNEL_UP can be asserted even when 8B/10B is 
not being used?

> If you are bypassing the 8B/10B encoder on transmit, are you doing
> something in your logic that guarantees that you are still sending
> a balanced code? what about max run length of "0" and "1"?
> 
> If you have disabled 10B/8B at the receiver, are you still sending
> it comma characters for it to sync to (K28.5 I think).

I have to admit that I don't understand what you are saying here. 
Unless I'm mistaken, if 10B/8B is disabled, the comma characters 
wouldn't (and actually, couldn't) be extracted from the datastream. 
Wouldn't that typically cause problems?

> I suspect the intention of the 8B/10B bypass is for an occasional
> character in a transmit stream that is predominantly valid 8B/10B
> encodes, with the bypass being used to achieve something that is
> very non-standard. While you could use it to send 100 10B characters
> of "0000000000", I would not expect a receiver to tolerate this.
> 
> What is you reason for wanting to bypass the 8B/10B encoder.

We bypass it to do SONET.

Have fun,

    Marc


Article: 63496
Subject: Re: Laptop without serial/parallel port
From: "Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com>
Date: Mon, 24 Nov 2003 08:40:50 +0100
Links: << >>  << T >>  << A >>
Hans wrote:
> Hi All,
> 
> I have recently received a new all singing all dancing (well nearly :-)
> laptop but unfortunately it no longer has a serial or parallel port (Dell
> 5150). In order to use my serial and parallel download/program cables I need
> one of those USB to serial/parallel converters.
> 
> Do they work (i.e. simulate a real parallel/serial port) or am I asking for
> trouble?
> 
> What about a PCMCIA parallel/serial card?
> 
> Thanks
> 
> Hans
> 
> www.ht-lab.com
> 
> 
Hi,

We tried months ago, but with only troubles. They do not come from 
hardware, but from software ... all is depending on how the drivers are 
written.

Amontec annouced a new USB pod for Xilinx and Altera JTAG access. The 
POD will be ready for Q1 2004.

Laurent
www.amontec.com

------------ And now a word from our sponsor ------------------
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Article: 63497
Subject: store program in external sdram
From: Tom <t_t_1232000@yahoo.com>
Date: Mon, 24 Nov 2003 09:39:33 +0100
Links: << >>  << T >>  << A >>
Hi, 

How do you store an entire program in external sdram, is it possible
to declare all sections in the linker script to sdram (eventually the
boot section to bram) ? Or is there another way to get all data in the
sdram ?

thanks

Tom 

Article: 63498
Subject: Re: Xilinx legacy situation
From: Tim Forcer <tmf@ecs.soton.ac.uk>
Date: Mon, 24 Nov 2003 08:42:46 +0000
Links: << >>  << T >>  << A >>
Neil Glenn Jacobson wrote:
> 
> Tim Forcer wrote:
>>
>> Neil Glenn Jacobson wrote:
>>
>>> iMPACT (all versions, full or WebPACK install) has
>>> supported and does support download via Parallel
>>> Cable III (in fact, I have one on my desk
>>> and it works just fine) as well as configuration
>>> of legacy devices.
>>
>> Err, not the version embedded in Project Navigator.
>> ...
> 
> There are several issues worthy of note:
> 
> (1) You may have "old" Xilinx parallel port drivers
> ...
> 
> http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=16494

Tried that - and some variants.  No change.

> (2) You are using a "clone" of Parallel Cable III not
> the "real deal".  We have seen situations in which the
> clones are not quite clones and fail for a variety of
> PC-related reasons.

No difference between clone circuitry and "real deal" hardware.

> (3) You may need to set your BIOS to use the Bidirectional
> (rather than ECP or EPP) mode for the parallel port.

Hmmm.  Haven't tried this, but I'm reluctant to mess around in
this way, particularly as other parallel port stuff works OK (eg
Lattice ispVM downloader).

The first set of students do their first FPGA exercises today,
and we're using the kludge of Webpack iMPACT installation used
stand-alone.  This works.

For the future, we're looking at Another Company's product. 
Shame, as we have invested a lot in Xilinx over many years. 
(That investment of time, effort and money would not have been
possible or had any point without substantial support from
Xilinx' University Program, which is freely and gratefully
acknowledged.)

-- 
Tim Forcer               tmf@ecs.soton.ac.uk
The University of Southampton, UK

The University is not responsible for my opinions

Article: 63499
Subject: Re: Laptop without serial/parallel port
From: "louis lin" <louis@zyflex.com.tw>
Date: Mon, 24 Nov 2003 17:22:04 +0800
Links: << >>  << T >>  << A >>

There's a tip on ISE5 of Xilinx:
Please set the environment variable XIL_IMPACT_LPT2_BASE_ADDRESS to the
base address used by your USB converter.
It's worked on a PCI printer card in ISE5 / Windows 2000.
However, I don't know if it will work on USB converter.



"Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com> :3FC1B602.7000303@amontecDELETEALLCAPS.com...
: Hans wrote:
: > Hi All,
: > 
: > I have recently received a new all singing all dancing (well nearly :-)
: > laptop but unfortunately it no longer has a serial or parallel port (Dell
: > 5150). In order to use my serial and parallel download/program cables I need
: > one of those USB to serial/parallel converters.
: > 
: > Do they work (i.e. simulate a real parallel/serial port) or am I asking for
: > trouble?
: > 
: > What about a PCMCIA parallel/serial card?
: > 
: > Thanks
: > 
: > Hans
: > 
: > www.ht-lab.com
: > 
: > 
: Hi,
: 
: We tried months ago, but with only troubles. They do not come from 
: hardware, but from software ... all is depending on how the drivers are 
: written.
: 
: Amontec annouced a new USB pod for Xilinx and Altera JTAG access. The 
: POD will be ready for Q1 2004.
: 
: Laurent
: www.amontec.com
: 
: ------------ And now a word from our sponsor ------------------
: Want to have instant messaging, and chat rooms, and discussion
: groups for your local users or business, you need dbabble!
: --  See http://netwinsite.com/sponsor/sponsor_dbabble.htm  ----




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