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Messages from 63500

Article: 63500
Subject: Re: verification vs validation
From: "Ian Poole" <ian.poole@doulos.delete-this-bit.com>
Date: Mon, 24 Nov 2003 10:34:44 -0000
Links: << >>  << T >>  << A >>
Verification proves (or at least, attempts to prove) that the design meets
the specification.
Validation proves that original specification was sound.

Check out www.dictionary.com

--
Ian Poole, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: ian.poole@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.


"Marc Randolph" <mrand@my-deja.com> wrote in message
news:_Ppvb.2138$n15.1506@newssvr24.news.prodigy.com...
> pradeep wrote:
> > hi rick,
> >
> > i am sorry for asking these type of trivial questions,
> >
> > let me be the first person to answer.
> >
> > Difference between verification and validation
> >
> > Validation and verification refer to the process of satisfying the
> > requirement, but the difference lies in the level of testing.
> >
> > Verification refer to lower level of test, like testing of module,
> > interface etc. Verification tests are conducted by the developer.
> >
> > Whereas validation occurs at the final stage prior to the acceptance
> > of a product for release. Validation tests are normally conducted by a
> > party that is independent of the developer (Quality Assurance or the
> > test group)
>
> Looking at the definition of those two words, you could just as easily
> reverse the wording of the last two paragraphs and you would be equally
> correct.
>
> The company I work for has a group called DVT (design verification and
> test).  They are the high level testers... the final stage prior to
> product release.  I'll bet others in the group have similar "final test"
> groups that use the word validation rather than verification.
>
> In my opinion, the words have close enough meanings that confusion would
> result if an organization tried to use them, by themselves, to mean two
> different things.
>
> Have fun,
>
>     Marc
>



Article: 63501
Subject: Re: PCI interface with attached PLD
From: "Nial Stewart" <nial@spamno.nialstewart.co.uk>
Date: Mon, 24 Nov 2003 11:35:35 -0000
Links: << >>  << T >>  << A >>
> I need to build a PCI interface - could be 64 bytes of write-only latches
> and 1 byte of status readback.
> Then I want to implement the rest of my logic, not to complex, in a PLD.
> I'd LIKE it all to be in one device, but I don't want to spend any time
> debugging PCI implementations.
> Anyone got any recommendations for where to go get my IP?
> David

David,

I'm just finishing off an Altera Cyclone based PCI core/board
combination.

The FPGA based cores I've seen require some PCI interface
understanding, mine has been designed to be as simple to
use as possible, 'Easy PCI' if you like.

The core is currently target only, takes minimal area (depending
on the number of memory areas you need but can be as low as
400 LUTs) and routes easily.

I'm waiting for the board house to get back to me so I can set
prices for the board, the core will be low cost compared to
anything else apart from the opencores core, but you would
have to implement this and debug hardware etc.

I'll sell the core, the board, the board and the core or can
develop custom hardware based round the two. This is similar to
your (Dexdyne's) 'zipper' idea. The PCI section of the board is
designed and debugged, custom hardware/logic design can be quickly
added. This could include a NIOS core is needs be.

Further details can be found here..

http://www.nialstewartdevelopments.co.uk/hardware.htm

The expansion connectors and mounting holes allow a daughter
board to be mounted for prototyping etc. These can be easily removed
to allow custom hardware to be implemented.


I hope this is of interest.



Nial Stewart

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk




Article: 63502
Subject: Has anyone had any luck complining examples for a Virtex-II multimedia board
From: "PM" <pwtm2@cam.ac.uk>
Date: Mon, 24 Nov 2003 13:12:27 -0000
Links: << >>  << T >>  << A >>
Dear All,

Has anyone had any success compiling the given examples files for the
Microblaze and Multimedia Development board (HW-V2000-MLTA)?

Regards,

PETE



Article: 63503
Subject: MDD file
From: "Frank" <someone@work.com>
Date: Mon, 24 Nov 2003 16:18:09 +0100
Links: << >>  << T >>  << A >>
Hi,

did anyone already tried to make an opb slave with multiple interrupt ports
and use the default interrupt handler? In order to assign your own interrupt
service routine to an interrupt, you have to make a driver for your opb
slave and in the mdd file you can make an array of interrupt handlers.
In that way you can specify in the mss file your interrupt service routine
for each interrupt port:

 PARAMETER INT_HANDLER = pec0_isr, INT_PORT = locbus_int_0
 PARAMETER INT_HANDLER = pec1_isr, INT_PORT = locbus_int_1
 PARAMETER INT_HANDLER = pec2_isr, INT_PORT = locbus_int_2
 PARAMETER INT_HANDLER = pec3_isr, INT_PORT = locbus_int_3

However, when I built the libraries, only the first isr is taken an placed
in the vector table (in XIntc_lg.c) the other three interrupts are routed to
the default interrupt handler. I can't even assign another default routine
in the mdd file:

BEGIN ARRAY interrupt_handler
  PROPERTY desc = "Interrupt Handler Information";
  PROPERTY size = 4, permit = none;
  PROPERTY default = ((test, locbus_int_0), (XIntc_DefaultHandler,
locbus_int_1), (XIntc_DefaultHandler, locbus_int_2), (XIntc_DefaultHandler,
locbus_int_3));
  PARAM name = int_handler, desc = "Name of Interrupt Handler", type =
string;
  PARAM name = int_port, desc = "Interrupt pin associated with interrupt
handler", permit = none;
END ARRAY

I expect here to assign the isr test to the locbus_int_0 port (only when I
left away the assignment in the mss file of coarse), but even now the
default isr is assigned (XIntc_DefaultHandler).

Hopefully its clear enough,
does anyone have experience with this?

TIA,
Frank



Article: 63504
Subject: How many dedicated clock pins EP20K1500EBC652 device?
From: enq_semi@yahoo.com (enq_semi)
Date: 24 Nov 2003 07:26:36 -0800
Links: << >>  << T >>  << A >>
How many dedicated clock pins are there for EP20K1500EBC652 device? 

I only found clk1p,clk2p,clk3p,clk4p (Pin w34, u2, y34, t2) are
dedicated clock pins. However, clk1p and clk2p are connected together,
clk3p and clk4p are connected together; So I can only have two
different clock signals drive the internal clock trees.

According to APEX 20K Programmable Logic Device Family Data Sheet,
there are "up to eight global clock signals" in the APEX 20K device.
How many are there for EP20K1500 device and how can I have more than
two different external clocks to drive the different internal clock
trees?

thanks,

Yi Zhang
ENQ Semi

Article: 63505
Subject: Re: Xilinx legacy situation
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Mon, 24 Nov 2003 11:23:05 -0500
Links: << >>  << T >>  << A >>
On Thu, 20 Nov 2003 16:48:47 +0000, Tim Forcer wrote:

> We have some well-established teaching laboratory kit, using
> Xilinx XC4013E (optionally XC4020E for project work), with
> download by JTAG and a clone of Xilinx Parallel Cable III
> (DLC5).
> 
> As has been discussed here before, despite some statements on
> Xilinx Website, the latest (full-spec) Xilinx software includes
> an iMPACT downloader which doesn't support Parallel Cable III. 
> Alternatively, latest Webpack 6 includes an iMPACT which
> supports the download, but not any flavour of XC4000 (although
> all the library and similar files seem to be present).
> 
>
Why don't you stick with the last version of the Xilinx tools that really
supported the 4000 series (probably 4.2)? All of the improvements in the
current tools are aimed at today's FPGAs not at a ten year old family.
From the standpoint of your students the only difference between 4.2 and
6.1 is that the GUI is a little different, but you shouldn't care about
that because the GUI changes with every release.

The one new tool that would be very helpful for your students is
ChipScope, but that uses block RAM which is only present in modern FPGAs. 


Article: 63506
Subject: Dual port RAM for Xilinx
From: Tobias =?iso-8859-1?Q?M=F6glich?= <Tobias.Moeglich@gmx.net>
Date: Mon, 24 Nov 2003 18:11:54 +0100
Links: << >>  << T >>  << A >>
Hello,

Is there someone who has experiences with designing a dual port RAM.
I use the device Spartan-IIE (XC2S300E). But it should be simular with
other devices (e.g. Virtex, Spartan 3, etc)
I know there is a Synthesis Template in "Xilinx ISE Foundation". Is
there someone who knows about a complete design
for a dual port RAM.
I know, I need to get some more experience with VHDL.

Thank you for any help.

Tobias Möglich




Article: 63507
Subject: Re: Xilinx legacy situation
From: Tim Forcer <tmf@ecs.soton.ac.uk>
Date: Mon, 24 Nov 2003 17:22:28 +0000
Links: << >>  << T >>  << A >>
"B. Joshua Rosen" wrote:
> 
> Why don't you stick with the last version
> of the Xilinx tools that really supported
> the 4000 series (probably 4.2)?

This is probably the simplest solution.  If I can find the
installation CD-ROM!

Means changing the standard installation on 70-odd PCs - so
ghosting will be fun (for one of the systems folk, not me).

-- 
Tim Forcer               tmf@ecs.soton.ac.uk
The University of Southampton, UK

The University is not responsible for my opinions

Article: 63508
Subject: Differential terminations in Virtex2 Pro.Attempt II!
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 24 Nov 2003 09:38:47 -0800
Links: << >>  << T >>  << A >>
Dear All,
    I'll phrase my questions differently from my last attempt!

Q1.    If I instantiate a 2.5V LVDS input with differential termination in
my design, e.g. LVDS_25_DT, then I power its VCCO with 3.3V, what happens? I
think the input DC thresholds should stay the same, as they're powered from
VCCAUX, but what about the termination impedance?
Q2.    If I instantiate a 2.5V LVDS output in my design, then I power its
VCCO with 3.3V, what happens? What are the output's DC characteristics?
Q3.    Will Xilinx publish pictures of the various outputs so I can figure
this out myself? You know, those little diagrams with transistors, current
sources and stuff that a lot of other datasheets have!

    Thanks all, Syms.



Article: 63509
Subject: Re: Differential terminations in Virtex2 Pro.Attempt II!
From: Austin Lesea <austin@xilinx.com>
Date: Mon, 24 Nov 2003 10:18:34 -0800
Links: << >>  << T >>  << A >>
Symon,

Let us try to get it this time!

See below,

Austin

Symon wrote:
> Dear All,
>     I'll phrase my questions differently from my last attempt!
> 
> Q1.    If I instantiate a 2.5V LVDS input with differential termination in
> my design, e.g. LVDS_25_DT, then I power its VCCO with 3.3V, what happens? I
> think the input DC thresholds should stay the same, as they're powered from
> VCCAUX, but what about the termination impedance?
Just fine, no problem.

> Q2.    If I instantiate a 2.5V LVDS output in my design, then I power its
> VCCO with 3.3V, what happens?
You exceed the abs max specs, and you void any warranties or guarantees.

  What are the output's DC characteristics?
> Q3.    Will Xilinx publish pictures of the various outputs so I can figure
> this out myself? You know, those little diagrams with transistors, current
> sources and stuff that a lot of other datasheets have!
The schematics for the IOBs are so large that they crash spice 
simulators.  So, no, we are not going to publish any schematics, other 
than the simplified ones that are already in the datasheet and user guides.

> 
>     Thanks all, Syms.
> 
> 


Article: 63510
Subject: Re: Xilinx legacy situation
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 24 Nov 2003 11:04:57 -0800
Links: << >>  << T >>  << A >>
Tim, if you have a problem finding the CD for 4.2, contact me or call
the Xilinx UK office. We will get you over that "hurdle".
Peter Alfke

Tim Forcer wrote:
> 
> "
> This is probably the simplest solution.  If I can find the
> installation CD-ROM!
>

Article: 63511
Subject: Re: Xilinx ISE 6.1i+SP2 And Modelsim 5.8
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 24 Nov 2003 11:17:35 -0800
Links: << >>  << T >>  << A >>
Peng Cong wrote:
> Hi all
>     I have a problem with Modelsim simulation.
>     When I use Modelsim 5.7f, I creat a project under ISE 6.1i+SP2, set
> Simulator value to Modelsim,
> it's fine. But yesterday after I upgrade Modelsim to version 5.8, when I
> open the project, it said
> that "This project was last saved with the project property 'Simulator' set
> an unvalid value of 'Modelsim'".
>     How can I solve this problem?
>     Thanks for any advance
> 
> 
try a

    vcom -refresh

from your source directory.

Consider calling vcom and vsim from the command
line instead of using the gui project manager.

   -- Mike Treseler


Article: 63512
Subject: Re: store program in external sdram
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 24 Nov 2003 11:21:48 -0800
Links: << >>  << T >>  << A >>
Tom wrote:
> Hi, 
> 
> How do you store an entire program in external sdram

Normally the boot code copies it over after the
sdram init is completed.

   -- Mike Treseler


Article: 63513
Subject: Reconstructing source code from JED file
From: "Kresten Nørgaard" <knc@remooov_develco.dk>
Date: Mon, 24 Nov 2003 20:41:42 +0100
Links: << >>  << T >>  << A >>
Hi

Im upgrading an old HW-design for a client, which includes and Xilinx
XC9536XL. Unfortunately he only seems to have the .JED file, which gives me
a hard time figuring out how the constuction was intended to work.

I wonder if there is a simple way to reconstruct the boolean equations from
the JED file?

Kresten



Article: 63514
Subject: Re: XILINX Foundation F1.5 Build 3.1.1.35 with XCS10PC84 and Digilab XLA
From: komara5@comcast.net (Kevin O'Mara)
Date: 24 Nov 2003 12:35:15 -0800
Links: << >>  << T >>  << A >>
Fix for Digilab XLA and Xilinx Foundation F1.5 Software
-------------------------------------------------------

http://www.digilentinc.com
http://www.xilinx.com

In order to get Xilinx Foundation F1.5 to work properly, it is first
necessary to install these two updates:

ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/15_service_pack1_nt.zip
ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/15_sp1_ftp2_nt.zip


If your DigiLab XLA board fails to run your designs, even after you
have transferred them via the parallel cable successfully, then this
board modification should remedy the problem.

1. Find chip U4 on the board (labeled "Japan 00 33 H 74HC125AP"),
which is located close to the parallel port.

2. Pull out the chip.

3. Find pin #6 on the chip.  Orient yourself by locating pin #1, which
is on the upper-left side of the chip.


		- |	| -
		- |	| -
		- |	| -
		- |	| -
		- |	| -
	-> #6	- |	| -
		- |	| -

	Figure 1 - Pin #6 on the U4 Chip.

4. Bend this pin (pin #6) out by extending it parallel to the base of
the chip.   It should not be able to reach the contacts when
reinserted into the board.

5. Reinsert the chip into the board.

6. Test the board.  It should function properly now.

Article: 63515
Subject: Re: Differential terminations in Virtex2 Pro.Attempt II!
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 24 Nov 2003 12:36:22 -0800
Links: << >>  << T >>  << A >>
Hi Austin,
    Thanks for that, very much appreciated, I knew you'd be able to help!
So, I've added some more questions!
            thanks again, Syms.

p.s. Please don't think I'm ungrateful, I'm a big fan of what you guys have
done with the IOs! The on-chip termination is a BIG help, as is the
excellent wide common mode range of the diff inputs!


"Austin Lesea" <austin@xilinx.com> wrote in message
news:bpti1q$hos1@cliff.xsj.xilinx.com...
> Symon,
>
> Let us try to get it this time!
>
> See below,
>
> Austin
>
> Symon wrote:
> > Dear All,
> >     I'll phrase my questions differently from my last attempt!
> >
> > Q1.    If I instantiate a 2.5V LVDS input with differential termination
in
> > my design, e.g. LVDS_25_DT, then I power its VCCO with 3.3V, what
happens? I
> > think the input DC thresholds should stay the same, as they're powered
from
> > VCCAUX, but what about the termination impedance?
> Just fine, no problem.

OK, cool! But why does it say in tiny writing in  "Figure 22: LVDS
Differential Termination Usage Examples" from "DS083-2 (v2.8) September 10,
2003", the Virtex-II Pro functional description:-
"NOTE: Only 2.5V LVDS standards are supported (VCCO = 2.5V only)" ?
Will the latest software prevent me from combining LVDS_25_DT and LVCMOS33
in the same bank?
It says in answer 17244:-
"Requirement to Turn on the On-chip Input Differential Termination
The VCCO of the I/O bank must be connected to 2.5V to provide 100 ohms of
effective termination.
NOTE: Starting ISE 6.1i, this requirement is implemented in the software. "
Are there any work-arounds? Like use LVCMOS25s and then power VCCO @ 3.3V?

>
> > Q2.    If I instantiate a 2.5V LVDS output in my design, then I power
its
> > VCCO with 3.3V, what happens?
> You exceed the abs max specs, and you void any warranties or guarantees.
>

I couldn't be sure I'd found this specification. I found "Table 8: LVDS DC
Specifications" in DS083-3 where there is a max for VCCO, but it's not clear
to me whether this is an abs max spec, or a spec for VCCO to meet the other
DC specs in the table. Could you clarify for me?
I presume 3.3V won't break the LVDS circuitry as it's probably still powered
from VCCO when LVCMOS33, for example, is used in the IOB. Correct?

>   What are the output's DC characteristics?
> > Q3.    Will Xilinx publish pictures of the various outputs so I can
figure
> > this out myself? You know, those little diagrams with transistors,
current
> > sources and stuff that a lot of other datasheets have!
> The schematics for the IOBs are so large that they crash spice
> simulators.  So, no, we are not going to publish any schematics, other
> than the simplified ones that are already in the datasheet and user
guides.
>

Fair enough, thought I'd try anyway!

> >
> >     Thanks all, Syms.
> >
> >
>



Article: 63516
Subject: Re: Reconstructing source code from JED file
From: "Jim Granville" <no.spam@designtools.co.nz>
Date: Tue, 25 Nov 2003 09:36:59 +1300
Links: << >>  << T >>  << A >>
"Kresten Nørgaard" wrote
> Hi
>
> Im upgrading an old HW-design for a client, which includes and Xilinx
> XC9536XL. Unfortunately he only seems to have the .JED file, which gives
me
> a hard time figuring out how the constuction was intended to work.
>
> I wonder if there is a simple way to reconstruct the boolean equations
from
> the JED file?

For some PLDs there are JED2EQN pathways - ask Xilinx ?.
Where this does not exist, you have some choices
a) reverse engineer the JED - not impossible, but will require many
iterations
and a good understanding of the CPLD structure to get the info.
Creating simple testcase templates with the tools helps identify the fuse
pattern areas.

Likely to be more productive to 'have a really good look for the source' :)

b) Reverse engineer the function.
They _should_ have a schematic, and info of things like memory or IO
mappings.
You can also generate JED test vectors, and use these to exercise the
existing device, and confirm the new one is functionally identical.

Be aware that because of the internal AND.OR structure, you
can create two JEDs functionally identical, but that fail a compare.

-jg



Article: 63517
Subject: Re: State Machines....
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 24 Nov 2003 13:14:54 -0800
Links: << >>  << T >>  << A >>
Hal Murray wrote:

> How big does a state machine have to get
> before you want to think of it as software?

A synchronous VHDL process is already
a virtual machine that runs a complete
loop every clock tick. I already can
shift, add, move to a variable, move to or from
a variable of any type I like. I am not even
limited to a single operation per tick.


My point is that rather than making
a new, more-limited language to suck up
unused block rams, let's add smarts to
synthesis so that it knows how to make
a block of logic *for any purpose*
out of a rom when other resources get tight.

  -- Mike Treseler


Article: 63518
Subject: Re: 400 Mb/s ADC
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Tue, 25 Nov 2003 08:14:29 +1000
Links: << >>  << T >>  << A >>
Jeff Peterson wrote:
>>The fastest slots on a PC Mainboard are the memory expansion slots.
>>It's an easy to design hardware interface and if you use a server
>>mainboard with multiple memory channels you get a hell lot of
>>bandwidth. I remember seeing a cryptoaccelerator on a DIMM somewhere
>>and SUN used to place graphics boards in memory slots.
> 
> hmmm...interesting idea

here's a reasonable place to start digging:

http://citeseer.nj.nec.com/leong01pilchard.html

John


Article: 63519
Subject: Re: Laptop without serial/parallel port
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Tue, 25 Nov 2003 08:19:23 +1000
Links: << >>  << T >>  << A >>
Hi,

Hans wrote:
> I have recently received a new all singing all dancing (well nearly :-)
> laptop but unfortunately it no longer has a serial or parallel port (Dell
> 5150). In order to use my serial and parallel download/program cables I need
> one of those USB to serial/parallel converters.
> 
> Do they work (i.e. simulate a real parallel/serial port) or am I asking for
> trouble?
> 
> What about a PCMCIA parallel/serial card?

I've had no problems with a Quatech PCMCIA parallel card.  It was 
expensive (relative to what you get). but it works.  And as another 
poster points out, you need to set an environment variable to tell the 
Xilinx S/W the correct IO port.

www.quatech.com

Regards,

John


Article: 63520
Subject: 5V I/O with 1.8V Core
From: "Jim Granville" <no.spam@designtools.co.nz>
Date: Tue, 25 Nov 2003 11:52:32 +1300
Links: << >>  << T >>  << A >>
 Following the recurring thread of 5V IO,
the loss thereof, and 'the price of progress', here are some
of the newest numbers from the uC industry :

                     Philips LPC2129      Spartan IIE
General        256KF/ARM              Advanced FPGA

Vcore            1.8V                            1.8V
Vio                <5.5V                            <3.6V
Icctyp           10uA                            10mA
IccMAX       <500uA                      <200mA

Icc numbers are Static, ie represent standby power levels.
FPGA of similar core Vcc is chosen, and smallest IIe device is chosen
to avoid too much die-area skew effect.
-jg




Article: 63521
Subject: Re: 400 Mb/s ADC
From: "Peter C. Wallace" <pcw@freeby.mesanet.com>
Date: Mon, 24 Nov 2003 15:29:16 -0800
Links: << >>  << T >>  << A >>
On Fri, 21 Nov 2003 08:29:08 -0800, Paul Smith wrote:

> Ulf Samuelsson wrote:
> 
> 
>> If you want to get some real speed, then maybe something like the Atmel
>> TS8308500 (500 Mspl/s), TS8388B (1 Gspl/s) or TS83102G0B (Gspl/s) could
>> be of interest.
>> Going up to Giga Samples per second, would make your problem worse
>> though
>> :-)
>> 
>> http://www.atmel.com/dyn/products/datasheets.asp?family_id=611
>> 
>> 
> When did Atmel start making flash ADCs?  Can someone actually buy these
> now?  How much do they cost?
> 
> see:
> 
> http://dustbunny.physics.indiana.edu/~paul/hallDrd
> 
> for our "merely" 250 Msps particle physics project.
> 
> 
> Paul Smith
> Indiana University Physics
 
One of the articles listed a price of $795 for the 2 Gspl/s converter in 1000's
 
Peter Wallace

Article: 63522
Subject: Re: 5V I/O with 1.8V Core
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 24 Nov 2003 16:04:58 -0800
Links: << >>  << T >>  << A >>

"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:CXvwb.9478$ws.845858@news02.tsnz.net...
> Following the recurring thread of 5V IO,
> the loss thereof, and 'the price of progress', here are some
> of the newest numbers from the uC industry :
>
>                      Philips LPC2129      Spartan IIE
> General        256KF/ARM              Advanced FPGA
>
> Vcore            1.8V                            1.8V
> Vio                <5.5V                            <3.6V
> Icctyp           10uA                            10mA
> IccMAX       <500uA                      <200mA
>
> Icc numbers are Static, ie represent standby power levels.
> FPGA of similar core Vcc is chosen, and smallest IIe device is chosen
> to avoid too much die-area skew effect.
> -jg
>
>
>

Hi Jim,
    I haven't used this Philips part but, just so I know you're not
comparing apple and oranges,  this Philips part supports upteen different
I/O standards? From 3.3V LVTTL to 2.5V LVDS at 622M?
            cheers, Syms



Article: 63523
(removed)


Article: 63524
Subject: ANN: Tyd-IP Code Generator ....VHDL for DSP
From: "Michael Gallen" <gallenm@tiscali.co.uk>
Date: Tue, 25 Nov 2003 00:09:19 -0000
Links: << >>  << T >>  << A >>
Hi,

Tyder has just released Tyd-IP Code Generator. This software produces
synthesisable VHDL for digital filters, FFTs and
Inverse FFTs. This software builds upon the success of the ONEoverT Digital
Filter Designer package. No longer are you
required to use 'black box' IP solutions, these applications produce
synthesizable, fully commented, easily readable VHDL 93
for use in your designs. The code can then be added to your IP code library
for future use.

For further information, software demo downloads, and design case studies,
visit our website at :
www.tyder.com


Michael Gallen
Tyder Ltd






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