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Threads Starting Apr 2006

100004: 06/04/01: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Modular Design and Incremental Design in ISE
100013: 06/04/01: smu: Xilinx SelectMAP problem
    100048: 06/04/02: jenze: Re: Xilinx SelectMAP problem
        100050: 06/04/02: smu: Re: Xilinx SelectMAP problem
    100073: 06/04/03: jenze: Re: Xilinx SelectMAP problem
100069: 06/04/02: Fizzy: Xilinx Kernel
100078: 06/04/03: <vedpsingh@gmail.com>: Inferring RAM with FOR loop
    100079: 06/04/03: Andy: Re: Inferring RAM with FOR loop
100086: 06/04/03: mughat: Problem erasing EEPROM XCF08P
    100090: 06/04/03: MM: Re: Problem erasing EEPROM XCF08P
    100112: 06/04/03: Isaac Bosompem: Re: Problem erasing EEPROM XCF08P
        100116: 06/04/04: mughat: Re: Problem erasing EEPROM XCF08P
    100115: 06/04/04: mughat: Re: Problem erasing EEPROM XCF08P
100087: 06/04/03: pinku: virtual slot implementation
100088: 06/04/03: Eli Hughes: Spartan 3E SPI Programming
    100089: 06/04/03: Antti: Re: Spartan 3E SPI Programming
        100092: 06/04/03: Eli Hughes: Re: Spartan 3E SPI Programming
    100098: 06/04/03: Antti: Re: Spartan 3E SPI Programming
100095: 06/04/03: Roger Bourne: Looking for chebychev equation
    100100: 06/04/03: robert bristow-johnson: Re: Looking for chebychev equation
    100101: 06/04/03: robert bristow-johnson: Re: Looking for chebychev equation
    100109: 06/04/03: Roger Bourne: Re: Looking for chebychev equation
    100113: 06/04/03: robert bristow-johnson: Re: Looking for chebychev equation
    100145: 06/04/04: Roger Bourne: Re: Looking for chebychev equation
    100151: 06/04/04: robert bristow-johnson: Re: Looking for chebychev equation
    100201: 06/04/05: Rune Allnor: Re: Looking for chebychev equation
100097: 06/04/03: John_H: Spartan3E data sheets
    100121: 06/04/04: RobJ: Re: Spartan3E data sheets
100102: 06/04/03: Brac: Virtex-4 readback via ICAP
    100117: 06/04/03: Paul Hartke: Re: Virtex-4 readback via ICAP
    100218: 06/04/05: Stephen Craven: Re: Virtex-4 readback via ICAP
        100220: 06/04/05: Austin Lesea: Re: Virtex-4 readback via ICAP
            100232: 06/04/05: Austin Lesea: Re: Virtex-4 readback via ICAP
    100224: 06/04/05: Stephen Craven: Re: Virtex-4 readback via ICAP
100103: 06/04/03: <prakash.na@gmail.com>: embedded design prototyping
    100134: 06/04/04: Rene Tschaggelar: Re: embedded design prototyping
100107: 06/04/03: <louis.dupont@gmail.com>: DMA with EDK
    100205: 06/04/05: Guru: Re: DMA with EDK
100108: 06/04/03: Lauri Ehrenpreis: Xilinx XST incremental synthesis tooo slow
100111: 06/04/03: shereen.ahmed: why the best code are the random codes ?
    100615: 06/04/13: Kolja Sulimma: Re: why the best code are the random codes ?
100114: 06/04/04: Jim Granville: Want HiSpeed USB on your FPGA ?
    100120: 06/04/03: <fpga_toys@yahoo.com>: Re: Want HiSpeed USB on your FPGA ?
100123: 06/04/04: Jeff Shafer: Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
    100163: 06/04/04: Joseph: Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
        100180: 06/04/04: Jeff Shafer: Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
100125: 06/04/03: prakash.na@gmail.com: xilinx xc2vp30
    100332: 06/04/07: manu: Re: xilinx xc2vp30
100126: 06/04/04: Andreas Ehliar: Cheap Spartan 3 PCI express starter kit
    100127: 06/04/04: Ian Muncaster: Re: Cheap Spartan 3 PCI express starter kit
        100132: 06/04/04: Ian Muncaster: Re: Cheap Spartan 3 PCI express starter kit
    100129: 06/04/04: Antti: Re: Cheap Spartan 3 PCI express starter kit
100130: 06/04/04: Morten Leikvoll: How fast is YOUR ise8.1?
    100131: 06/04/04: Morten Leikvoll: Re: How fast is YOUR ise8.1?
    100137: 06/04/04: John Adair: Re: How fast is YOUR ise8.1?
        100138: 06/04/04: Morten Leikvoll: Re: How fast is YOUR ise8.1?
100139: 06/04/04: Antti: xilinx legacy input error
100142: 06/04/04: Paul Lee: XUPV2P
    100155: 06/04/04: Paul Hartke: Re: XUPV2P
100143: 06/04/04: bjzhangwn: about the low power design
    100152: 06/04/04: Rene Tschaggelar: Re: about the low power design
    100165: 06/04/04: Ben Twijnstra: Re: about the low power design
    100175: 06/04/04: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: about the low power design
    100176: 06/04/04: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: about the low power design
    100181: 06/04/04: bjzhangwn: Re: about the low power design
    100185: 06/04/04: Paul Leventis: Re: about the low power design
    100186: 06/04/04: Paul Leventis: Re: about the low power design
    100213: 06/04/05: Gabor: Re: about the low power design
    100467: 06/04/10: bjzhangwn: Re: about the low power design
100146: 06/04/04: Eli Hughes: System Ace
100149: 06/04/04: Mich: HDL Options @ EDK
100154: 06/04/04: Phil Tomson: ISE under 64-bit Linux?
    100156: 06/04/04: Josh Rosen: Re: ISE under 64-bit Linux?
    100167: 06/04/04: Eric Smith: Re: ISE under 64-bit Linux?
        100179: 06/04/05: Phil Tomson: Re: ISE under 64-bit Linux?
            100272: 06/04/05: Eric Smith: Re: ISE under 64-bit Linux?
100157: 06/04/04: lecroy7200@chek.com: Altera Stratix II GX LVDS max speed
    100174: 06/04/04: KJ: Re: Altera Stratix II GX LVDS max speed
    100188: 06/04/04: Paul Leventis: Re: Altera Stratix II GX LVDS max speed
        100228: 06/04/05: Mike Treseler: Re: Altera Stratix II GX LVDS max speed
    100216: 06/04/05: lecroy7200@chek.com: Re: Altera Stratix II GX LVDS max speed
    100240: 06/04/05: Paul Leventis: Re: Altera Stratix II GX LVDS max speed
    100290: 06/04/06: lecroy7200@chek.com: Re: Altera Stratix II GX LVDS max speed
    100566: 06/04/12: lecroy7200@chek.com: Re: Altera Stratix II GX LVDS max speed
    101041: 06/04/24: <chrisawest@gmail.com>: Re: Altera Stratix II GX LVDS max speed
100159: 06/04/04: Maki: Lattice ispLever Starter Download
    100214: 06/04/05: Gabor: Re: Lattice ispLever Starter Download
    100235: 06/04/05: Maki: Re: Lattice ispLever Starter Download
100161: 06/04/04: Ira Thorpe: Streamlining FIRs in System Generator
    100190: 06/04/04: PeterC: Re: Streamlining FIRs in System Generator
    100342: 06/04/06: Jeff Cunningham: Re: Streamlining FIRs in System Generator
100166: 06/04/04: Craig Yarbrough: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
    100168: 06/04/04: John_H: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
    100169: 06/04/05: Jim Granville: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
    100170: 06/04/04: Austin Lesea: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
        100178: 06/04/05: Jim Granville: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
            100183: 06/04/04: Austin Lesea: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
            100256: 06/04/06: Jim Granville: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
                100257: 06/04/05: Austin Lesea: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
                    100259: 06/04/06: Jim Granville: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan3
                        100299: 06/04/06: Austin Lesea: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan3
        100182: 06/04/04: Austin Lesea: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
            100194: 06/04/05: Allan Herriman: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
    100172: 06/04/04: Craig Yarbrough: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
    100173: 06/04/04: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
    100177: 06/04/04: Craig Yarbrough: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
    100189: 06/04/04: PeterC: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
    100196: 06/04/04: PeterC: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
    100208: 06/04/05: Brian Davis: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
    100241: 06/04/05: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
    100261: 06/04/05: PeterC: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
    100302: 06/04/06: Brian Davis: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
    100454: 06/04/09: PeterC: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
100171: 06/04/05: Jeremy Stringer: Source-synchronous IO constraints in Synplify
100184: 06/04/04: PeterC: Dual-edge synthesizable D flip-flop - any pitfalls?
    100191: 06/04/04: Mike Treseler: Re: Dual-edge synthesizable D flip-flop - any pitfalls?
    100192: 06/04/04: Bob Perlman: Re: Dual-edge synthesizable D flip-flop - any pitfalls?
        100250: 06/04/05: Ralf Hildebrandt: Re: Dual-edge synthesizable D flip-flop - any pitfalls?
    100212: 06/04/05: Gabor: Re: Dual-edge synthesizable D flip-flop - any pitfalls?
100193: 06/04/04: <fpga_toys@yahoo.com>: interesting note -- altera C to hardware :)
    100197: 06/04/05: Jim Granville: Re: interesting note -- altera C to hardware :)
    100199: 06/04/04: <fpga_toys@yahoo.com>: Re: interesting note -- altera C to hardware :)
    100253: 06/04/05: <fpga_toys@yahoo.com>: Re: interesting note -- altera C to hardware :)
100195: 06/04/04: ahakan: done pin didn't go high
    100206: 06/04/05: Guru: Re: done pin didn't go high
        100209: 06/04/05: ahakan: Re: done pin didn't go high
            100277: 06/04/06: Zara: Re: done pin didn't go high
                101750: 06/05/05: Andrew Lohbihler: Re: done pin didn't go high
    100275: 06/04/05: <ghelbig@lycos.com>: Re: done pin didn't go high
    100305: 06/04/06: <kevinjwhite@comcast.net>: Re: done pin didn't go high
100198: 06/04/05: sjulhes: max lvds IO speed on V2Pro
    100222: 06/04/05: Austin Lesea: Re: max lvds IO speed on V2Pro
100200: 06/04/05: Sylvain Munaut <SomeOne@SomeDomain.com>: Xilinx java application freeze
    100202: 06/04/05: Ben Jones: Re: Xilinx java application freeze
        100211: 06/04/05: Ben Jones: Re: Xilinx java application freeze
            100322: 06/04/06: Salil Raje: Re: Xilinx java application freeze
                100406: 06/04/08: Sylvain Munaut: Re: Xilinx java application freeze
    100207: 06/04/05: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Xilinx java application freeze
100204: 06/04/05: <si007us@yahoo.com>: XAPP264 OPB slave peripherals using Syustem Generator - help
100210: 06/04/05: Julien Lochen: I2C bus controller Implementation
    100223: 06/04/05: Antti: Re: I2C bus controller Implementation
100215: 06/04/05: ALuPin@web.de: Compressing DVI stream
    100227: 06/04/05: Brannon: Re: Compressing DVI stream
    100231: 06/04/05: John_H: Re: Compressing DVI stream
    100234: 06/04/05: Thomas Womack: Re: Compressing DVI stream
    100268: 06/04/06: Andy Ray: Re: Compressing DVI stream
    100276: 06/04/05: Eric Smith: Re: Compressing DVI stream
    100280: 06/04/06: ALuPin@web.de: Re: Compressing DVI stream
100219: 06/04/05: chakra: EDK7.1 - error in Libgen for Linux OS - Xilinx ML300 board
    100225: 06/04/05: Anonymous: Re: EDK7.1 - error in Libgen for Linux OS - Xilinx ML300 board
    100226: 06/04/05: chakra: Re: EDK7.1 - error in Libgen for Linux OS - Xilinx ML300 board
100221: 06/04/05: Milind: Delay value for FDDRCPE in Virtex-II Pro FGPA
    100230: 06/04/05: John_H: Re: Delay value for FDDRCPE in Virtex-II Pro FGPA
    100270: 06/04/05: Milind: Re: Delay value for FDDRCPE in Virtex-II Pro FGPA
    100281: 06/04/06: Milind: Re: Delay value for FDDRCPE in Virtex-II Pro FGPA
100229: 06/04/05: <already5chosen@yahoo.com>: burstcount support in Quartus SOPC Component Editor
100233: 06/04/05: <praviendre@hotmail.com>: seq and comb modules of the FPGA, pls HELP me out !!
100236: 06/04/05: Fizzy: Data Validity and Freshness
    100246: 06/04/05: Fizzy: Re: Data Validity and Freshness
100237: 06/04/05: prakash.na@gmail.com: opensource vs commercial
100238: 06/04/05: prakash.na@gmail.com: design flow xilinx ise 7.1+synplify pro8.4
100242: 06/04/05: John_H: LVDS in Cyclone-II
    100244: 06/04/05: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: LVDS in Cyclone-II
        100249: 06/04/05: John_H: Re: LVDS in Cyclone-II
            100274: 06/04/06: John_H: Re: LVDS in Cyclone-II
                100383: 06/04/07: John_H: Re: LVDS in Spartan-3E
    100264: 06/04/05: Brian Davis: Re: LVDS in Cyclone-II
    100266: 06/04/06: Jim Granville: Re: LVDS in Cyclone-II
        100273: 06/04/06: John_H: Re: LVDS in Cyclone-II
            100279: 06/04/06: Jim Granville: Re: LVDS in Cyclone-II
    100336: 06/04/06: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: LVDS in Cyclone-II (or in Spartan-3E)
    100372: 06/04/07: Brian Davis: Re: LVDS in Cyclone-II (or in Spartan-3E)
    100396: 06/04/07: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: LVDS in Cyclone-II (or in Spartan-3E)
    100465: 06/04/10: Brian Davis: Re: LVDS in Cyclone-II (or in Spartan-3E)
100243: 06/04/05: Jeff Brower: initializing arrays with Verilog and XST
    100247: 06/04/05: John_H: Re: initializing arrays with Verilog and XST
    100260: 06/04/05: Jeff Brower: Re: initializing arrays with Verilog and XST
    100267: 06/04/05: vssumesh: Re: initializing arrays with Verilog and XST
    100271: 06/04/05: Jeff Brower: Re: initializing arrays with Verilog and XST
100245: 06/04/05: simon.stockton@baesystems.com: RocketIO MGT Clocking Arrangement!
    100312: 06/04/06: Helmut: Re: RocketIO MGT Clocking Arrangement!
    100354: 06/04/07: simon.stockton@baesystems.com: Re: RocketIO MGT Clocking Arrangement!
100248: 06/04/05: Subhasri krishnan: Difference in output between testbench and chipscope
    100283: 06/04/06: ALuPin@web.de: Re: Difference in output between testbench and chipscope
    100296: 06/04/06: Subhasri krishnan: Re: Difference in output between testbench and chipscope
    100348: 06/04/07: ALuPin@web.de: Re: Difference in output between testbench and chipscope
100269: 06/04/05: Eric: audio codec on the virtex-ii pro board
100282: 06/04/06: Rohit Tandon: Inferring SRL in Xilinx FPGA
    100286: 06/04/06: Ben Jones: Re: Inferring SRL in Xilinx FPGA
        100373: 06/04/07: Ben Jones: Re: Inferring SRL in Xilinx FPGA
    100288: 06/04/06: Marc Randolph: Re: Inferring SRL in Xilinx FPGA
    100293: 06/04/06: Rohit Tandon: Re: Inferring SRL in Xilinx FPGA
    100365: 06/04/07: Marc Randolph: Re: Inferring SRL in Xilinx FPGA
100287: 06/04/06: raphael: ddr in virtex2
    100303: 06/04/06: Duane Clark: Re: ddr in virtex2
100289: 06/04/06: Marc Randolph: Re: LVDS in Cyclone-II
100292: 06/04/06: <MikeShepherd564@btinternet.com>: Bizarre behaviour by Quartus?
    100294: 06/04/06: Mike Treseler: Re: Bizarre behaviour by Quartus?
        100298: 06/04/06: <MikeShepherd564@btinternet.com>: Re: Bizarre behaviour by Quartus?
        100316: 06/04/06: mk: Re: Bizarre behaviour by Quartus?
            100320: 06/04/06: Mike Treseler: Re: Bizarre behaviour by Quartus?
                100321: 06/04/06: mk: Re: Bizarre behaviour by Quartus?
                100331: 06/04/07: Jim Granville: Re: Bizarre behaviour by Quartus?
    100295: 06/04/06: Thomas Entner: Re: Bizarre behaviour by Quartus?
    100315: 06/04/06: mk: Re: Bizarre behaviour by Quartus?
        100329: 06/04/06: <MikeShepherd564@btinternet.com>: Re: Bizarre behaviour by Quartus?
            100340: 06/04/06: Ray Andraka: Re: Bizarre behaviour by Quartus?
100297: 06/04/06: Arlet: Xst warning, dangling RAMB16B output
    100388: 06/04/07: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Xst warning, dangling RAMB16B output
100300: 06/04/06: lecroy7200@chek.com: Altera Talkback
    100317: 06/04/06: Mike Treseler: Re: Altera Talkback
    100347: 06/04/06: Dave Greenfield: Re: Altera Talkback
100309: 06/04/06: Paul Lee: XUPv"P DDR failure log
    100313: 06/04/06: Eli Hughes: Re: XUPv"P DDR failure log
    100374: 06/04/07: Paul Lee: Re: XUPv"P DDR failure log
100310: 06/04/06: David: Virtex-4 Gigabit Ethernet design
    100325: 06/04/06: Guru: Re: Virtex-4 Gigabit Ethernet design
    100335: 06/04/07: Sylvain Munaut: Re: Virtex-4 Gigabit Ethernet design
    100346: 06/04/07: Marco T.: Re: Virtex-4 Gigabit Ethernet design
    100357: 06/04/07: <v_mirgorodsky@yahoo.com>: Re: Virtex-4 Gigabit Ethernet design
    100881: 06/04/20: David Quiñones: Re: Virtex-4 Gigabit Ethernet design
    101001: 06/04/24: David Quiñones: Re: Virtex-4 Gigabit Ethernet design
    101004: 06/04/24: David Quiñones: Re: Virtex-4 Gigabit Ethernet design
    101559: 06/05/03: David: Re: Virtex-4 Gigabit Ethernet design
    101642: 06/05/04: David Q.: Re: Virtex-4 Gigabit Ethernet design
    103290: 06/05/30: David Q.: Re: Virtex-4 Gigabit Ethernet design
100319: 06/04/06: <aiiadict@gmail.com>: gameboy camera to FPGA
    100339: 06/04/06: Ben Jackson: Re: gameboy camera to FPGA
        100341: 06/04/06: Ben Jackson: Re: gameboy camera to FPGA
100326: 06/04/06: Guru: OPB master
    100337: 06/04/07: manu: Re: OPB master
    100351: 06/04/07: John Adair: Re: OPB master
        100361: 06/04/07: Zara: Re: OPB master
        100362: 06/04/07: John Adair: Re: OPB master
            100366: 06/04/07: Sylvain Munaut: Re: OPB master
    100355: 06/04/07: Guru: Re: OPB master
    100358: 06/04/07: Guru: Re: OPB master
    100363: 06/04/07: Guru: Re: OPB master
100328: 06/04/06: Roger Bourne: rather simple gsr Q
    100334: 06/04/06: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: rather simple gsr Q
        100501: 06/04/10: Brian Philofsky: Re: rather simple gsr Q
    100338: 06/04/06: Roger Bourne: Re: rather simple gsr Q
    100371: 06/04/07: Roger Bourne: Re: rather simple gsr Q
    100378: 06/04/07: Roger Bourne: Re: rather simple gsr Q
    100387: 06/04/07: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: rather simple gsr Q
    100390: 06/04/07: Roger Bourne: Re: rather simple gsr Q
    100395: 06/04/07: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: rather simple gsr Q
    100397: 06/04/07: Roger Bourne: Re: rather simple gsr Q
    100503: 06/04/10: Roger Bourne: Re: rather simple gsr Q
100343: 06/04/06: <sachink321@gmail.com>: Accessing compact flash?????????
    100345: 06/04/07: John Williams: Re: Accessing compact flash?????????
    100376: 06/04/07: Eli Hughes: Re: Accessing compact flash?????????
        100380: 06/04/07: Jan Panteltje: Re: Accessing compact flash?????????
100344: 06/04/06: <sachink321@gmail.com>: C H S in a Compact flash
    100356: 06/04/07: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: C H S in a Compact flash
    100370: 06/04/07: Ray Andraka: Re: C H S in a Compact flash
100360: 06/04/07: <zhangxun0501@gmail.com>: one question for a error of map
100364: 06/04/07: amit: shared BRAM between PPC and FPGA fabric
    100418: 06/04/08: Joseph: Re: shared BRAM between PPC and FPGA fabric
    100430: 06/04/08: MM: Re: shared BRAM between PPC and FPGA fabric
100368: 06/04/07: <kulkarku@math.net>: what is architectural diffrence between block ram & distributed ram?
    100375: 06/04/07: John_H: Re: what is architectural diffrence between block ram & distributed
100369: 06/04/07: Ray Andraka: Re: Accessing compact flash?????????
    100410: 06/04/08: Ray Andraka: Re: Accessing compact flash?????????
        100453: 06/04/09: Ray Andraka: Re: Accessing compact flash?????????
100384: 06/04/07: Amal: Infer dual-clock block RAM for Xilinx
    100385: 06/04/07: John_H: Re: Infer dual-clock block RAM for Xilinx
    100386: 06/04/07: Symon: Re: Infer dual-clock block RAM for Xilinx
        100392: 06/04/07: Symon: Re: Infer dual-clock block RAM for Xilinx
        100420: 06/04/08: Mike Treseler: Re: Infer dual-clock block RAM for Xilinx
            100423: 06/04/08: Mike Treseler: Re: Infer dual-clock block RAM for Xilinx
    100391: 06/04/07: Amal: Re: Infer dual-clock block RAM for Xilinx
    100422: 06/04/08: Amal: Re: Infer dual-clock block RAM for Xilinx
100389: 06/04/07: <zhangxun0501@gmail.com>: who know what is the problem
    100398: 06/04/07: Ray Andraka: Re: who know what is the problem
100400: 06/04/07: <sachink321@gmail.com>: Re: Accessing compact flash?????????
100401: 06/04/07: Fizzy: Help needed
    100403: 06/04/07: motty: Re: Help needed
    100419: 06/04/08: Fizzy: Re: Help needed
    100431: 06/04/08: motty: Re: Help needed
100405: 06/04/08: <burn.sir@gmail.com>: FPGA FAQ and the spam problem
    100456: 06/04/10: Jeremy Stringer: Re: FPGA FAQ and the spam problem
    100509: 06/04/10: ziggy: Re: FPGA FAQ and the spam problem
    100565: 06/04/12: Philip Freidin: Re: FPGA FAQ and the spam problem
        100584: 06/04/12: Bob Perlman: Re: FPGA FAQ and the spam problem
    100583: 06/04/12: <burn.sir@gmail.com>: Re: FPGA FAQ and the spam problem
    100601: 06/04/12: Mike Treseler: Re: FPGA FAQ and the spam problem
100407: 06/04/08: <burn.sir@gmail.com>: Why does Synplify add clock buffers?
    100411: 06/04/08: Duane Clark: Re: Why does Synplify add clock buffers?
        100415: 06/04/08: Duane Clark: Re: Why does Synplify add clock buffers?
    100413: 06/04/08: <burn.sir@gmail.com>: Re: Why does Synplify add clock buffers?
    100459: 06/04/10: Alan Myler: Re: Why does Synplify add clock buffers?
100408: 06/04/08: Niels Sandmann: Compiler to FPSLIC
    100414: 06/04/08: Ralf Hildebrandt: Re: Compiler to FPSLIC
        100444: 06/04/09: Niels Sandmann: Re: Compiler to FPSLIC
    100416: 06/04/08: Adam Megacz: Re: Compiler to FPSLIC
        100443: 06/04/09: Niels Sandmann: Re: Compiler to FPSLIC
    100417: 06/04/08: Mike Treseler: Re: Compiler to FPSLIC
        100447: 06/04/09: Niels Sandmann: Re: Compiler to FPSLIC
    100421: 06/04/08: Tim Wescott: Re: Compiler to FPSLIC
        100448: 06/04/10: Niels Sandmann: Re: Compiler to FPSLIC
            100449: 06/04/09: Tim Wescott: Re: Compiler to FPSLIC
            100452: 06/04/10: Jim Granville: Re: Compiler to FPSLIC
    100424: 06/04/09: Jim Granville: Re: Compiler to FPSLIC
        100445: 06/04/09: Niels Sandmann: Re: Compiler to FPSLIC
            100451: 06/04/10: Jim Granville: Re: Compiler to FPSLIC
        100446: 06/04/09: Niels Sandmann: Re: Compiler to FPSLIC
            100450: 06/04/10: Jim Granville: Re: Compiler to FPSLIC
    100471: 06/04/10: <jetmarc@hotmail.com>: Re: Compiler to FPSLIC
        100491: 06/04/10: Adam Megacz: Atmel FPSLIC
        100532: 06/04/11: Adam Megacz: Re: Atmel FPSLIC
    100530: 06/04/11: <jetmarc@hotmail.com>: Re: Atmel FPSLIC
100409: 06/04/08: maxascent: DDR Termination
    100412: 06/04/08: Bob: Re: DDR Termination
100425: 06/04/08: <sachink321@gmail.com>: Re: Accessing compact flash?????????
100426: 06/04/09: Peter Winkler: C-Compiler for free VHDL controller core ?
    100427: 06/04/08: Isaac Bosompem: Re: C-Compiler for free VHDL controller core ?
        100434: 06/04/08: Tommy Thorn: Re: C-Compiler for free VHDL controller core ?
            100439: 06/04/09: Peter Winkler: Re: C-Compiler for free VHDL controller core ?
                100441: 06/04/09: Antti Lukats: Re: C-Compiler for free VHDL controller core ?
                100498: 06/04/10: Ulf Samuelsson: Re: C-Compiler for free VHDL controller core ?
        100442: 06/04/09: Peter Winkler: Re: C-Compiler for free VHDL controller core ?
    100435: 06/04/09: Antti: Re: C-Compiler for free VHDL controller core ?
    100436: 06/04/09: <burn.sir@gmail.com>: Re: C-Compiler for free VHDL controller core ?
        100440: 06/04/09: Antti Lukats: Re: C-Compiler for free VHDL controller core ?
    100461: 06/04/10: Philipp Klaus Krause: Re: C-Compiler for free VHDL controller core ?
    100505: 06/04/10: Peter Winkler: Re: C-Compiler for free VHDL controller core ?
        100507: 06/04/11: Jim Granville: Re: C-Compiler for free VHDL controller core ?
        100549: 06/04/12: Peter Winkler: Re: C-Compiler for free VHDL controller core ?
    100531: 06/04/11: Francesco: Re: C-Compiler for free VHDL controller core ?
100428: 06/04/08: kelvins: asynchronous FIFO design
    100429: 06/04/08: Peter Alfke: Re: asynchronous FIFO design
    100494: 06/04/10: Brian Philofsky: Re: asynchronous FIFO design
    100499: 06/04/10: Peter Alfke: Re: asynchronous FIFO design
100433: 06/04/08: shereen.ahmed: decoding
100455: 06/04/09: Superman: Creating macros
100457: 06/04/09: <bsmithtech@mail.com>: New FPGA Technology Reaches New Heights
100458: 06/04/10: prakash.na@gmail.com: xilinx DCM Timing warning
    100473: 06/04/10: Gabor: Re: xilinx DCM Timing warning
    100477: 06/04/10: Prakash: Re: xilinx DCM Timing warning
100460: 06/04/10: prav: 8:1 MUX implementaion in XILINX and ALTERA
    100469: 06/04/10: Ben Jones: Re: 8:1 MUX implementaion in XILINX and ALTERA
        100480: 06/04/10: Kolja Sulimma: Re: 8:1 MUX implementaion in XILINX and ALTERA
    100662: 06/04/14: Mike Hutton: Re: 8:1 MUX implementaion in XILINX and ALTERA
100462: 06/04/10: Prakash: xilinx JTAG
    100463: 06/04/10: Aurelian Lazarut: Re: xilinx JTAG
        100486: 06/04/10: Aurelian Lazarut: Re: xilinx JTAG
    100470: 06/04/10: Prakash: Re: xilinx JTAG
100464: 06/04/10: Arun: get the data from tranceiver
100466: 06/04/10: hitsx@hit.edu.cn: How to handle the high fanout
    100468: 06/04/10: bjzhangwn: Re: How to handle the high fanout
    100484: 06/04/10: Ralf Hildebrandt: Re: How to handle the high fanout
    100537: 06/04/11: hitsx@hit.edu.cn: Re: How to handle the high fanout
100472: 06/04/10: Prakash: unused pins
    100474: 06/04/10: bjzhangwn: Re: unused pins
    100478: 06/04/10: motty: Re: unused pins
    100479: 06/04/10: Prakash: Re: unused pins
100475: 06/04/10: shereen.ahmed: LDPC
    100476: 06/04/10: Antti: Re: LDPC
100481: 06/04/10: gretzteam: Register Map coding style
100482: 06/04/10: Prakash: location constraint doubt
    100488: 06/04/10: John_H: Re: location constraint doubt
100483: 06/04/10: mikel: ROM resource sharing
    100487: 06/04/10: John_H: Re: ROM resource sharing
        100506: 06/04/10: John_H: Re: ROM resource sharing
    100504: 06/04/10: mikel: Re: ROM resource sharing
100489: 06/04/10: shereen.ahmed: code
100490: 06/04/10: Fizzy: Very basic question
    100493: 06/04/10: John_H: Re: Very basic question
        100522: 06/04/10: Tommy Thorn: Re: Very basic question
    100556: 06/04/11: <kulkarku@math.net>: Re: Very basic question
100492: 06/04/10: Matt Fornero: NTSC video capture
    100495: 06/04/10: Anonymous: Re: NTSC video capture
100496: 06/04/10: nimayshah: Distributed Arithmetic
    100497: 06/04/10: nimayshah: Re: Distributed Arithmetic
    100500: 06/04/10: Peter Alfke: Re: Distributed Arithmetic
    100521: 06/04/10: nimayshah: Re: Distributed Arithmetic
    100529: 06/04/11: Symon: Re: Distributed Arithmetic
    100559: 06/04/12: Nial Stewart: Re: Distributed Arithmetic
100502: 06/04/10: Ira Thorpe: Interfacing to DDS v5.0 in System Generator
100508: 06/04/10: Jeff Brower: Configuration Rate with multiple .bit files
    100510: 06/04/10: Alan Nishioka: Re: Configuration Rate with multiple .bit files
        100517: 06/04/11: Jim Granville: Re: Configuration Rate with multiple .bit files
            100518: 06/04/11: Jim Granville: Re: Configuration Rate with multiple .bit files
    100512: 06/04/10: Jeff Brower: Re: Configuration Rate with multiple .bit files
    100515: 06/04/10: Alan Nishioka: Re: Configuration Rate with multiple .bit files
    100524: 06/04/10: Jeff Brower: Re: Configuration Rate with multiple .bit files
100511: 06/04/10: Jon: Simulating TFT core in EDK
    100514: 06/04/10: johnp: Re: Simulating TFT core in EDK
    100516: 06/04/10: Jon: Re: Simulating TFT core in EDK
100513: 06/04/10: <ace.shikha@gmail.com>: reading vhdl files
    100541: 06/04/11: John_H: Re: reading vhdl files
100519: 06/04/10: <shawnn@gmail.com>: very slow pull-up with CPLD design
    100520: 06/04/11: Jim Granville: Re: very slow pull-up with CPLD design
        100553: 06/04/11: Daniel Lang: Re: very slow pull-up with CPLD design
100523: 06/04/10: ssirowy@gmail.com: Area Constraints in Xilinx
    100540: 06/04/11: John_H: Re: Area Constraints in Xilinx
100525: 06/04/10: <tonerchips@hotmail.com>: want technical assistance in making toner chips
    100539: 06/04/11: John_H: Re: want technical assistance in making toner chips
        100564: 06/04/12: Symon: Re: want technical assistance in making toner chips
        100843: 06/04/19: <tonerchips@hotmail.com>: Re: want technical assistance in making toner chips
            100849: 06/04/19: John_H: Re: want technical assistance in making toner chips
100526: 06/04/10: vssumesh: To use adder and multiplier of DSP48 in V4
    100528: 06/04/11: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: To use adder and multiplier of DSP48 in V4
    100567: 06/04/12: Ray Andraka: Re: To use adder and multiplier of DSP48 in V4
    100603: 06/04/12: vssumesh: Re: To use adder and multiplier of DSP48 in V4
100527: 06/04/10: Prakash: xilinx XCVU2P-XC2VP30
100533: 06/04/11: bijoy: FPGA : Chip-scope + spartan-3e
100534: 06/04/11: vssumesh: simulation of DCM blocks
    100535: 06/04/11: vssumesh: Re: simulation of DCM blocks
100536: 06/04/11: Roger Bourne: timing constraints ?
    100538: 06/04/11: John_H: Re: timing constraints ?
    100599: 06/04/12: JustJohn: Re: timing constraints ?
        100600: 06/04/12: Bob Perlman: Re: timing constraints ?
    100614: 06/04/13: Roger Bourne: Re: timing constraints ?
100542: 06/04/11: Fizzy: SPI Problem
100543: 06/04/11: jmariano: spartan-3 starter kit board
    100548: 06/04/11: Guru: Re: spartan-3 starter kit board
    100572: 06/04/12: jmariano: Re: spartan-3 starter kit board
100544: 06/04/11: <dhruvakshad@gmail.com>: gemac
100545: 06/04/11: Sander & Stieneke Odekerken: Altera Nios II & PCI Compiler 4.1.0 Question
    100561: 06/04/12: Nial Stewart: Re: Altera Nios II & PCI Compiler 4.1.0 Question
        100575: 06/04/12: Sander & Stieneke Odekerken: Re: Altera Nios II & PCI Compiler 4.1.0 Question
100546: 06/04/11: Ricardo: PCI speed.
    100547: 06/04/11: John_H: Re: PCI speed.
    100562: 06/04/12: Kolja Sulimma: Re: PCI speed.
    100563: 06/04/12: Nial Stewart: Re: PCI speed.
    100606: 06/04/13: Ricardo: Re: PCI speed.
    100617: 06/04/13: Brannon: Re: PCI speed.
100550: 06/04/11: Weng Tianxiang: Re: PCI speed.
100552: 06/04/11: Matt Fornero: ISE 7.1 Map Error
100554: 06/04/11: ssirowy@gmail.com: State Machine and Area Estimate Question
    100555: 06/04/12: Jim Granville: Re: State Machine and Area Estimate Question
    100573: 06/04/12: ssirowy@gmail.com: Re: State Machine and Area Estimate Question
100557: 06/04/11: Prakash: xilinx board xupv2p xc2v30 software dev. doubt
100558: 06/04/12: Eric Smith: Spartan 3E Starter Kit is finally here!
    100598: 06/04/12: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan 3E Starter Kit is finally here!
    100613: 06/04/13: radarman: Re: Spartan 3E Starter Kit is finally here!
        100620: 06/04/13: Scott Schlachter: Re: Spartan 3E Starter Kit is finally here!
    100629: 06/04/13: John_H: Re: Spartan 3E Starter Kit is finally here!
100568: 06/04/12: <sachink321@gmail.com>: Print FAT table in a compact flash ??????????
    100580: 06/04/12: Alan Nishioka: Re: Print FAT table in a compact flash ??????????
    100596: 06/04/12: Ray Andraka: Re: Print FAT table in a compact flash ??????????
100569: 06/04/12: John_H: Spartan3E readback, SPI programming
    100570: 06/04/12: Antti: Re: Spartan3E readback, SPI programming
        100574: 06/04/12: John_H: Re: Spartan3E readback, SPI programming
            100579: 06/04/12: John_H: Re: Spartan3E readback, SPI programming
                100586: 06/04/12: John_H: Re: Spartan3E readback, SPI programming
                    100591: 06/04/12: John_H: Re: Spartan3E readback, SPI programming
                        100592: 06/04/12: Antti Lukats: Re: Spartan3E readback, SPI programming
                            100593: 06/04/12: John_H: Re: Spartan3E readback, SPI programming
                                100602: 06/04/13: Antti Lukats: Re: Spartan3E readback, SPI programming
                                    100611: 06/04/13: John_H: Re: Spartan3E readback, SPI programming
                                        100618: 06/04/14: Jim Granville: Re: Spartan3E readback, SPI programming
                100588: 06/04/12: John_H: Re: Spartan3E readback, SPI programming
    100577: 06/04/12: Alan Nishioka: Re: Spartan3E readback, SPI programming
    100581: 06/04/12: Antti: Re: Spartan3E readback, SPI programming
    100582: 06/04/12: Alan Nishioka: Re: Spartan3E readback, SPI programming
    100587: 06/04/12: Antti: Re: Spartan3E readback, SPI programming
    100597: 06/04/12: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan3E readback, SPI programming
    100616: 06/04/13: Antti: Re: Spartan3E readback, SPI programming
100576: 06/04/12: Hendra: Problem with Xilinx FTP
    100578: 06/04/12: Alan Nishioka: Re: Problem with Xilinx FTP
100585: 06/04/12: Scott Willis: vertex II and powerpc core
    100589: 06/04/12: Ed McGettigan: Re: vertex II and powerpc core
        100594: 06/04/12: Austin Lesea: Re: vertex II and powerpc core
    100590: 06/04/12: John_H: Re: virtex II and powerpc core
    100608: 06/04/13: Scott Willis: Re: vertex II and powerpc core
100595: 06/04/12: Eli Billauer: Published Verilog code: Timing improvement and FWFT FIFOs
100604: 06/04/13: maxascent: PCB Stack
    100605: 06/04/13: KJ: Re: PCB Stack
        100607: 06/04/13: maxascent: Re: PCB Stack
            100610: 06/04/13: Rene Tschaggelar: Re: PCB Stack
            100625: 06/04/13: KJ: Re: PCB Stack
                100640: 06/04/14: maxascent: Re: PCB Stack
                    100641: 06/04/14: Kolja Sulimma: Re: PCB Stack
                        100668: 06/04/15: Kolja Sulimma: Re: PCB Stack
                    100643: 06/04/14: John_H: Re: PCB Stack
        100619: 06/04/13: MM: Re: PCB Stack
    100609: 06/04/13: Joseph Samson: Re: PCB Stack
    100612: 06/04/13: John_H: Re: PCB Stack
    100621: 06/04/13: MM: Re: PCB Stack
    100648: 06/04/14: jai.dhar@gmail.com: Re: PCB Stack
    100651: 06/04/14: KJ: Re: PCB Stack
    100667: 06/04/15: jai.dhar@gmail.com: Re: PCB Stack
100622: 06/04/13: MM: RGMII mode on V4 Hard Tri-EMAC core
    100623: 06/04/13: Joseph Samson: Re: RGMII mode on V4 Hard Tri-EMAC core
        100626: 06/04/13: MM: Re: RGMII mode on V4 Hard Tri-EMAC core
            100627: 06/04/13: Joseph Samson: Re: RGMII mode on V4 Hard Tri-EMAC core
                100628: 06/04/13: MM: Re: RGMII mode on V4 Hard Tri-EMAC core
                    100812: 06/04/18: MM: Re: RGMII mode on V4 Hard Tri-EMAC core
                        100854: 06/04/19: MM: Re: RGMII mode on V4 Hard Tri-EMAC core
                100853: 06/04/19: Joseph Samson: Re: RGMII mode on V4 Hard Tri-EMAC core
    100776: 06/04/18: Florian: Re: RGMII mode on V4 Hard Tri-EMAC core
    100830: 06/04/18: Florian: Re: RGMII mode on V4 Hard Tri-EMAC core
    100862: 06/04/19: Florian: Re: RGMII mode on V4 Hard Tri-EMAC core
100624: 06/04/13: lecroy7200@chek.com: Did National cheat with the Virtex 4
    100632: 06/04/13: Austin Lesea: Re: Did National cheat with the Virtex 4? Or are they just smart
        100732: 06/04/17: Austin Lesea: Re: Did National cheat with the Virtex 4? Or are they just smart
            100739: 06/04/17: Austin Lesea: Re: Did National cheat with the Virtex 4? Doesn't look like it....
            100756: 06/04/17: Eric Smith: Re: Did National cheat with the Virtex 4? Or are they just smart engineers?
    100633: 06/04/13: Brian Davis: Re: Did National cheat with the Virtex 4
    100723: 06/04/17: lecroy7200@chek.com: Re: Did National cheat with the Virtex 4
    100724: 06/04/17: lecroy7200@chek.com: Re: Did National cheat with the Virtex 4? Or are they just smart engineers?
    100725: 06/04/17: Brian Davis: Re: Did National cheat with the Virtex 4
    100733: 06/04/17: lecroy7200@chek.com: Re: Did National cheat with the Virtex 4
    100736: 06/04/17: lecroy7200@chek.com: Re: Did National cheat with the Virtex 4? Or are they just smart engineers?
    100743: 06/04/17: lecroy7200@chek.com: Re: Did National cheat with the Virtex 4? Doesn't look like it....
    100758: 06/04/17: Brian Davis: Re: Did National cheat with the Virtex 4
    100766: 06/04/17: lecroy7200@chek.com: Re: Did National cheat with the Virtex 4
100630: 06/04/13: morpheus: ARM Emulator
    100634: 06/04/13: <onyx49@juno.com>: Re: ARM Emulator
    100713: 06/04/17: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: ARM Emulator
100631: 06/04/13: chakra: Problem: Invalid Processor Version Number 0x00000000- EDK-7.1- latest service pack, ML310, bootloop, download bitsream
    100994: 06/04/23: chakra: Re: Problem: Invalid Processor Version Number 0x00000000- EDK-7.1- latest service pack, ML310, bootloop, download bitsream
100635: 06/04/13: John Larkin: humble suggestion for Xilinx
    100636: 06/04/14: John_H: Re: humble suggestion for Xilinx
        100645: 06/04/14: John Larkin: Re: humble suggestion for Xilinx
    100639: 06/04/14: KJ: Re: humble suggestion for Xilinx
        100644: 06/04/14: John Larkin: Re: humble suggestion for Xilinx
    100657: 06/04/15: Jim Granville: Re: humble suggestion for Xilinx
        100663: 06/04/14: John Larkin: Re: humble suggestion for Xilinx
            100665: 06/04/15: Jim Granville: Re: humble suggestion for Xilinx
                100673: 06/04/15: John Larkin: Re: humble suggestion for Xilinx
    100658: 06/04/14: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: humble suggestion for Xilinx
        100659: 06/04/14: John Larkin: Re: humble suggestion for Xilinx
100637: 06/04/14: Marco: PROG_B and JTAG
    100638: 06/04/14: Antti Lukats: Re: PROG_B and JTAG
100646: 06/04/14: kelvins: what wrong of this counter ?
    100700: 06/04/16: kelvins: Re: what wrong of this counter ?
    100704: 06/04/16: Peter Alfke: Re: what wrong of this counter ?
    100734: 06/04/17: kelvins: Re: what wrong of this counter ?
    100738: 06/04/17: Peter Alfke: Re: what wrong of this counter ?
100647: 06/04/14: Gerr: Xilinx USB Platform Cable not working anymore (linux)
    100785: 06/04/18: Andreas Ehliar: Re: Xilinx USB Platform Cable not working anymore (linux)
    100787: 06/04/18: Gerr: Re: Xilinx USB Platform Cable not working anymore (linux)
100649: 06/04/14: rickman: Spartan 3 chips in power up
    100653: 06/04/14: <ghelbig@lycos.com>: Re: Spartan 3 chips in power up
    100655: 06/04/14: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan 3 chips in power up
        100679: 06/04/16: Jim Granville: Re: Spartan 3 chips in power up
        100803: 06/04/18: John_H: Re: Spartan 3 chips in power up
    100672: 06/04/15: rickman: Re: Spartan 3 chips in power up
    100760: 06/04/17: Jeff Brower: Re: Spartan 3 chips in power up
    100761: 06/04/17: Jeff Brower: Re: Spartan 3 chips in power up
    100762: 06/04/17: Peter Alfke: Re: Spartan 3 chips in power up
    100764: 06/04/17: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan 3 chips in power up
    100794: 06/04/18: Jeff Brower: Re: Spartan 3 chips in power up
    100816: 06/04/18: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan 3 chips in power up
    100883: 06/04/20: rickman: Re: Spartan 3 chips in power up
    100891: 06/04/20: rickman: Re: Spartan 3 chips in power up
    100904: 06/04/20: Jeff Brower: Re: Spartan 3 chips in power up
    100933: 06/04/21: rickman: Re: Spartan 3 chips in power up
100652: 06/04/14: <andrewfelch@gmail.com>: Counting bits
    100654: 06/04/14: Brannon: Re: Counting bits
        100669: 06/04/15: Jan Panteltje: Re: Counting bits
        100671: 06/04/15: Sylvain Munaut: Re: Counting bits
            100680: 06/04/16: Kolja Sulimma: Re: Counting bits
    100656: 06/04/14: Jan Panteltje: Re: Counting bits
    100664: 06/04/14: <andrewfelch@gmail.com>: Re: Counting bits
    100666: 06/04/15: <andrewfelch@gmail.com>: Re: Counting bits
    100670: 06/04/15: Kolja Sulimma: Re: Counting bits
    100674: 06/04/15: David M. Palmer: Re: Counting bits
        100686: 06/04/16: news.verizon.net: Re: Counting bits
    100675: 06/04/15: <andrewfelch@gmail.com>: Re: Counting bits
    100716: 06/04/16: <andrewfelch@gmail.com>: Re: Counting bits
    100735: 06/04/17: Michael Hennebry: Re: Counting bits
    100779: 06/04/18: Thomas Womack: Re: Counting bits
    100827: 06/04/18: <andrewfelch@gmail.com>: Re: Counting bits
    100836: 06/04/19: JustJohn: Re: Counting bits
    100867: 06/04/19: Michael Hennebry: Re: Counting bits
    100874: 06/04/19: JustJohn: Front Side Bus, was Re: Counting bits
100660: 06/04/14: Aaron: C# and Spartan 3 Starter Kit
    100661: 06/04/14: Eli Hughes: Re: C# and Spartan 3 Starter Kit
    100872: 06/04/19: radarman: Re: C# and Spartan 3 Starter Kit
100676: 06/04/15: <jaxato@gmail.com>: Where is the xilinx online store gone?
    100677: 06/04/15: Antti Lukats: Re: Where is the xilinx online store gone?
        100682: 06/04/16: Jim Granville: Re: Where is the xilinx online store gone?
            100688: 06/04/16: Alex Gibson: Re: Where is the xilinx online store gone?
            100691: 06/04/16: Alex Gibson: Re: Where is the xilinx online store gone?
            100692: 06/04/16: Antti Lukats: Re: Where is the xilinx online store gone?
                100698: 06/04/16: Mike Treseler: Re: Where is the xilinx online store gone?
                    100699: 06/04/16: Jan Panteltje: Re: Where is the xilinx online store gone?
            100695: 06/04/16: Mike Harrison: Re: Where is the xilinx online store gone?
            101079: 06/04/25: Brian Drummond: Re: Where is the xilinx online store gone?
        100683: 06/04/16: Jim Granville: Re: Where is the xilinx online store gone?
            100684: 06/04/16: Jim Granville: Re: Where is the xilinx online store gone?
            100697: 06/04/16: Mike Treseler: Re: Where is the xilinx online store gone?
    100678: 06/04/15: Peter Alfke: Re: Where is the xilinx online store gone?
    100685: 06/04/15: <jaxato@gmail.com>: Re: Where is the xilinx online store gone?
    100687: 06/04/15: Peter Alfke: Re: Where is the xilinx online store gone?
    100693: 06/04/16: Labo.EKO: Petition about the xilinx online store ?
        100701: 06/04/16: PC: Re: Petition about the xilinx online store ?
            100706: 06/04/16: Antti Lukats: Re: Petition about the xilinx online store ?
                100749: 06/04/17: Jon Elson: Re: Petition about the xilinx online store ?
        100780: 06/04/18: Uwe Bonnes: Re: Petition about the xilinx online store ?
            100781: 06/04/18: Mike Harrison: Re: Petition about the xilinx online store ?
                100808: 06/04/18: PC: Re: Petition about the xilinx online store ?
    100696: 06/04/16: <jaxato@gmail.com>: Re: Petition about the xilinx online store ?
    100707: 06/04/16: <jaxato@gmail.com>: Re: Petition about the xilinx online store ?
    100708: 06/04/16: Labo.EKO: Re: Where is the xilinx online store gone?
        100709: 06/04/16: Labo.EKO: Re: Where is the xilinx online store gone?
            100710: 06/04/16: Antti Lukats: Re: Where is the xilinx online store gone?
                100717: 06/04/17: Antti Lukats: Re: Where is the xilinx online store gone?
                100720: 06/04/17: Kolja Sulimma: Re: Where is the xilinx online store gone?
                    100721: 06/04/17: Mike Harrison: Re: Where is the xilinx online store gone?
                        100722: 06/04/17: Kolja Sulimma: Re: Where is the xilinx online store gone?
                            100755: 06/04/17: Eric Smith: Re: Where is the xilinx online store gone?
                                100782: 06/04/18: Mike Harrison: Re: Where is the xilinx online store gone?
                                100811: 06/04/18: Jon Elson: Re: Where is the xilinx online store gone?
    100711: 06/04/16: Peter Alfke: Re: Where is the xilinx online store gone?
    100768: 06/04/17: <circaeng@hotmail.com>: Re: Where is the xilinx online store gone?
100681: 06/04/16: Ron Baker, Pluralitas!: systemc
    100689: 06/04/16: mk: Re: systemc
        100690: 06/04/16: Ron Baker, Pluralitas!: Re: systemc
            100694: 06/04/16: Hans: Re: systemc
                100702: 06/04/16: Ron Baker, Pluralitas!: Re: systemc
100703: 06/04/16: Yaseen Zaidi: Boolean as port type
100705: 06/04/16: Jeff Brower: XST not inferring distributed RAM
    100714: 06/04/16: JustJohn: Re: XST not inferring distributed RAM
    100728: 06/04/17: Jeff Brower: Re: XST not inferring distributed RAM
100712: 06/04/16: motty: DCM Question
100718: 06/04/17: vssumesh: How to apply timing constrains for large bus
    100726: 06/04/17: vssumesh: Re: How to apply timing constrains for large bus
        100727: 06/04/17: John_H: Re: How to apply timing constrains for large bus
    100765: 06/04/17: vssumesh: Re: How to apply timing constrains for large bus
100719: 06/04/17: maxascent: Virtex II Pro Config
100729: 06/04/17: Superman: INFO: *.XDL file
    100842: 06/04/19: Martin Thompson: Re: INFO: *.XDL file
    100859: 06/04/19: Superman: Re: INFO: *.XDL file
        100888: 06/04/20: Martin Thompson: Re: INFO: *.XDL file
100730: 06/04/17: Marco T.: Which is the best way to measure low frequencies?
    100731: 06/04/17: Jan Panteltje: Re: Which is the best way to measure low frequencies?
    100742: 06/04/17: Peter Alfke: Re: Which is the best way to measure low frequencies?
    100750: 06/04/18: Jim Granville: Re: Which is the best way to measure low frequencies?
    100763: 06/04/17: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Which is the best way to measure low frequencies?
    100772: 06/04/18: Marco T.: Re: Which is the best way to measure low frequencies?
100737: 06/04/17: samiam: PLD610
    100741: 06/04/17: John_H: Re: PLD610
        100744: 06/04/17: samiam: Re: PLD610
            100746: 06/04/17: mk: Re: PLD610
                100754: 06/04/17: samiam: Re: PLD610
            100747: 06/04/17: Mike Treseler: Re: PLD610
            100748: 06/04/18: Jim Granville: Re: PLD610
                100752: 06/04/17: John_H: Re: PLD610
                    100753: 06/04/17: samiam: Re: PLD610
            100757: 06/04/17: Eric Smith: Re: PLD610
                100805: 06/04/18: Stephen Williams: Re: PLD610
                100820: 06/04/18: samiam: Re: PLD610
                    100835: 06/04/19: Jim Granville: Re: PLD610
100740: 06/04/17: PC: FLASH memory VHDL controller
100745: 06/04/17: Carsten: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!
    100751: 06/04/17: John_H: Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!
        100777: 06/04/18: Carsten: Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!
            100789: 06/04/18: John_H: Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!
                100802: 06/04/18: John_H: Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!
    100759: 06/04/17: Eric Smith: Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!
        100778: 06/04/18: Carsten: Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!
100767: 06/04/17: Jeff Brower: comparison with integer
    100795: 06/04/18: Mike Treseler: Re: comparison with integer
    100806: 06/04/18: Jeff Brower: Re: comparison with integer
100769: 06/04/17: Andrew FPGA: Xilinx DCI resistor placement guidelines
    100960: 06/04/21: <mr_dsp@myrealbox.com>: Re: Xilinx DCI resistor placement guidelines
        100964: 06/04/21: Austin Lesea: Re: Xilinx DCI resistor placement guidelines
        100965: 06/04/21: Bob Perlman: Re: Xilinx DCI resistor placement guidelines
            101015: 06/04/24: Austin Lesea: Re: Xilinx DCI resistor placement guidelines
    100995: 06/04/23: Andrew FPGA: Re: Xilinx DCI resistor placement guidelines
    101013: 06/04/24: Andy: Re: Xilinx DCI resistor placement guidelines
100770: 06/04/17: Tommy Thorn: Quartus SignalTap and bus turn around
    100771: 06/04/18: Mark McDougall: Re: Quartus SignalTap and bus turn around
        100775: 06/04/18: Tommy Thorn: Re: Quartus SignalTap and bus turn around
100773: 06/04/18: Thomas Reinemann: How to connect FPGA and =?ISO-8859-15?Q?=B5C?=
    100774: 06/04/18: Mark McDougall: Re: How to connect FPGA and =?ISO-8859-1?Q?=B5C?=
    100796: 06/04/18: Tim Wescott: Re: How to connect FPGA and =?ISO-8859-15?Q?=B5C?=
    100799: 06/04/18: Mike Treseler: Re: How to connect FPGA and =?ISO-8859-15?Q?=B5C?=
100783: 06/04/18: al99999: Virtex 4 Unbonded IOB
100784: 06/04/18: prav: Implementation of cascadable shift register in virtex FPGA
    100788: 06/04/18: Gabor: Re: Implementation of cascadable shift register in virtex FPGA
    100790: 06/04/18: John_H: Re: Implementation of cascadable shift register in virtex FPGA
100786: 06/04/18: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: FPGA + MAC board?
    100793: 06/04/18: Eli Hughes: Re: FPGA + MAC board?
    100800: 06/04/18: damc4: Re: FPGA + MAC board?
    100815: 06/04/18: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: FPGA + MAC board?
    101194: 06/04/27: Fredrik: Re: FPGA + MAC board?
100791: 06/04/18: radarman: Re: PLD610
100792: 06/04/18: Eli Hughes: FPGA + FTDI
    100797: 06/04/18: Mike Harrison: Re: FPGA + FTDI
    100798: 06/04/18: <ammonton@cc.full.stop.helsinki.fi>: Re: FPGA + FTDI
    100813: 06/04/18: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: FPGA + FTDI
    100837: 06/04/19: Guru: Re: FPGA + FTDI
100801: 06/04/18: chinmayshah.edi@googlemail.com: blowfish encryption algorithm
100804: 06/04/18: <ghelbig@lycos.com>: Re: blowfish encryption algorithm
100807: 06/04/18: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: FPGA availability & distribution options.
    100814: 06/04/18: Gregory C. Read: Re: FPGA availability & distribution options.
    100818: 06/04/18: Rene Tschaggelar: Re: FPGA availability & distribution options.
    100832: 06/04/18: Fredrik: Re: FPGA availability & distribution options.
100809: 06/04/18: John: RIO Reference clock oscillator part
100817: 06/04/18: Rene Tschaggelar: MaxPlus2 and the Byteblaster MV
    100819: 06/04/18: Mike Treseler: Re: MaxPlus2 and the Byteblaster MV
    100829: 06/04/18: <chark.chen@gmail.com>: Re: MaxPlus2 and the Byteblaster MV
        100844: 06/04/19: Rene Tschaggelar: Re: MaxPlus2 and the Byteblaster MV
            100851: 06/04/19: Rene Tschaggelar: Re: MaxPlus2 and the Byteblaster MV
    100846: 06/04/19: Lars: Re: MaxPlus2 and the Byteblaster MV
100821: 06/04/19: Sanka Piyaratna: driving high speed ADC using an FPGA
    100823: 06/04/18: John_H: Re: driving high speed ADC using an FPGA
    100825: 06/04/18: Ray Andraka: Re: driving high speed ADC using an FPGA
    100839: 06/04/19: Venkat: Re: driving high speed ADC using an FPGA
        100848: 06/04/19: Sanka Piyaratna: Re: driving high speed ADC using an FPGA
100822: 06/04/18: Ingenrepons: cannot be synthesized, bad synchronous description
100824: 06/04/18: Venkat: Viterbi IP Core
100826: 06/04/18: Ken Reeves: How is the max clock rate of a device fixed?
    100828: 06/04/18: Peter Alfke: Re: How is the max clock rate of a device fixed?
        100840: 06/04/19: Symon: Re: How is the max clock rate of a device fixed?
    100845: 06/04/19: Rene Tschaggelar: Re: How is the max clock rate of a device fixed?
    100857: 06/04/19: John_H: Re: How is the max clock rate of a device fixed?
100831: 06/04/18: Dioptre: Multiple Independent Circuits on a Single FPGA
    100833: 06/04/19: Thomas Stanka: Re: Multiple Independent Circuits on a Single FPGA
    100838: 06/04/19: Venkat: Re: Multiple Independent Circuits on a Single FPGA
    100858: 06/04/19: Brannon: Re: Multiple Independent Circuits on a Single FPGA
    100870: 06/04/19: radarman: Re: Multiple Independent Circuits on a Single FPGA
        100902: 06/04/20: Jon Elson: Re: Multiple Independent Circuits on a Single FPGA
        100906: 06/04/20: John_H: Re: Multiple Independent Circuits on a Single FPGA
        102727: 06/05/19: Falk Salewski: Re: Multiple Independent Circuits on a Single FPGA
            102934: 06/05/23: Ray Andraka: Re: Multiple Independent Circuits on a Single FPGA
    100878: 06/04/20: Thomas Stanka: Re: Multiple Independent Circuits on a Single FPGA
    100887: 06/04/20: radarman: Re: Multiple Independent Circuits on a Single FPGA
    100899: 06/04/20: Kolja Sulimma: Re: Multiple Independent Circuits on a Single FPGA
    100905: 06/04/20: Weng Tianxiang: Re: Multiple Independent Circuits on a Single FPGA
    100915: 06/04/21: Thomas Stanka: Re: Multiple Independent Circuits on a Single FPGA
100834: 06/04/19: <marcobuffa@gmail.com>: incremental synthesis xst ise 8.1
100841: 06/04/19: simon.stockton@baesystems.com: Is there anything fundamentally wrong with this code?
    100847: 06/04/19: Symon: Re: Is there anything fundamentally wrong with this code?
        100865: 06/04/19: Symon: Re: Is there anything fundamentally wrong with this code?
        100882: 06/04/20: KJ: Re: Is there anything fundamentally wrong with this code?
    100861: 06/04/19: simon.stockton@baesystems.com: Re: Is there anything fundamentally wrong with this code?
    100875: 06/04/20: backhus: Re: Is there anything fundamentally wrong with this code?
    100877: 06/04/20: simon.stockton@baesystems.com: Re: Is there anything fundamentally wrong with this code?
    100879: 06/04/20: simon.stockton@baesystems.com: Re: Is there anything fundamentally wrong with this code?
100850: 06/04/19: bjzhangwn: clock mux in spartan2e fpga
    100873: 06/04/19: JustJohn: Re: clock mux in spartan2e fpga
    100886: 06/04/20: bjzhangwn: Re: clock mux in spartan2e fpga
    100901: 06/04/20: Peter Alfke: Re: clock mux in spartan2e fpga
    100903: 06/04/20: JustJohn: Re: clock mux in spartan2e fpga
100852: 06/04/19: Marco T.: Storing Variables into LMB Memory
100855: 06/04/19: Jeff Brower: XST issues with loop code
    100856: 06/04/19: John_H: Re: XST issues with loop code
100860: 06/04/19: <sabatini@tiscali.nl>: Xilinx FPGA status after configuration.
    100863: 06/04/19: John_H: Re: Xilinx FPGA status after configuration.
    100864: 06/04/19: <sabatini@tiscali.nl>: Re: Xilinx FPGA status after configuration.
100866: 06/04/19: Sylvain Munaut: EDK : FSL macros defined by Xilinx are wrong
    100967: 06/04/21: Sylvain Munaut: Re: EDK : FSL macros defined by Xilinx are wrong
        100968: 06/04/21: Austin Lesea: Re: EDK : FSL macros defined by Xilinx are wrong
            100969: 06/04/21: Austin Lesea: Re: EDK : FSL macros defined by Xilinx are wrong
                100977: 06/04/22: Sylvain Munaut: Re: EDK : FSL macros defined by Xilinx are wrong
100868: 06/04/19: Michael Laajanen: XILINX 7.1 EDK Solaris 10
100869: 06/04/19: Peter C. Wallace: XC9500XL Keeper - can it be disabled?
100871: 06/04/19: radarman: =?iso-8859-1?q?Re:_ow_to_connect_FPGA_and_=B5C?=
100876: 06/04/20: Falk Salewski: Reliability CPLD/FPGA vs Microcontroller
    100885: 06/04/20: Mike Treseler: Re: Reliability CPLD/FPGA vs Microcontroller
        100894: 06/04/20: Slurp: Re: Reliability CPLD/FPGA vs Microcontroller
    100900: 06/04/20: Jon Elson: Re: Reliability CPLD/FPGA vs Microcontroller
    100941: 06/04/21: Kolja Sulimma: Re: Reliability CPLD/FPGA vs Microcontroller
        101202: 06/04/27: Falk Salewski: Re: Reliability CPLD/FPGA vs Microcontroller
            101640: 06/05/04: Falk Salewski: Re: Reliability CPLD/FPGA vs Microcontroller
        101605: 06/05/03: Colin Paul Gloster: Re: Reliability CPLD/FPGA vs Microcontroller
    101011: 06/04/24: radarman: Re: Reliability CPLD/FPGA vs Microcontroller
    101586: 06/05/03: Rene Tschaggelar: Re: Reliability CPLD/FPGA vs Microcontroller
100880: 06/04/20: Dolphin: OPB_SPI timing problems
100884: 06/04/20: imp.chris: Xilinx OPB Arbiter
100889: 06/04/20: vssumesh: Synthesizer is creating unwanted global resources
    100892: 06/04/20: Mike Treseler: Re: Synthesizer is creating unwanted global resources
        100912: 06/04/20: Mike Treseler: Re: Synthesizer is creating unwanted global resources
    100909: 06/04/20: vssumesh: Re: Synthesizer is creating unwanted global resources
    100914: 06/04/20: vssumesh: Re: Synthesizer is creating unwanted global resources
    100998: 06/04/23: vssumesh: Re: Synthesizer is creating unwanted global resources
    100999: 06/04/23: Peter Alfke: Re: Synthesizer is creating unwanted global resources
    101003: 06/04/24: vssumesh: Re: Synthesizer is creating unwanted global resources
    101123: 06/04/25: vssumesh: Re: Synthesizer is creating unwanted global resources
100890: 06/04/20: John_H: For those looking for the Spartan3E starter board...
100893: 06/04/20: Stephen Williams: Xilinx PCIe core vs. Icarus Verilog
    100911: 06/04/20: <ghelbig@lycos.com>: Re: Xilinx PCIe core vs. Icarus Verilog
        100913: 06/04/20: Mike Treseler: Re: Xilinx PCIe core vs. Icarus Verilog
100895: 06/04/20: Roger Bourne: fpga space estimate
    100897: 06/04/20: John_H: Re: fpga space estimate
        100950: 06/04/21: Austin Lesea: Re: fpga space estimate
        100955: 06/04/21: John_H: Re: fpga space estimate
            100961: 06/04/21: John_H: Re: fpga space estimate
    100898: 06/04/20: JJ: Re: fpga space estimate
    100946: 06/04/21: Roger Bourne: Re: fpga space estimate
    100956: 06/04/21: Roger Bourne: Re: fpga space estimate
100896: 06/04/20: Weng Tianxiang: An experience with Xilinx 8.1.02i
100907: 06/04/20: Adam Megacz: cheapest board (of any sort) with an Atmel At94k40 FPSLIC on it?
100908: 06/04/20: radarman: Re: Reliability CPLD/FPGA vs Microcontroller
    100921: 06/04/21: Falk Salewski: Re: Reliability CPLD/FPGA vs Microcontroller
    100982: 06/04/22: Kolja Sulimma: Re: Reliability CPLD/FPGA vs Microcontroller
        100987: 06/04/23: Simon Peacock: Re: Reliability CPLD/FPGA vs Microcontroller
100910: 06/04/20: srini: How to trsiate o/p pins?
    100918: 06/04/21: Martin Thompson: Re: How to trsiate o/p pins?
    100935: 06/04/21: Gabor: Re: How to trsiate o/p pins?
100916: 06/04/21: Morten Leikvoll: Editing Spartan3 DCM in FPGA(8.1.03) editor
    100928: 06/04/21: Brian Davis: Re: Editing Spartan3 DCM in FPGA(8.1.03) editor
        100934: 06/04/21: Morten Leikvoll: Re: Editing Spartan3 DCM in FPGA(8.1.03) editor
    100939: 06/04/21: Brian Davis: Re: Editing Spartan3 DCM in FPGA(8.1.03) editor
100917: 06/04/21: <allanca@gmail.com>: Initializing array of BlockRAM instances in verilog
    100937: 06/04/21: Gabor: Re: Initializing array of BlockRAM instances in verilog
    100957: 06/04/21: Allan: Re: Initializing array of BlockRAM instances in verilog
    100963: 06/04/21: Gabor: Re: Initializing array of BlockRAM instances in verilog
    100973: 06/04/21: Allan: Re: Initializing array of BlockRAM instances in verilog
    101106: 06/04/25: Gabor: Re: Initializing array of BlockRAM instances in verilog
100919: 06/04/21: <Chandru.Kundagol@gmail.com>: problem with shift operation
    100923: 06/04/21: Kantha: Re: problem with shift operation
100920: 06/04/21: John Adair: Raggedstone1 and Opencores PCI
100922: 06/04/21: Guru: Re: Virtex-4 Gigabit Ethernet design
100924: 06/04/21: aymmmm@gmail.com: Bluetooth with FPGA?????
    100930: 06/04/21: Marc Randolph: Re: Bluetooth with FPGA?????
    100931: 06/04/21: Mike Harrison: Re: Bluetooth with FPGA?????
    100974: 06/04/21: Eric Smith: Re: Bluetooth with FPGA?????
    101043: 06/04/24: Cristian CIRESSAN: Re: Bluetooth with FPGA?????
100925: 06/04/21: <syshen@nudt.edu.cn>: is Rocket io complaient with IEEE 802.3ae standard
100926: 06/04/21: Fred: Video circle generator
    100927: 06/04/21: Arlet: Re: Video circle generator
    100938: 06/04/21: John_H: Re: Video circle generator
    100940: 06/04/21: Ray Andraka: Re: Video circle generator
    100942: 06/04/21: Ben Jones: Re: Video circle generator
        100981: 06/04/22: Kolja Sulimma: Re: Video circle generator
    100949: 06/04/21: Thomas Womack: Re: Video circle generator
    100992: 06/04/24: Fred: Re: Video circle generator
100929: 06/04/21: aan.woodz@gmail.com: Using another crystal oscillator..
    100936: 06/04/21: rickman: Re: Using another crystal oscillator..
100932: 06/04/21: mohan: XILINX : IBIS model creation
100943: 06/04/21: johnp: Xilinx Map & Physical Synthesis dies...
    100944: 06/04/21: Brannon: Re: Xilinx Map & Physical Synthesis dies...
    100945: 06/04/21: Ben Jones: Re: Xilinx Map & Physical Synthesis dies...
100947: 06/04/21: Brannon: XST duplicate register option does not work
    100962: 06/04/21: Gabor: Re: XST duplicate register option does not work
100948: 06/04/21: freechip: CAM, TCAM in Stratix
    100952: 06/04/21: Austin Lesea: Re: CAM, TCAM in Stratix
    100953: 06/04/21: John_H: Re: CAM, TCAM in Stratix
        101005: 06/04/24: freechip: Re: CAM, TCAM in Stratix
            101008: 06/04/24: freechip: Re: CAM, TCAM in Stratix
            101010: 06/04/24: John_H: Re: CAM, TCAM in Stratix
                101023: 06/04/24: Mike Treseler: Re: CAM, TCAM in Stratix
                    101031: 06/04/24: John_H: Re: CAM, TCAM in Stratix
                        101076: 06/04/25: freechip: Re: CAM, TCAM in Stratix
                            101078: 06/04/25: John_H: Re: CAM, TCAM in Stratix
    101007: 06/04/24: ALuPin@web.de: Re: CAM, TCAM in Stratix
100951: 06/04/21: johnp: More Xilinx S/W problems... ISE won't start
    100954: 06/04/21: johnp: Re: More Xilinx S/W problems... ISE won't start
        100989: 06/04/23: Terry Brown: Re: More Xilinx S/W problems... ISE won't start
    102257: 06/05/12: <briwalk@gmail.com>: Re: More Xilinx S/W problems... ISE won't start
100958: 06/04/21: vssumesh: Why Edge is required to read from Block RAM of V4
    100959: 06/04/21: John_H: Re: Why Edge is required to read from Block RAM of V4
    100975: 06/04/21: Peter Alfke: Re: Why Edge is required to read from Block RAM of V4
    100996: 06/04/23: vssumesh: Re: Why Edge is required to read from Block RAM of V4
    100997: 06/04/23: vssumesh: Re: Why Edge is required to read from Block RAM of V4
100966: 06/04/21: Jeff Brower: XST pre-defined macros
100970: 06/04/21: fpgabuilder: altera async fifo with different read/write port widths?
    100971: 06/04/22: Rob: Re: altera async fifo with different read/write port widths?
100972: 06/04/21: Davy: Tcl used in Modelsim?
    100978: 06/04/22: Hans: Re: Tcl used in Modelsim?
100976: 06/04/21: AnonymousFC4: Re: Microblaze & Linux tools. (repost)
    100980: 06/04/22: Austin Lesea: Re: Microblaze & Linux tools. (repost)
        100983: 06/04/22: AnonymousFC4: Re: Microblaze & Linux tools. (repost)
            100984: 06/04/22: Gob Stopper: Re: Microblaze & Linux tools. (repost)
                100986: 06/04/22: AnonymousFC4: Re: Microblaze & Linux tools. (repost)
            100985: 06/04/22: Austin Lesea: Re: Microblaze & Linux tools. (repost)
            101030: 06/04/24: John_H: Re: Microblaze & Linux tools. (repost)
100979: 06/04/22: motty: Re: Microblaze & Linux tools. (repost)
100988: 06/04/22: Devlin: How to avoid this waring in ISE 8.1?
    101022: 06/04/24: Dave Pollum: Re: How to avoid this waring in ISE 8.1?
    101027: 06/04/24: John_H: Re: How to avoid this waring in ISE 8.1?
        101038: 06/04/24: John_H: Re: How to avoid this waring in ISE 8.1?
            101060: 06/04/25: Zara: Re: How to avoid this waring in ISE 8.1?
    101036: 06/04/24: Dave Pollum: Re: How to avoid this waring in ISE 8.1?
100990: 06/04/23: =?ISO-8859-1?Q?J=FCrgen_B=F6hm?=: ISE 8.1i for Linux ?
    100991: 06/04/23: Dan McDonald: Re: ISE 8.1i for Linux ?
        100993: 06/04/24: Daniel O'Connor: Re: ISE 8.1i for Linux ?
        101147: 06/04/26: Eric Smith: Re: ISE 8.1i for Linux ?
            101159: 06/04/26: Uwe Bonnes: Re: ISE 8.1i for Linux ?
                101265: 06/04/28: Markus Kuhn: Re: ISE 8.1i for Linux ?
                    101482: 06/05/02: Daniel O'Connor: Re: ISE 8.1i for Linux ?
    101035: 06/04/24: Bob Smith: Re: ISE 8.1i for Linux ?
    101119: 06/04/25: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: ISE 8.1i for Linux ?
101000: 06/04/24: Antti: Xilinx EDK 8.1 DDR controller behavior
    101019: 06/04/24: John: Re: Xilinx EDK 8.1 DDR controller behavior
    101020: 06/04/24: Sylvain Munaut: Re: Xilinx EDK 8.1 DDR controller behavior
        101047: 06/04/25: Antti Lukats: Re: Xilinx EDK 8.1 DDR controller behavior
101002: 06/04/24: bachimanchi@gmail.com: regarding memories using megafunction wizard(altera)
    101006: 06/04/24: ALuPin@web.de: Re: regarding memories using megafunction wizard(altera)
    101026: 06/04/24: John_H: Re: regarding memories using megafunction wizard(altera)
101009: 06/04/24: Robin Bruce: comp.arch.reconfig
    101024: 06/04/24: Mike Treseler: Re: comp.arch.reconfig
    101028: 06/04/24: Symon: Re: comp.arch.reconfig
    101040: 06/04/24: Sean Durkin: Re: comp.arch.reconfig
    101050: 06/04/24: <fpga_toys@yahoo.com>: Re: comp.arch.reconfig
    101066: 06/04/25: Robin Bruce: Re: comp.arch.reconfig
    101067: 06/04/25: Robin Bruce: Re: comp.arch.reconfig
    101099: 06/04/25: <fpga_toys@yahoo.com>: Re: comp.arch.reconfig
101012: 06/04/24: Roger Bourne: Xilinx ISE Project Navigator bug
    101014: 06/04/24: Mike Treseler: Re: Xilinx ISE Project Navigator bug
101016: 06/04/24: Eli Hughes: ISE 8.1 Sub module Synthesis
    101017: 06/04/24: Zara: Re: ISE 8.1 Sub module Synthesis
        101054: 06/04/25: Gerhard Hoffmann: Re: ISE 8.1 Sub module Synthesis
            101059: 06/04/25: Zara: Re: ISE 8.1 Sub module Synthesis
101018: 06/04/24: rickman: Spartan 3 documentation confusing...
    101021: 06/04/24: Austin Lesea: Re: Spartan 3 documentation confusing...
        101046: 06/04/24: Austin Lesea: Re: Spartan 3 documentation confusing...
            101057: 06/04/24: Austin Lesea: Re: Spartan 3 documentation confusing...
                101085: 06/04/25: Austin Lesea: Re: Spartan 3 documentation confusing...
                101331: 06/04/29: RobJ: Re: Spartan 3 documentation confusing...
                    101339: 06/04/29: John_H: Re: Spartan 3 documentation confusing...
                        101352: 06/04/29: Austin Lesea: Re: Spartan 3 documentation confusing...
                            101354: 06/04/29: David Brown: Re: Spartan 3 documentation confusing...
    101042: 06/04/24: rickman: Re: Spartan 3 documentation confusing...
    101048: 06/04/25: Antti Lukats: Re: Spartan 3 documentation confusing...
    101055: 06/04/24: rickman: Re: Spartan 3 documentation confusing...
    101073: 06/04/25: rickman: Re: Spartan 3 documentation confusing...
    101117: 06/04/25: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan 3 documentation confusing...
        101381: 06/04/30: Ulf Samuelsson: Re: Spartan 3 documentation confusing...
    101206: 06/04/27: rickman: Re: Spartan 3 documentation confusing...
    101230: 06/04/27: Michael Hennebry: Re: Spartan 3 documentation confusing...
    101264: 06/04/28: rickman: Re: Spartan 3 documentation confusing...
    101369: 06/04/29: Peter Alfke: Re: Spartan 3 documentation confusing...
    101424: 06/04/30: John Larkin: Re: Spartan 3 documentation confusing...
        101449: 06/05/01: Austin Lesea: Spartan 3 documentation confusing...no more
            101510: 06/05/02: John_H: Re: Spartan 3 documentation confusing...no more
            101524: 06/05/02: John_H: Re: Spartan 3 documentation confusing...no more
        101501: 06/05/02: David Brown: Re: Spartan 3 documentation confusing...
    101425: 06/04/30: Peter Alfke: Re: Spartan 3 documentation confusing...
    101438: 06/05/01: rickman: Re: Spartan 3 documentation confusing...
    101521: 06/05/02: rickman: Re: Spartan 3 documentation confusing...no more
101025: 06/04/24: john: Heating problem of the CPLD
    101029: 06/04/24: Austin Lesea: Re: Heating problem of the CPLD
        101034: 06/04/24: Austin Lesea: Re: Heating problem of the CPLD
    101032: 06/04/24: john: Re: Heating problem of the CPLD
    101037: 06/04/24: John_H: Re: Heating problem of the CPLD
    101063: 06/04/25: Rene Tschaggelar: Re: Heating problem of the CPLD
    101118: 06/04/26: Jim Granville: Re: Heating problem of the CPLD
    101128: 06/04/26: KJ: Re: Heating problem of the CPLD
101033: 06/04/24: Fizzy: PLB communication
101039: 06/04/24: <andrewfelch@gmail.com>: Max and Argmax across 1,000 unsigned 10-bit numbers
    101071: 06/04/25: Aurelian Lazarut: Re: Max and Argmax across 1,000 unsigned 10-bit numbers
        101083: 06/04/25: Kolja Sulimma: Re: Max and Argmax across 1,000 unsigned 10-bit numbers
    101081: 06/04/25: <andrewfelch@gmail.com>: Re: Max and Argmax across 1,000 unsigned 10-bit numbers
    101100: 06/04/25: <andrewfelch@gmail.com>: Re: Max and Argmax across 1,000 unsigned 10-bit numbers
101044: 06/04/24: <nkmlists@gmail.com>: vhdl cpu emulator (any interest?)
    101052: 06/04/25: ziggy: Re: vhdl cpu emulator (any interest?)
    101053: 06/04/24: Mike Treseler: Re: vhdl cpu emulator (any interest?)
    101058: 06/04/24: <ghelbig@lycos.com>: Re: vhdl cpu emulator (any interest?)
101045: 06/04/24: potter: XDL router info needed
    101489: 06/05/02: Markus: Re: XDL router info needed
        101530: 06/05/02: Superman: Re: XDL router info needed
101049: 06/04/24: <charles.eddleston@gmail.com>: Xilinx Virtex-4 OCM Usage Issues
    101064: 06/04/25: Andreas Ehliar: Re: Xilinx Virtex-4 OCM Usage Issues
    101089: 06/04/25: charles.eddleston@gmail.com: Re: Xilinx Virtex-4 OCM Usage Issues
    101092: 06/04/25: Ben Jones: Re: Xilinx Virtex-4 OCM Usage Issues
        101195: 06/04/27: Ben Jones: Re: Xilinx Virtex-4 OCM Usage Issues
            101256: 06/04/28: Ben Jones: Re: Xilinx Virtex-4 OCM Usage Issues
            101260: 06/04/28: Brian Drummond: Re: Xilinx Virtex-4 OCM Usage Issues
                101263: 06/04/28: Ben Jones: Re: Xilinx Virtex-4 OCM Usage Issues
                    101350: 06/04/29: Brian Drummond: Re: Xilinx Virtex-4 OCM Usage Issues
            101266: 06/04/28: Andreas Ehliar: Re: Xilinx Virtex-4 OCM Usage Issues
    101105: 06/04/25: charles.eddleston@gmail.com: Re: Xilinx Virtex-4 OCM Usage Issues
    101225: 06/04/27: charles.eddleston@gmail.com: Re: Xilinx Virtex-4 OCM Usage Issues
    101289: 06/04/28: charles.eddleston@gmail.com: Re: Xilinx Virtex-4 OCM Usage Issues
    101518: 06/05/02: charles.eddleston@gmail.com: Re: Xilinx Virtex-4 OCM Usage Issues
101051: 06/04/25: ziggy: Opinions on Viva
    101065: 06/04/25: Kolja Sulimma: Re: Opinions on Viva
        101111: 06/04/25: Ray Andraka: Re: Opinions on Viva
    101098: 06/04/25: c d saunter: Re: Opinions on Viva
101056: 06/04/24: Justin Erickson: Smallest uClinux configuration
    101113: 06/04/26: John Williams: Re: Smallest uClinux configuration
101061: 06/04/24: king: How to avoid lossing channel bonding when using Rocket IO?
    101068: 06/04/25: Symon: Re: How to avoid lossing channel bonding when using Rocket IO?
    101074: 06/04/25: colin: Re: How to avoid lossing channel bonding when using Rocket IO?
        101140: 06/04/26: Ed McGettigan: Re: How to avoid lossing channel bonding when using Rocket IO?
            101284: 06/04/28: Ed McGettigan: Re: How to avoid lossing channel bonding when using Rocket IO?
    101120: 06/04/25: king: Re: How to avoid lossing channel bonding when using Rocket IO?
    101237: 06/04/27: king: Re: How to avoid lossing channel bonding when using Rocket IO?
    101855: 06/05/07: king: Re: How to avoid lossing channel bonding when using Rocket IO?
101062: 06/04/24: <shailbadwaik@gmail.com>: How to get divider in CRC32 , while implementatinh it in VHDL?
    101095: 06/04/25: Mike Treseler: Re: How to get divider in CRC32 , while implementatinh it in VHDL?
101069: 06/04/25: Guru: Re: Virtex-4 Gigabit Ethernet design
101070: 06/04/25: Robin Bruce: FPGA with ASIC FPU units
    101096: 06/04/25: Rene Tschaggelar: Re: FPGA with ASIC FPU units
101072: 06/04/25: Eka From Indonesia: SPARTAN3E SK LCD
    101116: 06/04/25: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: SPARTAN3E SK LCD
101075: 06/04/25: Jerome: Virtex 2 Config Times
    101086: 06/04/25: John_H: Re: Virtex 2 Config Times
    101088: 06/04/25: Austin Lesea: Re: Virtex 2 Config Times
101077: 06/04/25: AAA: VERIFICATION AND TESTPLAN
101080: 06/04/25: oopere: Simulated Quartus II delays are much greater than measured
    101082: 06/04/25: Kolja Sulimma: Re: Simulated Quartus II delays are much greater than measured
        101121: 06/04/26: Jim Granville: Re: Simulated Quartus II delays are much greater than measured
            101132: 06/04/26: Kolja Sulimma: Re: Simulated Quartus II delays are much greater than measured
    101090: 06/04/25: oopere: Re: Simulated Quartus II delays are much greater than measured
    101091: 06/04/25: oopere: Re: Simulated Quartus II delays are much greater than measured
101084: 06/04/25: al99999: Xilinx ML401 Virtex 4 USB Peripheral
101087: 06/04/25: Andrew Greensted: XST Internal error: VHDL constant record support
    101094: 06/04/25: Ben Jones: Re: XST Internal error: VHDL constant record support
        101125: 06/04/26: Andrew Greensted: Re: XST Internal error: VHDL constant record support
            101127: 06/04/26: Ben Jones: Re: XST Internal error: VHDL constant record support
101093: 06/04/25: <dancedynamix@hotmail.com>: clock multiplication
    101097: 06/04/25: Rene Tschaggelar: Re: clock multiplication
        101103: 06/04/25: Rene Tschaggelar: Re: clock multiplication
    101101: 06/04/25: <dancedynamix@hotmail.com>: Re: clock multiplication
    101102: 06/04/25: unfrostedpoptart: Re: clock multiplication
    101107: 06/04/25: <dancedynamix@hotmail.com>: Re: clock multiplication
    101114: 06/04/25: Peter Alfke: Re: clock multiplication
    101115: 06/04/25: John_H: Re: clock multiplication
101104: 06/04/25: bad synchrounous assignment: 116 warnings... successive approximation register using both phases of clock by spliting them
    101109: 06/04/25: Sylvain Munaut: Re: 116 warnings... successive approximation register using both
101108: 06/04/25: johnp: Xilinx Map vs IOB tri-state with clock enable...
    101110: 06/04/25: johnp: Re: Xilinx Map vs IOB tri-state with clock enable...
101112: 06/04/25: chakra: USB slot on Xilinx ML310 board - linux platform
101122: 06/04/26: Jim Granville: Async FPGA ~2GHz
    101124: 06/04/26: Uwe Bonnes: Re: Async FPGA ~2GHz
        101126: 06/04/26: Jim Granville: Re: Async FPGA ~2GHz
            101141: 06/04/26: John_H: Re: Async FPGA ~2GHz
                101145: 06/04/26: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Async FPGA ~2GHz
                    101152: 06/04/26: John_H: Re: Async FPGA ~2GHz
                101185: 06/04/27: Jim Granville: Re: Async FPGA ~2GHz
                    101192: 06/04/27: David Brown: Re: Async FPGA ~2GHz
    101130: 06/04/26: Bevan Weiss: Re: Async FPGA ~2GHz
    101150: 06/04/26: dp: Re: Async FPGA ~2GHz
        101155: 06/04/26: Austin Lesea: Re: Async FPGA ~2GHz
    101151: 06/04/26: Bob Perlman: Re: Async FPGA ~2GHz
        101166: 06/04/26: Eric Smith: Re: Async FPGA ~2GHz
            101172: 06/04/27: Jim Granville: Re: Async FPGA ~2GHz
                101456: 06/05/01: Austin Lesea: Re: Async FPGA ~2GHz
                101469: 06/05/02: Jim Granville: Re: Async FPGA ~2GHz
                    101478: 06/05/02: Jim Granville: Re: Async FPGA ~2GHz
                    101491: 06/05/02: Kolja Sulimma: Re: Async FPGA ~2GHz
            101232: 06/04/27: Eric Smith: Re: Async FPGA ~2GHz
                101253: 06/04/28: Jim Granville: Re: Async FPGA ~2GHz
                    101271: 06/04/28: Symon: Re: Async FPGA ~2GHz
                    101299: 06/04/28: Eric Smith: Re: Async FPGA ~2GHz
                101297: 06/04/28: Eric Smith: Re: Async FPGA ~2GHz
                    101341: 06/04/29: Allan Herriman: Re: Async FPGA ~2GHz
    101153: 06/04/26: <fpga_toys@yahoo.com>: Re: Async FPGA ~2GHz
        101156: 06/04/26: Austin Lesea: Re: Async FPGA ~2GHz
    101158: 06/04/26: <fpga_toys@yahoo.com>: Re: Async FPGA ~2GHz
    101161: 06/04/26: Peter Alfke: Re: Async FPGA ~2GHz
    101162: 06/04/26: <fpga_toys@yahoo.com>: Re: Async FPGA ~2GHz
    101163: 06/04/26: <fpga_toys@yahoo.com>: Re: Async FPGA ~2GHz
    101167: 06/04/26: dp: Re: Async FPGA ~2GHz
    101168: 06/04/26: <fpga_toys@yahoo.com>: Re: Async FPGA ~2GHz
    101169: 06/04/26: <fpga_toys@yahoo.com>: Re: Async FPGA ~2GHz
    101173: 06/04/26: Josh Rosen: Re: Async FPGA ~2GHz
    101174: 06/04/26: <fpga_toys@yahoo.com>: Re: Async FPGA ~2GHz
    101242: 06/04/27: <fpga_toys@yahoo.com>: Re: Async FPGA ~2GHz
    101244: 06/04/27: <fpga_toys@yahoo.com>: Re: Async FPGA ~2GHz
    101250: 06/04/28: <fpga_toys@yahoo.com>: Re: Async FPGA ~2GHz
    101303: 06/04/28: <fpga_toys@yahoo.com>: Re: Async FPGA ~2GHz
    101451: 06/05/01: Jon Beniston: Re: Async FPGA ~2GHz
    101455: 06/05/01: Peter Alfke: Re: Async FPGA ~2GHz
    101459: 06/05/01: mike_la_jolla: Re: Async FPGA ~2GHz
    101471: 06/05/01: Peter Alfke: Re: Async FPGA ~2GHz
    101474: 06/05/01: Jon Beniston: Re: Async FPGA ~2GHz
101129: 06/04/26: Dave: Spartan 3E Starter Board Question
    101139: 06/04/26: John_H: Re: Spartan 3E Starter Board Question
101131: 06/04/26: dp: Re: Async FPGA ~2GHz
    101134: 06/04/26: Austin Lesea: Re: Async FPGA ~2GHz
        101157: 06/04/27: Jim Granville: Re: Async FPGA ~2GHz
            101160: 06/04/26: Austin Lesea: Re: Async FPGA ~2GHz
    101154: 06/04/27: Jim Granville: Re: Async FPGA ~2GHz
101133: 06/04/26: Kolja Sulimma: Virtex-4 MGTPower Distribution
101135: 06/04/26: Roger Bourne: expanding multipliers, problem
    101136: 06/04/26: Roger Bourne: Re: expanding multipliers, problem
    101138: 06/04/26: John_H: Re: expanding multipliers, problem
    101164: 06/04/26: Ray Andraka: Re: expanding multipliers, problem
    101197: 06/04/27: Roger Bourne: Re: expanding multipliers, problem
101137: 06/04/26: bjzhangwn: the problem when I design the udma33 interface
    101191: 06/04/27: =?ISO-8859-1?Q?Michael_Sch=F6berl?=: Re: the problem when I design the udma33 interface
    101196: 06/04/27: bjzhangwn: Re: the problem when I design the udma33 interface
101142: 06/04/26: Fizzy: PLB
101143: 06/04/26: simon.stockton@baesystems.com: What is the best way to clock data in on one clock edge and out on another?
    101146: 06/04/26: KJ: Re: What is the best way to clock data in on one clock edge and out on another?
        101149: 06/04/26: Kolja Sulimma: Re: What is the best way to clock data in on one clock edge and out
    101170: 06/04/26: simon.stockton@baesystems.com: Re: What is the best way to clock data in on one clock edge and out on another?
    101175: 06/04/26: Peter Alfke: Re: What is the best way to clock data in on one clock edge and out on another?
    101181: 06/04/26: Ron: Re: What is the best way to clock data in on one clock edge and out
101144: 06/04/26: Francesco: Picoblaze C Compiler
    101148: 06/04/26: Stephen Williams: Re: Picoblaze C Compiler
        101171: 06/04/26: Mike Harrison: Re: Picoblaze C Compiler
    101176: 06/04/26: bluetooth with FPGA: Re: Picoblaze C Compiler
    101180: 06/04/27: Jim Granville: Re: Picoblaze C Compiler
        101231: 06/04/28: Jim Granville: Re: Picoblaze C Compiler
    101189: 06/04/27: Francesco: Re: Picoblaze C Compiler
    101190: 06/04/27: Francesco: Re: Picoblaze C Compiler
    101346: 06/04/29: electro: Re: Picoblaze C Compiler
    101490: 06/05/02: Francesco: Re: Picoblaze C Compiler
101165: 06/04/26: Rene Tschaggelar: The use of analog switches as level translators
    101178: 06/04/26: <langwadt@ieee.org>: Re: The use of analog switches as level translators
        101179: 06/04/27: Jim Granville: Re: The use of analog switches as level translators
101177: 06/04/26: <karrelsj@gmail.com>: OpenRisc 1200 on a XUP
    101209: 06/04/27: Javier Castillo: Re: OpenRisc 1200 on a XUP
101182: 06/04/26: Yaseen Zaidi: Modelsim Simulation
    101184: 06/04/26: Abs: Re: Modelsim Simulation
101183: 06/04/26: Peter Alfke: Re: Async FPGA ~2GHz
101186: 06/04/26: Peter Alfke: Re: Async FPGA ~2GHz
101187: 06/04/27: Antti: Working Altera Byteblaster compatible design published under GPL
    101188: 06/04/27: Antti: Re: Working Altera USB-Blaster compatible design published under GPL
        101267: 06/04/28: Amontec, Larry: Re: Working Altera USB-Blaster compatible design published under
            101270: 06/04/28: Amontec, Larry: Re: Working Altera USB-Blaster compatible design published under
            101287: 06/04/28: Stephen Williams: Re: Working Altera USB-Blaster compatible design published under
                101321: 06/04/28: Stephen Williams: Re: Working Altera USB-Blaster compatible design published under
                    101327: 06/04/29: Antti Lukats: Re: Working Altera USB-Blaster compatible design published under GPL
                    101329: 06/04/29: Jim Granville: Re: Working Altera USB-Blaster compatible design published underGPL
                        101340: 06/04/29: Antti Lukats: Re: Working Altera USB-Blaster compatible design published underGPL
                            101357: 06/04/29: Eric Smith: Re: Working Altera USB-Blaster compatible design published underGPL
                                101360: 06/04/29: Antti Lukats: Re: Working Altera USB-Blaster compatible design published underGPL
                101433: 06/05/01: Amontec, Larry: Re: Working Altera USB-Blaster compatible design published under
    101269: 06/04/28: Antti: Re: Working Altera USB-Blaster compatible design published under GPL
    101291: 06/04/28: Antti: Re: Working Altera USB-Blaster compatible design published under GPL
    101529: 06/05/02: Antti: Re: Working Altera USB-Blaster compatible design published under GPL
101193: 06/04/27: sjulhes: Xilinx PCI 64/32 bits IP
    101220: 06/04/27: John_H: Re: Xilinx PCI 64/32 bits IP
        101249: 06/04/28: sjulhes: Re: Xilinx PCI 64/32 bits IP
    101234: 06/04/27: Jeff Brower: Re: Xilinx PCI 64/32 bits IP
        101245: 06/04/28: sjulhes: Re: Xilinx PCI 64/32 bits IP
101198: 06/04/27: Roger Bourne: How are constants stored ?
    101199: 06/04/27: Mike Treseler: Re: How are constants stored ?
        101200: 06/04/27: Aurelian Lazarut: Re: How are constants stored ?
    101203: 06/04/27: c d saunter: Re: How are constants stored ?
        101207: 06/04/27: Ben Jones: Re: How are constants stored ?
    101204: 06/04/27: Roger Bourne: Re: How are constants stored ?
        101205: 06/04/27: c d saunter: Re: How are constants stored ?
    101228: 06/04/27: Jon Elson: Re: How are constants stored ?
        101258: 06/04/28: Aurelian Lazarut: Re: How are constants stored ?
            101314: 06/04/29: Simon Peacock: Re: How are constants stored ?
101208: 06/04/27: vssumesh: Synplify is not translating xilinx template for block ram
    101222: 06/04/27: Andy: Re: Synplify is not translating xilinx template for block ram
        101243: 06/04/28: John_H: Re: Synplify is not translating xilinx template for block ram
    101233: 06/04/27: Mike Treseler: Re: Synplify is not translating xilinx template for block ram
    101239: 06/04/27: vssumesh: Re: Synplify is not translating xilinx template for block ram
    101279: 06/04/28: vssumesh: Re: Synplify is not translating xilinx template for block ram
101210: 06/04/27: jimwu88NOOOSPAM@yahoo.com: UCF-mode for Emacs
    101212: 06/04/27: Antti: Re: UCF-mode for Emacs
    101221: 06/04/27: Andy Peters: Re: UCF-mode for Emacs
101211: 06/04/27: Dolphin: Xilinx: Prohibit propagation of timing constraint through a mux
    101213: 06/04/27: Peter Alfke: Re: Xilinx: Prohibit propagation of timing constraint through a mux
        101248: 06/04/28: Dolphin: Re: Xilinx: Prohibit propagation of timing constraint through a mux
    101240: 06/04/27: Jeff Brower: Re: Xilinx: Prohibit propagation of timing constraint through a mux
    101277: 06/04/28: jimwu88NOOOSPAM@yahoo.com: Re: Xilinx: Prohibit propagation of timing constraint through a mux
101214: 06/04/27: <pavithra.eswaran@gmail.com>: LED Driver
    101216: 06/04/27: Antti: Re: LED Driver
    101229: 06/04/28: Jim Granville: Re: LED Driver
        101246: 06/04/28: Kolja Sulimma: Re: LED Driver
            101251: 06/04/28: Jim Granville: Re: LED Driver
    101500: 06/05/02: mohan: Re: LED Driver
    101515: 06/05/02: Peter Alfke: Re: LED Driver
101215: 06/04/27: Peter Alfke: Re: Async FPGA ~2GHz
101217: 06/04/27: Fizzy: CLock Issue
    101218: 06/04/27: Ben Jones: Re: CLock Issue
        101227: 06/04/27: John_H: Re: CLock Issue
    101219: 06/04/27: John_H: Re: CLock Issue
    101223: 06/04/27: Fizzy: Re: CLock Issue
    101226: 06/04/27: Peter Alfke: Re: CLock Issue
    101257: 06/04/28: Kantha: Re: CLock Issue
101224: 06/04/27: Fizzy: System Generator
101235: 06/04/27: <gburx@yahoo.com.au>: Development Platform for begginer
    101238: 06/04/27: dc_rockclimbing: Re: Development Platform for begginer
    101262: 06/04/28: Brian Drummond: Re: Development Platform for begginer
    101281: 06/04/28: <gburx@yahoo.com.au>: Re: Development Platform for begginer
    101296: 06/04/28: Dave Pollum: Re: Development Platform for begginer
101236: 06/04/27: Stephen Williams: Xilinx SystemACE on multi-FPGA board
    101288: 06/04/28: Ed McGettigan: Re: Xilinx SystemACE on multi-FPGA board
        101300: 06/04/28: Stephen Williams: Re: Xilinx SystemACE on multi-FPGA board
            101320: 06/04/28: Ed McGettigan: Re: Xilinx SystemACE on multi-FPGA board
                101325: 06/04/28: Stephen Williams: Re: Xilinx SystemACE on multi-FPGA board
101241: 06/04/27: Jeff Brower: initializing array of registers in XST
    101295: 06/04/28: Dave Pollum: Re: initializing array of registers in XST
    101309: 06/04/28: Brian Dam Pedersen: Re: initializing array of registers in XST
    101312: 06/04/28: Jeff Brower: Re: initializing array of registers in XST
    101315: 06/04/28: Jeff Brower: Re: initializing array of registers in XST
    101318: 06/04/28: Andy: Re: initializing array of registers in XST
101247: 06/04/27: billu: Assigning MGT's in sample Aurora Design
    101254: 06/04/28: colin: Re: Assigning MGT's in sample Aurora Design
    101255: 06/04/28: sjulhes: Re: Assigning MGT's in sample Aurora Design
    101276: 06/04/28: Paul Hartke: Re: Assigning MGT's in sample Aurora Design
101259: 06/04/28: Roland: HSTL classes and termination schemes
    101268: 06/04/28: colin: Re: HSTL classes and termination schemes
    101272: 06/04/28: colin: Re: HSTL classes and termination schemes
101261: 06/04/28: Fabio Rodrigues de la Rocha: Bus macros compatible with ISE 8.1
101273: 06/04/28: <andrew.hood@gmail.com>: Xilinix SPI programming with USB Platform Cable
    101274: 06/04/28: Antti: Re: Xilinix SPI programming with USB Platform Cable
    101278: 06/04/28: Larry: Re: Xilinix SPI programming with USB Platform Cable
        101317: 06/04/29: Jim Granville: Re: Xilinix SPI programming with USB Platform Cable
    101282: 06/04/28: Antti: Re: Xilinix SPI programming with USB Platform Cable
    101319: 06/04/28: Antti: Re: Xilinix SPI programming with USB Platform Cable
101275: 06/04/28: kaps: help me friend
    101498: 06/05/02: mohan: Re: help me friend
101283: 06/04/28: <jaxato@gmail.com>: What would be the tariff classification of an FPGA development board?
    101351: 06/04/29: Rene Tschaggelar: Re: What would be the tariff classification of an FPGA development
        101359: 06/04/29: Philipp Klaus Krause: Re: What would be the tariff classification of an FPGA development
            101366: 06/04/29: Philipp Klaus Krause: Re: What would be the tariff classification of an FPGA development
    101358: 06/04/29: <jaxato@gmail.com>: Re: What would be the tariff classification of an FPGA development board?
    101364: 06/04/29: <jaxato@gmail.com>: Re: What would be the tariff classification of an FPGA development board?
101285: 06/04/28: JJ: Opteron HT coprocessors
    101293: 06/04/28: Rainer Buchty: Re: Opteron HT coprocessors
    101298: 06/04/28: JJ: Re: Opteron HT coprocessors
    101311: 06/04/28: c d saunter: Re: Opteron HT coprocessors
    101337: 06/04/28: JJ: Re: Opteron HT coprocessors
        101356: 06/04/29: c d saunter: Re: Opteron HT coprocessors
            101765: 06/05/05: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Opteron HT coprocessors
                101776: 06/05/06: Thomas Womack: Re: Opteron HT coprocessors
                    101810: 06/05/07: c d saunter: Re: Opteron HT coprocessors
    101795: 06/05/06: JJ: Re: Opteron HT coprocessors
    101879: 06/05/08: Guru: Re: Opteron HT coprocessors
    102104: 06/05/10: JJ: Re: Opteron HT coprocessors
    102129: 06/05/10: Oleg O.: Re: Opteron HT coprocessors
101286: 06/04/28: Lovely Robot: please help me out
    101294: 06/04/28: Dave Pollum: Re: please help me out
101290: 06/04/28: rickman: Pull up resistors on Spartan 3 mode pins
    101292: 06/04/28: Antti: Re: Pull up resistors on Spartan 3 mode pins
        101302: 06/04/28: John_H: Re: Pull up resistors on Spartan 3 mode pins
    101305: 06/04/28: Antti: Re: Pull up resistors on Spartan 3 mode pins
    101313: 06/04/28: Peter Alfke: Re: Pull up resistors on Spartan 3 mode pins
    101322: 06/04/29: Jim Granville: Re: Pull up resistors on Spartan 3 mode pins
        101372: 06/04/30: John_H: Re: Pull up resistors on Spartan 3 mode pins
            101377: 06/04/30: Jim Granville: Re: Pull up resistors on Spartan 3 mode pins
                101387: 06/04/30: Jim Granville: Re: Pull up resistors on Spartan 3 mode pins
                101406: 06/04/30: John_H: Re: Pull up resistors on Spartan 3 mode pins
            101386: 06/04/30: Dave: Re: Pull up resistors on Spartan 3 mode pins
                101388: 06/04/30: Jim Granville: Re: Pull up resistors on Spartan 3 mode pins
            101403: 06/04/30: John_H: Re: Pull up resistors on Spartan 3 mode pins
            101428: 06/05/01: Jim Granville: Re: Pull up resistors on Spartan 3 mode pins
            101432: 06/05/01: RobJ: Re: Pull up resistors on Spartan 3 mode pins
        101392: 06/04/30: nospam: Re: Pull up resistors on Spartan 3 mode pins
    101362: 06/04/29: rickman: Re: Pull up resistors on Spartan 3 mode pins
    101363: 06/04/29: rickman: Re: Pull up resistors on Spartan 3 mode pins
    101368: 06/04/29: Peter Alfke: Re: Pull up resistors on Spartan 3 mode pins
    101373: 06/04/29: Peter Alfke: Re: Pull up resistors on Spartan 3 mode pins
    101376: 06/04/29: John Larkin: Re: Pull up resistors on Spartan 3 mode pins
        101423: 06/04/30: John Larkin: Re: Pull up resistors on Spartan 3 mode pins
    101378: 06/04/29: Peter Alfke: Re: Pull up resistors on Spartan 3 mode pins
    101393: 06/04/30: Leon: Re: Pull up resistors on Spartan 3 mode pins
    101396: 06/04/30: rickman: Re: Pull up resistors on Spartan 3 mode pins
    101416: 06/04/30: Jeff Brower: Re: Pull up resistors on Spartan 3 mode pins
    101419: 06/04/30: Peter Alfke: Re: Pull up resistors on Spartan 3 mode pins
    101426: 06/04/30: rickman: Re: Pull up resistors on Spartan 3 mode pins
    101430: 06/04/30: Peter Alfke: Re: Pull up resistors on Spartan 3 mode pins
101301: 06/04/28: Jan Panteltje: DRC has announced its newest FPGA that drops into AMD's Socket 940
    101304: 06/04/28: <tomstdenis@gmail.com>: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
        101306: 06/04/28: Paul Rubin: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
            101323: 06/04/28: Paul Rubin: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
                101328: 06/04/28: Austin Lesea: Re: DRC has announced its newest FPGA that drops into AMD's Socket
                    101342: 06/04/29: Allan Herriman: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
                    101788: 06/05/07: Piotr Wyderski: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
                        101791: 06/05/06: Eric Smith: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
        101307: 06/04/28: c d saunter: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
            101332: 06/04/28: DJ Delorie: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
            101334: 06/04/28: DJ Delorie: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
            101711: 06/05/05: Rob Warnock: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
    101308: 06/04/28: <tomstdenis@gmail.com>: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
    101310: 06/04/28: <tomstdenis@gmail.com>: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
        101316: 06/04/28: c d saunter: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
    101324: 06/04/28: <tomstdenis@gmail.com>: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
    101333: 06/04/28: JJ: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
    101335: 06/04/28: JJ: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
    101336: 06/04/28: JJ: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
    101727: 06/05/05: <tomstdenis@gmail.com>: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
101326: 06/04/29: Quazar: PCI bridge
101330: 06/04/28: Weng Tianxiang: How to see *.vcd file outported from ChipScope from different computer
    101338: 06/04/28: <ghelbig@lycos.com>: Re: How to see *.vcd file outported from ChipScope from different computer
    101343: 06/04/29: Hans: Re: How to see *.vcd file outported from ChipScope from different computer
    101353: 06/04/29: Weng Tianxiang: Re: How to see *.vcd file outported from ChipScope from different computer
101344: 06/04/29: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: URGENT: Xilinx site
    101345: 06/04/29: Leon: Re: URGENT: Xilinx site
    101347: 06/04/29: Stephen Craven: Re: URGENT: Xilinx site
    101348: 06/04/29: Gabor: Re: URGENT: Xilinx site
    101349: 06/04/29: Peter Alfke: Re: URGENT: Xilinx site
    101390: 06/04/30: Leon: Re: URGENT: Xilinx site
101355: 06/04/29: avishay: Quartus and source control
    101361: 06/04/29: Petter Gustad: Re: Quartus and source control
    101367: 06/04/29: johnp: Re: Quartus and source control
    101370: 06/04/30: Subroto Datta: Re: Quartus and source control
        101484: 06/05/02: Subroto Datta: Re: Quartus and source control
            101502: 06/05/02: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: Quartus and source control
                101506: 06/05/02: David Brown: Re: Quartus and source control
                    101509: 06/05/02: Subroto Datta: Re: Quartus and source control
                        101557: 06/05/03: David Brown: Re: Quartus and source control
                            101680: 06/05/04: Petter Gustad: Re: Quartus and source control
                            101701: 06/05/05: Subroto Datta: Re: Quartus and source control
            101538: 06/05/02: Mike Treseler: Re: Quartus and source control
        101485: 06/05/02: KJ: Re: Quartus and source control
        101746: 06/05/05: Petter Gustad: Re: Quartus and source control
        101906: 06/05/08: Markus Kuhn: Re: Quartus and source control
            103370: 06/05/31: Mike Treseler: Re: Quartus and source control
                103419: 06/06/01: Mike Treseler: Re: Quartus and source control
                103568: 06/06/06: Martin Thompson: Re: Quartus and source control
    101431: 06/04/30: avishay: Re: Quartus and source control
    101483: 06/05/01: Derek Simmons: Re: Quartus and source control
    101531: 06/05/02: Derek Simmons: Re: Quartus and source control
    101651: 06/05/04: avishay: Re: Quartus and source control
    101740: 06/05/05: johnp: Re: Quartus and source control
    103366: 06/05/31: <kevinwolfe@gmail.com>: Re: Quartus and source control
    103378: 06/05/31: toby: Re: Quartus and source control
    103379: 06/05/31: toby: Re: Quartus and source control
    103401: 06/06/01: <kevinwolfe@gmail.com>: Re: Quartus and source control
    103404: 06/06/01: Andy: Re: Quartus and source control
    103561: 06/06/05: <antti.tyrvainen@luukku.com>: Re: Quartus and source control
101365: 06/04/29: tuxfriend: Book Software for XC3190A?
    101371: 06/04/29: Peter Alfke: Re: Book Software for XC3190A?
        101379: 06/04/30: tuxfriend: Re: Book Software for XC3190A?
            101394: 06/04/30: Josh Rosen: Re: Book Software for XC3190A?
                101397: 06/04/30: Phil Hays: Re: Book Software for XC3190A?
                101398: 06/04/30: tuxfriend: Re: Book Software for XC3190A?
                    101473: 06/05/01: Duane Clark: Re: Book Software for XC3190A?
                        101475: 06/05/01: tuxfriend: Re: Book Software for XC3190A?
                        101535: 06/05/02: tuxfriend: Re: Book Software for XC3190A?
                101552: 06/05/02: Ray Andraka: Re: Book Software for XC3190A?
                    101699: 06/05/04: Ray Andraka: Re: Book Software for XC3190A?
            101465: 06/05/01: tuxfriend: Re: Book Software for XC3190A?
                101467: 06/05/01: tuxfriend: Re: Book Software for XC3190A?
                101468: 06/05/01: John_H: Re: Book Software for XC3190A?
    101462: 06/05/01: Dave Pollum: Re: Book Software for XC3190A?
    101645: 06/05/04: Robin Bruce: Re: Book Software for XC3190A?
101374: 06/04/29: Fizzy: Reset
    101375: 06/04/29: Peter Alfke: Re: Reset
    101495: 06/05/02: Jochen: Re: Reset
        101801: 06/05/07: Alif Wahid: Re: Reset
    101534: 06/05/02: Andy: Re: Reset
101380: 06/04/30: Antti Lukats: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101383: 06/04/30: Hans: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
        101395: 06/04/30: Ben Twijnstra: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
            101405: 06/04/30: Antti Lukats: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
                101417: 06/04/30: Ben Twijnstra: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
        101401: 06/04/30: Antti Lukats: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
            101402: 06/04/30: Austin Lesea: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
                101404: 06/04/30: Antti Lukats: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
            101441: 06/05/01: Hans: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
                101444: 06/05/01: Jan Panteltje: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101384: 06/04/30: Jim Granville: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
        101408: 06/04/30: Antti Lukats: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
            101413: 06/05/01: Jim Granville: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101389: 06/04/30: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101463: 06/05/01: Kolja Waschk: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
        101464: 06/05/01: Kolja Waschk: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
            101546: 06/05/02: Kryten: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101493: 06/05/02: Thomas Stanka: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101505: 06/05/02: Josep Durán: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101507: 06/05/02: colin: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101526: 06/05/02: Antti: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101553: 06/05/02: Ray Andraka: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101558: 06/05/02: Tommy Thorn: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101584: 06/05/03: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101382: 06/04/30: maxascent: Xilinx PROM
    101410: 06/04/30: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Xilinx PROM
    101418: 06/04/30: Gabor: Re: Xilinx PROM
    101443: 06/05/01: Antti: Re: Xilinx PROM
101385: 06/04/30: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: ML403 ZBT SRAM
    101479: 06/05/01: Brad Smallridge: Re: ML403 ZBT SRAM
        101585: 06/05/03: Brad Smallridge: Re: ML403 ZBT SRAM
    101494: 06/05/02: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: ML403 ZBT SRAM
    101641: 06/05/04: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: ML403 ZBT SRAM
101391: 06/04/30: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Xilinx MPPR failing
101399: 06/04/30: <harikris@gmail.com>: design optimization
    101400: 06/04/30: Peter Alfke: Re: design optimization
        101407: 06/04/30: Rob: Re: design optimization
            101411: 06/04/30: Kolja Sulimma: Re: design optimization
                101412: 06/04/30: Antti Lukats: Re: design optimization
            101480: 06/05/01: Eric Smith: Re: design optimization
                101486: 06/05/01: David M. Palmer: Re: design optimization
                101496: 06/05/02: Symon: Re: design optimization
                101499: 06/05/02: Kolja Sulimma: Re: design optimization
    101409: 06/04/30: Antti Lukats: Re: design optimization
    101414: 06/05/01: Jim Granville: Re: design optimization
    101421: 06/04/30: <harikris@gmail.com>: Re: design optimization
    101458: 06/05/01: Dave Pollum: Re: design optimization
101415: 06/04/30: motty: OPB Clocking Question
    101566: 06/05/03: Guru: Re: OPB Clocking Question
101420: 06/04/30: jmariano: Microblaze GPIO (basic) question
    101422: 06/04/30: motty: Re: Microblaze GPIO (basic) question
101427: 06/04/30: <ashutoshkaushik@gmail.com>: fpga programming
    101445: 06/05/01: Antti: Re: fpga programming
    101454: 06/05/01: Joseph: Re: fpga programming
    101503: 06/05/02: Aurelian Lazarut: Re: fpga programming


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