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hi all i indent to make chips for toner cartridges ( specially hp ) in singapore i need technical assistance in this regard and willing to pay reasonable amount for technology. kindly let me know if anyone can help thanks tonerchips -- NewsGuy.Com 30Gb $9.95 Carry Forward and On Demand BandwidthArticle: 100526
Hi all, Is it possible to use the adder and multiplier in the DSP48 block of the virtex4 FPGA separately but simultaniously. From the user guide i get a feeling "No" but i wanted to know your expert openion on this issue. Thanks and regards Sumesh V SArticle: 100527
Hi, In my design I want to use the compact flash interface to my processor in FPGA. In the development board ACE controller is in between compact Flash and processor. I think the power PC access the ace controller for all read of Flash. Are there anyways I can make this flash as just memory device (PROM), and access without ACE controller. I'd seen some articles saying usage of flash as non volatile storage but it uses ace controller in between and the EDK supports power PC for interfacing to Ace controller. PrakashArticle: 100528
No ;p The adder is also there to add the two partial products of the multiplier so ... And indeed in the manual it's quite clear there is no way ...Article: 100529
"nimayshah" <nimayshah@gmail.com> wrote in message news:1144693869.452038.114940@z34g2000cwc.googlegroups.com... > I've compared the synthesis reports of my core > with that of xilinx coregen DA FIR V9.0. The area usage is pretty much > the same but the frequency is almost half. Also a stark difference in > the synthesis report is that my core's lut synthesizes into a Block RAM > and the Xilinx core uses nothing like that. > So my questions are: > 1. What does the core use for storing LUT contents? > 2. What can i do for speed optimization? > Please send in your replies as time is running out real fast. > Regards, > Nimay Shah > Hi Nimay, Here's an answer to 2) The BlockRAMs (BRAMS) are slower than the CLB based RAMS. Check out the clock-to-output times for the BRAMs in the data sheet. Tcko. Or something like that. So, use two BRAMs and interleave between them. You could use both ports, but I guess you're using one port for dynamic loading? Cheers, Syms.Article: 100530
> Marc, could you elaborate on this? Typically hold violations are the
> result of a path being too *long* (and, as a result, the signal has not
> propagated and held by the time the clock edge arrives).
>
> Have Atmel's tools PARed your designs in such a way that some paths
> were too long for the clock rate you requested?
Hi Adam,
Atmels timing analyser knows two types of critital paths: long and
short. Long paths are those that you mention. A signal doesn't
propagate fast enough to its destination before the next clock, which
results in a setup violation at the destination.
The tools can be configured to detect this, and to optimize according
to a timing constraints file. After this step, the tools inform you
whether the constraints have been satisfied, and what the maximum
allowed clock speed is.
The other type of critical path is the short path. That means that a
signal races with the clock, and arrives at the destination too early.
This can be caused by a poor clock distribution tree (with a lot of
skew), or by slow flipflops with longish hold requirements. When the
data signal arrives early, the hold time of the destination flipflop is
violated (at all clock speeds).
As with the long paths, the Atmel tools can be configured to detect
short paths. However, it is not possible to optimize for them to go
away. If you have a short path, you are left alone. You can do only
three things:
a) re-run the optimizer. It has a random decision element and produces
a different output on each run. Maybe the short path goes away, or
moves to a different part of your design.
b) change your design to be less efficient, for example by adding
combinatorial logic. Make sure the synthesizer doesn't optimize it
away, though.
c) do manual PAR, or touch-up the PAR output manually. I tried to do
this. But since routing resources saturate quickly even on design with
moderate resource usage, I almost never managed to "repair" a short
path by hand.
I emailed a few times about this with the (excellent) Atmel technical
support, but they had no plans to improve their tools with respect to
the short path problem.
During development (working with just one silicon), I found it most
convenient to implement extensive self-tests and re-run the optimizer
until the test passed. This was the quickest way to make a design work.
Here's a sample timing report of a short path. The design had about
60% resource usage, and there were about 15 similar short paths (with
actual hold violations).
Path #10
Slack = -1.18ns
Type = Flop -> Flop ('rj45_i1_notri_reg_reg_t_plus_1(1) CLK' ->
'rj45_i1_notri_RX_STATUS_FILE/R2_0/$E1 AIN0')
ClockEdge: GCLK5 on SYSCLKBUF_inst ACT
_/ 0.00ns
ClockDelay: SYSCLKBUF_inst ACT -> rj45_i1_notri_RX_STATUS_FILE
CLK _/ 4.69ns
------
Required Arrival Time:
_/ 4.69ns
Clock Edge: GCLK5 on
SYSCLKBUF_inst ACT _/ 0.00ns
Clock Delay: SYSCLKBUF_inst ACT ->
rj45_i1_notri_reg_reg_t_plus_1(1) CLK _/ 4.39ns
Data Path Delay: rj45_i1_notri_reg_reg_t_plus_1(1) CLK ->
rj45_i1_notri_RX_STATUS_FILE/R2_0/$E1 AIN0 _/ 4.22ns
Hold Time: rj45_i1_notri_RX_STATUS_FILE/R2_0/$E1 AIN0
_/ -5.10ns
-------
Actual Arrival Time:
_/ 3.51ns
Regards,
Marc
Article: 100531Peter Winkler wrote: > Thanks for all your input. > > I think it makes most sense for me to have a closer look > at PicoBlaze. > > Is there a good place for PicoBlaze designs apart from the > Xilinx PicoBlaze home ? I mean some kind of community like > avrfreaks or the piclist ? A place to ask stupid newbie > questions, you know ;) > > P. Hi Peter, if you want to use Picoblaze, then why you don't try the free C compiler for Picoblaze? you can download for free on www.poderico.co.uk Next week please check on my website for the next release of the compiler. Best regards, FrancescoArticle: 100532
jetmarc@hotmail.com writes: > The other type of critical path is the short path. That means that a > signal races with the clock, and arrives at the destination too early. > This can be caused by a poor clock distribution tree (with a lot of > skew), or by slow flipflops with longish hold requirements. When the > data signal arrives early, the hold time of the destination flipflop is > violated (at all clock speeds). Ah, I get it! The FF's require a stable input for a period *after* the clock as well. I had forgotten about this -- or rather, I had (wrongly) assumed that this time period was so small in comparison to the propagation delays between cells (even on the fast nearest-neighbor lines). Do you think this is always explained by clock skew? I've been experimenting with asynchronous circuits on the At94k and I've gotten some awesome results, but so far I'm only using the LUTs and the internal feedback line (routed *around* the register) to create various stateful elements (Muller C-element, for example). It's incredibly robust, even in response to temperature changes -- the self-timed lore really works. I was planning on trying to exploit the FF's to make an asynchronous latch without having to waste another LUT (don't ask for the details; I'm still working this out!). I don't distribute a global clock, so skew is not a concern, and I use handshaking to ensure the pre-"clock" setup time is obeyed (no runts or glitches on the H4/V4 lines that drive the "clock" input to the FF's). But I hadn't given any thought to the post-clock hold time. The problem scenario would be two FF's in the same sector-column (group of four cells clocked together) wherein the following events occur: 1. Edge of clock 2. FF #1's output changes as a result of clock 3. Output of FF #1 propagates to Input of FF #2, causing a change there ... where the time between #1 and #3 is less than the FF hold time. Can this happen? Or are hold-time violations always a result of clock skew? I always handshake between differently-clocked cells. I had hoped that none of the routes would be that fast (or rather, that the FF's wouldn't be so slow). But now that I think about it, the internal feedback wire (from the register's output to the W-input) is local to the cell, so it must be pretty fast. I guess some experiments are in order. - aArticle: 100533
Hi I have a board with Spartan-3e with SPI-interface. i am using the JTAG interface to program the SPI-flash. all JTAG connections are correct. when i connect chip-scope it is not detecting any device in the JTAG chain. tried using iMPACT tool also, there also i am not able to detect the FPGA in the chain. am using Parallel cable III. and the cable is OK as we are using the same cable with another board haing spartan-3 device. Is the spartan-3e device has got any problem with JTAG or chip-scope. any pointers are helpful rgds bijoyArticle: 100534
Hi all,
I am designing a hadware which use clk and 2xclk. I am planning to
use DCm block in the V4 to get the 2x clock. But the board is not yet
available. So i thought to proceed with the post PAR test. Synthesized
the a DCM block in which clk0 is fedback to clkfb through a bufg.
generated post par simulation model using ISE 7.1. And simulated it on
model sim with libraries X_DCM_ADV.v etc attached. But the clk0 and
clk2x gives a flat '1' output not clock. Why is this behaviour. Is it
possible to simulate the DCM behaviour ??
Sumesh V S
Article: 100535I got it correctly problem was applied active low reset. Locked after some 30 clk cycles. The lock pin is high but the edges of the clkin and clk1x and clk2x are at different time. Why it is like that. Is this the problem with the simulation.Article: 100536
Hmmm.... Timing constraints ? Are *.ucf files created for a *typical* FPGA design ? I am designing an FPGA (xilinx spartan 3 family, xc3s400), which I have not done for years. (I have been designing relatively simple asic modules in the last couple of years, but I digress). I cannot seem to recall if timing constraints (*.ucf file) are user-entered OR IF timing-constraints entry is typically ignored and the fpga typically generates it for the user. (...I am in the process of going over the help files as I am typing this post...) P.S by "typical design" I mean a design that does not push the FPGA to its limits (frequency limits, size limits, ect ..) Please advise -RogerArticle: 100537
I Got the answer. I have add an attribute of equivalent_register_removal to "no" to forbidden ISE to remove the maunally duplicated register. and the fanout decreases.Article: 100538
The .ucf (user constraints file) is typically required for pin assignments. If your design has *no* timing concerns (1 MHz or less, perhaps) then timing constraints aren't required. If you enter timing constraints in your synthesis tool, you often have the .ncf generated with the synthesizer's version of the timing constraints that make it to the place & route tool. The timing analyzer can give default analysis if nothing is specified. "Roger Bourne" <rover8898@hotmail.com> wrote in message news:1144760150.992455.324770@j33g2000cwa.googlegroups.com... > Hmmm.... > > Timing constraints ? Are *.ucf files created for a *typical* FPGA > design ? > I am designing an FPGA (xilinx spartan 3 family, xc3s400), which I have > not done for years. (I have been designing relatively simple asic > modules in the last couple of years, but I digress). I cannot seem to > recall if timing constraints (*.ucf file) are user-entered OR IF > timing-constraints entry is typically ignored and the fpga typically > generates it for the user. > (...I am in the process of going over the help files as I am typing > this post...) > > P.S by "typical design" I mean a design that does not push the FPGA to > its limits (frequency limits, size limits, ect ..) > > Please advise > -Roger >Article: 100539
Contact HP for licensing information. I believe they are legally required to make available - for a reasonable price - the chips or the technology for toner refillers and alternative suppliers. Doing so without their permission may result in the product you produce violating copyrights or considered black market. <tonerchips@hotmail.com> wrote in message news:e1fg5i01hpf@drn.newsguy.com... > hi all > i indent to make chips for toner cartridges ( specially hp ) in singapore > i need technical assistance in this regard and willing to pay reasonable > amount > for technology. > kindly let me know if anyone can help > > thanks > tonerchipsArticle: 100540
<ssirowy@gmail.com> wrote in message news:1144729643.494565.106330@u72g2000cwu.googlegroups.com... > Hi, > Im somewhat new to the ISE and was wondering if there was a way to > give the Xilinx tool an area constraint ( say in number of LUT's used) > for a given VHDL implementation? For instance, I have created a module > that I want to restrict to 500 LUT's if possible, because I will be > having other modules that will need the pending space. Im not exactly > sure how I would go about this using the PACE tool, and any help would > be appreciated. I am sure there is a trivial way to do it, but I seem > to be overlooking it at the moment Check out the AREA GROUP constraint in the online software manual. You can associate the module with a group and provide a range for elements in that group.Article: 100541
<ace.shikha@gmail.com> wrote in message news:1144717828.664344.170360@u72g2000cwu.googlegroups.com... > hi > > i am working on mp3 decoder in vhdl. i need to read the bitstream and > decode it. the bitstream is in a file so i used the commands for file > reading. but i found that quartus doesn't support the read, readin, > write, writein commands, i.e textio is not supported. what should i do > now to read that bitstream..plz suggest. > > regards > shikha If your intent is synthesis, where do you expect your file to reside? You don't have a windows formatted hard disk on your FPGA so how does the bitstream get stored for your purposes?Article: 100542
Hi all, I am trying to connect a device (DEI 1067) to Virtex4 FX and having problems to understand how to make this happen. This device communicates over SPI. I read the data sheet for DEI 1067 but could not get a lot out of it. Device data sheet is available at http://www.deiaz.com/data-sheets/DS-MW-01067-01-B.pdf Can sombuddy help me to translate that please.... I am not sure about the setup and hold times. I have a simple code for SPI where master clock is running at 60 MHz and i am driving 2 MHZ clock from master. This 2 MHz clock is later used to clock received SPI data into register with 1MHz clock (50% duty Cycle). I am having problems to understand setup and hold times. ThanksArticle: 100543
Hi everybody Sorry for the basic question. I'm starting with FPGA and I'm using a Spartan-3 Starter Kit board. I would like to be able to implement a design using microblaze, let's say one of xilinx's microblaze reference designs, in a way that it runs at power-on. Do you know of a documentation that explains how to do that? Tanks jmarianoArticle: 100544
I have a doubt regarding the gemac core which we can generate using the core generator with hardware evaluation license. Can we instantiate it in our plb master module? I do not want to use the plb_gemac core and want to write a customized master module with gemac in it.Is it possible? Regards, DArticle: 100545
Hi, I'm using SOPC Builder and added some components, including NIOS II, external RAM and a PCI Host-Bridge (PCI Compiler 4.1.0). Is there, by coincidence, a reference design available of a system using Nios II and the PCI Compiler together? I know there is a reference design in the PCI Compiler User Guide, but it doesn't use the Nios II processor, which I really need in my design. Another problem I'm facing is that I can't read/write any information from/to the configuration space of the internal PCI master/target device or any other (external) PCI device (actually I didn't tried that because I first want to know if it works before I blow up the device :-) ). Should configuration be done in VHDL or can it be done in software? If it is possible using software, do I have to write to the Avalon bus or directly to the PCI Bus Access slave port? Do you have any examples or reference of how to do a configuration by software? Thanks, Sander OdekerkenArticle: 100546
Hi. I have a PCI board developed and I have little acess to the FPGA PCI core, since it was not developed in house. I can say it makes no burst accesses. My proble is that I used to have a reasonable speed with these boards with athlon/semprom boards, regardless of chipset. After the chipsets/processors changed to socket 754 and 939 (and got HyperTransport, but I don't know whether it's related) i got a 20% speed drop, a little too much. With the nForce4 chipset I may get to the same speed as before, but I can't achieve it with a stable bandwidth. I don't have any intel boxex around to test with it. Does anyone has any clue on what's going on (even better, a solution)? Thanks, RicardoArticle: 100547
Do you have a PCI Analyzer? If you're a PCI target, I wonder if you're getting an abort and a retry on occasion for data that your design doesn't supply fast enough. I thought the abort period was somewhat programmable in some PCI bridges. "Ricardo" <spamgoeshere1978@yahoo.com> wrote in message news:4a2fkaFqo01qU1@individual.net... > Hi. > > I have a PCI board developed and I have little acess to the FPGA PCI core, > since it was not developed in house. I can say it makes no burst accesses. > My proble is that I used to have a reasonable speed with these boards with > athlon/semprom boards, regardless of chipset. After the > chipsets/processors changed to socket 754 and 939 (and got HyperTransport, > but I don't know whether it's related) i got a 20% speed drop, a little > too much. With the nForce4 chipset I may get to the same speed as before, > but I can't achieve it with a stable bandwidth. I don't have any intel > boxex around to test with it. > Does anyone has any clue on what's going on (even better, a solution)? > > Thanks, > RicardoArticle: 100548
Hi J You probably mean that you would like to use non-volatile memory (PROM) for bitstream storage. For that purpose you need to convert the bitstream (updated with executable.elf if you intend to use microprocessor in your design located at #project root#\implementation\download.bit) into PROM.mcs file used for programming PROM. For mcs file creation and downloading use ISE's accessory iMPACT. iMPACT's nice wizard will guide you through this (ver 8.1). Select Prepare PROM file -> Xilinx PROM, MCS file format, PROM filename and location -> Select proper PROM (xcf0xs - look at StarterKit User guide) -> Add -> Find your bitstream file -> Clik to -> Generate file and voila the mcs file is prepared. Connect the device to JTAG cable!!!!! Then run Boundary Scan (and press Cntrl+I for Initialize chain). Select generated mcs for PROM (and maybe files -bit, bmm, elf for directly loading Spartan3). With right click on the device and program it. Have fun GuruArticle: 100549
>if you want to use Picoblaze, then why you don't try the free C >compiler for Picoblaze? I will definitely do that, thanks :) P.
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