Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 100075

Article: 100075
Subject: Re: deglitching a clock
From: "Brian Davis" <brimdavis@aol.com>
Date: 3 Apr 2006 04:23:46 -0700
Links: << >>  << T >>  << A >>
Nico Coesel wrote:
>
> I can't find any references to these limitations in the datasheet. A
> DDR memory interface application note makes a short notice of some
> limitations on placement, but thats all there is.
>

 Try XAPP609 and Answer Record 17697 for a description of local clock
placement and routing restrictions (although I think XAPP609 only
describes V2, the structure is similar but not identical in S3).

Brian


Article: 100076
Subject: Re: ModelSim Designer
From: se <no@email.nyet>
Date: Mon, 03 Apr 2006 11:56:45 GMT
Links: << >>  << T >>  << A >>
Brian Drummond wrote:
  > But overall I'm with Hans that I'd definitely not want to work without
> it.
> 
> I don't know how much use this is to you, given the version differences.
> But I'd question the value of the full product, and ask if Modelsim
> Designer doesn't give you most of what you need (basic non-graphical
> VHDL import, block diagrams, and state machines) as well as another
> Modelsim seat (full function PE as far as I can tell). 

We've ended up banning the use of HDL Designer.  A minor issue was it's 
incompatibility with our CM tools.  We also had managers think that good 
  power supply designers, good servo designers, etc. could easily design 
FPGAs using schematic entry.  This caused some problems.  But the icing 
on the cake was finding unconstrained clocks added to the logic without 
the designer being aware.  Mentor's response was we needed more 
training.  Our response was to provide more training to the engineers in 
using VHDL to develop FPGAs.

							Sam

Article: 100077
Subject: Re: Spartan3E Phase-Shifter
From: oen_no_spam@yahoo.com.br
Date: 3 Apr 2006 05:22:10 -0700
Links: << >>  << T >>  << A >>
Hi Steven,

"Is the confusion with the "ns" term in the equation?   It was added
only to emphasize that the equation is operating in time, not
frequency."
No, TCLKIN is period, it must be given in seconds, no confusion here.
But n (nano) is a number (0.0000000001), so, the equation is wrong. For
the 20M[Hz], the TCLKIN=50n[s]=50000p[s]=0.05u[s] (same number).
Use your calculator or your computer to evaluate the equation, using
TCLKIN=1/FCLKIN (frequency) and you'll see what I mean.

"I have a clarifying question on your question.  Are you using VARIABLE

phase shift mode to shift beyond -360 or +360 degrees and asking what
happens when you exceed a full period?"
Yes, I would like to shift beyond +/-2pi (360 degrees). If you look at
"Stratum4E holdover" topic, you'll see what I want to do.
I could use 2 DCMs, and whenever the active DCM reaches the +/-2pi,
switch to the other one (locked at 0 radians). Or, maybe, just reset
the DCM. But it looks like the Spartan3E Frequency-Shifter in the
VARIABLE phase shift mode, can't reach the +/-2pi shifts. Is thet true?

Thanks,

Luiz Carlos


Article: 100078
Subject: Inferring RAM with FOR loop
From: vedpsingh@gmail.com
Date: 3 Apr 2006 05:52:40 -0700
Links: << >>  << T >>  << A >>
Hi all,
I have written a simple code where data from a matrix(2-D array) is
Xored with single dimensional array.
On synthesis, things are being mapped in LUT's and Latch. I want to use
Block RAM's as in my case B-RAM's are sufficiently available on
VIRTEX-II FPGA device. I have read help of synplicity and XST and have
used ATTRIBUTE as told by them.

Synplicity and Xilinx guys are telling me that this cant be done in FOR
loop and are recommending to use a template. But this defeats the
flexibility of VHDL, as using templates is as good as doing schematic
entry.
I need coments from you experts.

---------------------
library IEEE;
        use IEEE.STD_LOGIC_1164.ALL;
        use IEEE.STD_LOGIC_SIGNED.ALL;
package CONV is
          constant N : integer := 16 ;  -- number of elements to sort
          constant M : integer := 8 ;   -- size of word to sort

		  constant A : integer := 3 ; --counter_length = Length of Vector
Matrix = 2^A

		type MATRIX is array (0 to (2**A)-1 , 0 to N-1) of std_logic ;

		type HQARRAY is array (0 to N-1) of std_logic ;

end CONV;

----------------------------------------------------------------------
--- -------------------------------
--SIGNAL XORed_sig should become RAM.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.CONV.all;

entity XORblock is
	port(
		Reset : in STD_LOGIC;
		clock : in STD_LOGIC;
		WE : in STD_LOGIC;
		HardQuantIN : in HQARRAY;
		MatrixIN    : in MATRIX ;
		XORed_out : out MATRIX
		);
end XORblock;

architecture archXORblock of XORblock is

signal  XORed_sig : MATRIX ;
-------****Attribute for BLOCK RAM*****-----
attribute syn_ramstyle : string;
attribute syn_ramstyle of XORed_sig : signal is "block_ram";
--------------------------------------------

begin

	XORing:process (clock,Reset)

	begin
	if Rising_edge(clock) then
    if Reset = '1'  then
       ---Fill the Array with '0'
	 	 for l in 0 to M-1 loop
			for m in 0 to N-1 loop

				XORed_sig(l,m) <= '0';

			end loop;
		end loop;

		for i in 0 to M-1 loop
			for k in 0 to N-1 loop

				XORed_sig(i,k) <= MatrixIN(i,k)  xor HardQuantIN(k);

			end loop;
		end loop;
 end if ;

    if (we='1') then
		XORed_out <= XORed_sig ;
	 end if;	
 end if;
end process XORing;
	
end archXORblock;


Article: 100079
Subject: Re: Inferring RAM with FOR loop
From: "Andy" <jonesandy@comcast.net>
Date: 3 Apr 2006 06:09:56 -0700
Links: << >>  << T >>  << A >>
Two problems:

First, Rams are inferred from arrays of arrays, not 2-dimensional
arrays. You can also infer rams from arrays of integers, enums,
booleans, etc. You can even infer a single bit ram from a
std_logic_vector if the access conditions are right. Dual port rams
give you access to two addresses at a time (each clock cycle).

Second, you can only access one address of a single port ram in the
same clock cycle. You are trying to access every address in one cycle,
which forces the synthesis tool to infer registers.  You need to set up
an address counter that steps through the addresses, and accesses only
one address on each clock.

Andy


Article: 100080
Subject: =?iso-8859-1?q?Re:_how_to_read_this_book=AB_Digital_integrated_circuits.a_design_perspective(Second_Edition)=BB?=
From: "mynewlifever@yahoo.com.cn" <mynewlifever@yahoo.com.cn>
Date: 3 Apr 2006 06:26:59 -0700
Links: << >>  << T >>  << A >>

Hi,chris_ivan
Thank you for your response!What your have say is very useful for me.
According to what your say,I think this book is very useful for layout
disigner,not me.
If I want do better in digital disign everyday,how can I do?Only
writing code everyday is not a good method.Please give me some advice.
I have an FPGA board with spartan,but I donot exactly know I can make
what .Do what project,and how to do are always puzzled me.
Please help me!
Thank you!
                   mynewlifever


Article: 100081
Subject: Re: PCB Bypass Caps
From: "Andy" <jonesandy@comcast.net>
Date: 3 Apr 2006 06:30:30 -0700
Links: << >>  << T >>  << A >>
You're right in that the decoupling at higher speeds is done by the
planes (and on-package caps, if applicable), no the capacitors on the
board.  However, the on-board capacitors' job is to decouple the
planes, not the device. Anything that can be done to reduce the
effective inductance in the capacitor package and its connections to
the planes (not just to the chip) helps, including broadside packages
and adjacent/doubled vias.

Andy


Article: 100082
Subject: Re: need your comments
From: "Marco" <marco@marylon.com>
Date: 3 Apr 2006 06:36:41 -0700
Links: << >>  << T >>  << A >>
Dale,
the signal voltage is 3.3V, so I use the LVCOMS33 standard for the
whole I/Os. I also placed 100 Ohm current limiting resistances on TCK,
TDI, TMS, CCLK, PROG_B. Then TDO, CCLK, PROG_B and DONE are all pulled
up with 10kOhm, should I do the same for INIT_B (that will later be
used as GPIO)?
Your suggestion helps me with point 3 (thanks so much), do you or
others have any comments also on terminations and PDS questions?
I'd really appreciate.
Marco


Article: 100083
Subject: Re: PCB Bypass Caps
From: "Andy" <jonesandy@comcast.net>
Date: 3 Apr 2006 06:43:10 -0700
Links: << >>  << T >>  << A >>
We've had best luck when signal reference planes are continuous,
whether they are power or ground. When we use segmented power planes
(we don't segment ground planes anymore), we bury them between
continuous ground or power planes, or at least try to keep the
segmented layers away from signal layers.  Differential signals, routed
broadside, not over-under, are more forgiving WRT routing over
segmented planes.

Andy


Article: 100084
Subject: Re: Doubt about SERDES
From: "pinku" <praveenkumar.bm@gmail.com>
Date: 3 Apr 2006 06:59:46 -0700
Links: << >>  << T >>  << A >>

Thanks all for your response.

Regards
Kumar


Article: 100085
Subject: Re: ModelSim Designer
From: "Mike Treseler" <mike_treseler@comcast.net>
Date: Mon, 03 Apr 2006 07:00:42 -0700
Links: << >>  << T >>  << A >>
Kim Enkovaara wrote:

> Actually HDL designer creates quite clean code from the FSM editor
> and block diagrams. It can easily be read also manually. The
> problem is lack of comments in the code if it is automatically
> generated tough.

Yes, and once I add a comment, the graphical tool
is out of the source control loop.

>> A single block HDL style allows the bottom up
>> use of variable (register) structures, functions and procedures
>> to construct a design of arbitrary complexity
>> from a standard template. 

> Just be wary with functions and procedures. Especially
> procedures seem to be a big problem still for design tools. I think
> I have seen all the major implementation tools to create garbage or crash
> with very simple procedures (DC, Synplify, FormalPro, Formality, few 
> linters etc.)

If you have access to any of those tools, would you mind
running my reference design through and see how it does?

  http://home.comcast.net/~mike_treseler/uart.vhd

>> For designers who know an HDL for synthesis and simulation,
>> tools like HDL designer are largely irrelevant.
> 
> Actually what I have seen very experienced VHDL coders (10+ years) also
> like HDL designer. They usually use only the block diagrams and
> text views. Block diagrams are good way of documenting
> the functionality.

I agree that HDL designer is a fine browser.
My point to the OP was that it is not necessary
for design entry and that there are more
economic ways to get this design browser function.

          -- Mike Treseler

Article: 100086
Subject: Problem erasing EEPROM XCF08P
From: "mughat" <mughat@gmail.com>
Date: Mon, 3 Apr 2006 16:14:32 +0200
Links: << >>  << T >>  << A >>
I have installed a XCF08P EEPROM in my fpga board.
The first time i wrote a program to it, it worked fine. But I can not erase 
the EEPROM.
When i write to it now verify fails, I suspect i have to erase it before 
writing a new program.

Using: Impact 8.1.03i
JTAG programmer: JTAG 3 i belive (Parallel port), came with a digilent 
starter board.

Thanks
Andreas Beier 



Article: 100087
Subject: virtual slot implementation
From: "pinku" <praveenkumar.bm@gmail.com>
Date: 3 Apr 2006 07:24:42 -0700
Links: << >>  << T >>  << A >>
Hello Groups,

We have aggregate and segregate datas from two processor in
FPGA.So we will have to snooping the data so that data is send to
the corresponding processor. Instead of snooping the data can i
implement 2 virtual slots but i have no idea has to how to implement
this virtual slots.

Please tell me if u know how to implement it.

Regards
Kumar


Article: 100088
Subject: Spartan 3E SPI Programming
From: Eli Hughes <emh203@psu.edu>
Date: Mon, 03 Apr 2006 10:32:57 -0400
Links: << >>  << T >>  << A >>

Hello

I was reading through XAPP445 (SPI Configuration), on page 9 an indirect 
method of programming the SPI configuration device is proposed use the 
JTAG interface to bit-bang the SPI interface.  Does anyone know if the 
Impact tool supports this?

-Eli

Article: 100089
Subject: Re: Spartan 3E SPI Programming
From: "Antti" <Antti.Lukats@xilant.com>
Date: 3 Apr 2006 07:49:21 -0700
Links: << >>  << T >>  << A >>
not yet. indirect JTAG programming is supported by Altera and Lattice
tools, Xilinx might add this in ISE 9.x release I think.

we have some tools that do indirect SPI flash programming (IP core +
host side sw) but we have so far not released any full solutions for
SPI indirect programming. when we do then all FPGAs will be supported
:)

Antti


Article: 100090
Subject: Re: Problem erasing EEPROM XCF08P
From: "MM" <mbmsv@yahoo.com>
Date: Mon, 3 Apr 2006 11:19:26 -0400
Links: << >>  << T >>  << A >>
I have seen this behaviour. In my case it was enough to set "erase before
programming" check mark in the Impact GUI. Generally speaking, Impact is
full of small bugs, which sometimes make it crash and sometimes it just
wouldn't behave properly. In many cases it is enough to reset the cable and
re-initialize the chain, in other cases you need to restart the program...

/Mikhail


"mughat" <mughat@gmail.com> wrote in message
news:e0ralq$42v$1@news.net.uni-c.dk...
> I have installed a XCF08P EEPROM in my fpga board.
> The first time i wrote a program to it, it worked fine. But I can not
erase
> the EEPROM.
> When i write to it now verify fails, I suspect i have to erase it before
> writing a new program.
>
> Using: Impact 8.1.03i
> JTAG programmer: JTAG 3 i belive (Parallel port), came with a digilent
> starter board.
>
> Thanks
> Andreas Beier
>
>



Article: 100091
Subject: Re: Discrete
From: "Fizzy" <fpgalearner@gmail.com>
Date: 3 Apr 2006 08:21:00 -0700
Links: << >>  << T >>  << A >>

Well,

I agree with you on that and i think he should put some thought in it
but Interestingly NOT ALL WORKING IN A sophisticated company may be
engineers :-) is that right ? and who knows if this person is NOT an
engineer So we all should be tolerent and should be careful in
answering because this is a public forum not a personal area. Plus if
you think its naive and impossible to answer than do not answer .....


Peter Alfke wrote:
> I suppose Duane is wondering how such a naive ( impossible to answer)
> and poorly worded question comes from somebody working in such a
> sophisticated company..."interesting"
> We all want to be helpful, but I will also point out that posters
> should do a little bit of thinking and googling before they embarrass
> themselves.
> We learned recently that we must be tolerant of "creative spelling"...
> Peter Alfke


Article: 100092
Subject: Re: Spartan 3E SPI Programming
From: Eli Hughes <emh203@psu.edu>
Date: Mon, 03 Apr 2006 11:22:47 -0400
Links: << >>  << T >>  << A >>
Antti wrote:
> not yet. indirect JTAG programming is supported by Altera and Lattice
> tools, Xilinx might add this in ISE 9.x release I think.
> 
> we have some tools that do indirect SPI flash programming (IP core +
> host side sw) but we have so far not released any full solutions for
> SPI indirect programming. when we do then all FPGAs will be supported
> :)
> 
> Antti
> 


What would also be nice is a Systam ACE Solution that uses MMC cards. 
I really hate that huge system ACE chip!  I also dislike the fact that I 
have to use FAT16 for configuration. A FAT32 solution would be even 
better. I spent a long time trying to get a compact flash card to format 
correctly.  I noticed that FAT32 always worked for file system access 
(EDK) but was missing some critical functions such as delete file!

-Eli


Article: 100093
Subject: Re: Discrete
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 03 Apr 2006 15:38:59 GMT
Links: << >>  << T >>  << A >>
"Fizzy" <fpgalearner@gmail.com> wrote in message 
news:1144077660.439014.287360@v46g2000cwv.googlegroups.com...
>
> Well,
>
> I agree with you on that and i think he should put some thought in it
> but Interestingly NOT ALL WORKING IN A sophisticated company may be
> engineers :-) is that right ? and who knows if this person is NOT an
> engineer So we all should be tolerent and should be careful in
> answering because this is a public forum not a personal area. Plus if
> you think its naive and impossible to answer than do not answer .....

Thank you for taking on the job as forum moderator.

Many of us appreciate the time and effort of those who are ready and willing 
to contribute to the policing of posts in an effort to make people look 
silly.

Again, your time and attention is appreciated.

- John Handwork 



Article: 100094
Subject: Re: OpenSPARC released
From: "Ira Baxter" <idbaxter@semdesigns.com>
Date: Mon, 3 Apr 2006 10:47:53 -0500
Links: << >>  << T >>  << A >>
I started this thread, because I found what appears to be a named-parameter
assignment to a UDP instance in the OpenSparc files.

This doesn't appear to be legal according to standard Verilog,
at least what I see in the 2001 standard.
I haven't gotten a clear response on this,
but I'm sure the community knows.

Can somebody with experience here say if this is supposed
to be legal, or if it is a manufacturer's extension
(and suggest which manufacterer?)

Thanks,

-- 
Ira Baxter, CTO
www.semanticdesigns.com

"Allan Herriman" <allanherriman@hotmail.com> wrote in message
news:hmke229g4ufv7h35htt4ohqhbikrvc26mo@4ax.com...
> On Mon, 27 Mar 2006 01:12:41 GMT, mk <kal*@dspia.*comdelete> wrote:
>
> >On Sun, 26 Mar 2006 22:47:13 +1000, Allan Herriman
> ><allanherriman@hotmail.com> wrote:
> >
> >>>>   dff #4  park_reg(.din  (next_pv),
> >>>>      .clk  (clk),
> >>>>      .q    (park_vec),
> >>>>      .se   (se), .si(), .so());
> >...
> >>dff isn't a gate primitive, so it must be a UDP.  However, it seems
> >>that the standard only allows ordered parameter assignments and not
> >>named parameter assigments for UDPs.
> >>
> >>
> >>Therefore the code isn't legal according to the standard.
> >>
> >>This seems to be a mistake in the standard.  Does anyone know why it
> >>doesn't allow named parameter assignments for UDPs?
> >
> >I must be missing something. Why is a named parameter assignment
> >needed ? Isn't this an ordered parameter assignment ?
>
> In the above code,
>
> (
> .din(next_pv),
> .clk(clk),
> .q(park_vec),
> .se(se),
> .si(),
> .so()
> )
>
> is a named parameter assignment.
>
>
> An ordered parameter assignment would look more like
>
> (
> next_pv,
> clk,
> park_vec,
> se
> )
>
>
> Regards,
> Allan



Article: 100095
Subject: Looking for chebychev equation
From: "Roger Bourne" <rover8898@hotmail.com>
Date: 3 Apr 2006 09:00:49 -0700
Links: << >>  << T >>  << A >>
Hello all,

I am looking for the equations used in the calculations of the
coeffcients of chebychev IIR (2nd order) low pass filters for biquad
sections (w.r.t passband ripple, stopband attenuation ...). I have been
googling for the past hour, but alas no cigar (I suspect my search
criteria may be too narrow...) . I would appreciate any help,
particularly links and such.
I have encountered several links to applets and programs, though.

Thx in advance
-Roger


Article: 100096
Subject: Re: OpenSPARC released
From: "J o h n _ E a t o n (at) hp . com (no spaces)" <"J o h n _ E a t o n (at) hp . com (no spaces)">
Date: Mon, 03 Apr 2006 09:03:30 -0700
Links: << >>  << T >>  << A >>
Ira Baxter wrote:
> I started this thread, because I found what appears to be a named-parameter
> assignment to a UDP instance in the OpenSparc files.
> 
> This doesn't appear to be legal according to standard Verilog,
> at least what I see in the 2001 standard.
> I haven't gotten a clear response on this,
> but I'm sure the community knows.
> 
> Can somebody with experience here say if this is supposed
> to be legal, or if it is a manufacturer's extension
> (and suggest which manufacterer?)
> 
> Thanks,
> 

   dff #4  park_reg(.din  (next_pv),
      .clk  (clk)
      .q    (park_vec),
      .se   (se), .si(), .so());


Does the database contain a module description for dff
that has a parametized width ? If so this is simply instantiating
that module with a width of 4.

John Eaton


Article: 100097
Subject: Spartan3E data sheets
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 03 Apr 2006 16:10:15 GMT
Links: << >>  << T >>  << A >>
The newest version (3.0) of the Spartan3E complete data sheet came out a 
week or two ago.  I just wanted to give my Kudos to the Xilinx folks for 
adding the DESIGN NOTE boxes complete with bright yellow attention symbol to 
address the design issues that wouldn't be apparent to the casual data sheet 
reader.

I've noted before that designers would appreciate full attention to detail 
in the data sheet as opposed to relying on the answer records or help line 
calls.  The notes don't appear to detract from the technical "confidence" in 
the devices at all, at least for this engineer.  It's fantastic to see the 
full disclosure.

Once the device tables specify "logic cells" as opposed to "equivalent logic 
cells" I won't have anything to complain about!

- John_H 



Article: 100098
Subject: Re: Spartan 3E SPI Programming
From: "Antti" <Antti.Lukats@xilant.com>
Date: 3 Apr 2006 09:10:30 -0700
Links: << >>  << T >>  << A >>
this is one our TODO list as well, its all doable now since latticeXP
FPGAs are available :)

Antti
PS my MMC card (non SPI mode) FPGA configurator IP core (free at
openocores) uses 21 PLD macrocells (xilinx SPI flash loaded ip from
xilinx appnote is over 50 PLD macrocells). So you bet XP3 makes a real
cool replacement for systemACE ugly chip. Ok the 21 PLD cell version is
only possible for old small MMC cards that support CMD11 (most new
cards dont).


Article: 100099
Subject: Re: hwicap can be used in the virtex4
From: "Denaice" <dgalerin@gmail.com>
Date: 3 Apr 2006 09:17:32 -0700
Links: << >>  << T >>  << A >>
Does someone have a working design using an ICAP in Virtex-4 ? We are
trying to send a difference-based partial bitstream to it by using
GPIOs but it doesn't seem to work. (The bitstream is ok, it works in
iMPACT by JTAG)




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search