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> Jim Wu wrote: >> FWIW, my ISE8.1 installation has libPlXil_Legal.so in >> $XILINX/xilinx/bin/lin64 on my RedHat EL3 64-bit machine. > Strange... It's not there on my machine... I'll do a reinstall tomorrow, > maybe it'll show up... Tried again just now, no luck, no libPlXil_Legal.so anywhere. Strange thing is, it's not there on any other machine either. I have ISE8.1 installed on several Windows and Linux machines, none of the installations has a libPlXil_Legal.so/libPlXil_Legal.dll, but they all work fine, except the one on the 64bit-machine. cu, SeanArticle: 103626
Hello, I use Xilinx xcv200e to sum the measurement result in FPGA, in order to average the result in PC. Most of the time, the system can work well, but sometimes there are small noise-like vibration in the average chart and it can lasts several seconds. Of course, with very big average count, the vibration is not clear. What's the possible reason? In addtion to possible hardware problem, if vhdl software can also cause such phenomena? Thanks BrianArticle: 103627
subint wrote:
> hi,
> it's true, but i was not able to run the mig from the core
> generator.don't know why.
> Actually i am opening the mig from the installed directory(there is a
> batch file named mig.) .
> subin
> Joseph Samson wrote:
Hi subin,
opening this batchfile, you should find something like
mig -cg_exc_inp test\mig_input.txt -cg_exc_out mig_output.txt
so - edit "test\mig_input.txt" and change
SET_PREFERENCE designentry verilog
to
SET_PREFERENCE designentry vhdl
btw: you'll have to change the other entries,too, for changing i.e. the
part etc.
good luck
Jochen
Article: 103628Hello, I'm trying to implement a simple delay line for a 1MHz clock with an even number of inverter cells but the Synthetizer/Mapper doesn't work!! I think the logic optimizer is simplifying my even inverter cells in a short circuit... Wich kind of options can I use for the Xilinx tools? I'm using ISE7.1 and ISE8.1 with a Spartan3 device. How can I implement a simple delay line with about 500ps of delay in a FPGA? Thanks a lot!!Article: 103629
> > you are using a crosslink cable? some NICs have some > auto-swap-input-pins feature ... maybe your intel has - try to run the > connection over a switch where you can see the link status of both sides > Yes I'm using crossover cable. BartekArticle: 103630
Hi everyone.
I'm trying to implement a gigabit ethernet mac connected to a
external gigabit PHY using a SGMII link.
I've used the coregen wrapper generator (v4.1 + the patch in answer
record 22332 and the new calibration block 1.4.1) to generate an
example design that I've slighty modified to fit my need. The
mais modifications are :
- Connect the EMAC client interface to some packet generator
- Change some PLL and DCM settings to fit my reference
frequency which is 250MHz instead of the 125MHz using in the
example design.
- Bypassed the internal AC coupling of the rocket io (already
done using external components)
- Activated the PCS/PMA Autonegotiation (tieoff pins).
The problem I'm having is that nothing is received nor send.
I see that the DCM lock and so does the pll of the rocketio.
When I look at the interface of the rocket io :
- On the TX side, I see the EMAC sending the correct stuff
when trying to send a packet :
/SFD/ = *0xFB
<ethernet.preamble> = 0x55 0x55 0x55 0x55 0x55
<ethernet.sfd> = 0xD5
<ethernet.data> = ....
<ethernet.fcs> = 0x?? 0x?? 0x?? 0x??
*0xFD *0xF7
and when doing nothing is sends IDLEs *0xBC 0x50
- On the RX side, I see the MAC keeping sending it's configuration
register
*0xBC 42 01 98
*0xBC B5 01 98
....
I haven't found really clear SGMII doc, but from what I understand, the
PHY sending it's configuration means it's not in "data-mode" because
it's awaiting the SGMII autonegotiation process to take place,
but the MAC is already in data mode. And the mac is supposed to answer
to the configuration registers
sent by the phy or am I wrong ?
The components i'm using are :
- The DiniGroup DVI card : http://www.dinigroup.com/dvidc.php
which has a V4FX60 CES4 and numerous rocket io on SMA.
- The xilinx phy daughter card :
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNavPick=&sSecondaryNavPick=&iLanguageID=1&key=HW-AFX-BERG-EPHY
which has two marvell alaska PHY connected to SMA.
The two board are connected using SMA cables (and nothing else,
the MDIO interface of the PHY is not connected) and the phy card
has been configured thru jumpers to be in sgmii mode at reset.
Thanks for any help,
Sylvain
Article: 103631On 7 Jun 2006 00:07:49 -0700, "dmos" <daniel.mosconi@gmail.com> wrote: >Hello, I'm trying to implement a simple delay line for a 1MHz clock >with an even number of inverter cells but the Synthetizer/Mapper >doesn't work!! I think the logic optimizer is simplifying my even >inverter cells in a short circuit... >Wich kind of options can I use for the Xilinx tools? >I'm using ISE7.1 and ISE8.1 with a Spartan3 device. >How can I implement a simple delay line with about 500ps of delay in a >FPGA? I think this is a very bad approach. Gate delay times depend greatly on temperature, so your 500 ps may be almost anything, but most of the time they will not be 500 ps. In fact, the propagation time from G to Y in a CLB varies from 530 to 610 ps, which is always more than what you want. Do you really need such a fine delay? It is only 0.05%! Regards ZaraArticle: 103632
It's correct, it's a very bad approach, but I think it's the simplest... The delay depends on temperature, but for my application, is not so important the absolute value of this delay if it's less than 1ns. It's more important that two contiguous delay cells have the same delay. RegardsArticle: 103633
On 7 Jun 2006 01:53:55 -0700, "dmos" <daniel.mosconi@gmail.com> wrote: ## >Hello, I'm trying to implement a simple delay line for a 1MHz clock ## >with an even number of inverter cells but the Synthetizer/Mapper ## >doesn't work!! I think the logic optimizer is simplifying my even ## >inverter cells in a short circuit... ## ## ## I think this is a very bad approach. Gate delay times depend greatly ## on temperature, so your 500 ps may be almost anything, but most of the ## time they will not be 500 ps. ## >It's correct, it's a very bad approach, but I think it's the >simplest... >The delay depends on temperature, but for my application, is not so >important the absolute value of this delay if it's less than 1ns. >It's more important that two contiguous delay cells have the same >delay. > Probably the best is to use LUT1/2/3/4 and (R)LOCs to ensure that the buffer/inverter/logic function is synthesized as one CLB only. ZaraArticle: 103634
<boxi.yang@gmail.com> wrote: > it would be use on academic research only). Would you please tell me > where can I get a copy of the API or tell me the email address of > Delon Levi? Eager for your help, thank you > Heve you tried Delon (dot) Levi (at) xilinx (dot) com ? J.Article: 103635
These types of packages are a serious issue in our mil systems that
we've been working for sometime. We have techniques that address the
problem but keep looking for a real solution.
Sam
Austin Lesea wrote:
> bh,
>
> We are actively working with many military contractors on packaging.
>
> And, they have been tested, and they don't fare well. All our packages
> breath. If they get conformal coated, then any moisture inside is
> trapped. If they could bake before coat, potentially this works ... but
> the tests continue.
>
> Then when the heat is on, they POP if they adsorbed any moisture (even
> through the coating).
>
> This is not unique to Xilinx, but an industry wide problem with all flip
> chip packages today.
>
> In the FPGA business we have the distinction of making the largest die
> in the industry.
>
> In the lobby of the IDA building
> http://www.ida.org/
> there area series of posters of pcbs. Center in many of them is a
> Xilinx FPGA. These posters caught many by surprise, as in most recent
> systems, there is a Xilinx FPGA. (Even the military had no idea how
> pervasive FPGAs have become)
>
> Coatings are typically used where there is no protection from the
> environment at all. Many systems provide environmental protection at
> the box level.
>
> There are some packages which are qualified for coating (hermetic), but
> they are either too small for our die, or they have not been qualified
> for our use, yet.
>
> Austin
>
> bh wrote:
>
>>Xilinx app note XAPP426 v1.3 (March 2006) indictes that:
>>"Xilinx has no experience or reliability data on flip-chip BGA packages
>>on board after exposure to conformal coating."
>>
>>WTFO ?
>>
>>How is it possible with Xilinx being so tight with Military
>>developers that they haven't tested their parts under the
>>conditions which nearly all military boards are produced?
>>
>>What am I missing? Have they been sworn to secrecy? :-))
>>
>>-BH
>>
>>
>>
Article: 103636In article <e643rf$nq415@xco-news.xilinx.com>, Austin Lesea <austin@xilinx.com> wrote: >In the FPGA business we have the distinction of making the largest die >in the industry. Are you allowed to mention what the actual die size for something like a XC4VLX200 is? I would have tended to guess that the MPU people with 200mm^2 dice were at the higher end of the industry, except for the people who make camera sensors and are up to 900mm^2 of CCD. TomArticle: 103637
Andy wrote:
> Good point, but just for grins, let's turn this around into a read,
> rather than a write:
>
> If a then
> data <= a_thing;
> end if;
>
> if b then
> data <= b_thing;
> end if;
>
> There is still an implied priority of B over A which, without
> explicitly coding an and-or tree, is pretty difficult to code with no
> priority implied.
Since a and b are exclusive,
I might save a gate by doing
a single bit selection,
if b_thing is ok as default data:
if a then
data <= a_thing;
else
data <= b_thing;
end if;
-- Mike Treseler
Article: 103638If you use "falling_edge(awe)" then awe will get tied to the clock input on one or more registers that will hold the signal values that you assign within that if-then clause. Storing data on falling edges of strobes will work, but think about what you are going to do with that data in the latches. The timing can be very difficult to manage if you need to use that data elsewhere in a synchronous (clocked) system. Handling asynchronous buses in a synchronous system is beyond the scope of this conversation. Whole chapters/books have been written on it. Generally speaking, you usually end up syncrhonizing the control lines, and using those synchronized versions to control storage into synchronous registers (i.e. they form clock enables on registers that are clocked by your system clock). If your clock is not fast enough to handle the timing of the controls, then you may need to latch the data with the asynchronous strobe, then use a synchronized version of the strobe to enable transfer from the latch into a register on the system clock. Andy Srikanth BJ wrote: > Hi Andy,thanks a lot for your response. > Andy wrote: > > First, your code (both versions) will create latches, not registers. > > You need a clock edge specification: > > > > if rising_edge(clk) then > > -- decode/assignment statements go here > > end if; > > > I am using address decoding logic irrespective of the Clock i.e based > on that particular address., i am implementing read and write > functionalities.If i need a edge, could I use the /ARE low or /AWE low > i.e > if falling_edge(AWE) > -- decoding > end if; > Please clarify..Article: 103639
Conformal coating is not usually a sufficient moisture-mitigation technique on its own for equipment that has very long (decades) storage and/or operational requirements in severe environments. With so many devices available only in plastic, non-hermetic packages, many projects end up mitigating at the box level, which means completely sealed boxes, purged with dry air or nitrogen, and the use of dessicants based on the leak rates of the seals on the box. However, conformal coating is often used, even in these sealed environments, as FOD (foreign object debris/damage) mitigation. It prevents debris that may come about because of vibration, age/decay, etc. from causing operational problems (like shorting out conductors). AndyArticle: 103640
Zara wrote: > On 7 Jun 2006 01:53:55 -0700, "dmos" <daniel.mosconi@gmail.com> wrote: > > ## >Hello, I'm trying to implement a simple delay line for a 1MHz > clock > ## >with an even number of inverter cells but the Synthetizer/Mapper > ## >doesn't work!! I think the logic optimizer is simplifying my > even > ## >inverter cells in a short circuit... > ## > ## > ## I think this is a very bad approach. Gate delay times depend > greatly > ## on temperature, so your 500 ps may be almost anything, but most > of the > ## time they will not be 500 ps. > ## > > >It's correct, it's a very bad approach, but I think it's the > >simplest... > >The delay depends on temperature, but for my application, is not so > >important the absolute value of this delay if it's less than 1ns. > >It's more important that two contiguous delay cells have the same > >delay. > > > > Probably the best is to use LUT1/2/3/4 and (R)LOCs to ensure that the > buffer/inverter/logic function is synthesized as one CLB only. Also make sure the routing resources are locked too. DIRT (direct routing) strings may help. HTH, Jim http://home.comcast.net/~jimwu88/tools/Article: 103641
Sean Durkin wrote: > > Jim Wu wrote: > >> FWIW, my ISE8.1 installation has libPlXil_Legal.so in > >> $XILINX/xilinx/bin/lin64 on my RedHat EL3 64-bit machine. > > Strange... It's not there on my machine... I'll do a reinstall tomorrow, > > maybe it'll show up... > > Tried again just now, no luck, no libPlXil_Legal.so anywhere. Strange > thing is, it's not there on any other machine either. I have ISE8.1 > installed on several Windows and Linux machines, none of the > installations has a libPlXil_Legal.so/libPlXil_Legal.dll, but they all > work fine, except the one on the 64bit-machine. > > cu, > Sean I don't know why they all work w/o this file. I just checked my other installations (WinXP, and FC3 32-bit) and they all have this file. Windows: in $XILINX\\xilinx\bin\nt FC3 32-bit: $XILINX/bin/lin/ Jim http://home.comcast.net/~jimwu88/tools/Article: 103642
Thomas Womack wrote: > > Are you allowed to mention what the actual die size for something like > a XC4VLX200 is? I would have tended to guess that the MPU people with > 200mm^2 dice were at the higher end of the industry, except for the > people who make camera sensors and are up to 900mm^2 of CCD. The top-end device in each of the Virtex families is larger than 20 mm x 20 mm, but smaller than 25 x 25 mm. So, we are talking about roughly 500 square mm of silicon, much larger than typical CPUs. Within each family, the area is roughly proportional to the part number. Thanks to careful design techniques, and superb processing at our foundries, we do get acceptable yield with these big chips. (BTW, Altera is in a similar situation. It's a competitive world). Peter Alfke,Xilinx ApplicationsArticle: 103643
Hi out there,
does anyone succeeded using ICAP_VIRTEX4 in 32 bit mode?
I have implemented a small ICAP controller hanging on the "B" side of a
DPRAM.
The ICAP is configured as 32 bits wide, but it does not work....
1. If I assumed active low CE, and WE - the ICAP shows BUSY state -
always...
If I read whatever it presented on the 32 bit ports show: 0x0000009F.
Does anyone know what this 9F is?
2. If I assumed active high CE and WE, something got wiser:
BUSY has started low, and went high only if I initiated an R or W ABORT.
The next normal read will made it LOW again. It seems OK.
I have tried almost everything: bitorder reversing by octet and
by 32 bits words. Change the Endianness. None. In this case the
device can only present big fat zeroes..
Note1: I have changed the polarity of the CE/WE by using the FPGA editor
Note2: I have played the sequence:
write:
DUMMY
SYNC
NOP
RDSTATUS or RDIDCODE
NOP
NOP
NOP
read:
ZERO (0x00000000)
always....
Any idea?
Best regards,
Gyuri
Article: 103644bh, The problem is even after bake, a conformal coat is not 100% moisture proof (adsorbs water). We have seen conformal coated flip chip packages where the moisture gets inside and then corrodes things. The underfill is 100% epoxy, so there is no concern with anything actually getting under the die itself. AustinArticle: 103645
Thomas, It is no secret now, as there are companies which tear the parts apart. I'll save you the $20,000 for buying their report. The LX200 is close to reticle limited, which means that is is about 22 X 24 mm. Just shy of 500 sq mm. At least one family member is always at this limit, as that is how we maintain "sir superiority." The 4VFX140 is also right about at that size. That makes us at least 2x the size of any other commercial product. Most ASIC houses never make a die much larger than 10 X 10 mm, for example. If asked, their foundries can't yield anything that large, because they never have had to. I have talked to the guys who make the 900 mm square (and larger) die. They get less than one die per 8" wafer. That kind of yield is obscene. Since they get $125,000 per die when they are done, they can afford to do this. That is one hell of a camera sensor, however. AustinArticle: 103646
what's the difference with LVTTL, LVCMOS and 3.3V-PCI for signalling a PCI fpga/cpld? And if 3.3V-PCI is not available, what should be used as the replacement(LVTTL or LVCMOS)? thanks.Article: 103647
Jim, Answers, below, Austin -snip- > I was wondering why the Altera results differed in two areas, but > Xilinx's did not. Did the report not clarify that, or was it a typo ? Not sure what you are referring to. One thing is that Hardcopy is including in those Altera numbers, and we don't see Hardcopy as anything but an ASIC, so it makes it hard to compare how the programmable logic sector is doing (is Altera falling more rapidly behind in FPGAs?). > Yes, and an even better year for Foundries, who some could consider the > ultimate 'ASIC suppliers' :) Foundries are doing well, right now. Tough business. Low margins. Cycles up and down. Huge capital costs. Glad I am not in it. > Did those numbers include OnSemi/Philips/TI etc standard logic devices ? No, they did not. All standard logic products were not included in any of the numbers. Neither were memories, microprocessors, nor DSP. Standard logic in 2005 was $1,579 million total. DSP was $7,569 million total. uP+Memories was $104 billion! As I said, you can make the numbers tell any story you want. For example, comparing 2005 with 2002: (using company reports) 2002: Altera, $712 million revenue for the year (No Hardcopy back then) Xilinx, $1,016 million revenue 2005: Altera, $1,124 million (4% or $45 million is Hardcopy, really $1,079 million, as noted in their public filing) Xilinx, $1,573 million So we grew 1573/1016= 55% and Altera grew 1079/712= 52%. Could have fun all day with numbers, but I need to get some work done now.Article: 103648
In article <e66pgr$7bn4@xco-news.xilinx.com>, Austin Lesea <austin@xilinx.com> wrote: >Thomas, > It is no secret now, as there are companies which tear the parts > apart. I'll save you the $20,000 for buying their report. Many thanks: I'd googled and found the competitive analysis companies, but they clearly regard the device-size figure as being part of the meat of their report, and want you to buy the report before they mentioned it. > The LX200 is close to reticle limited, which means that is is about > 22 X 24 mm. Just shy of 500 sq mm. > At least one family member is always at this limit, as that is how > we maintain "sir superiority." The 4VFX140 is also right about at > that size. That makes a lot of sense; I presume that the reticles stay fairly similarly sized across generations, so the V5LX330 will be the same sort of physical size. The Intel Montecito processor is 27mmx22mm, which I suspect means Intel acquired machinery with a slightly larger reticle. > I have talked to the guys who make the 900 mm square (and larger) > die. They get less than one die per 8" wafer. That kind of yield > is obscene. Since they get $125,000 per die when they are done, > they can afford to do this. That is one hell of a camera sensor, > however. Astronomical sensors are really crazily priced: http://www.buytelescopes.com/product.asp?t=76&pid=2846&m= has a 13cm^2 chip, and costs the same as a new Ford hybrid car. The Canon 5D has a 36x24mm sensor and costs about $3000; on the other hand, I imagine the yield for image sensors isn't so enormous an issue: provided the output circuitry is all there you can interpolate around single dud pixels. I don't know, and I'm sure this is something for which the competitive analysers would charge the earth, whether the routing circuitry in FPGAs has redundant paths selectible by fuse. http://www.ctio.noao.edu/pipermail/ccd-world/2005/002584.html is quite an interesting article about the issues involved with getting astronomical chips made. They're clearly using very different fabs from Chartered, UMC, TSMC and the other usual suspects - a CCD fab engineer was talking about the possibility of moving to six-inch wafers this year, whilst I get the impression that the big fabricators have been on 12" ones for a while. TomArticle: 103649
Add 4 Gb/s Ethernet links to FPGA systems easily & at low cost.
High bandwidth, low latency control & data transfers.
Low gate count & low pin count.
Define your own protocol. No TCP/IP/UDP processing required.
Connection through standard switches or direct to PCs.
Simple & easy. No driver programming.
www.chipethernet.com
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