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Messages from 101050

Article: 101050
Subject: Re: comp.arch.reconfig
From: fpga_toys@yahoo.com
Date: 24 Apr 2006 16:36:14 -0700
Links: << >>  << T >>  << A >>

Robin Bruce wrote:
> I'd like to canvass opinion here. I'm sure opinions will vary greatly.
> The question is:
> Is is time to create a new group devoted entirely to general-purpose
> reconfigurable computing.

Actually, all the electrical engineering design questions, and FPGA
product support questions here are probably off topic, as this forum
was SUPPOSED to be about FPGA computing, not hardware design and FPGA
VHDL/Verilog design support questions.

Maybe what needs to happen, is creating an FPGA hardware design forum
some place else for the hardware designers and FPGA vendors product
support discussions?


Article: 101051
Subject: Opinions on Viva
From: ziggy <ziggy@fakedaddress.com>
Date: Tue, 25 Apr 2006 00:28:31 GMT
Links: << >>  << T >>  << A >>
Just ran across this today, really inexpensive... Wonder how it stacks 
up to the 'free' tools from xilinx?  ( im not qualified to do a review )


Their Hypercomputing things look really cool, but wont even ask how much 
they cost :)


http://www.starbridgesystems.com/

Article: 101052
Subject: Re: vhdl cpu emulator (any interest?)
From: ziggy <ziggy@fakedaddress.com>
Date: Tue, 25 Apr 2006 00:32:27 GMT
Links: << >>  << T >>  << A >>
In article <1145910988.749638.321840@v46g2000cwv.googlegroups.com>,
 nkmlists@gmail.com wrote:

> During the design of my latest FPGA, I wrote a vhdl cpu emulator. I
> would like to know if there is interest in the (open source) FPGA
> community for such a vhdl cpu emulator?
> 
> The emulator supports:
> reading and writing from / to memory on the FPGA
> waiting for interrupts or set periods of time
> multiple threads
> cpu global registers
> thread local registers
> setting local registers based on thread arguments when spawning
> one level while loop
> one level of if with else statement
> outputting data read during a read to a file
> 
> CPU commands come from a main file, and each thread has its own
> separate file.
> 
> If there is already something like this out there, I would love to hear
> about it.
> 
> Thanx,
> nachum

So i assume this would be somewhat generic, so any CPU could be emulated?

Sounds interesting to me at least.

Article: 101053
Subject: Re: vhdl cpu emulator (any interest?)
From: "Mike Treseler" <mike_treseler@comcast.net>
Date: Mon, 24 Apr 2006 18:11:53 -0700
Links: << >>  << T >>  << A >>
nkmlists@gmail.com wrote:
> During the design of my latest FPGA, I wrote a vhdl cpu emulator. I
> would like to know if there is interest in the (open source) FPGA
> community for such a vhdl cpu emulator?

Try comp.lang.vhdl

         -- Mike Treseler

Article: 101054
Subject: Re: ISE 8.1 Sub module Synthesis
From: Gerhard Hoffmann <dk4xp@freenet.de>
Date: Tue, 25 Apr 2006 03:39:22 +0200
Links: << >>  << T >>  << A >>
On Mon, 24 Apr 2006 17:29:34 +0200, Zara <yozara@terra.es> wrote:


>I don't know if it will work in verilgo, but I soppes it will. It
>works on VHDL. Right click on source node , "Select as Top Module". Do
>remember to reselect original Top module when done.

I did this, too (vhdl), but then the  "real top module" user constraint file was
changed to  empty. Gave not so funny results with the router deciding arbitrarily 
which pin is wich. I had connected new hardware to the eval board and 
assumed that I had killed the Virtex4  :-(
Luckily, it was too late already to order a new one.
It would help if one could see in the log files what  the reason was for a
signal to end up at a certain pin.
 
Dependency checking seems to be messed up in 8.1 .  That could be a 
reason for the above, too.
Today, I got warnings about incompatible components and instantiatons. 
I removed some instantiations completely ( commenting out large
blocks is _such_ a fun in VHDL..) but still they appeared in the error list.
It looks like ISE has made own copies of my source files. 
I don't use the internal editor but gvim, so maybe ISE does not see every 
file update?
Using Project -> CleanupProjectFiles reduced the number of error messages
by 80%, but not completely.

And, because I'm in the mood: The ISE gui is almost dead after kicking
off a synthesis. Sometimes, the routing has run to completion before 
the gui wakes up again. The first run after booting seems not to be
affected by this.  I use the windows task manager to keep track of
what's going on (shows top CPU eating processes).

When I double click on "ConfigureDevice" to kick off synthesis & everything,
and do 5 times edit-compile-load-measure, then I end up with 5 incarnations  of
IMPACT, as if one wasn't enough, and each one asking me what to do and 
if it should update the project file on exit, as if anything had changed.

ISE knows enough about my project so that one doubleclick should be enough
to go from source to logic analyzer. We had that already in XC3020 times.
Impact should not ask ME if it needs a mask file for verify. 

I changed from 7.1 to 8.1 because 7.1 crashed may computer abt. 6 times
a day. Those crashes are history with 8.1,  but all in all, things have 
gone from bad to worse. 
Retreating to 6.3 like others here do is probably no option for a virtex4.
Perhaps I should convert everything to makefiles.

regards, Gerhard

environment: Athlon64-4000+, 2 GB RAM, striped raptors :-), XP,
Modelsim PE, ISE 8.1.3, ML402, platform cable USB, vim

Article: 101055
Subject: Re: Spartan 3 documentation confusing...
From: "rickman" <spamgoeshere4@yahoo.com>
Date: 24 Apr 2006 18:53:14 -0700
Links: << >>  << T >>  << A >>
I found the missing info.  Instead of putting the details along with
the other details in the pin descriptions, the pull ups are mentioned
in the section header which I did not read.  That seems to be the only
info in the section header, the pull ups.  The pins I was researching
were on the following page and so the header was not apparent.

The confusing sentance still stands however.  Whatever the words mean,
I assume it is simply saying that there are pull up resistors on all of
the configuration pins regardless of the state of the HSWAP_EN pin.

I don't know what to make of you Austin.  You certainly don't come
across as a people person.  But thanks for the permission to post here.
 ;^)

Just FYI, I have to fight just as hard in the company where I work to
get people to produce decent documentation.  It's not that it should
always be perfect... we're all human.  But so many people don't feel
documentation matters much.  They think it is all about the product.
But people's lives depend on our products and I am taking that very
seriously.

As to this issue, it almost cost me a pointless board spin; not life
threatening, but certainly that could be career threatening.

As to contacting Steve, I have done that.  I hope that the pull up
issue becomes more widely understood.  The combination of poorly
documented pull ups and the stiff value of these pull ups in the
Spartan 3 devices can make a lot of trouble for a lot of designs.


Article: 101056
Subject: Smallest uClinux configuration
From: "Justin Erickson" <jerickson@stanford.edu>
Date: Mon, 24 Apr 2006 19:26:29 -0700
Links: << >>  << T >>  << A >>
I am trying to get uClinux to run in under 2MB of RAM without flash and if 
possible to still have networking support. All I need is basic command line 
support and the ability to load and execute one additional program.

I'd guess that a bunch of people have tried this before and would appreicate 
any help/suggestions on how best to setup the uClinux build configuration.

Thanks,
Justin 



Article: 101057
Subject: Re: Spartan 3 documentation confusing...
From: Austin Lesea <austin@xilinx.com>
Date: Mon, 24 Apr 2006 19:53:52 -0700
Links: << >>  << T >>  << A >>
Rick,

Well, I hope you keep up the comments.

I am seriously trying to improve the documentaion process.

If we explain it right the first time, we get less confusion, and we get 
to market faster.

Really very simple, and very self serving:  the better the docs, the 
less time wasted, and the faster our customers either gain success, or 
fail.  The faster money changes hands.  The faster we succeed (or fail 
to succeeed).

It is so simple, yet so many (most) companies get it wrong.

Just make it simple to succeed, and don't get in the way, or make things 
any tougher than they already are.

As for my personality, my wife thinks I am completely impossible ('how 
can anyone work for you?').  My staff thinks I am the best boss they 
every had ('how can your boss deal with you?').  My supervisors love 
that I always come to them with a solution to the problem ('how do you 
keep your people so happy?').  My (totally grown) kids claim I am 
totally mad, and can not be trusted even for a moment ('that's not 
fair!').  My grandchildren sense I can be completely trusted to see to 
their well being and happiness (which I can be).

So, I have a personality:  guilty as charged.  Member of the human race.

Austin

Article: 101058
Subject: Re: vhdl cpu emulator (any interest?)
From: ghelbig@lycos.com
Date: 24 Apr 2006 22:05:17 -0700
Links: << >>  << T >>  << A >>
nkmlists@gmail.com wrote:
> During the design of my latest FPGA, I wrote a vhdl cpu emulator. I
> would like to know if there is interest in the (open source) FPGA
> community for such a vhdl cpu emulator?
>
    <snip>

> If there is already something like this out there, I would love to hear
> about it.
>
> Thanx,
> nachum

comp.lang.vhdl is the correct group.
www.opencores.org should be willing to host it.

Sounds useful to me; I'd like to see it.


Article: 101059
Subject: Re: ISE 8.1 Sub module Synthesis
From: Zara <yozara@terra.es>
Date: Tue, 25 Apr 2006 07:29:41 +0200
Links: << >>  << T >>  << A >>
On Tue, 25 Apr 2006 03:39:22 +0200, Gerhard Hoffmann
<dk4xp@freenet.de> wrote:

>On Mon, 24 Apr 2006 17:29:34 +0200, Zara <yozara@terra.es> wrote:
>
>
>>I don't know if it will work in verilgo, but I soppes it will. It
>>works on VHDL. Right click on source node , "Select as Top Module". Do
>>remember to reselect original Top module when done.
>
>I did this, too (vhdl), but then the  "real top module" user constraint file was
>changed to  empty. Gave not so funny results with the router deciding arbitrarily 
>which pin is wich. I had connected new hardware to the eval board and 
>assumed that I had killed the Virtex4  :-(
>Luckily, it was too late already to order a new one.
>It would help if one could see in the log files what  the reason was for a
>signal to end up at a certain pin.

Well, never tried it like that. I just limit all work to synthesis
when my tuop module is not *the top module*.

> 
>Dependency checking seems to be messed up in 8.1 .  That could be a 
>reason for the above, too.
>Today, I got warnings about incompatible components and instantiatons. 
>I removed some instantiations completely ( commenting out large
>blocks is _such_ a fun in VHDL..) but still they appeared in the error list.
>It looks like ISE has made own copies of my source files. 
>I don't use the internal editor but gvim, so maybe ISE does not see every 
>file update?

I use Crimson Editor, ans everything works fine.

>Using Project -> CleanupProjectFiles reduced the number of error messages
>by 80%, but not completely.
>
>And, because I'm in the mood: The ISE gui is almost dead after kicking
>off a synthesis. Sometimes, the routing has run to completion before 
>the gui wakes up again. The first run after booting seems not to be
>affected by this.  I use the windows task manager to keep track of
>what's going on (shows top CPU eating processes).

It is the "feature" of reading all reports to create the desgin
summary. It is nice, but it is a heavy load.

BTW, I run ISE on an athlon dual core machine, and it is funny to see
50% of the "CPU" (that is, a full core) used up by
synthesis/xlate/map/par while the other 50%( the other full core) is
used byISE itself to keep reports updated. Most ilustrating.

>
>When I double click on "ConfigureDevice" to kick off synthesis & everything,
>and do 5 times edit-compile-load-measure, then I end up with 5 incarnations  of
>IMPACT, as if one wasn't enough, and each one asking me what to do and 
>if it should update the project file on exit, as if anything had changed.

Yes, that is really stupid.

>
>ISE knows enough about my project so that one doubleclick should be enough
>to go from source to logic analyzer. We had that already in XC3020 times.
>Impact should not ask ME if it needs a mask file for verify. 

Right.

>
>I changed from 7.1 to 8.1 because 7.1 crashed may computer abt. 6 times
>a day. Those crashes are history with 8.1,  but all in all, things have 
>gone from bad to worse. 
>Retreating to 6.3 like others here do is probably no option for a virtex4.
>Perhaps I should convert everything to makefiles.

Best luck. I use only Spartan3, and I can keep up with some of these
nuisances. Going back is not a choice.

Best regards.

Zara

Article: 101060
Subject: Re: How to avoid this waring in ISE 8.1?
From: Zara <yozara@terra.es>
Date: Tue, 25 Apr 2006 07:33:06 +0200
Links: << >>  << T >>  << A >>
On Mon, 24 Apr 2006 19:52:37 GMT, "John_H" <johnhandwork@mail.com>
wrote:

>"Dave Pollum" <vze24h5m@verizon.net> wrote in message 
>news:1145906965.687960.25460@u72g2000cwu.googlegroups.com...
>>
>> John;
>> This is the warning message I get when running a VHDL project using ISE
>> 8.1SP3: "..MON_v3.NGR line 0 duplicate design unit: Module|Mon_v3",
>> where "MON_v3" is my top VHDL module.  I also have 2 lower level
>> modules.  I built a  very similar project with no errors/warnings when
>> I used ISE 7.1SP4.
>>
>> I tried seaching for "duplicate design unit" on Xilinx's web site, but
>> didn't find the warning.
>> Would this be suitable for a web-case?
>> -Dave Pollum
>
>I'd expect unexplained/undocumented errors and warnings would each warrant a 
>web case.
>I haven't run VHDL through XST - I'm a Verilog guy in Synplicity tools.
>
>Would it be safe to say you don't use include files (at least ones that 
>reference the modules)?  If you don't use them, the "duplicate" arrangement 
>I envisioned wouldn't be an issue. 
>


I have a nice test project that uses only one VHDL file with the
description of a dual ported RAM. It gives that warning too. In fact
*every* VHDL project I have gives that warning.

Best regards,

Zara

PS: I never gave it more than five seconds thought, because I am more
worried by the hundreds of unavoidable warnings given by a project
containing an XPS/microblaze module.

Article: 101061
Subject: How to avoid lossing channel bonding when using Rocket IO?
From: "king" <frogkinger908@sina.com>
Date: 24 Apr 2006 22:41:53 -0700
Links: << >>  << T >>  << A >>

 Hi

 I'm using RocketIO with 4 channels, but they would loss banding when
the data flow
 becomes fast.
 What would result in lossing channel banding?
 And how to avoid this problem?

 Many thanks!

 king


Article: 101062
Subject: How to get divider in CRC32 , while implementatinh it in VHDL?
From: shailbadwaik@gmail.com
Date: 24 Apr 2006 23:22:24 -0700
Links: << >>  << T >>  << A >>
I am working on MAC802.3 & not getting How to get divider in CRC32 ?


Article: 101063
Subject: Re: Heating problem of the CPLD
From: Rene Tschaggelar <none@none.net>
Date: Tue, 25 Apr 2006 10:27:22 +0200
Links: << >>  << T >>  << A >>
john wrote:

> Hello,
> 
> I am using atmel's ATF1508AS-7QC160. My clock frequency is 20MHz. Now,
> my cpld some times work and sometimes does not work at that frequency.
> If I lower the clcok frequency to 12MHz then it always work. bu tin
> both cases the chip does get hot. I put a heat sink on the chip but if
> the chip works for long hours then it effects its functionality. Can
> anybody advice me how to slove this problem?

Any open, unconnected inputs ?
Are the inputs on defined valid levels ?

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Article: 101064
Subject: Re: Xilinx Virtex-4 OCM Usage Issues
From: Andreas Ehliar <ehliar@lysator.liu.se>
Date: Tue, 25 Apr 2006 08:33:27 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2006-04-24, charles.eddleston@gmail.com <charles.eddleston@gmail.com> wrote:
> Basically it seems like the bus is hooked up correctly, but that maybe
> a register bit or mode is not correct.  I am wondering if anyone in
> this forum has the IOCM/DOCM working and also executes code out of
> SDRAM (or anyone else who has comment) - are there any register bits
> that I might have left out? Does software have to do anything
> differently now that the design is non-cached (I have tried
> initializing all cached registers...)?

I assume that the end of your bootloader looks something like this:

copy_program_to_sdram();
jump_to_sdram();

Do you issue a sync and isync instruction before jumping to sdram?
Personally I've had the experience that the ppc405 can act very weird if
you don't issue a sync and isync instruction before you jump to
recently modified code.


/Andreas

Article: 101065
Subject: Re: Opinions on Viva
From: Kolja Sulimma <news@sulimma.de>
Date: Tue, 25 Apr 2006 10:38:27 +0200
Links: << >>  << T >>  << A >>
ziggy schrieb:

> Their Hypercomputing things look really cool, but wont even ask how much 
> they cost :)
> 
> 
> http://www.starbridgesystems.com/

Isn't that the company that "put the hype back into hypercomputing?"

Kolja Sulimma

Article: 101066
Subject: Re: comp.arch.reconfig
From: "Robin Bruce" <robin.bruce@gmail.com>
Date: 25 Apr 2006 01:43:58 -0700
Links: << >>  << T >>  << A >>
I suppose it would make sense to change the charter of this newsgroup
to reflect usage. Joking aside, c.a.f pretty well reflects how the
majority of FPGAs are actually used, so I wouldn't make the case that
there's anything wrong with the group. I suppose I believe that there's
more interest in reconfigurable computing than is being suggested by
the volume of posts here. Maybe the best thing for me to do in the
short run is to try and start up a few reconfigurable-computing posts
here and see what happens.

Robin

fpga_toys@yahoo.com wrote:
> Robin Bruce wrote:
> > I'd like to canvass opinion here. I'm sure opinions will vary greatly.
> > The question is:
> > Is is time to create a new group devoted entirely to general-purpose
> > reconfigurable computing.
>
> Actually, all the electrical engineering design questions, and FPGA
> product support questions here are probably off topic, as this forum
> was SUPPOSED to be about FPGA computing, not hardware design and FPGA
> VHDL/Verilog design support questions.
>
> Maybe what needs to happen, is creating an FPGA hardware design forum
> some place else for the hardware designers and FPGA vendors product
> support discussions?


Article: 101067
Subject: Re: comp.arch.reconfig
From: "Robin Bruce" <robin.bruce@gmail.com>
Date: 25 Apr 2006 01:53:04 -0700
Links: << >>  << T >>  << A >>
Sean,

thanks for your post. Partial Reconfiguration is something that is of
interest to reconfigurable computing as I understand it, but it's not
something that anyone is putting on their critical path. Xilinx FPGAs
are not currently designed with commercially-viable partial
reconfiguration and the toolchains, although developing, are still not
there. Dynamic reconfiguration is probably about as far as it goes for
most people.

The best example of "reconfigurable computing" as I understand it at
present is embodied by SRC computers. Their SRC-6 and SRC-7 machines
tightly couple microprocessors to FPGAs and provide a development
environment that balances a high-level of abstraction from FPGA design
with high performance. Check out the performance stats for the SRC-7:

http://www.srccomp.com/SRC7_Performance.htm

Cheers,

Robin


Article: 101068
Subject: Re: How to avoid lossing channel bonding when using Rocket IO?
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 25 Apr 2006 09:59:12 +0100
Links: << >>  << T >>  << A >>
Your Majesty,
Google this:-
"channel bonding" site:xilinx.com

Answer 15050? Some of the many other answers?

Or maybe rogue clowns* have desoldered the FPGA? Seriously, a little more 
information is required! :-)

Your humble subject, Syms.

*http://www.megat.co.uk/wrong/ :-)

"king" <frogkinger908@sina.com> wrote in message 
news:1145943713.179040.36240@t31g2000cwb.googlegroups.com...
>
> Hi
>
> I'm using RocketIO with 4 channels, but they would loss banding when
> the data flow
> becomes fast.
> What would result in lossing channel banding?
> And how to avoid this problem?
>
> Many thanks!
>
> king
> 



Article: 101069
Subject: Re: Virtex-4 Gigabit Ethernet design
From: "Guru" <ales.gorkic@email.si>
Date: 25 Apr 2006 02:02:16 -0700
Links: << >>  << T >>  << A >>
Yes it is true, FIFOs can be expanded. The only problem is that the
UCII is not XPS conmpatible design. Modifcations should be done
manually in ISE with no guarantee that the modified design will work.

Regards,  Guru


Article: 101070
Subject: FPGA with ASIC FPU units
From: "Robin Bruce" <robin.bruce@gmail.com>
Date: 25 Apr 2006 02:24:35 -0700
Links: << >>  << T >>  << A >>
SRC are talking about the following characteristics for a
field-programmable floating-point device that they intend to put in one
of the variants of their SRC-7 reconfigurable computer:

Hard floating point units with field-programmable interconnect

>50 DPFP mults and adders per chip -> 30 GFLOPS

>100 SPFP mults and adders per chip -> 60 GFLOPS

Each FP unit also performs 53 or 24 bit integer ops with 106 or 48 bit
results

Selectable 150 MHz or 300 MHz operation

I've heard that these units will have single-cycle latency. I don't
imagine that these FPGAs will be cheap as there must be considerable
NRE costs that won't be recouped so easily as they would be for a
Xilinx chip. However, they open up a whole new world of possibilities
for scientific computing, making double-precision much more viable than
it has been previously.

Is this the device reconfigurable computing has been waiting for?


Article: 101071
Subject: Re: Max and Argmax across 1,000 unsigned 10-bit numbers
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Tue, 25 Apr 2006 12:06:31 +0100
Links: << >>  << T >>  << A >>
andrewfelch@gmail.com wrote:
> Hello,
> 
> I recently requested advice as to performing bit-matrix multiplication
> on bit matrices (bitwise AND followed by a population count), one
> matrix stored onboard an fpga in block rams, the other one (first
> operand) streaming in row by row.
> 
> It was thought that one of the latest pcie cards would be able to
> provide dot-product throughput limited by the pcie input speed of 16
> Gbps for pcie x8.  The adders would be 80-bits wide (80 bits arrive per
> cycle at 200 mhz over pcie x8) and each column of the onboard matrix
> would be stored in 80 block rams.
Not sure from where did you get the PCIE express numbers, I was under 
the impresion that a PCIE lane is running at 2.5Gbit/s, so if you divide 
by 10 (10b/8b decoding) you'll have 250Mhz for a byte word.
(and x8 lanes will be 20 Gbit/s not 16 Gbit/s)
Aurash
> 
> My question is: How much more difficult is the problem if I must find
> out the maximum dot-product, and which column produced it, for each
> input vector?  This operation must be performed for each input row,
> yielding 1 max and argmax for every 1000 input bits.  The input vector
> is 1000 bits long, of course, and finishes arriving over pcie after
> about 12 pcie cycles.  Is there a fast enough way to argmax 1000
> numbers that are 10-bits (representing each columns dot-product)?  What
> would the cost of the argmax operation be in fpga space as compared to
> the column adders (which are probably 80-bits wide for each column)?
> 
> Thanks for your help.  I want to make sure that the max and argmax
> functions will not be a limiting factor in the design of the bit-matrix
> multiplier.
> 
> Also, thanks for so many helpful comments that have gotten me to this
> level of understanding of the problem.
> 
> - AndrewF
> 

Article: 101072
Subject: SPARTAN3E SK LCD
From: "Eka From Indonesia" <aan.woodz@gmail.com>
Date: 25 Apr 2006 04:28:29 -0700
Links: << >>  << T >>  << A >>
I have SPARTAN3E STARTER KIT and I'm uncomfortable with its LCD
off-backlight. I would like to turn on it permanently. Is it safe to
turn on LCD backlight with 5V SPARTAN3E SK-PSU by connecting pin15 (LCD
BL Anode) to pin2 (LCD VDD) and pin16 (LCD BL Cathode) to pin1 (LCD VSS
/ Ground)? Please advise me, thank you.


Article: 101073
Subject: Re: Spartan 3 documentation confusing...
From: "rickman" <spamgoeshere4@yahoo.com>
Date: 25 Apr 2006 04:31:11 -0700
Links: << >>  << T >>  << A >>
As long as you brought up your personality, I'll just say that I
remember reading about someone who reminds me of you, Napoleon.  He
thought a lot of himself too.

Austin Lesea wrote:
> Rick,
>
> Well, I hope you keep up the comments.
>
> I am seriously trying to improve the documentaion process.
>
> If we explain it right the first time, we get less confusion, and we get
> to market faster.
>
> Really very simple, and very self serving:  the better the docs, the
> less time wasted, and the faster our customers either gain success, or
> fail.  The faster money changes hands.  The faster we succeed (or fail
> to succeeed).
>
> It is so simple, yet so many (most) companies get it wrong.
>
> Just make it simple to succeed, and don't get in the way, or make things
> any tougher than they already are.
>
> As for my personality, my wife thinks I am completely impossible ('how
> can anyone work for you?').  My staff thinks I am the best boss they
> every had ('how can your boss deal with you?').  My supervisors love
> that I always come to them with a solution to the problem ('how do you
> keep your people so happy?').  My (totally grown) kids claim I am
> totally mad, and can not be trusted even for a moment ('that's not
> fair!').  My grandchildren sense I can be completely trusted to see to
> their well being and happiness (which I can be).
>
> So, I have a personality:  guilty as charged.  Member of the human race.
> 
> Austin


Article: 101074
Subject: Re: How to avoid lossing channel bonding when using Rocket IO?
From: "colin" <colin_toogood@yahoo.com>
Date: 25 Apr 2006 05:18:26 -0700
Links: << >>  << T >>  << A >>
I have no idea why you think this would happen.
If you have four channels and you clocked them identically at the
source they will arrive at the destination at different times due and
data on different channels would not be synchronised with each other.
Channel bonding simply transmits a marker on all four channels on the
same clock so that when they arrive at the destination the very small
elastic buffer adjusts itself so that data out from the four channels
comes out on the same clock correctly.
In theory you only ever need to do it once but noise could confuse it.
It doen't matter how much data you then send, the system knows that
data a,b,c&d was all sent on clock x and the receiver presents a,b,c&d
out on the same clock

Colin


king wrote:
> Hi
>
>  I'm using RocketIO with 4 channels, but they would loss banding when
> the data flow
>  becomes fast.
>  What would result in lossing channel banding?
>  And how to avoid this problem?
> 
>  Many thanks!
> 
>  king




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